STMICROELECTRONICS L9942

L9942
Integrated stepper motor driver for bipolar stepper motors
with microstepping and programmable current profile
PRELIMINARY DATA
Features
■
Two full bridges for max. 1.3 A load (RDSON =
500 mΩ)
■
Programmable current waveform with look-up
table: 9 entries with 5bit resolution
■
Current regulation by integrated PWM
controller and internal current sensing
■
Programmable stepping mode: Full, Half, Mini
and Microstepping
■
Programmable slew rate for EMC and power
dissipation optimisation
■
Programmable Fast-, Slow-, Mixed-and AutoDecay Mode
■
Full-Scale Current programmable with 3bit
resolution
■
Very low current consumption in standby mode
IS < 3µA, typ. Tj ≤ 85 °C
■
All outputs short circuit protected with
Openload, Overloadcurrent, Temperature
Warning and Thermal Shutdown
■
The PWM signal of the internal PWM controller
is available as digital output.
■
All parameters guaranteed for 7V < Vs < 20V
Applications
PowerSSO-24
Description
The device is an integrated stepper motor driver
for bipolar stepper motors with microstepping and
programmable current profile look-up-table to
allow a flexible adaptation of the stepper motor
characteristics and intended operating conditions.
It is possible to use different current profiles
depending on target criteria: audible noise,
vibrations, rotation speed or torque. The decay
mode used in PWM-current control circuit can be
programmed to slow-, fast-, mixed-and autodecay. In autodecay mode device will use slow
decay mode if the current for the next step will
increase and the fast decay or mixed decay mode
if the current will decrease.
Stepper Motor Driver for bipolar Stepper Motors in
Automotive Applications like Light Levelling,
Bending Light and Throttle Control.
Order codes
Part number
Junction Temp range, °C
Package
Packing
L9942
-40 to 150
PowerSSO-24
Tube
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev 1
1/37
www.st.com
37
L9942
Contents
1
Block diagram and Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
2/37
2.1
Dual Power Supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Standby-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3
Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Over-voltage and Under-voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5
Temperature Warning and Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6
Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.7
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.8
PWM Current Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.9
Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.10
Over Current Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.11
Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.12
Stepping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.13
Decay Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.1
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.2
Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.3
Reference Current Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.4
Charge Pump Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.5
Outputs: Qxn (x=A;B n=1;2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.6
Outputs: Qxn (x=A;B n=1;2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.7
PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description of the Logic with SPI . . . . . . . . . . . . . . . . . . . . . . 19
4.1
Motor Stepping Clock Input( STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
PWM Output (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
L9942
5
6
7
4.3
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7
Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI - Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2
Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3
Counter and Profiles Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4
Signal and Profile Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5
Counter and Profile (Register 4 and Register 5) . . . . . . . . . . . . . . . . . . . . . . 23
5.6
Control, Status and Profile Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7
Status Register7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.8
Auxiliary logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.8.1
Fault Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.8.2
SPI communication monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.8.3
PWM monitoring for stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Logic with SPI - Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1
Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3
Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4
Output: DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6
STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1
Stall Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2
Load Current Control and Detection of Overcurrent (Shortages at Outputs) 31
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
L9942
1 Block diagram and Pin information
1
Block diagram and Pin information
Figure 1.
Block diagram
VBAT
ReversePolarityProtection
VCC
CP
Charge
Pump
Oscillator
STEP
QA1
Diagnostic
SPI + Register + Logic
Phase Counter+Current Profile
⇓
PWM Current DAC
EN
PWM
µC
VS
DO
DI
CLK
CSN
Gate-Driver
&
PWM-Controller
Note: value of capacitor has
to be choosen carefully to
limit the VS voltage below
absolute maximum ratings in
case of an unexpected
freewheeling condition (e.g.
TSD, POR)
QA2
Stepper
Motor
QB1
Gate-Driver
&
PWM-Controller
Diagnostic
QB2
U/IConverter
Biasing
GND
RREF
GNDP
GND
Figure 2.
Pin connection (Top view)
PGND
1
Power SSO24
23 QA2
QA1 2
VS 3
22 VS
CLK 4
21 EN
20 RREF
DI 5
CSN 6
DO 7
Slugdown
19 VCC
18 TEST
PWM 8
17 GND
STEP 9
16 CP
VS 10
15 VS
14 QB2
QB1 11
13 PGND
PGND 12
All pins with the same name must be externally connected!
All pins PGND are internally connected to the heat slug.
4/37
24 PGND
L9942
1 Block diagram and Pin information
Table 1.
Pin Description
Pin
Symbol
1, 12, 13, 24
PGND
3, 10, 15, 22
VS
Function
Power ground: All pins PGND are internally connected to the heat slug.
Important: All pins of PGND must be externally connected!
Power supply voltage (external reverse protection required): For EMI
reason a ceramic capacitor as close as possible to PGND is recommended.
Important: All pins of VS must be externally connected !
2, 23
Fullbridge-outputs An: The output is built by a highside and a lowside switch,
which are internally connected. The output stage of both switches is a power
QA1,QA2 DMOS transistor. Each driver has an internal reverse diode (bulk-drain-diode:
highside driver from output to VS, lowside driver from PGND to output). This
output is over-current protected.
11, 14
Fullbridge-outputs Bn: The output is built by a highside and a lowside switch,
which are internally connected. The output stage of both switches is a power
QB1,QB2 DMOS transistor. Each driver has an internal reverse diode (bulk-drain-diode:
highside driver from output to VS, lowside driver from PGND to output). This
output is over-current protected.
4
CLK
SPI clock input: The input requires CMOS logic levels. The CLK input has a
pull-down current. It controls the internal shift register of the SPI.
5
DI
Serial data input: The input requires CMOS logic levels. The DI input has a
pull-down current. It receives serial data from the microcontroller. The data is a
16bit control word and the least significant bit (LSB, bit 0) is transferred first.
6
CSN
Chip Select Not input The input requires CMOS logic levels. The CSN input
has a pull-up current. The serial data transfer between device and micro
controller is enabled by pulling the input CSN to low level.
7
DO
SPI data output: The diagnosis data is available via the SPI and it is a tristateoutput. The output is CMOS compatible will remain highly resistive, if the chip
is not selected by the input CSN (CSN = high)
8
PWM
PWM output This CMOS compatible output reflects the current duty cycle of
the internal PWM controller of bridge A. It is an high resistance output until
VCC has reached minimum voltage ore can switched off via the SPI command.
9
STEP
Step clock input: The input requires CMOS logic levels. The STEP input has
a pull-down current. It is clock of up and down counter of control register 0.
Rising edge starts new PWM cycle to drive motor in next position.
16
CP
17
GND
Ground: Reference potential besides power ground e.g. for reference resistor
RREF. From this pin exist a resistive path via substrate to PGND.
18
TEST
Test input The TEST input has a pull-down current. Pin used for production
test only. In the application it must be connected to GND.
19
VCC
Logic supply voltage: For this input a ceramic capacitor as close as possible
to GND is recommended.
RREF
Reference Resistor The reference resistor is used to generate a temperature
stable reference current used for current control and internal oscillator. At this
output a voltage of about 1.28V is present. The resistor should be chosen that
a current of about 200uA will flow through the resistor.
EN
Enable input: The input requires CMOS logic levels. The EN input has a pulldown resistor. In standby-mode outputs will be switched off and all registers
will be cleared. If EN is set to a logic high level then the device will enter the
active mode.
20
21
Charge Pump Output: A ceramic capacitor (e.g.100 nF) to VS can be
connected to this pin to buffer the charge-pump voltage.
5/37
2 Device description
2
Device description
2.1
Dual Power Supply: VS and VCC
L9942
The power supply voltage VS supplies the half bridges. An internal charge-pump is used to
drive the highside switches. The logic supply voltage VCC (stabilized) is used for the logic part
and the SPI of the device. Due to the independent logic supply voltage the control and status
information will not be lost, if there are temporary spikes or glitches on the power supply
voltage. In case of power-on (VCC increases from under voltage to VPOR OFF = 2.60 V, typical)
the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC
decreases under the minimum threshold (VPOR ON = 2.45 V, typical), the outputs are switched
to tristate (high impedance) and the internal registers are cleared.
2.2
Standby-Mode
The EN input has a pull-down resistor. The device is in standby mode if EN input isn't set to a
logic high level. All latched data will be cleared and the inputs and outputs are switched to high
impedance. In the standby mode the current at VS (VCC) is less than 3 µA (1µA) for CSN =
high (DO in tristate). If EN is set to a logic high level then the device will enter the active mode.
In the active mode the chargepump and the supervisor functions are activated.
2.3
Diagnostic Functions
All diagnostic functions (overload/-current, open load, power supply over-/undervoltage,
temperature warning and thermal shutdown) are internally filtered (tGL = 32µs, typical) and the
condition has to be valid for a minimum time before the corresponding status bit in the status
registers will be set. The filters are used to improve the noise immunity of the device. Open load
and temperature warning function are intended for information purpose and will not change the
state of the bridge drivers. On contrary, the overload/-current and thermal shutdown condition
will disable the corresponding driver (overload/-current) or all drivers (thermal shutdown),
respectively. The microcontroller has to clear the status bit to reactivate the bridge driver.
2.4
Over-voltage and Under-voltage Detection
If the power supply voltage VS rises above the over-voltage threshold VSOV OFF (typical 20 V),
the outputs are switched to high impedance state to protect the load. When the voltage VS
drops below the undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages
are switched to the high impedance to avoid the operation of the power devices without
sufficient gate driving voltage (increased power dissipation). Error condition is lached and the
microcontroller needs to clear the status bits to reactivate the drivers.
2.5
Temperature Warning and Thermal Shutdown
If junction temperature rises above Tj TW a temperature warning flag is set which is detectable
via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal
shutdown bit will be set and power DMOS transistors of all output stages are switched off to
6/37
L9942
2 Device description
protect the device. In order to reactivate the output stages the junction temperature must
decrease below Tj SD -Tj SD HYS and the thermal shutdown bit has to be cleared by the
microcontroller.
2.6
Inductive Loads
Each half bridge is built by an internally connected highside and a lowside power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven without external free-wheeling diodes. In order to reduce the power dissipation during
free-wheeling condition the PWMcontroller will switch-on the output transistor parallel to the
freewheeling diode (synchronous rectification).
2.7
Cross-current protection
The four half-brides of the device are cross-current protected by an internal delay time
depending on the programmed slew rate. If one driver (LS or HS) is turned-off then activation of
the other driver of the same half bridge will be automatically delayed by the cross-current
protection time .
2.8
PWM Current Regulation
An internal current monitor output of each high-side and low-side transistor sources a current
image which has a fixed ratio of the instantaneous load current. This current images are
compared with the current limit in PWM control. Range of limit can reach from programmed full
scale value (register1 DAC Scale) down belonging LSB value of 5 bit DAC (register1 DAC
Phase x). The data of the two 5 bit DACs comes form set up in 9 current profiles (register2 to 6).
If signal changes to logic high at pin STEP then 2 currentprofiles are moved in register1 for
DAC Phase A and B. Number of profile depends on phase counter reading and direction bit in
register0 (Figure 7). The bridges are switched on until the load current sensed at HS switch
exceeds the limit . Load current comparator signal is used to detect open load or overcurrent
condition also.
2.9
Decay modes
During off-time the device will use one of several decay modes programmable by SPI (Figure 4
top). In slow decay mode HS switches are activated after cross current protection time for
synchronous rectification to reduce the power dissipation (Figure 4 detail A). In fast decay
opposite halfbridge will switched on after cross current protection time, that is same like change
in the direction. For mixed decay the duration of fast decay period before slow decay can be set
to a fixed time (Figure 4 detail B continuous line ) or is triggered by under-run of the load current
limit (Figure 4 detail B dashed line), that can be detected at LS switch. The special mode where
the actual phase counter value is taken into account to select the decay mode is called auto
decay (e.g. in Figure 3 Micro Stepping DIR=1). If the absolute value of the current limit is higher
as during step before then PWM control uses slow decay mode always. Otherwise one of the
fast decay modes is automatic selected for a quick decrease of the load current and so it
obtains new lower target value.
7/37
L9942
2 Device description
2.10
Over Current Detection
The overcurrent detection circuit monitors the load current in each activated output stage. In HS
stage it is in function after detection of currentlimit during PWM cycle and in LS stage it works
permanently. If the load current exceeds the overcurrent detection threshold for at least tISC =
4 µs, the over-current flag is set and the corresponding driver is switched off to reduce the
power dissipation and to protect the integrated circuit. Error condition is lached and the
microcontroller needs to clear the status bits to reactivate the drivers.
2.11
Open Load Detection
The open load detection monitors the activity time of the PWM controller and is available for
each phase. If the limit of load current is below around 100mA then open load condition is
detectable. Open load bit for a bridge is set in the register6 if this low current limit can't reached
after at least 15 consecutive PWM cycles.
Table 2.
Truth table
DC2
DC1
DC0
I4
I3
I2
I1
I0
max. IOL
0
0
0
0
x
x
x
x
48mA
0
0
1
0
x
x
x
x
72mA
0
1
0
0
0
x
x
x
56mA
1
1
0
0
0
x
x
x
90mA
1
0
0
0
0
0
x
x
58mA
1
0
1
0
0
0
x
x
87mA
1
1
0
0
0
0
0
1
42mA
1
1
1
0
0
0
0
1
48mA
Truth table shows possible profiles for active open load detection. Maximum threshold IOL is
shown in left column if x bits are 1 (see also Figure 7). Lowest possible limit is e.g. 3.1 mA for
DC2=DC1=DC0=0 and it is set only I0=1.
2.12
Stepping Modes
One full revolution can consist of four full steps, eight half steps, sixteen mini steps or 32
microsteps.
Mode is set up in register 0 and it defines increment size of phase counter. Phase counter value
defines address of corresponding currentprofile. Stepping modes with typical profile values can
see in Figure 3 (e.g. also so called 'Two Phase On' shown in dashed line).
8/37
L9942
2 Device description
Figure 3.
Stepping Modes
Full-Stepping Mode: DIR=0
0
8
Full-Stepping Mode: DIR=1
16
Phase Counter
24
24
16
8
0
0
Current Driver A
Current Driver A
0
8
Address of Current
Profile Entry
8
0
8
0
8
Current Driver B
Current Driver B
8
0
8
Address of Current
Profile Entry
0
8
0
8
STEP Signal
STEP Signal
Half-Stepping Mode: DIR=0
0
4
8
12
16
20
Half-Stepping Mode: DIR=1
24
Phase Counter
28
0
28
24
20
Current Driver A
0
4
8
8
4
0
4
0
8
4
8
4
Address of Current
Profile Entry
0
4
8
4
0
4
Address of Current
Profile Entry
8
4
0
4
4
6
8
10
12
14
16
18
20
22
24
2
4
6
8
6
8
6
4
2
0
2
4
2
0
6
8
28
30
Phase Counter
0
30
28
26
2
4
24
22
6
8
6
4
2
Adress of Current
Profile Entry
0
2
4
6
8
6
6
4
2
0
2
4
6
Adress of Current
Profile Entry
8
6
4
2
0
2
4
8
4
0
4
20
18
16
14
12
10
8
6
4
2
Mixed Decay
Mode
2
4
6
8
6
4
2
4
6
8
6
4
2
0
2
4
6
0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Slow Decay
Mode
Adress of Current
Profile Entry
Slow Decay
Mode
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Mixed Decay
Mode
0
Current Driver A
Mixed Decay
Mode
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Current Driver B
2
Micro Stepping Mode: DIR=1 (e.g. auto decay)
Phase Counter
Current Driver A
Slow Decay
Mode
4
STEP Signal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Slow Decay
Mode
8
Current Driver B
Micro Stepping Mode: DIR=0 (e.g auto decay)
Mixed Decay
Mode
4
Current Driver A
STEP Signal
Slow Decay
Mode
0
4
Current Driver B
4
4
Mini-Stepping Mode: DIR=1
26
Current Driver A
0
8
STEP Signal
Mini-Stepping Mode: DIR=0
2
12
Driver Current B
STEP Signal
0
16
Driver Current A
Current Driver B
4
0
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Slow Decay
Mode
Mixed Decay
Mode
Adress of Current
Profile Entry
Mixed Decay
Mode
Current Driver B
Mixed Decay
Mode
Slow Decay
Mode
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Slow Decay
Mode
Mixed Decay
Mode
9/37
L9942
2 Device description
2.13
Decay Modes
Figure 4.
Decay Modes
Load
Current
ON
SLOW
DECAY
FAST
DECAY
MIXED
DECAY
VS
VS
on
on
A
VS
on
on
on
on
B
VS
VS
on
on
on
Time
Internal PWM_CLK
Detail A: SWITCH ON AND SLOW DECAY
Step
Limit
HS
ON
TB
TCC
TFT
TCC
TB
register0
DM2 DM1 DM0
0
0
0
TCC SLOW DECAY
T FT
fast decay
fast decay
Load
Current
MODE
slow
VS
Time
Fast decay is caused by
current through internal
diodes during cross current
protection time.
OFF
OFF
OFF
Filter time for the purpose of switch off delay in on mode is set by FT register6
Cross current protection time is set by SR1 SR0 register0
Blank time of load current comparator TB=TCC
Detail B:
MIXED DECAY
register0
DM2 DM1 DM0 MODE CURVE
X
X
X
Load
Current
TCC
Step
Limit
LS
TFT
FAST
DECAY
Tmc
0
1
1
1
0
1
T MD1
T MD2
T mc
Load
Current
TCC
SLOW DECAY
after current
undershoot
T mc>= T FT + 2TCC
TCC
FAST
DECAY
T MDx= TMD1
or T MD2
T MDx
SLOW DECAY
with delay
TCC
Time
TFT Filter time for purpose of delay when decay mode has to change after limit under-run
TMD When limit is reached so fast decay duration time is set by DM1 DM2 register0
10/37
OFF
Time
L9942
3 Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
VS
Value
Unit
-0.3...28
V
40
V
-0.3 to 5.5
V
-0.3 to VCC + 0.3
V
-0.3 to VCC + 0.3
V
DC supply voltage
single pulse tmax < 400 ms
VCC
stabilized supply voltage, logic supply
VDI,VDO,
VCLK VCSN,
VSTEP VEN
VRREF
digital input / output voltage
current reference resistor
VCP
charge pump output
-0.3 to VS + 11
V
VQxn
(x=A;B n=1;2) output voltage
-0.3 to VS + 0.3
V
IQxn
(x=A;B n=1;2) output current
±2.5
A
Note:
Leaving the limitation of any of these values may cause an irreversible damage of the
integrated circuit !
3.2
ESD Protection
Table 4.
ESD Protection
Parameter
Value
Unit
All pins
±2 1
kV
output pins: Qxn (x=A;B n=1;2)
±4 2
kV
Value
Unit
-40 to 150
°C
Note: 1 HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A
2 HBM with all unzapped pins grounded
3.3
Thermal data
Table 5.
Symbol
Tj
Operating junction temperature
Parameter
operating junction temperature
11/37
L9942
3 Electrical specifications
Table 6.
Temperature warning and thermal shutdown
Symbol
Parameter
TjTW ON
temperature warning threshold
junction temperature
TjTW OFF
temperature warning threshold
junction temperature
TjSD ON
thermal shutdown
thresholdjunction temperature
TjSD OFF
thermal shutdown threshold
junction temperature
TjSD HYS
thermal shutdown hysteresis
Figure 5.
Thermal data of package
Min.
Typ.
Tj increasing
Max.
Unit
150
°C
130
°C
170
150
°C
°C
5
K
Note:
1s
1 signal layer
2s2p 2 signal layers 2 internal planes
12/37
L9942
3 Electrical specifications
3.4
Electrical characteristics
3.4.1
Supply
VS = 7 to 16V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 °C, IREF = -200 µA , unless otherwise
specified. The voltages are referred to GND and currents are assumed positive, when the
current flows into the pin.
Table 7.
Symbol
Supply
Parameter
VS DC supply current in
active mode
VS = 13.5 V, EN=VCC outputs
floating
VS quiescent supply current
Tj = -40 °C
VS = 13.5 V, TEST,
to
25°C
EN = 0V outputs
floating
Tj = 125 °C
IS
ICC
ICC
Test Condition
VCC DC supply current in
active mode
VCC quescent suppy current
Min.
Typ.
Max.
Unit
7
20
mA
3
10
µA
6
20
VCC = 5.0 V EN=VCC,
DI=CLK=STEP=0V
1
3
mA
VCC = 5.0 V TEST;
Tj = -40 °C
EN = 0V; CSN =
VCC no clocks
to 25°C
outputs floating
1
3
µA
CSN=VCC no
clocks outputs
floating
Tj = 125 °C
2
6
µA
VS = 13.5 V, VCC = Tj = -40 °C
5.0 V
to 25°C
4
13
IS + ICC
TEST; EN=0V
CSN=VCC no
Sum quiescent supply current
clocks outputs
floating
tsetPOR 1
VCC on set up time
µA
Tj = 125 °C
EN = 5V, CSN=CLK=0V DO
changes from high ohmic to logic
level LOW
8
2
26
µs
Note: 1 This parameter is guaranteed by design.
13/37
L9942
3 Electrical specifications
3.4.2
Over- and undervoltage detection
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.
Table 8.
Over- and undervoltage detection .
Symbol
Parameter
Test Condition
Min.
Typ.
VSUV ON
VS UV-threshold voltage
VS increasing
VSUV OFF
VS UV-threshold voltage
VS decreasing
VSUV hyst
VS UV-hysteresis
VSUV ON -VSUV OFF
VSOV OFF
VS OV-threshold voltage
VS increasing
VSOV ON
VS OV-threshold voltage
VS decreasing
VSOV hyst
VS OV-hysteresis
VSOV OFF -VSOV ON
0.5
VPOR OFF
power-on-reset threshold
VCC increasing
2.6
VPOR ON
power-on-reset threshold
VCC decreasing
VPOR hyst
power-on-reset hysteresis
VPOR OFF -VPOR ON
Figure 6.
Unit
6.90
V
4.8
V
0.3
V
25
V
20
2.00
V
V
2.9
V
2.3
V
0.11
V
VS Monitoring
Register 7
OV
Register 7
UV
1
1
0
0
VS
VS
VSUV OFF
3.4.3
Max.
VSOV ON
VSUV ON
VSOV OFF
Reference Current Output
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.
Table 9.
Reference Current Output
Symbol
Parameter
VREF
reference voltage range
IREFshorted
IREFopen
Test Condition
IREF = -200 µA
Min.
Typ.
Max.
Unit
1.05
1.25
1.45
V
-250
µA
reference current
register6 bit7 RERR = 1
threshold shorted pin REF
reference current
threshold open pin REF
register6 bit7 RERR = 1
-150
µA
The device works properly without the external resistor at pin REF. In this case it doesn't have
to fullfill all specified parameters.
14/37
L9942
3.4.4
3 Electrical specifications
Charge Pump Output
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.
Table 10.
Charge Pump Output
Symbol
Parameter
Test Condition
VS=7V
VCP
charge pump output voltage
VS=13.5V
VS=20V
Min.
ICP= -100µA, all
switches off at
Qxn
Typ.
Max.
Unit
11
20
V
20
35
V
30
40
V
The ripple of voltage at CP can suppressed using a capicity of e.g.100nF.
3.4.5
Outputs: Qxn (x=A;B n=1;2)
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin
Table 11.
Symbol
Outputs: Qxn (x=A;B n=1;2)
Parameter
Test Condition
Min.
VS = 13.5 V, Tj = 25 °C,
IQxn = -1.0A
RDSON HS
on-resistance Qxn to
VS
VS = 13.5 V, Tj = 125 °C,
IQxn = -1.0 A
VS = 7.0 V, Tj = 25 °C,
IQxn = -1.0 A
VS = 13.5 V, Tj = 25 °C,
IQxn = + 1.0A
RDSON LS
on-resistance Qxn to
PGND
VS = 13.5 V, Tj = 125 °C,
IQxn = + 1.0 A
VS = 7.0 V, Tj = 25 °C,
IQxn = + 1.0 A
|IQxnOC |
output overcurrent
limitation to VS or
PGND
testmode exclusive of
filtertime 4us (Chapter 2.10)
1.6
Typ.
Max.
Unit
500
700
mΩ
750
1000
mΩ
550
750
mΩ
500
700
mΩ
750
1000
mΩ
550
750
mΩ
2
A
15/37
L9942
3 Electrical specifications
3.4.6
Outputs: Qxn (x=A;B n=1;2)
The comparator, which is monitoring current image of HS, is working during ON cycle of PWM
control. If load current is higher as set value then the signal ILIMIT is generated and after filter
time the bridge is switched off. Test mode gets access to signal ILIMIT and threshold of current
can be measured.
Table 12.
Outputs: Qxn (x=A;B n=1;2)
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin
Symbol
IQxnFS_HS
IQxnLIM_HS
Parameter
Value of output current
to supply VS ( so called
full scale value)1
sourcing from HS
switch
Test Condition
Min.
Typ.
Max.
Bits: DC2 DC1 DC0=000
60
95
130
Bits: DC2 DC1 DC0=001
100
140
180
Bits: DC2 DC1 DC0=010
180
230
280
Bits: DC2 DC1 DC0=011
300
360
420
Bits: DC2 DC1 DC0=100
485
550
615
Bits: DC2 DC1 DC0=101
720
810
900
Bits: DC2 DC1 DC0=110
1000
1150
1300
Bits: DC2 DC1 DC0=111
1200
1350
1500
Unit
mA
Accuracy of micro steps
current limit
MIN2
MAX2
mA
Note: 1 Current profile has to pre set with I4 I3 I2 I1 I0 = 11111 and load to register 1 .
2 MIN= 0.92 · IQxnLIM – 0.02 · |IQxnFS_HS | , MAX= 1.08 · IQxnLIM + 0.02 · |IQxnFS_HS |
Output current limit IQxnLIM is product of full scale current |IQxnFS_ | ( bits DC2 DC1 DC0)
and value of DAC
PhaseA/B ( bits I4 I3 I2 I1 I0) in register1.
Values of DAC Phase A and B can read out and depends on set up done before:
16/37
1.
direction DIR , stepping mode ST1 ST0 and phase counter P4 P3 P2 P1 P0 in register 0
and
2.
value of corresponding current profile (for address of current profile entry see also
Figure 3).
L9942
3 Electrical specifications
Figure 7.
Logic to Set Load Current Limit
Register 0
UP/Down
Count by
1,2,4,8
PhaseCounter
P4
P3
P2
Decay Mode
P1
DM2
P0
DM1
DM0
Slew Rate
StepMode
SR1
ST1 ST0
SR0
DIR
STEP
0
0
0
0 1 2 3 0 1 2 3 0 1 2 3
A2 A1 A0
MUX
A3
A2
MUX
A1
MUX
A0
Address Calculation
Phase A
Adr
A3=0
A[3..0]
Adr
Phase B
A3=1
neg(A[3..0])
Adr
Current-Profile Table
stored in register2, ...6
5
9
I4
I4
I3
I3
I2
I2
I1
I1
I0
I0
Profile 8
Profile 7
I0
Profile 6
I1
I0
Profile 5
I2
I1
I0
Profile 4
I3
I2
I1
I0
Profile 3
I4
I3
I2
I1
I0
Profile 2
I4
I3
I2
I1
I0
Profile 1
I4
I3
I2
I1
I0
Profile 0
I4
I3
I2
I4
I3
I2
I4
I3
I4
I1
A3=1
Adr A[3..0]
A3=0
neg(A[3..0])
Register 1
5
5
DI
DAC Phase A
DAC Phase B
DAC Scale
DC2 DC1 DC0 I4
I3
I2
I1
I0
I4
I3
I2
I1
I0
QA1
5
5 bit DAC
Phase B
5
5
REF
I REF
DAC
Full Scale
LIMIT B
5 bit DAC
Phase A
I LIMIT A
I QA1LIM
1000
I Qx1LIM
QA2
I MAX
I QB1LIM
1000
5
5
QB1
5
IQA2LIM
1000
I Qx2LIM
5
QB2
IQB2LIM
1000
3.4.7
PWM Control
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.
Table 13.
Symbol
fPWM 1
PWM Control (see Figure 4 and Figure 7)
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Bit: FRE= 1
20.8
kHz
Bit: FRE= 0
31.3
kHz
Bits: DM1 DM0= 0 1
4
us
Bits: DM1 DM0= 1 0
8
us
Bit: FILTER= 0
1.5
us
Bit: FILTER= 1
2.5
us
Frequency of PWM cycles
TMD1
Mixed decay switch off delay time
TFT1
Glitch filter delay time
17/37
L9942
3 Electrical specifications
Table 13.
PWM Control (see Figure 4 and Figure 7) (continued)
Symbol
Parameter
Test Condition
Min.
Bits: SR1 SR0= 0 0
Tcc 1
TB
1
VSR
Typ.
Max.
Unit
0.5
us
Cross current protection time Blank Bits: SR1 SR0= 0 1
time of comparator
Bits: SR1 SR0= 1 0
1
us
2
us
Bits: SR1 SR0= 1 1
4
us
Bits: SR1 SR0= 0 0
13
V/us
Bits: SR1 SR0= 0 1
13
V/us
Bits: SR1 SR0= 1 0
6
V/us
Bits: SR1 SR0= 1 1
6
V/us
Slew rate (dV/dt 30%-70%) @HS
switches on resistive load of 10Ω,
VS=13.5V
Note: 1 This parameter is guaranteed by design.
Time base is an internal trimmed oscillator of typical 2MHz and it has an accuracy of ±6% .
Figure 8.
Switching on Minimum Time
Load current
at Qxn
T FT Filter time of current comparator
T FT
TCC
T
CC
Cross current protection time
T B Blank time of current comparator
Step limit
e.g. T B = TCC = 1 us
T CC
TB
Time
Internal PWM
clock
20 or 30 kHz
TINT _2MHz
Pin PWM
(for bridge A)
18/37
TPWM
on
decay
T FT = 1.5 us
L9942
4 Functional Description of the Logic with SPI
4
Functional Description of the Logic with SPI
4.1
Motor Stepping Clock Input( STEP)
Rising edge of signal STEP is latched. It is synchronised by internal clock. At next start of a new
PWM cycle the new values of output current limit are used to drive motor in next position.
Before start new motor step this signal has to be low for at least two internal clock periods to
reset latch.
4.2
PWM Output (PWM)
This output reflects the current duty cycle of the internal PWM controller of bridge A. High level
indicates on state to increase current through load and low level is in off state so load current
decreases depending on chosen decay mode.
4.3
Serial Peripheral Interface (SPI)
This device uses a standard 16 bit SPI to communicate with a microcontroller. The SPI can be
driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and
CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and output
data is changed from the high to low transition of CLK.
A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect an
internal Error Flag of the device which is a logical-or of all status bits in the Status Register
(reg7) and in the Current Profile Register 4 (reg6). The microcontroller can poll the status of the
device without the need of a full SPI-communication cycle.
4.4
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output
pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial
communication can be started. The state when CSN is going low until the rising edge of CSN
will be called a communication frame.
4.5
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and latched into an internal 16 bit shift register.
The first 3 bit are interpreted as address of the data register. At the rising edge of the CSN
signal the contents of the shift register will be transferred to the selected data register. The
writing to the register is only enabled if exactly 16 bits are transmitted within one
communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame
the complete frame will be ignored. This safety function is implemented to avoid an activation of
the output stages by a wrong communication frame.
19/37
L9942
4 Functional Description of the Logic with SPI
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
4.6
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high
impedance to a low or high level depending on the status bit 0 (fault condition). The first rising
edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the
selected status register into the data out shift register. Each subsequent falling edge of the CLK
will shift the next bit out.
4.7
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
4.8
Data Register
The device has eight data registers. The first three bits (bit0 ... bit2) at the DI-input are used to
select one of the input registers. All bits are first shifted into an input shift register. After the
rising edge of CSN the contents of the input shift register will be written to the selected Input
Data Register only if a frame of exact 16 data bits are detected. The selected register will be
transferred to DO during the current communication frame.
Figure 9.
SPI and Registers
DI
CLK
D
CSN
CLK_ADR
INT_2MHz
POR
SPIControll
DO
D0
D A0
D1
A1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 D12
A0
A1
A2
A2
SEL_ERROR
SPI2REG
Phase Counter
Control Register 0
P4
P3
P2
Decay Mode
P1
P0
DM2
DM1
DM0
Slew Rate
Step Mode
SR1
ST1
SR0
ST0
DIR
Read Only
DAC_Scale
Control Register 1
DC2
DC1 DC0
BI4
BI3
DAC Phase B
BI2
BI1
Counter and Profiles Register 2
I4
Current Profile 1
I3
I2
I1
I0
Test
T2
Singnal and Profiles Register 3
I4
Current Profile 3
I3
I2
I1
I0
T5
Counter and Profiles Register 5
Control, Status and Profile
Register 6
I4
I3
I2
I1
I3
CLR
Status SST
I2
Filter
I1
PWM
Freq
DT1
T4
I0
DT4
DT3
ST
DT7
DT6
AI0
I4
Current Profile 0
I3
I2
I1
I0
PWM
NPWM
T3
I4
Current Profile 2
I3
I2
I1
I0
I4
Current Profile 4
I3
I2
I1
I0
I4
Current Profile 6
I3
I2
I1
I0
I4
Current Profile 8
I3
I2
I1
I0
DT2
PWM Counter
I0
DAC Phase A
AI3
AI2
AI1
DT0
PWM Counter
Current Profile 7
I4
AI4
PWM Counter
Test
Current Profile 5
Counter and Profiles Register 4
BI0
DT5
Read-Only
Openload
RREF
Error Phase Phase
B
A
Read-Only
Status Register 7
20/37
CLR Temperature
Status TSD
TW
VS Monitor
OV
UV HSB2 HSB1 LSB2
Overcurrent
LSB1 HSA2 HSA1 LSA2
LSA1
L9942
5 SPI - Control and Status Registers
5
SPI - Control and Status Registers
5.1
Control Register 0
Phase Counter
Decay Mode
Slew Rate
Step Mode
DIR
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
P4
P3
P2
P1
P0
DM2
DM1
DM0
SR1
SR0
ST1
ST0
DIR
The meaning of the different bits is as follows:
DIR
ST1 ST0
This bit controls direction of motor movement. DIR=1 clockwise DIR=0 counter clockwise.
This bits controls step mode of motor movement (Figure 3).
00
Micro-stepping
01
Mini-stepping
10
Half-stepping
11
Full-stepping
SR1 SR0
DM2 DM1 DM0
This bit controls slew rate of bridge switches. See also parameter Table 13
This bits controls decay mode of output current (Figure 3).
000
Slow decay
001
Mixed decay, fast decay until TMD > 4us
010
Mixed decay, fast decay until TMD > 8us
011
Mixed decay, fast decay until current undershoot Tmc =TFT +TCC
100
Auto decay, fast decay without delay time
101
Auto decay, fast decay until TMD > 4us
110
Auto decay, fast decay until TMD > 8us
111
Auto decay, fast decay until current
undershoot Tmc
P4 P3 P2 P1 P0
Auto decay uses mixed decay automatically
to reduce current for next step if required (
see Figure 3 down right).
This bits control position of motor, e.g. 00000 step angle is 0° , 01111 step angle is 180°..
21/37
L9942
5 SPI - Control and Status Registers
5.2
Control Register 1
DAC Scale
DAC Phase B
DAC Phase A
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
rw
rw
rw
r
r
r
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
DC2
DC1
DC0
BI4
BI3
BI2
BI1
BI0
AI4
AI3
AI2
AI1
AI0
The meaning of the different bits is as follows:
These bits control DAC of
bridge A.
AI4 AI3 AI2 AI1 AI0
Value depends on address and the value of
corresponding current profile.
BI4 BI3 BI2 BI1 BI0
These bits control DAC of
bridge B .
DC2 DC1 DC0
These bits set full scale range
of limit, e.g. 000 for 100 mA or
111for e.g. 1500mA
5.3
See also parameter Table 12.
Counter and Profiles Register 2
Current Profile 1
Not used
Current Profile 0
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
I4
I3
I2
I1
I0
T2
T1
T0
I4
I3
I2
I1
I0
The meaning of the different bits is as follows:
I4 I3 I2 I1 I0
T2 T1 T0
5.4
These bits are loaded in register1 DAC Phase A or B if needed. See also parameter Table 12
These bits are used in test mode only.
Signal and Profile Register 3
PWM
Counter
Current Profile 3
Bit
PWM
Current Profile 2
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
w
w
w
w
w
w
w
w
w
w
w
w
w
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
I4
I3
I2
I1
I0
D1
(T5)
D0
(T4)
NPW
M(T3)
I4
I3
I2
I1
I0
Access
22/37
L9942
5 SPI - Control and Status Registers
The meaning of the different bits is as follows:
I4 I3 I2 I1 I0
These bits are loaded in register1 DAC Phase A or B if needed.
These bits are for threshold value in counter of active time
during signal PWM.
DT1 DT0
This bit switches internal PWM signal of bridge A to pin PWM if
it is set to 0, otherwise pin is in high resistance status.
NPWM
(T5 T4 T3)
5.5
See also parameter Table 12
These bits are used in test mode only.
Counter and Profile (Register 4 and Register 5)
Current Profile 5 (7)
PWM Counter
Current Profile 4 (6)
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
I4
I3
I2
I1
I0
D4(7)
D3(6)
D2(5)
I4
I3
I2
I1
I0
The meaning of the different bits is as follows:
These bits are loadedneeded. in register1 DAC Phase A
or B if needed.
I4 I3 I2 I1 I0
See also parameter Table 12
D4 D3 D2 (register4) These bits are for threshold value in counter of active time
during signal PWM. LSB and next value are set in
register3 by D0 and D1.
D7 D6 D5 (register5)
5.6
Control, Status and Profile Register 6
CLR
ST
Filter
(PWM)
Freq
ST
REF
ERR
Openload
Current Profile 8
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
rw
rw
rw
rw
r
r
r
r
rw
rw
rw
rw
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
CLR6
SST
FT
FRE
ST
RERR
OB
OA
I4
I3
I2
I1
I0
The meaning of the different bits is as follows:
I4 I3 I2 I1 I0
These bits are loaded in register1 DAC Phase A or B if
needed
See also parameter Table 12
OB OA
These bits indicate openload at bridges
RERR
This bit indicates if reference current is OK (150uA <IREF < 250uA), then is RERR=0.
ST
FRE
This bit indicates stall detection.
This bit sets frequency of PWM cycle. FRE=1 frequency 20kHz, FRE=0 frequency 30kHz
23/37
L9942
5 SPI - Control and Status Registers
FT
This bit sets filter time in glitch filter. FT=0 TF =1.5us, FT=1 TF =2.5us
SST
This bit specifies output PWM to reflect same logical level like bit ST.
CLR6
5.7
This bit resets all bits to 0 in register 6.
Status Register7
CLR
Temperature
VS Monitor
Overcurrent
Bit
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
rw
r
r
r
r
r
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
CLR7
TSD
TW
OV
UV
LSB2
LSB1
HSA2
HSA1
LSA2
LSA1
HSB2 HSB1
The meaning of the different bits is as follows:
bit7 ... bit0
1
OV UV
These bits indicate overcurrent in each lowside or highside power transistor.
overcurrent failure I > 2A
These bits indicates failure at VS ( See also parameter Table 8)
01
Voltage at pin VS is too low.
10
Voltage at pin VS is too high.
TSD TW
These bits indicates temperature failure ( See also parameter Table 6)
01
Only for information set at temperature warning threshold.
10
In case of thermal shutdown all bridges are switched off. It has to reset by bit CLR7.
CLR7
This bit resets all bits to 0 in register7.
5.8
Auxiliary logic blocks
5.8.1
Fault Condition
Logical level at pin D0 represents fault condition. It is valid from first high to low edge of signal
CLK up to transfer of data bit D12. Fault bit is an logical OR of:
Control and Status Register 6 bit 5 and 6 for Open Load, bit7 reference current failure
(RERR) and
Control and Status Register 7 bit 0 to bit 7 for Overcurrent, bit 8 and 9 failure at VS
(UV,OV) and
bit 10 and bit 11 during high temperature (TW,TSD)
24/37
L9942
5.8.2
5 SPI - Control and Status Registers
SPI communication monitoring
At the rising edge of the CSN signal the contents of the shift register will be transferred to the
selected data register. A counter monitors proper SPI communication. It counts rising edges at
pin CLK. The writing to the register is only enabled if exactly 16 bits are transmitted within one
communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame
the complete frame will be ignored. This safety function is implemented to avoid an activation of
the output stages by a wrong communication frame. SPI communication can be checked by
loading a command twice and then answer at pin DO must be same.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
5.8.3
PWM monitoring for stall detection
Control registers 4, 5, and 3 contain bits D0-D7, use for setting a stall detection threshold. The
value in this set of bits determine the minimum time for current rise over one quadrant of motor
driving. D7-D0 is compared with the sum of the rise times over one quadrant. When the sum is
less than the value stored in D7-D0 the ST bit (register6 bit 8) is set to a logic “1”.
The PWM pin reflects the PWM control signal of the load current in bridge A. This is so after
power on when the SST bit (register 6, bit11) is reset to a logic “0”. If this bit is set to a logical
“1” then status of the ST bit 8 is mirrored to pin PWM. This provides stall detection without the
need of reading register 6 through the SPI bus.
25/37
L9942
6 Logic with SPI - Electrical Characteristics
6
Logic with SPI - Electrical Characteristics
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 °C, IREF = -200 µA, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.
6.1
Inputs: CSN, CLK, STEP, EN and DI
Table 14.
Inputs: CSN, CLK, STEP, EN and DI
Symbol
Parameter
Test Condition
Min.
Typ.
1.5
2.0
Max.
Unit
Vin L
input low level
VCC = 5 V
Vin H
input high level
VCC = 5 V
Vin Hyst
input hysteresis
VCC = 5 V
0.5
ICSN in
pull up current at input CSN
VCSN = VCC-1.5 V,
-50
-25
-10
µA
ICLK in
pull down current at input CLK
VCLK = 1.5 V
10
25
50
µA
pull down current at input DI
VDI = 1.5 V
10
25
50
µA
ISTEP in
pull down current at input STEP
VSTEP = 1.5 V
10
25
50
µA
REN in
resistance at input EN to GND
VEN in = VCC
110
510
kΩ
Cin (1)
input capacitance at input CSN,
CLK, DI and PWM
0 V < VCC < 5.3 V
10
15
pF
Typ.
Max.
Unit
IDI in
3.0
V
3.5
V
V
(1) Parameter guaranteed by design.
6.2
DI timing
Table 15.
DI timing (see Figure 11 and Figure 13) (2)
Symbol
Parameter
Test Condition
Min.
tCLK
clock period
VCC = 5 V
250
ns
tCLKH
clock high time
VCC = 5 V
100
ns
tCLKL
clock low time
VCC = 5 V
100
ns
tset CSN
CSN set up time, CSN low before
rising edge of CLK
VCC = 5 V
100
ns
tset CLK
CLK set up time, CLK high before
rising edge of CSN
VCC = 5 V
100
ns
tset DI
DI set up time
VCC = 5 V
50
ns
thold DI
DI hold time
VCC = 5 V
50
ns
tr in
rise time of input signal DI, CLK,
CSN
VCC = 5 V
25
ns
tf in
fall time of input signal DI, CLK, CSN VCC = 5 V
25
ns
(2) DI timing parameters tested in production by a passed/failed test:
Tj=-40°C/+25°C: SPI communication @5MHz; T j=+125°C: SPI communication @4.25MHz
26/37
L9942
6.3
6 Logic with SPI - Electrical Characteristics
Outputs: DO, PWM
Table 16.
Outputs: DO, PWM
Symbol
Parameter
VDOoutL
Test Condition
Min.
Typ.
Max.
Unit
0.2
0.4
V
output low level
VCC = 5 V, ID = 2 mA
output high level
VCC = 5 V, ID = -2 mA
IDOoutLK
tristate leakage current
VCSN = VCC,
0 V < VDO < VCC
-10
10
µA
IPWMoutLK
tristate leakage current
Register3bit5=1 (NPWM)
0 V < VPWM < VCC
-10
10
µA
tristate input capacitance
VCSN = VCC,
0 V < VCC < 5.3 V
10
15
pF
Typ.
Max.
Unit
VPWMoutL
VDOoutH
VPWMoutH
Cout (1)
6.4
VCC 0.4
VCC 0.2
V
Output: DO timing
Output: DO timing (see Figure 12 and Figure 13)
Table 17.
Symbol
Parameter
Test Condition
Min.
tr DO
DO rise time
CL = 100 pF, Iload = -1 mA
50
100
ns
tf DO
DO fall time
CL = 100 pF, Iload = 1 mA
50
100
ns
ten DO tri L
DO enable time from tristate to low CL = 100 pF, Iload = 1 mA pulllevel
up load to VCC
50
250
ns
tdis DO L tri
DO disable time from low level to
tristate
CL = 100 pF, Iload = 4 mA pullup load to VCC
50
250
ns
ten DO tri H
DO enable time from tristate to
high level
CL = 100 pF, Iload = -1 mA pulldown load to GND
50
250
ns
tdis DO H tri
DO disable time from high level to
tristate
CL = 100 pF, Iload = -4 mA
50
250
ns
50
250
ns
Typ.
Max.
Unit
td DO
6.5
DO delay time
pull-down load to GND
VDO < 0.3 VCC, VDO > 0.7
VCC, CL = 100 pF
CSN timing
Table 18.
Symbol
CSN timing
Parameter
tCSN_HI,min (1) CSN high time, active mode
Test Condition
Transfer of SPI-command to
Input Register
Min.
2
µs
27/37
L9942
6 Logic with SPI - Electrical Characteristics
6.6
STEP timing
Table 19.
STEP timing
Symbol
Parameter
Test Condition
Min.
tSTEPmin (1) STEP low or high time
Typ.
Max.
Unit
2
µs
(1) Parameter guaranteed by design.
Figure 10. Transfer Timing Diagram
t
CSN_HI,min
CSN high to low: DO enabled
CSN
time
CLK
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
0
1
time
DI: data will be accepted on the rising edge of CLK signal
actual data
DI
A2
A1 A0 D12D11 D10 D9 D8 D7 D6
new data
D5 D4 D3 D2
D1 D0
A2
A1
time
DO: data will change on the falling edge of CLK signal
status information
DO
D12D11 D10 D9 D8 D7 D6
D5 D4 D3 D2
D1 D0
time
fault bit
CSN low to high: actual data is
transfered to registers
fault bit
actual data
old data
Control and Status Register
time
Figure 11. Input Timing
0.8 VCC
t CLK
CSN
0.2 VCC
t set CSN
t CLKH
t
set CLK
0.8 VCC
CLK
0.2 VCC
t set DI
t hold DI
t CL KL
0.8 VCC
DI
Valid
Valid
0.2 VCC
28/37
L9942
6 Logic with SPI - Electrical Characteristics
Figure 12. SPI - DO Valid Data Delay Time and Valid Time
tf in
t r in
0.8 VCC
0.5 VCC
0.2 VCC
CLK
t r DO
DO
(low to high)
0.8 VCC
0.2 VCC
td DO
t f DO
0.8 VCC
DO
(high to low)
0.2 VCC
Figure 13. DO Enable and Disable Time
t f in
t r in
0 .8 V C C
50%
0 .2 V C C
CSN
DO
p u ll - u p lo a d to V C C
C L = 100 pF
50%
ten
D O tri L
t d is
D O L tri
50%
DO
p u ll- d o w n lo a d t o G N D
C L = 100 pF
ten
D O tri H
t d is
D O H tri
29/37
L9942
6 Logic with SPI - Electrical Characteristics
Figure 14. Timing of Status Bit 0 (Fault Condition)
C S N h ig h t o l o w a n d C L K s t a y s lo w : s t a t u s in f o r m a t i o n o f d a t a b it 0 ( f a u lt c o n d it io n ) is t r a n s f e r e d t o D O
CSN
t im e
CLK
t im e
DI
t im e
D I: d a ta is n o t a c c e p te d
DO
0t im e
D O : s t a t u s in f o r m a t io n o f d a t a b it 0 ( f a u lt c o n d it i o n ) w ill s t a y a s l o n g a s C S N is lo w
30/37
L9942
7 Appendix
7
Appendix
7.1
Stall Detection
The L9942 contains logic blocks designed to detect a motor stall caused by excessive
mechanical load.
During a motor stall condition the load current rises much faster than during normal operation.
The L9942 measures this time and compares it to a programmed value.
This is done by summing the PWM on times for one full quadrant. For a full wave stepping this
is just one value (step 0). For microstepping this includes 8 separate values added together,
one for each step. This measurement is only done on phase A during the quadrants where the
current is increasing naturally (quadrants 1 and 3 of Figure 15); e.g. stall detection is active
during phase counter values 1 to 8 and 17 to 24 for DIR=0. During the quadrants where the
current is decreasing fast decay recirculation interferes with accurate measurement of this time.
If the sum of the PWM on time is less than a programmed threshold stored in D0-D7, stall is
detected and indicated as a logic “1” in the stall (ST) bit found in register 6 bit 8 (Figure 15
bottom). If bit 11 of register 6 is set to logical “1” then the ST bit is mirrored to the PWM pin
providing detection externally.
The register values DT7-DT0 store the threshold value in 16us intervals. These bits can be
found interstitially in register 3 (D0, D1), register4 (D2, D3, D4) and register5 (D5, D6, D7).
Care should be taken when deciding the threshold timing. Motor current slew rates are
dependant on the driving voltage, the actual speed of the motor, the back EMF of the motor as
well as the motor and the inductance. Be sure to set your threshold well away from what can be
seen in normal operation at any temperature.
7.2
Load Current Control and Detection of Overcurrent (Shortages
at Outputs)
The L9942 controls load current in the two full bridges by using a pulls with modulation (PWM)
regulator. The mirrored output current of active HS switch is compared with a programmed
reference current (e.g. in figure A2 HSA1 and HSB2). Bridge is switched off if current has
exceeded the programmed limit value.
A second comparator of the related LS switch uses the mirrored load current to detect an
overcurrent to ground during ON state of bridges (e.g. in Figure 16 LSA2 and LSB1). The event
of shortage from output to supply voltage VS is detectable, but short current between outputs is
limited through PWM controller and so an overcurrent failure will not occur.
Load currents decrease more or less fast during OFF state of bridges depending on selected
decay mode. Slow decay mode is realised by activating the HS switches of the bridge and
current comparator has as new reference the overcurrent limit. A shortage to ground can be
detected, but not between the outputs.
Is it recommended to use the different fast decay modes too, especially in period if the load
current has to reduce from step to step. The duration of fast decay can set by fixed time ore that
it depends on the comparator signal utilising the second current mirror at LS switch. There can
be monitored the undershoot of bridge current during OFF state.
31/37
L9942
7 Appendix
Fast decay can be seen as switching the bridge in opposite direction, if it is compared to ON
state before. The load current control at HS switch is not used, but the comparator is still active.
The reference value is changed to overcurrent limit and a shortage to ground or now between
the outputs too will result in a signal. The internal filter time of at least 4 us will inhibit the signal
in many applications. Then you can use the mode “auto decay without any delay time“ (On
Section 5.1 on page 21 mode 100). On page 34 you can find in the lower part of Figure 3 the
phase counter values, when fast decay as only part of mixed decay is used and the shortages
can be detected during a longer time. After this it is signalised in register 7 as overcurrent in HS
switch (e.g. in Figure 17 HSA1).
Figure 15. Stall Detection
Load Current Rising During High Speed
Counter value is above threshold value.
PWM activ detection
Stall
Time
Threshold
16us *
Register 5
Register 4 Reg3
bit7 bit6 bit5 bit7 bit6 bit5 bit7 bit6
D7
D6
PWM activ detection
Time
D5
D4
D3
D2
D1
D0
PWM activ detection
Stall
Threshold
Stall
Threshold
PWM activ
counter
PWM activ
counter
No
Stall Signal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Phase Counter
0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Activ
sampling and
threshold
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Activ
sampling and
threshold
Current Driver A
Current Driver A
Adress of Current
Profile Entry
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Adress of Current
Profile Entry
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Current Driver B
Current Driver B
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
STEP Signal
Micro Stepping Mode: DIR=0
Micro Stepping Mode: DIR=1
Load Current Rising During Low Speed or Stall
Counter value is below threshold value.
PWM activ detection
PWM activ detection
PWM activ detection
Time
Stall
Threshold
Stall Signal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Phase Counter
Activ
sampling and
threshold
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Activ
sampling and
threshold
Current Driver A
Stall Signal
0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Current Driver A
Adress of Current
Profile Entry
0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
Adress of Current
Profile Entry
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
Current Driver B
Current Driver B
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
PWM activ
counter
PWM activ
counter
Stall
Threshold
STEP Signal
Micro Stepping Mode: DIR=0
32/37
Micro Stepping Mode: DIR=1
L9942
7 Appendix
Figure 16. Reference Generation for PWM Control (Switch On)
1
Register 0
UP/Down
PhaseCounter 1
Count by
1,2,4,8
0
0
Decay Mode
0
0
DM2
1
DM1
DM0
Slew Rate
SR1
Counter value changes after an signal at STEP to next one
depending on selected stepping mode described in figure 3
(e.g. during micro stepping to value 2) .
StepMode DIR
SR0
0
0
0
STEP
0
0
0
0 1 2 3 0 1 2 3 0 1 2 3
A3
Address Calculation
A2
A1
A0
MUX
MUX
MUX
A2
A1
A0
Phase A
Adr
A3=0
A[3..0]
Adr
Phase B
A3=1
neg(A[3..0])
Adr
A3=0
neg(A[3..0])
PWM Control With HS Current Monitoring
Overcurrent Detection At LS Switch
A3=1
Adr A[3..0]
Current-Profile Table
stored in register2, ...6
9
5
1
1
1
1
1
Profile 8
1
1
1
1
0
Profile 7
1
1
1
0
1
Profile 6
1
1
0
1
0
Profile 5
1
0
1
1
0
Profile 4
1
0
0
0
1
Profile 3
0
1
1
0
0
Profile 2
Phase Counter
5
0
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1
Current Driver A
5
Adress of Current
Profile Entry
Phase A
5
5
0
1
2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
8
7
6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
5
5
Current Driver B
Adress of Current
Profile Entry
Phase B
5
0
0
1
1
0
Profile 1
0
0
0
0
0
Profile 0
5
STEP Signal
5
HS Current
Monitoring
(Load control)
Register 1
DAC Scale
DI
0
0
0
95 mA
DAC Phase A
DAC Phase B
1
1
1
1
0
I
5 bit DAC
Phase B
I REF
REF
200 uA
0
DAC
Full Scale
0
1
1
0
100mA * 6/31 = 18.4mA
100mA * 30/31 = 91.9mA
LIMIT B
LIMIT HSA1
I LIMIT A
5 bit DAC
Phase A
+
2mA
2mA
I MAX
HS1 on
QA1
+
-
IA
+
+
QB1
2mA
LS Current
Monitoring
(Overcurrentl)
IQA1LIM
1000
-
2mA
OC LSB1
-
+
LS1 on
+
-
2mA
IB
+
QA2
2mA
OC
LSA2
+
-
LS2 on
-
LIMIT HSB2
HS Current
Monitoring
(Load control)
+
2mA
2mA
IQA2LIM
1000
HS2on
+
QB2
-
LS Current
Monitoring
(Overcurrent)
+
-
+
-
33/37
L9942
7 Appendix
Figure 17. Reference Generation for PWM Contro (Decay)l
1
Register 0
UP/Down
1
PhaseCounter
Count by
1,2,4,8
0
0
0
Decay Mode
0
1
DM2
DM1
DM0
StepMode DIR
Slew Rate
SR1
Counter value changes after an signal at STEP to next one
depending on selected stepping mode described in figure 1.2
(e.g. during micro stepping to value 2) .
SR0
0
0
0
STEP
0
0 1 2 3
A3
Address Calculation
0
0 1 2 3
0 1 2 3
A2
A1
A0
MUX
MUX
MUX
A2
A1
A0
Phase A
Adr
A3=0
A[3..0]
Adr
Auto Decay
0
Mixed Decay
Fast and Slow
Decay
Slow Decay
Phase B
A3=1
neg(A[3..0])
Adr
A3=0
neg(A[3..0])
A3=1
Adr A[3..0]
Current-Profile Table
stored in register2, ...6
9
5
1
1
1
1
1
Profile 8
1
1
1
1
0
Profile 7
1
1
1
0
1
Profile 6
1
1
0
1
0
Profile 5
1
0
1
1
0
Profile 4
1
0
0
0
1
Profile 3
0
1
1
0
0
Profile 2
Phase Counter
5
0
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Current Driver A
5
Adress of Current
Profile Entry
Phase A
5
5
0
1
2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1
8
7
6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
5
5
Current Driver B
Adress of Current
Profile Entry
Phase B
5
0
0
1
1
0
Profile 1
0
0
0
0
0
Profile 0
5
STEP Signal
5
HS Current
Monitoring
(Overcurrent)
Register 1
DAC Scale
DI
0
0
0
95 mA
DAC Phase A
DAC Phase B
1
1
1
1
0
I
5 bit DAC
Phase B
I REF
REF
200 uA
DAC
Full Scale
0
0
1
1
0
100mA * 6/31 = 18.4mA
95mA * 30/31 = 91.9mA
LIMIT B
OC
I LIMIT A
5 bit DAC
Phase A
HSA1
+
QA1
2mA
-
I MAX
HS Current
Monitoring
(Overcurrent)
+
-
OC
HSB1
+
2mA
2mA
IQB1
1000
+
HS1 on
-
HSB1
+
Fast
Decay
IB
2mA
+
-
+
+
QB2
2mA
+
-
LIMIT LSB2
-
34/37
LS2on
-
+
HS2 on
QA2
2mA
-
2mA
IA
-
OC
+
Slow
Decay
QB1
+
-
LS Current
Monitoring
(Load Control)
HS1 on
2mA
-
HS Current
Monitoring
(Overcurrent)
L9942
8
8 Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect. The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 18. PowerSSO-24 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
2.47
0.085
0.085
TYP.
MAX.
A
2.15
A2
2.15
2.40
a1
0
0.075
b
0.33
0.51
0.013
0.02
c
0.23
0.32
0.009
0.012
D
10.10
10.50
0.398
0.413
E
7.4
7.6
0.291
0.299
e
0.8
e3
8.8
G1
0.06
k
L
10.5
0.004
0.002
0.398
5˚
h
N
0.413
5˚
0.4
0.55
0.094
0.003
0.346
0.1
10.1
OUTLINE AND
MECHANICAL DATA
0.031
G
H
0.097
0.85
0.016
0.021
0.033
10˚
10˚
X
4.1
4.7
0.161
0.185
Y
6.5
7.1
0.256
0.279
PowerSSO-24
(Exposed Pad)
35/37
L9942
9 Revision history
9
36/37
Revision history
Date
Revision
7-Nov-2005
1
Changes
Initial release.
L9942
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
37/37