STMICROELECTRONICS M41ST95WMX6

M41ST95Y*
M41ST95W
5.0 or 3.0V, 512 bit (64 bit x8) Serial RTC
(SPI) SRAM and NVRAM Supervisor
FEATURES SUMMARY
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5.0 OR 3.0V OPERATING VOLTAGE
SERIAL PERIPHERAL INTERFACE (SPI)
NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY
CHOICE OF POWER-FAIL DESELECT
VOLTAGES:
– M41ST95Y*: VCC = 4.5 to 5.5V
4.20V ≤ VPFD ≤ 4.50V
– M41ST95W: VCC = 2.7 to 3.6V
2.55V ≤ VPFD ≤ 24.70V
1.25V REFERENCE (FOR PFI/PFO)
COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY
44 BYTES OF GENERAL PURPOSE RAM
PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING
BATTERY BACK-UP MODE)
WATCHDOG TIMER
MICROPROCESSOR POWER-ON RESET
BATTERY LOW FLAG
32kHz FREQUENCY OUTPUT AVAILABLE
IMMEDIATELY UPON POWER-ON (300mil
SO28 MX PACKAGE ONLY)
AUTOMATICALLY RECORDS TIME WHEN
POWER-FAIL OCCURS
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 550nA (MAX)
PACKAGING INCLUDES A 28-LEAD SOIC
and SNAPHAT® TOP (to be ordered
separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY and
CRYSTAL
Figure 1. 28-pin SOIC Package*
SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
Figure 2. 28-pin (300mil) SOIC Package
Embedded Crystal
SOX28 (MX)
* Contact Local Sales Office
September 2004
1/35
M41ST95Y*, M41ST95W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 28-pin SOIC Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin (300mil) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3.
Table 1.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
......
......
......
......
......
......
.....5
.....5
.....6
.....6
.....7
.....8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Data and Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.Output Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11.WRITE Cycle Timing: RTC and External SRAM Control Signals . . . . . . . . . . . . . . . . . . 11
Table 3. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
READ and WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. TIMEKEEPER ® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Alarm Repeat Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15.Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Full-time F32k Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
(Available only in 28-pin, 300mil SOIC (MX) package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Input (RSTIN1 and RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16.RSTIN1 and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/35
M41ST95Y*, M41ST95W
Table 7. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17.Power-Fail Comparator Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Preferred Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. tREC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline . . . . . . . . 29
Table 15. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 29
Figure 23.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 30
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data30
Figure 24.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 31
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 31
Figure 25.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline . . . . . . . . 32
Table 18. SOX28 – 28-lead Plastic Small, 300mils, Embedded Crystal, Package Mech. Data . . . 32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3/35
M41ST95Y*, M41ST95W
SUMMARY DESCRIPTION
The M41ST95Y/W Serial TIMEKEEPER® SRAM
is a low power, 512-bit static CMOS SRAM organized as 64 words by 8 bits. A built-in 32,768Hz
oscillator (external crystal controlled) and 8 bytes
of the SRAM (see Table 4., page 16) are used for
the clock/calendar function and are configured in
binary coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially
via a serial SPI interface. The built-in address register is incremented automatically after each
WRITE or READ data byte. The M41ST95Y/W
has a built-in power sense circuit which detects
power failures and automatically switches to the
battery supply when a power failure occurs. The
energy needed to sustain the SRAM and clock operations can be supplied by a small lithium buttoncell supply when a power failure occurs. Functions
available to the user include a non-volatile, timeof-day clock/calendar, Alarm interrupts, Watchdog
Timer and programmable Square Wave output.
Other features include a Power-On Reset as well
as two additional debounced inputs (RSTIN1 and
RSTIN2) which can also generate an output Reset
(RST). The eight clock address locations contain
the century, year, month, date, day, hour, minute,
second and tenths/hundredths of a second in 24
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made automatically.
4/35
The M41ST95Y/W is supplied in a 28-lead SOIC
SNAPHAT® (MH) package (which integrates both
crystal and battery in a single SNAPHAT top), or a
28-pin, 300mil SOIC package (MX) which includes
an embedded 32kHz crystal.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device surface-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SNAPHAT SOIC and battery/crystal packages are shipped separately in plastic anti-static
tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT)
part number is “M4TXX-BR12SH” (see Table
20., page 33).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile operation.
M41ST95Y*, M41ST95W
Figure 3. Logic Diagram
Table 1. Signal Names
VCC VBAT(1)
E
ECON
SCL
RST(2)
SDI
IRQ/FT/OUT
(2)
EX
RSTIN1
ECON
Conditioned Chip Enable Output
EX
External Chip Enable
E
Chip Enable
IRQ/FT/OUT
Interrupt/Frequency Test/Out
Output (Open Drain)
RST
Reset Output (Open Drain)
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
SCL
Serial Clock Input
SDI
Serial Data Input
SDO
Serial Data Output
SQW
Square Wave Output
F32k(2)
32kHz Square Wave Output
SQW
M41ST95Y/W
RSTIN2
SDO
PFO
WDI
VOUT
WDI
Watchdog Input
PFI
F32k(3)
PFI
Power-Fail Input
PFO
Power-Fail Output
VOUT
Voltage Output
VBAT(1)
Battery Supply Voltage
VCC
Supply Voltage
VSS
Ground
NC
No Connect
NF
No Function
VSS
AI06369
Note: 1. For SOX28 package only.
2. Open drain
3. Available only in 28-pin, 300mil SOIC (MX) package.
Note: 1. For SOX28 package only.
2. Available only in 28-pin, 300mil SOIC (MX) package.
5/35
M41ST95Y*, M41ST95W
Figure 4. 28-pin SOIC Connections
SQW
NC
NC
NC
NC
NC
NC
WDI
RSTIN1
RSTIN2
NC
NC
PFO
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7 M41ST95Y 22
8 M41ST95W 21
9
20
10
19
11
18
12
17
13
16
14
15
Figure 5. 28-pin, 300mil SOIC (MX)
Connections
VCC
E
IRQ/FT/OUT
VOUT
NC
NC
PFI
NC
SCL
EX
RST
SDI
SDO
ECON
AI06370
NF(1)
NF(1)
NF(1)
(1)
NF
NC
NC
NC
SQW
WDI
RSTIN1
RSTIN2
PFO
NC
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7 M41ST95Y 22
8 M41ST95W 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
E
IRQ/FT/OUT
VOUT
NC
PFI
SCL
F32k
EX
RST
SDI
SDO
ECON
VBAT
AI06370b
Note: 1. No Function (NF) pins (1, 2, 3, and 4) pins must be tied to
VSS, and are internally shorted together.
6/35
M41ST95Y*, M41ST95W
Figure 6. Block Diagram
REAL TIME CLOCK
CALENDAR
E
SDO
44 BYTES
USER RAM
SPI
INTERFACE
SDI
RTC w/ALARM
& CALIBRATION
SCL
OUTPUT DRIVER
FREQUENCY TEST
WATCHDOG
32kHz
OSCILLATOR
Crystal
SQUARE WAVE
AFE
OUT
FT
(1)
WDS
IRQ/FT/OUT
SQW
(2)
WDI
VCC
F32k
VOUT
VBAT
VBL
COMPARE
VSO
COMPARE
VPFD
COMPARE
BL
POR
RST(1)
RSTIN1
RSTIN2
ECON
EX
PFI
COMPARE
PFO
1.25V
(Internal)
AI06371
Note: 1. Open Drain Output
2. Available only in 28-pin, 300mil SOIC (MX) package.
7/35
M41ST95Y*, M41ST95W
Figure 7. Hardware Hookup
SPI Interface with
(CPOL, CPHA)(1) =
('0','0') or ('1','1')
Master
(ST6, ST7, ST9,
ST10, Others)
D
Q
C
C
Q
D
C
M41ST95Y/W
CS3
CS2
CS1
E
Q
D
C
XXXXX
E
Q
D
XXXXX
E
AI06372
Note: 1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU.
8/35
M41ST95Y*, M41ST95W
OPERATION
The M41ST95Y/W clock operates as a slave device on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI
bus compatible. The bus signals are SCL, SDI and
SDO (see Table 1., page 5 and Figure 7., page 8).
The device is selected when the Chip Enable input
(E) is held low. All instructions, addresses and
data are shifted serially in and out of the chip. The
most significant bit is presented first, with the data
input (SDI) sampled on the first rising edge of the
clock (SCL) after the Chip Enable (E) goes low.
The 64 bytes contained in the device can then be
accessed sequentially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20.
Square Wave Register
21 - 64.User RAM
The M41ST95Y/W clock continually monitors VCC
for an out-of tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automatically switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO , the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD (min) plus tREC (min). For more information
on Battery Storage Life refer to Application Note
AN1012.
SPI Bus Characteristics
The Serial Peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41ST95Y/W) devices.
The SCL input, which is generated by the microcontroller, is active only during address and data
transfer to any device on the SPI bus (see Figure
7., page 8).
The M41ST95Y/W can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2., page 10 and Figure 8., page 10).
There is one clock for each bit transferred. Address and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).
9/35
M41ST95Y*, M41ST95W
Signal Description
Serial Data Output (SDO). The output pin is
used to transfer data serially out of the Memory.
Data is shifted out on the falling edge of the serial
clock.
Serial Data Input (SDI). The input pin is used to
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each received this way. Input is latched on the rising edge
of the serial clock.
Serial Clock (SCL). The serial clock provides the
timing for the serial interface (as shown in Figure
9., page 11 and Figure 10., page 11). The W/R
Bit, addresses, or data are latched, from the input
pin, on the rising edge of the clock input. The output data on the SDO pin changes state after the
falling edge of the clock input.
The M41ST95Y/W can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2 and Figure 8).
Chip Enable (E). When E is high, the memory
device is deselected, and the SDO output pin is
held in its high impedance state.
After power-on, a high-to-low transition on E is required prior to the start of any operation.
Table 2. Function Table
Mode
E
SCL
SDI
SDO
Disable Reset
H
Input Disabled
Input Disabled
High Z
WRITE
L
Data Bit latch
High Z
X
Next data bit shift (1)
AI04630
READ
L
AI04631
Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 8. Data and Clock Timing
CPOL
CPHA
0
0
SCL
1
1
SCL
SDI
MSB
LSB
SDO
MSB
LSB
AI06368
10/35
M41ST95Y*, M41ST95W
Figure 9. Input Timing Requirements
tEHEL
E
tELCH
tCHEH
tEHCH
SCL
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
SDI
HIGH IMPEDANCE
SDO
LSB IN
tDLDH
tDHDL
AI04633
Figure 10. Output Timing Requirements
E
tCH
SCL
tCLQV
tCL
tEHQZ
tCLQX
LSB OUT
MSB OUT
SDO
tQLQH
tQHQL
SDI
ADDR. LSB IN
AI04634
Figure 11. WRITE Cycle Timing: RTC and External SRAM Control Signals
EX
tEXPD
tEXPD
ECON
AI03663
11/35
M41ST95Y*, M41ST95W
Table 3. AC Characteristics
Parameter(1)
Symbol
Min
Max
Unit
2
MHz
fSCL
Serial Clock Input Frequency
DC
tCH(2)
Clock High
200
tCHCL(3)
Clock Transition (Fall Time)
ns
1
µs
tCHDX
Serial Clock Input High to Input Data Transition
50
ns
tCHEH
Serial Clock Input High to Chip Enable High
200
ns
tCL(2)
Clock Low
200
ns
tCLCH(3)
Clock Transition (Rise Time)
tCLQV
Serial Clock Input Low to Output Valid
tCLQX
Serial Clock Input Low to Output Data Transition
1
µs
150
ns
0
ns
tDHDL(3)
Input Data Transition (Fall Time)
1
µs
tDLDH(3)
Input Data Transition (Rise Time)
1
µs
tDVCH
Input Data to Serial Clock Input High
40
ns
tEHCH
Chip Enable High to Serial Clock Input High
200
ns
tEHEL
Chip Enable High to Chip Enable Low
200
ns
tEHQZ(3)
tELCH
Chip Enable High to Output High-Z
250
Chip Enable Low to Serial Clock Input High
200
ns
ns
tQHQL(3)
Output Data Transition (Fall Time)
100
ns
tQLQH(3)
Output Data Transition (Rise Time)
100
ns
M41ST95Y
10
ns
M41ST95W
15
ns
tEXPD
EX to ECON Propagation Delay
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. tCH + tCL ≥ 1/fSCL
3. Value guaranteed by design, not 100% tested in production.
12/35
M41ST95Y*, M41ST95W
READ and WRITE Cycles
Address and data are shifted MSB first into the Serial Data Input (SDI) and out of the Serial Data
Output (SDO). Any data transfer considers the first
bit to define whether a READ or WRITE will occur.
This is followed by seven bits defining the address
to be read or written. Data is transferred out of the
SDO for a READ operation and into the SDI for a
WRITE operation. The address is always the second through the eighth bit written after the Enable
(E) pin goes low. If the first bit is a '1,' one or more
WRITE cycles will occur. If the first bit is a '0,' one
or more READ cycles will occur (see Figure 12
and Figure 13., page 14).
Data transfers can occur one byte at a time or in
multiple byte burst mode, during which the address pointer will be automatically incremented.
For a single byte transfer, one byte is read or written and then E is driven high. For a multiple byte
transfer all that is required is that E continue to remain low. Under this condition, the address pointer
will continue to increment as stated previously. Incrementing will continue until the device is deselected by taking E high. The address will wrap to
00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). Although the clock continues to maintain the correct time, this will prevent
updates of time and date during either a READ or
WRITE of these address locations by the user.
The update will resume either due to a deselect
condition or when the pointer increments to an
non-clock or RAM address (08h to 3Fh).
Note: This is true both in READ and WRITE mode.
Figure 12. READ Mode Sequence
E
0
1
3
2
5
4
7
6
8
9
12 13 14 15 16 17
22
SCL
7 BIT ADDRESS
W/R BIT
SDI
7
6
5
4
3
2
1
0
MSB
SDO
HIGH IMPEDANCE
DATA OUT
(BYTE 1)
7
MSB
6
5
4
3
2
DATA OUT
(BYTE 2)
1
0
7
6
5
4
3
2
1
0
MSB
AI04635
13/35
M41ST95Y*, M41ST95W
Figure 13. WRITE Mode Sequence
E
0
1
3
2
4
5
6
7
8
9
15
10
SCL
SDI
DATA BYTE
7 BIT ADDR
W/R BIT
7
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
SDO
HIGH IMPEDANCE
AI04636
Data Retention Mode
With valid VCC applied, the M41ST95Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST95Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when VCC falls between VPFD(max) and
VPFD(min). This is accomplished by internally inhibiting access to the clock registers. At this time,
the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner
by forcing ECON to a high level. This level is within
0.2 volts of the VBAT. ECON will remain at this level
as long as VCC remains at an out-of-tolerance condition. When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the SNAPHAT® battery, and
the clock registers and external SRAM are maintained from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100 µA of current to the attached memory with less than 0.3 volts drop under
this condition. On power up, when VCC returns to
a nominal value, write protection continues for
tREC by inhibiting ECON. The RST signal also remains active during this time (see Figure
21., page 28).
Note: Most low power SRAMs on the market today can be used with the M41ST95Y/W RTC SUPERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use.
14/35
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M41ST95Y/W
and SRAMs to be “Don’t Care” once VCC falls below VPFD(min). The SRAM should also guarantee
data retention down to VCC = 2.0 volts. The chip
enable access time must be sufficient to meet the
system needs with the chip enable output propagation delays included. If the SRAM includes a
second chip enable pin (E2), this pin should be
tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data retention current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST95Y/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT® of your choice
can then be divided by this current to determine
the amount of data retention available (see 20).
For a further more detailed review of lifetime calculations, please see Application Note AN1012.
M41ST95Y*, M41ST95W
CLOCK OPERATION
The eight byte clock register (see Table
4., page 16) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained
within the first four registers.
Note: The Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of
data during the READ.
Power-down Time-Stamp
When a power failure occurs, the Halt Update Bit
(HT) will automatically be set to a '1.' This will prevent the clock from updating the clock registers,
and will allow the user to read the exact time of the
power-down event. Resetting the HT Bit to a '0' will
allow the clock to update the clock registers with
the current time.
TIMEKEEPER ® Registers
The M41ST95Y/W offers 20 internal registers
which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data (see Table
4., page 16). These registers are memory locations which contain external (user accessible) and
internal copies of the data (usually referred to as
BiPORT™ TIMEKEEPER cells). The external copies are independent of internal functions except
that they are updated periodically by the simultaneous transfer of the incremented internal copy.
The internal divider (or clock) chain will be reset
upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be
halted whenever the clock addresses (00h to 07h)
are being written. The update will resume either
due to a deselect condition or when the pointer increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Registers store data in Binary format.
15/35
M41ST95Y*, M41ST95W
Table 4. TIMEKEEPER® Register Map
Addr
D7
00h
D6
D5
D4
D3
D2
0.1 Seconds
D1
D0
Function/Range
BCD Format
0.01 Seconds
10ths/100ths
of Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
0
10 Minutes
Minutes
Minutes
00-59
03h
CEB
CB
Hours (24 Hour Format)
Century/Hours
0-1/00-23
04h
TR
0
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 Hours
0
0
0
10 Date
0
Day of Week
10M
10 Years
08h
OUT
FT
S
09h
WDS
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
ABE
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
HT
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
AF
0
BL
0
0
0
0
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
0
0
0
0
SQW
BMB1
BMB0
Control
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
Keys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
16/35
Calibration
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
TR = tREC Bit
M41ST95Y*, M41ST95W
Calibrating the Clock
The M41ST95Y/W is driven by a quartz-controlled
oscillator with a nominal frequency of 32,768Hz.
Uncalibrated clock accuracy will not exceed ±35
ppm (parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm
at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 18., page 24). Therefore, the
M41ST95Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure
19., page 24. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration Bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register (8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST95Y/W may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration Byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop Bit (ST, D7 of 1h) is '0,' the Frequency Test Bit (FT, D6 of 8h) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of Ah) is '0,' and the Watchdog Steering Bit (WDS, D7 of 9h) is '1' or the
Watchdog Register (9h = 0) is reset.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor for proper operation. A 500 to 10kΩ resistor is recommended in order to control the rise time. The FT Bit is cleared
on power-down.
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be programmed to go off while the M41ST95Y/W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 5., page 18 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT/OUT pin.
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different address.
It should also be noted that if the last address written is the “Alarm Seconds,” the address pointer
will increment to the Flag address, causing this situation to occur.
17/35
M41ST95Y*, M41ST95W
To disable the alarm, write '0' to the Alarm Date
Register and to RPT1-5. The IRQ/FT/OUT output
is cleared by a READ to the Flags Register as
shown in Figure 14. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set.
The ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST95Y/W was in the deselect mode during power-up. Figure 15., page 19
illustrates the back-up mode alarm timing.
Figure 14. Alarm Interrupt Reset Waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT
AI03664
Table 5. Alarm Repeat Mode
18/35
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
M41ST95Y*, M41ST95W
Figure 15. Back-up Mode Alarm Waveforms
VCC
VPFD
VSO
tREC
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
HIGH-Z
HIGH-Z
AI03920
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second,
10 = 1 second, and 11 = 4 seconds. The amount
of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M41ST95Y/W sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by
reading the Flags Register (0Fh).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for tREC.
The Watchdog register and the AFE, ABE, SQWE,
and FT Bits will reset to a '0' at the end of a Watchdog time-out when the WDS Bit is set to a '1.'
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI), or
2. the microprocessor can perform a WRITE of
the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the
original time-out period can be written into the
Watchdog Register, effectively restarting the
count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function prevails and the Frequency Test function is denied.
19/35
M41ST95Y*, M41ST95W
Square Wave Output
The M41ST95Y/W offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish
the square wave output frequency. These frequencies are listed in Table 6. Once the selection
of the SQW frequency has been completed, the
SQW pin can be turned on and off under software
control with the Square Wave Enable Bit (SQWE)
located in Register 0Ah.
Table 6. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
Full-time F32k Square Wave Output
(Available only in 28-pin, 300mil SOIC (MX) package).
and can only be disabled by setting the ST Bit to
The M41ST95Y/W offers the user a special 32kHz
'1,' or while the device is in back-up. If not used,
square wave function which is always output on
the F32k pin should be disconnected and allowed
the F32k pin (Pin 21) as long as VCC ≥ VSO, and the
oscillator is running (ST Bit = '0'). This function is
to float.
available within four seconds of initial power-up
20/35
M41ST95Y*, M41ST95W
Power-on Reset
The M41ST95Y/W continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC after VCC passes VPFD (max).
The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control
rise time.
Reset Input (RSTIN1 and RSTIN2)
The M41ST95Y/W provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a
reset generated by a power cycle. Table 7 and Figure 16 illustrate the AC reset characteristics of this
function. Pulses shorter than tRLRH1 and tRLRH2
will not generate a reset condition. RSTIN1 and
RSTIN2 are each internally pulled up to VCC
through a 100kΩ resistor.
Figure 16. RSTIN1 and RSTIN2 Timing Waveforms
RSTIN1
tRLRH1
RSTIN2
tRLRH2
RST
(1)
tR1HRH
tR2HRH
AI03665
Note: 1. Open Drain Output
Table 7. Reset AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tRLRH1(2)
RSTIN1 Low to RSTIN1 High
200
ns
tRLRH2(3)
RSTIN2 Low to RSTIN2 High
100
ms
tR1HRH(4)
RSTIN1 High to RST High
96
98
ms
tR2HRH(4,5)
RSTIN2 High to RST High
96
98
ms
Note: 1.
2.
3.
4.
5.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
Pulse width less than 50ns will result in no RESET (for noise immunity).
Pulse width less than 20ms will result in no RESET (for noise immunity).
Programmable (see Table 8., page 23)
After crystal oscillator has started
21/35
M41ST95Y*, M41ST95W
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an internal reference voltage (1.25V). If PFI is less than
the power-fail threshold (VPFI), the Power-Fail
Output (PFO) will go low. This function is intended
for use as an under-voltage detector to signal a
failing power supply. Typically PFI is connected
through an external voltage divider (see Figure 17)
to either the unregulated DC input (if it is available)
or the regulated output of the VCC regulator. The
voltage divider can be set up such that the voltage
at PFI falls below VPFI several milliseconds before
the regulated VCC input to the M41ST95Y/W or the
microprocessor drops below the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI
for the write protect time (tREC), which is the time
from VPFD(max) until the inputs are recognized. At
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to VSS and PFO
left unconnected.
Figure 17. Power-Fail Comparator Hookup
VIN
VCC
M41ST95Y/W
Regulator
Unregulated
Voltage
VCC
VCC
VOUT
VCC
ECON
E
From MCU
EX
E
SDI
SCL
SDO
WDI
RST
To RST
RSTIN1
R1
RSTIN2
Pushbutton
Reset
SQW
To LED Display
PFO
To NMI
IRQ/FT/OUT
To INT
PFI
R2
VBAT
F32k
(1)
VSS
AI06373
Note: 1. Available only in 28-pin, 300mil SOIC (MX) package.
22/35
M41ST95Y*, M41ST95W
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Output Driver Pin
When the FT Bit, AFE Bit and Watchdog Register
are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ/FT/OUT pin will be driven low.
Note: The IRQ/FT/OUT pin is an open drain which
requires an external pull-up resistor.
Battery Low Warning
The M41ST95Y/W automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT® top
may be replaced while VCC applied to the device.
The M41ST95Y/W only monitors the battery when
a nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
tREC Bit
Bit D7 of Clock Register 04h contains the tREC Bit
(TR). tREC refers to the automatic continuation of
the deselect time after VCC reaches VPFD. This allows for a voltage setting time before WRITEs may
again be performed to the device after a powerdown condition. The tREC Bit will allow the user to
set the length of this deselect time as defined by
Table 8.
Preferred Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watchdog Register, TR, FT, AFE, ABE, and SQWE. The
following bits are set to a '1' state: OUT and HT
(see Table 9).
Table 8. tREC Definitions
tREC Bit (TR)
STOP Bit (ST)
0
tREC Time
Units
Min
Max
0
96
98(1)
ms
0
1
40
200
ms
1
X
50
2000
µs
Note: 1. Default Setting; after oscillator has started
Table 9. Default Values
Condition
Initial Power-up (Battery Attach
for SNAPHAT)(2)
Subsequent power-up (with
battery back-up)(3)
TR
ST
HT
Out
FT
AFE
ABE
SQWE
WATCHDOG
Register(1)
0
0
1
1
0
0
0
0
0
UC
UC
1
UC
0
0
0
0
0
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged.
23/35
M41ST95Y*, M41ST95W
Figure 18. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
∆F = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 19. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
24/35
M41ST95Y*, M41ST95W
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 10. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature (VCC Off, Oscillator Off)
VCC
Supply Voltage
TSLD
TSLD(1,2)
VIO
Lead Solder Temperature for 10 seconds
Lead Solder Temperature for 10 seconds
Input or Output Voltage
Value
Unit
–55 to 125
°C
M41ST95Y
–0.3 to 7
V
M41ST95W
–0.3 to 4.6
V
Lead-free lead finish(1)
260
°C
Standard (SnPb)
lead finish(2,3)
240
°C
260
°C
–0.3 to VCC+0.3
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. For SOH28 package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed
245°C for greater than 30 seconds).
2. For SOH28 package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
3. The SOX28 package has Lead-free (Pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240°C
(use same reflow profile as standard (SnPb) lead finish).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
25/35
M41ST95Y*, M41ST95W
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 11. DC and AC Measurement Conditions
Parameter
M41ST95Y
M41ST95W
VCC Supply Voltage
4.5 to 5.5V
2.7 to 3.6V
Ambient Operating Temperature
–40 to 85°C
–40 to 85°C
Load Capacitance (CL)
100pF
50pF
Input Rise and Fall Times
≤ 50ns
≤ 50ns
Input Pulse Voltages
0.2 to 0.8VCC
0.2 to 0.8VCC
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
0.3 to 0.7VCC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 20. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 12. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input Capacitance
7
pF
Output Capacitance
10
pF
Low-pass filter input time constant (SDI and SCL)
50
ns
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs are deselected.
26/35
M41ST95Y*, M41ST95W
Table 13. DC Characteristics
Sym
IBAT
(2)
Parameter
Battery Current OSC
ON
Battery Current OSC
OFF
Test
Condition(1)
M41ST95Y
Min
TA = 25°C,
VCC = 0V,
VBAT = 3V
M41ST95W
Typ
Max
400
550
Min
50
Unit
Typ
Max
400
550
50
nA
nA
ICC1
Supply Current
f = 2MHz
2
2
mA
ICC2
Supply Current
(Standby)
SCL, SDI =
VCC – 0.3V
1.4
1.4
mA
Input Leakage Current
0V ≤ VIN ≤
VCC
±1
±1
µA
25
nA
ILI(3)
Input Leakage Current
(PFI)
–25
2
25
–25
2
0V ≤ VIN ≤
VCC
±1
±1
µA
IOUT1(5) VOUT Current (Active)
VOUT1 >
VCC – 0.3V
175
100
mA
VOUT Current (Battery
Back-up)
VOUT2 >
VBAT – 0.3V
100
100
µA
ILO(4)
IOUT2
Output Leakage
Current
VIH
Input High Voltage
0.7VCC
VCC + 0.3
0.7VCC
VCC + 0.3
V
VIL
Input Low Voltage
–0.3
0.3VCC
–0.3
0.3VCC
V
VBAT
Battery Voltage
2.5
3.5(6)
2.5
3.5(6)
V
VOH
Output High Voltage(7)
IOH = –1.0mA
Power Supply Voltage
(Open Drain)
IRQ/FT/OUT,
RST
VOHB(8) VOH (Battery Back-up)
IOUT2 =
–1.0µA
3.0
2.4
3.0
2.4
V
5.5
2.5
2.9
3.5
2.5
2.9
3.6
V
3.5
V
Output Low Voltage
IOL = 3.0mA
0.4
0.4
V
VOL
Output Low Voltage
(Open Drain)(9)
IOL = 10mA
0.4
0.4
V
VPFD
Power Fail Deselect
VPFI
PFI Input Threshold
PFI Hysteresis
VSO
Battery Back-up
Switchover
VCC = 5V(Y)
VCC = 3V(W)
PFI Rising
4.20
4.40
4.50
2.55
2.60
2.70
V
1.225
1.250
1.275
1.225
1.250
1.275
V
20
70
20
70
mV
2.5
2.5
V
Note: 1.
2.
3.
4.
5.
6.
7.
8.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
Measured with VOUT and ECON open.
RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
Outputs Deselected.
External SRAM must match RTC SUPERVISOR chip VCC specification.
For rechargeable back-up, VBAT(max) may be considered VCC.
For PFO, F32k, and SQW pins (CMOS).
Conditioned output (ECON) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will reduce battery life.
9. For IRQ/FT/OUT, RST pins (Open Drain); if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when
VCC = 0V (during battery back-up mode).
27/35
M41ST95Y*, M41ST95W
Figure 21. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
tPD
tREC
PFO
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
ECON
AI03661
Table 14. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
tPFD
PFI to PFO Propagation Delay
tREC(4,5)
Power up Deselect Time
15
96
25
µs
98
ms
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until
200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. Programmable (see Table 8., page 23)
5. After crystal oscillator has started
28/35
M41ST95Y*, M41ST95W
PACKAGE MECHANICAL INFORMATION
Figure 22. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 15. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
CP
1.27
0.050
28
0.10
0.004
29/35
M41ST95Y*, M41ST95W
Figure 23. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
9.78
Max
0.3850
A1
6.73
7.24
0.2650
0.2850
A2
6.48
6.99
0.2551
0.2752
A3
30/35
Max
0.38
0.0150
B
0.46
0.56
0.0181
0.0220
D
21.21
21.84
0.8350
0.8598
E
14.22
14.99
0.5598
0.5902
eA
15.55
15.95
0.6122
0.6280
eB
3.20
3.61
0.1260
0.1421
L
2.03
2.29
0.0799
0.0902
M41ST95Y*, M41ST95W
Figure 24. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
10.54
Max
0.4150
A1
6.73
7.24
0.2650
0.2850
A2
6.48
6.99
0.2551
0.2752
A3
0.38
0.0150
B
0.46
0.56
0.0181
0.0220
D
21.21
21.84
0.8350
0.8598
E
14.22
14.99
0.5598
0.5902
eA
15.55
15.95
0.6122
0.6280
eB
3.20
3.61
0.1260
0.1421
L
2.03
2.29
0.0799
0.0902
31/35
M41ST95Y*, M41ST95W
Figure 25. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline
D
h x 45˚
1
14
C
E
15
H
28
A2
A
B
ddd
A1
e
A1
α
L
SO-E
Note: Drawing is not to scale.
Table 18. SOX28 – 28-lead Plastic Small, 300mils, Embedded Crystal, Package Mech. Data
millimeters
inches
Symbol
Typ
Min
Max
A
2.44
A1
Min
Max
2.69
0.096
0.106
0.15
0.31
0.006
0.012
A2
2.29
2.39
0.090
0.094
B
0.41
0.51
0.016
0.020
C
0.20
0.31
0.008
0.012
D
17.91
18.01
0.705
0.709
ddd
0.10
E
7.57
7.67
–
–
H
10.16
L
0.004
0.298
0.302
–
–
10.52
0.400
0.414
0.51
0.81
0.020
0.032
α
0°
8°
0°
8°
N
28
e
32/35
Typ
1.27
0.050
28
M41ST95Y*, M41ST95W
PART NUMBERING
Table 19. Ordering Information Scheme
Example:
M41ST
95Y
MH
6
Device Type
M41ST
Supply Voltage and Write Protect Voltage
95Y(1) = VCC = 4.5 to 5.5V; 4.20V ≤ VPFD ≤ 4.50V
95W = VCC = 2.7 to 3.6V; 2.55V ≤ VPFD ≤ 2.70V
Package
MH(1,2) = SOH28
MX(3) = SOX28
Temperature Range
6 = –40 to 85°C
Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)
E = Lead-free Package (ECO
PACK®), Tubes
F = Lead-free Package (ECO
PACK®), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For SOX28:
blank = Tubes
TR = Tape & Reel
Note: 1. Contact Local Sales Office
2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under the part number “M4TXXBR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 20).
3. The SOX28 package includes an embedded 32,768Hz crystal.
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 20. SNAPHAT Battery Table
Part Number
Description
Package
M4T28-BR12SH
Lithium Battery (48mAh) and Crystal SNAPHAT
SH
M4T32-BR12SH
Lithium Battery (120mAh) and Crystal SNAPHAT
SH
33/35
M41ST95Y*, M41ST95W
REVISION HISTORY
Table 21. Document Revision History
Date
Rev. #
Revision Details
February 2002
1.0
First draft
27-Mar-02
1.1
Change tREC Definition (Table 8)
01-Apr-02
1.2
Addition of new package option and inherent features
12-Apr-02
2.0
Document promoted
21-Jan-03
2.1
Add marketing note; (Figure 1); modify logic, signals (Figure 3; Table 1); modify block
diagram (Figure 6)
25-Feb-03
2.2
Update Definitions (Table 8); correct mechanical dimensions (Figure 25; Table 18)
20-Mar-03
3.0
Document promoted
27-Mar-03
3.1
Add marketing status (Table 19)
06-May-03
3.2
Update 32kHz information (Figure 3, 5, 6, 17; Table 1, 13, 14, 7)
15-Jun-04
4.0
Reformatted; update characteristics; added Lead-free information (Figure 5, 6, 18; Table 1,
4, 7, 8, 10, 13, 14, 19)
13-Sep-04
5.0
Update Maximum ratings (Table 10)
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SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI,
SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI,
SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, SPI, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,
Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,
Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,
Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Oscillator, Oscillator, Oscillator, Oscillator,
Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor,
Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write
Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect,
Write Protect, Write Protect, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Watchdog,
Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover,
Switchover, Switchover, Switchover, Switchover, Switchover, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail,
Power-fail, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM,
SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC,
SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 2.7V, 2.7V, 2.7V, 2.7V, 2.7V, 2.7V, 2.7V, 2.7V, 2.7V, 2.7V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V
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M41ST95Y*, M41ST95W
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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