STMICROELECTRONICS M68AF511AL55MC6T

M68AF511A
4 Mbit (512K x8), 5V Asynchronous SRAM
FEATURES SUMMARY
■ SUPPLY VOLTAGE: 4.5 to 5.5V
■
512K x 8 bits SRAM with OUTPUT ENABLE
■
EQUAL CYCLE and ACCESS TIMES: 55ns
■
LOW STANDBY CURRENT
■
■
LOW VCC DATA RETENTION: 2V
TRI-STATE COMMON I/O
■
LOW ACTIVE and STANDBY POWER
Figure 1. Packages
32
1
TSOP32 Type II (NC)
SO32 (MC)
October 2002
1/18
M68AF511A
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . .
Table 1. Signal Names . . . . . . . . . . . . . . . .
Figure 3. TSOP and SO Connections . . . . .
Figure 4. Block Diagram . . . . . . . . . . . . . . .
......................................
......................................
......................................
......................................
.....
.....
.....
.....
3
3
4
5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . 9
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Low V CC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . . . . 14
TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . . . . . 14
SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/18
M68AF511A
SUMMARY DESCRIPTION
The M68AF511A is a 4 Mbit (4,194,304 bit) CMOS
SRAM, organized as 524,288 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal address access and cycle times. It requires a single
4.5 to 5.5V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AF511A is available in a 32 lead TSOP
Type II and 32 lead SO packages.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
19
8
A0-A18
W
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Output
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
DQ0-DQ7
M68AF511A
E
G
VSS
AI03948C
3/18
M68AF511A
Figure 3. TSOP and SO Connections
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
8
9
16
32
M68AF511A
25
24
17
AI03949C
4/18
VCC
A15
A18
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
M68AF511A
Figure 4. Block Diagram
A18
ROW
DECODER
MEMORY
ARRAY
VCC
VSS
A8
DQ7
I/O CIRCUITS
COLUMN
DECODER
DQ0
A0
A7
E
W
G
AI05916
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1 sec may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
documents.
Table 2. Absolute Maximum Ratings
Symbol
Value
Unit
20
mA
Ambient Operating Temperature
–55 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VCC
Supply Voltage
–0.5 to 6.5
V
–0.5 to VCC +0.5
V
1
W
IO (1)
TA
VIO (2)
PD
Parameter
Output Current
Input or Output Voltage
Power Dissipation
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating VCC of 6.0V only.
5/18
M68AF511A
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M68AF511A
VCC Supply Voltage
4.5 to 5.5V
Range 1: Commercial
0 to 70°C
Ambient Operating Temperature
Range 6: Industrial
–40 to 85°C
Load Capacitance (CL)
100pF
Output Circuit Protection Resistance (R1)
3.0kΩ
Load Resistance (R2)
3.1kΩ
Input Rise and Fall Times
1ns/V
0 to VCC
Input Pulse Voltages
Input and Output Timing Ref. Voltages
VCC/2
Output Transition Timing Ref. Voltages
VRL = 0.3VCC; VRH = 0.7VCC
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage
R1
VCC
VCC/2
0V
DEVICE
UNDER
TEST
OUT
CL
Output Transition Timing Reference Voltage
VCC
0V
R2
0.7VCC
0.3VCC
AI05910
CL includes probe and 1 TTLcapacitance
AI05832
6/18
M68AF511A
Table 4. Capacitance
CIN
COUT
Test
Condition
Parameter(1,2)
Symbol
Input Capacitance on all pins (except DQ)
Output Capacitance
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Max
Unit
Note: 1. Sampled only, not 100% tested.
2. At TA = 25°C, f = 1MHz, VCC = 5.0V.
Table 5. DC Characteristics
Symbol
Parameter
Test Condition
Min
Typ
ICC1 (1,2)
Operating Supply Current
VCC = 5.5V,
f = 1/tAVAV, IOUT = 0mA
55
mA
ICC2 (3)
Operating Supply Current
VCC = 5.5V,
f = 1MHz, IOUT = 0mA
5
mA
ILI
Input Leakage Current
ILO (4)
Output Leakage Current
0V ≤ VIN ≤ VCC
–1
1
µA
0V ≤ VOUT ≤ VCC
–1
1
µA
10
µA
VCC = 5.5V, E ≥ VCC – 0.2V,
f=0
ISB
Standby Supply Current CMOS
VIH
Input High Voltage
2.2
VCC + 0.3
V
VIL
Input Low Voltage
–0.3
0.8
V
VOH
Output High Voltage
IOH = –1.0mA
VOL
Output Low Voltage
IOL = 2.1mA
Note: 1.
2.
3.
4.
5
2.4
V
0.4
V
Average AC current, cycling at tAVAV minimum.
E = VIL, VIN = V IH or VIL.
E ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ V CC – 0.2V.
Output disable.
7/18
M68AF511A
OPERATION
The M68AF511A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E = High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table (Table 6).
Table 6. Operating Modes
Operation
E
W
G
DQ0-DQ7
Power
Output disabled
VIL
X
VIH
Hi-Z
Active (ICC)
Read
VIL
VIH
VIL
Data Output
Active (ICC)
Write
VIL
VIL
X
Data Input
Active (ICC)
Deselect
VIH
X
X
Hi-Z
Standby (ISB)
Note: X = VIH or VIL.
Read Mode
The M68AF511A is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This provides access to data from eight of the 4,194,304
locations in the static memory array, specified by
the 19 address inputs. Valid data will be available
at the eight output pins within tAVQV after the last
stable address, providing G is Low and E is Low.
If Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t ELQV or tGLQV) rather than the
address. Data out may be indeterminate at tELQX
and tGLQX, but data lines will always be valid at
tAVQV.
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A18
VALID
tAVQV
DQ0-DQ7
tAXQX
DATA VALID
AI03034
Note: E = Low, G = Low, W = High.
8/18
M68AF511A
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV
A0-A18
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
VALID
DQ0-DQ7
AI05912
Note: Write Enable (W) = High.
Figure 9. Chip Enable Controlled, Standby Mode AC Waveforms
E
ICC
ISB
tPU
tPD
50%
AI03036
9/18
M68AF511A
Table 7. Read and Standby Mode AC Characteristics
M68AF511A
Symbol
Parameter
Unit
55
70
tAVAV
Read Cycle Time
Min
55
70
ns
tAVQV
Address Valid to Output Valid
Max
55
70
ns
tAXQX (1)
Data hold from Address change
Min
5
5
ns
tEHQZ (2,3)
Chip Enable High to Output Hi-Z
Max
20
25
ns
tELQV
Chip Enable Low to Output Valid
Max
55
70
ns
Chip Enable Low to Output Transition
Min
5
5
ns
tGHQZ (2,3)
Output Enable High to Output Hi-Z
Max
20
25
ns
tGLQV
Output Enable Low to Output Valid
Max
25
35
ns
Output Enable Low to Output Transition
Min
5
5
ns
tPD (4)
Chip Enable High to Power Down
Max
0
0
ns
tPU (4)
Chip Enable Low to Power Up
Min
55
70
ns
tELQX (1)
tGLQX (1)
Note: 1. Test conditions assume transition timig reference level = 0.3V CC or 0.7VCC.
2. At any given temperature and voltage condition, tEHQZ is less than t ELQX and tGHQZ is less than t GLQX for any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters
10/18
M68AF511A
Write Mode
The M68AF511A is in the Write mode whenever
the W and E pins are Low. Either the Chip Enable
input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. Write begins with the concurrence of Chip Enable being active with W low.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as tAVWL and tAVEH
respectively, and is determined by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E, or W.
if the Output is enabled (E = Low and G = Low),
then W will return the outputs to high impedance
within t WLQZ of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the
rising edge of E, whichever occurs first, and remain valid for tWHDX or tEHDX.
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A18
tAVWH
tWHAX
tELWH
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA
(1)
DATA INPUT
DATA (1)
tDVWH
AI05913
Note: 1. During this period DQ0-DQ7 are in output state and input signal should not be applied.
11/18
M68AF511A
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A18
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tWLEH
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI05914
Table 8. Write Mode AC Characteristics
M68AF511A
Symbol
Parameter
Unit
55
70
tAVAV
Write Cycle Time
Min
55
70
ns
tAVEH
Address Valid to Chip Enable High
Min
45
60
ns
tAVEL
Address Valid to Chip Enable Low
Min
0
0
ns
tAVWH
Address Valid to Write Enable High
Min
45
60
ns
tAVWL
Address Valid to Write Enable Low
Min
0
0
ns
tDVEH
Input Valid to Chip Enable High
Min
25
30
ns
tDVWH
Input Valid to Write Enable High
Min
25
30
ns
tEHAX
Chip Enable High to Address Transition
Min
0
0
ns
tEHDX
Chip Enable High to Input Transition
Min
0
0
ns
tELEH
Chip Enable Low to Chip Enable High
Min
45
60
ns
tELWH
Chip Enable Low to Write Enable High
Min
45
60
ns
tWHAX
Write Enable High to Address Transition
Min
0
0
ns
tWHDX
Write Enable High to Input Transition
Min
0
0
ns
tWHQX (1)
Write Enable High to Output Transition
Min
5
5
ns
tWLEH
Write Enable Low to Chip Enable High
Min
45
60
ns
Write Enable Low to Output Hi-Z
Max
20
25
ns
Write Enable Low to Write Enable High
Min
45
60
ns
tWLQZ (1,2)
tWLWH
Note: 1. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
2. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device.
12/18
M68AF511A
Figure 12. Low VCC Data Retention AC Waveforms.
DATA RETENTION MODE
5.5V
VCC
4.5V
VDR > 2.0V
tCDR
tR
E ≥ VDR – 0.2V
E
2.2V
AI05915
Table 9. Low V CC Data Retention Characteristics
Symbol
Parameter
ICCDR (1) Supply Current (Data Retention)
Test Condition
Min
VCC = 2V, E ≥ VCC – 0.2V, f = 0 (3)
Typ
Max
Unit
4.5
9
µA
tCDR (1,2)
Chip Deselected to Data
Retention Time
0
ns
tR (2)
Operation Recovery Time
tAVAV
ns
2
V
VDR (2)
Supply Voltage (Data Retention)
E ≥ VCC – 0.2V, f = 0
Note: 1. All other Inputs at V IH ≥ VCC –0.2V or VIL ≤ 0.2V.
2. Tested initially and after any design or process that may affect these parameteres. tAVAV is Read cycle time.
3. No input may exceed VCC +0.2V.
13/18
M68AF511A
PACKAGE MECHANICAL
Figure 13. TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Outline
D
N
E1
1
E
N/2
b
e
A2
A
C
A1
α
L
CP
TSOP-e
Note: Drawing is not to scale.
Table 10. TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.20
Max
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
b
0.30
0.52
0.012
0.020
C
0.12
0.21
0.005
0.008
CP
0.10
D
20.82
21.08
–
–
E
11.56
E1
0.004
0.820
0.830
–
–
11.96
0.455
0.471
10.03
10.29
0.395
0.405
L
0.40
0.60
0.016
0.024
α
0°
5°
0°
5°
N
32
e
14/18
Max
1.27
0.050
32
M68AF511A
Figure 14. SO32 - 32 lead Plastic Small Outline, Package Outline
D
16
1
E
17
E1
32
A
A2
B
A1
e
C
CP
L
L1
SO-C
Note: Drawing is not to scale.
Table 11. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
3.00
Max
0.118
A1
0.10
A2
2.57
2.82
0.101
0.111
B
0.36
0.51
0.014
0.020
C
0.15
0.30
0.006
0.012
D
20.14
20.75
0.793
0.817
E
11.18
11.43
0.440
0.450
E1
13.87
14.38
0.546
0.566
–
–
–
–
L
0.58
0.99
0.023
0.039
L1
1.19
1.60
0.047
0.063
e
CP
1.27
0.004
0.10
0.050
0.004
15/18
M68AF511A
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M68AF511
A
L
55 NC
1
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
F = 4.5V to 5.5V
Array Organization
511 = 4 Mbit (512K x8)
Option 1
A = 1 Chip Enable
Option 2
L = L-Die
M = M-Die
Speed Class
55 = 55ns
70 = 70 ns
Package
NC = TSOP32 Type II
MC = SO32
Operative Temperature
1 = 0 to 70 °C
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
16/18
M68AF511A
REVISION HISTORY
Table 13. Document Revision History
Date
Version
Revision Details
July 2001
-01
First Issue
08-Aug-2001
-02
SO32 Package added
55ns Speed class introduced
Industrial Temperature Range added (Range 6)
27-Sep-2001
-03
Typing error, Table 4, Note 2
18-Oct-2001
-04
SO32 Package Mechanical and Data added
29-Nov-2001
-05
Note Removed from Ordering Information Scheme
08-Jan-2002
-06
PDIP32 package added
Document fully revised
08-Feb-2002
-07
tELQX, tAXQX changed in Read and Standby Mode AC Characteristics Table (Table 7)
tDVEH, tDVWH, tWLWH changed in Write Mode AC Characteristics Table (Table 8)
25-Feb-2002
-08
PDIP32 package removed
Block Diagram clarified (Figure 4)
Absolute Maximum Ratings table clarified (Table 2)
Operating and AC Measurement Conditions table and figure clarified (Table 3, Figure 6)
DC Characteristics table clarified (Table 5)
Read and Standby Mode AC Characteristics table clarified (Table 7)
Write Mode AC Characteristics table clarified (Table 8)
03-Mar-2002
-09
Operating and AC Measurement Conditions table clarified (Table 3)
ICCDR Test Condition clarified (Table 9)
25-Mar-2002
-10
Read and Standby Mode AC Characteristics clarified (Table 7)
Low VCC Data Retention Characteristics clarified (Table 9)
18-Apr-2002
-11
Read and Standby Mode AC Characteristics (Table 7): tPD and tPU clarified
26-Apr-2002
-12
DC Characteristics Table clarified (Table 5)
Write Mode AC Characteristics Table clarified (Table 8)
17-May-2002
-13
ISB and ICCDR values clarified
02-Oct-2002
13.1
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 013 equals 13.0).
New part number added.
09-Oct-2002
13.2
Datasheet number simplified.
17/18
M68AF511A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
© 2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
18/18