M68Z128 5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable ■ ULTRA LOW DATA RETENTION CURRENT – 10nA (typical) – 2.0µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 128Kb x 8 VERY FAST SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55ns ■ LOW VCC DATA RETENTION: 2V ■ TRI-STATE COMMON I/O ■ LOW ACTIVE and STANDBY POWER ■ AUTOMATIC POWER-DOWN WHEN DESELECTED ■ INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS TSOP32 (N) 8 x 20mm Figure 1. Logic Diagram DESCRIPTION The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible. VCC 17 8 A0-A16 DQ0-DQ7 Table 1. Signal Names A0-A16 Address Inputs W DQ0-DQ7 Data Input/Output E1 E1 Chip Enable 1 E2 E2 Chip Enable 2 G G Output Enable W Write Enable VCC Supply Voltage VSS Ground NC Not Connected Internally March 2000 M68Z128 VSS AI00647 1/12 M68Z128 Table 2. Absolute Maximum Ratings (1) Symbol Parameter TA Ambient Operating Temperature TSTG Storage Temperature VIO (2) Input or Output Voltage Value Unit 0 to 70 °C –65 to 150 °C –0.3 to VCC + 0.3 V VCC Supply Voltage –0.3 to 7.0 V IO (3) Output Current 20 mA Power Dissipation 1 W PD Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Up to a maximum operating VCC of 5.5V only. 3. One output at a time, not to exceed 1 second duration. Figure 2. TSOP Connections A11 A9 A8 A13 W E2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 8 9 16 32 M68Z128 25 24 17 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 AI00657 This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z128 is available in TSOP32 (8 x 20mm) package. 2/12 READ MODE The M68Z128 is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and both Chip Enables (E1 and E2) are asserted. This provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low, E1 is Low and E2 is High. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, t E2HQX and t GLQX, but data lines will always be valid at tAVQV. WRITE MODE The M68Z128 is in the Write mode whenever the W and E1 pins are Low, with E2 High. Either the Chip Enable inputs (E1 and E2) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of both Chip Enables being active with W low. Therefore, address setup time is referenced to Write Enable and both Chip Enables as tAVWL , tAVE1L and t AVE2H respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E1, W, or the falling edge of E2. If the Output is enabled (E1 = Low, E2 = High and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVE1H before the rising edge of E1 or for tDVE2L before the M68Z128 Table 3. Operating Modes Operation E1 E2 W G DQ0-DQ7 Power Read VIL VIH VIH VIH Hi-Z Active Read VIL VIH VIH VIL Data Output Active Write VIL VIH VIL X Data Input Active Deselect VIH X X X Hi-Z Standby Deselect X VIL X X Hi-Z Standby Note: 1. X = VIH or VIL. Table 4. AC Measurement Conditions Figure 3. AC Testing Load Circuit Input Rise and Fall Times ≤ 15ns Input Pulse Voltages 0 to 3V 5.0V Input and Output Timing Ref. Voltages 1.5V Note: Output Hi-Z is defined as the point where data is no longer driven. 1800Ω falling edge of E2, whichever occurs first, and remain valid for tWHDX, tE1HDX or tE2LDX. OPERATIONAL MODE The M68Z128 has a Chip Enable power down feature which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E1 = High or E2 = Low). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, and E2 as summarized in the Operating Modes table. DEVICE UNDER TEST OUT 990Ω CL = 50pF or 5pF CL includes JIG capacitance AI00658B Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN COUT (2) Parameter Input Capacitance on all pins (except DQ) Output Capacitance Test Condition Min Max Unit VIN = 0V 9 pF VOUT = 0V 9 pF Note: 1. Sampled only, not 100% tested. 2. Outputs deselected. 3/12 M68Z128 Figure 4. Block Diagram VCC VSS A ROW DECODER (9) MEMORY ARRAY A CHIP ENABLE. DQ I/O CIRCUITS INPUT DATA CTRL (8) COLUMN DECODER DQ CHIP ENABLE. CHIP ENABLE (8) A A W E1 E2 G AI00665 Table 6. DC Characteristics (TA = 0 to 70°C; VCC = 5V ±10%) Symbol Parameter Test Condition ILI Input Leakage Current ILO Min Typ Max Unit 0V ≤ VIN ≤ VCC ±1 µA Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA ICC1 (1) Supply Current VCC = 5.5V, (-55) 30 70 mA ICC2 (2) Supply Current (Standby) TTL VCC = 5.5V, E1 = VIH or E2 = VIL, f =0 0.1 2 mA ICC3 (3) Supply Current (Standby) CMOS VCC = 5.5V, E1 ≥ VCC – 0.3V or E2 ≤ 0.3V, f = 0 0.4 20 µA VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = –1mA Note: 1. Average AC current, Outputs open, cycling at tAVAV minimum. 2. All other Inputs at V IL ≤ 0.8V or VIH ≥ 2.2V. 3. All other Inputs at V IL ≤ 0.3V or VIH ≥ VCC –0.3V. 4/12 2.4 V M68Z128 Table 7. Read and Standby Modes AC Characteristics (TA = 0 to 70°C; VCC = 5V ±10%) M68Z128 Symbol Parameter -55 Min tAVAV Read Cycle Time Unit Max 55 ns tAVQV (1) Address Valid to Output Valid 55 ns tE1LQV (1) Chip Enable 1 Low to Output Valid 55 ns tE2HQV (1) Chip Enable 2 High to Output Valid 55 ns tGLQV (1) Output Enable Low to Output Valid 20 ns tE1LQX (3) Chip Enable 1 Low to Output Transition 5 ns tE2HQX (3) Chip Enable 2 High to Output Transition 5 ns tGLQX (3) Output Enable Low to Output Transition 0 ns tE1HQZ (2,3) Chip Enable 1 High to Output Hi-Z 20 ns tE2LQZ (2,3) Chip Enable 2 Low to Output Hi-Z 20 ns tGHQZ (2,3) Output Enable High to Output Hi-Z 20 ns tAXQX (1) Address Transition to Output Transition 5 ns tPU Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 ns tPD Chip Enable 1 High or Chip Enable 2 Low to Power Down 55 ns Note: 1. CL = 100pF. 2. CL = 5pF. 3. At any given temperature and voltage condition, tEIHQZ + tEZHQZ is less than tEILQX and tEZLQX, tGHQZ is less than tGLQX for any given device. Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI01078 Note: E1 = Low, E2 = High, G = Low, W = High. 5/12 M68Z128 Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV VALID A0-A16 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ E2 tE2HQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI00805 Note: Write Enable (W) = High. Figure 7. Standby Mode AC Waveforms E1 E2 ICC1 ICC2 tPU tPD 50% AI00806B 6/12 M68Z128 Table 8. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 5V ±10%) M68Z128 Symbol Parameter -55 Min Unit Max tAVAV Write Cycle Time 55 ns tAVWL Address Valid to Write Enable Low 0 ns tAVWH Address Valid to Write Enable High 45 ns tAVE1H Address Valid to Chip Enable 1 High 45 ns tAVE2L Address Valid to Chip Enable 2 Low 45 ns tWLWH Write Enable Pulse Width 45 ns tWHAX Write Enable High to Address Transition 0 ns tWHDX Write Enable High to Input Transition 0 ns tWHQX (2) Write Enable High to Output Transition 5 ns tWLQZ (1,2) Write Enable Low to Output Hi-Z 20 ns tAVE1L Address Valid to Chip Enable 1 Low 0 ns tAVE2H Address Valid to Chip Enable 2 High 0 ns tE1LE1H Chip Enable 1 Low to Chip Enable 1 High 45 ns tE2HE2L Chip Enable 2 High to Chip Enable 2 Low 45 ns tE1HAX Chip Enable 1 High to Address Transition 0 ns tE2LAX Chip Enable 2 Low to Address Transition 0 ns tDVWH Input Valid to Write Enable High 25 ns tDVE1H Input Valid to Chip Enable 1 High 25 ns tDVE2L Input Valid to Chip Enable 2 Low 25 ns Note: 1. CL = 5pF. 2. At any given temperature and voltage condition, tWHQX is less than tWLQZ for any given device. 7/12 M68Z128 Figure 8. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI00807 Note: Output Enable (G) = Low. Figure 9. Chip Enable Controlled, Write AC Waveforms (1, 2) tAVAV A0-A16 VALID tAVE1H tAVE1L tE1LE1H tE1HAX E1 tAVE2L tAVE2H tE2HE2L tE2LAX E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L Note: 1. Output Enable (G) = High. 2. If E1 goes High or E2 goes Low simultaneously with W high, the output remains in a high-impedance state. 8/12 AI00808 M68Z128 Table 9. Low V CC Data Retention Characteristics (TA = 0 to 70°C) Symbol Parameter Test Condition Min Typ Max Unit ICCDR Supply Current (Data Retention) VCC = 3V, E1 ≥ VCC – 0.3V or E2 ≤ 0.3V, f = 0 0.01 2 µA VDR Supply Voltage (Data Retention) E1 ≥ VCC – 0.3V or E2 ≤ 0.3V, f = 0 2 V tCDR Chip Disable to Power Down E1 ≥ VCC – 0.3V or E2 ≤ 0.3V, f = 0 0 ns tER (1) Operation Recovery Time tAVAV ns Note: 1. See Figure 10 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time. Figure 10. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 5V VCC 3V VDR > 2.0V tCDR tER E1 ≥ VDR – 0.3V E1 2.2V E2 0.8V E2 ≤ 0.3V AI00659 9/12 M68Z128 Table 10. Ordering Information Scheme Example: M68Z128 -55 N 1 Device Type M68Z Speed -55 = 55ns Package N = TSOP32 (8 x 20mm) Temperature Range 1 = 0 to 70 °C For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 11. Revision History Date Revision Details May 1999 First Issue 03/20/00 TSOP32 Package Mechanical Data changed (Table 12) 10/12 M68Z128 Table 12. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data mm inch Symbol Typ Min Max A Typ Min 1.200 Max 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.950 1.050 0.0374 0.0413 B 0.150 0.270 0.0059 0.0106 C 0.100 0.210 0.0039 0.0083 D 19.800 20.200 0.7795 0.7953 D1 18.300 18.500 0.7205 0.7283 – – – – E 7.900 8.100 0.3110 0.3189 L 0.500 0.700 0.0197 0.0276 α 0° 5° 0° 5° e 0.500 CP 0.0197 0.100 N 0.0039 32 32 Figure 11. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a A1 α L Drawing is not to scale. 11/12 M68Z128 Information furnished is believed to be accurate and reliable. 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