M68AW127B 1Mbit (128K x8), 3.0V Asynchronous SRAM FEATURES SUMMARY ■ SUPPLY VOLTAGE: 2.7 to 3.6V ■ 128K x 8 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns ■ LOW STANDBY CURRENT ■ ■ LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O ■ LOW ACTIVE and STANDBY POWER Figure 1. Packages SO32 (MC) TSOP32 8 x 20 mm (N) TSOP32 8 x 13.4 mm (NK) August 2003 1/20 M68AW127B TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 12. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . 15 TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline. . . . . . . . . . . . . . . . . . . . . . . . 16 TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data . . . . . . . . . . . . . . . . 16 TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . 17 TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data . . . . . . . . . . . . . . 17 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 M68AW127B SUMMARY DESCRIPTION The M68AW127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW127B is available in SO32, TSOP32 8x20mm and TSOP32 8x13.4mm packages. Figure 2. Logic Diagram Table 1. Signal Names VCC 17 8 A0-A16 DQ0-DQ7 A0-A16 Address Inputs DQ0-DQ7 Data Input/Output E1 Chip Enable E2 Chip Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground W E1 M68AW127B E2 G VSS AI05972b 3/20 M68AW127B Figure 3. SO Connections NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 4. TSOP Connections 1 8 9 16 32 M68AW127B 25 24 17 AI05931b 4/20 VCC A15 E2 W A13 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 A11 A9 A8 A13 W E2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 8 9 16 32 M68AW127B 25 24 17 AI05973c G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 M68AW127B Figure 5. Block Diagram A16 ROW DECODER MEMORY ARRAY A7 DQ7 I/O CIRCUITS COLUMN DECODER DQ0 E1 Ex E2 A0 A6 W G AI05471 MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol IO (1) TA Parameter Output Current Value Unit 20 mA Ambient Operating Temperature –55 to 125 °C TSTG Storage Temperature –65 to 150 °C VCC Supply Voltage –0.3 to 4.6 V –0.5 to VCC +0.5 V 1 W VIO (2) PD Input or Output Voltage Power Dissipation Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 3.6V only. 5/20 M68AW127B DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M68AW127B VCC Supply Voltage 2.7 to 3.6V Range 1 0 to 70°C Range 6 –40 to 85°C Ambient Operating Temperature Load Capacitance (CL) 100pF Output Circuit Protection Resistance (R1) 3.0kΩ Load Resistance (R2) 3.1kΩ Input Rise and Fall Times 1ns/V 0 to VCC Input Pulse Voltages Input and Output Timing Ref. Voltages VCC/2 Output Transition Timing Ref. Voltages VRL = 0.3VCC; VRH = 0.7VCC Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit VCC I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST OUT CL Output Transition Timing Reference Voltage VCC 0V R2 0.7VCC 0.3VCC AI04831 CL includes JIG capacitance AI05814 6/20 M68AW127B Table 4. Capacitance CIN COUT Test Condition Parameter (1,2) Symbol Input Capacitance on all pins (except DQ) Output Capacitance Min Max Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1MHz, VCC = 3.0V. Table 5. DC Characteristics Symbol ICC1 (1,2) Parameter Supply Current Operating Supply Current ICC2 (3) Operating Supply Current (READ) Operating Supply Current (WRITE) ILI Input Leakage Current ILO (4) Output Leakage Current ISB Standby Supply Current CMOS VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage VOL Note: 1. 2. 3. 4. Output Low Voltage Test Condition VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA VCC = 3.6V, f = 1MHz, IOUT = 0mA VCC = 3.6V, f = 1MHz, IOUT = 0mA Min Typ Max Unit 70 6.0 15 mA 100 25 35 mA 2 mA 1.5 5 mA 10 15 mA 70 100 0V ≤ VIN ≤ VCC –1 1 µA 0V ≤ VOUT ≤ VCC –1 1 µA VCC = 3.6V, E1 ≥ VCC – 0.2V, E2 ≤ 0.2V, f = 0 IOH = –1mA IOL = 2.1mA 70 2.5 15 µA 100 0.3 10 µA 2.2 VCC + 0.3 V 70 –0.3 0.8 V 100 –0.3 0.6 V 70 2.4 V 100 2.2 V 0.4 V Average AC current, cycling at tAVAV minimum. E1 = VIL, E2 = VIH, VIN = VIH or VIL. E1 ≤ 0.2V or E2 ≥ VCC –0.2V, VIN ≤ 0.2V or VIN ≥ VCC –0.2V. Output disabled. 7/20 M68AW127B OPERATION The M68AW127B has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High), or Chip Select is asserted (E2 = Low). An Output Enable (G) signal provides a high-speed, tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E1 as summarized in the Operating Modes table (Table 6). Table 6. Operating Modes Operation E1 E2 W G DQ0-DQ7 Power Read VIL VIH VIH VIH Hi-Z Active (ICC) Read VIL VIH VIH VIL Data Output Active (ICC) Write VIL VIH VIL X Data Input Active (ICC) Deselect VIH X X X Hi-Z Standby (ISB) Deselect X VIL X X Hi-Z Standby (ISB) Note: X = VIH or VIL. Read Mode The M68AW127B is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, Chip Enable (E1) is asserted and Chip Select (E2) is de-asserted. This provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV. Figure 8. Address Controlled, Read Mode AC Waveforms tAVAV A0-A16 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI05474 Note: E1 = Low, E2 = High, G = Low, W = High. 8/20 M68AW127B Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV VALID A0-A16 tAVQV tAXQX tELQV tEHQZ E1 E2 tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI05476 Note: Write Enable (W) = High. Figure 10. Chip Enable Controlled, Standby Mode AC Waveforms E1 E2 ICC ISB tPU tPD 50% AI05477 9/20 M68AW127B Table 7. Read and Standby Mode AC Characteristics M68AW127B Symbol Parameter Unit 70 100 tAVAV Read Cycle Time Min 70 100 ns tAVQV Address Valid to Output Valid Max 70 100 ns tAXQX (1) Data hold from address change Min 5 15 ns tEHQZ (2,3) Chip Enable High to Output Hi-Z Max 25 30 ns tELQV Chip Enable Low to Output Valid Max 70 100 ns Chip Enable Low to Output Transition Min 5 10 ns tGHQZ (2,3) Output Enable High to Output Hi-Z Max 25 30 ns tGLQV Output Enable Low to Output Valid Max 35 50 ns Output Enable Low to Output Transition Min 5 5 ns tPD (4) Chip Enable or UB/LB High to Power Down Max 0 0 ns tPU (4) Chip Enable or UB/LB Low to Power Up Min 70 100 ns tELQX (1) tGLQX (2) Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters. 10/20 M68AW127B Write Mode The M68AW127B is in the Write mode whenever the W and E1 pins are Low and the E2 pin is High. Either the Chip Enable input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of E1 being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH, respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E1, or W. If the Output is enabled (E1 = Low, E2 = High and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1, whichever occurs first, and remain valid for tWHDX or tEHDX. Figure 11. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVWH tELWH tAVEL tWHAX E1 E2 tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI05478 11/20 M68AW127B Figure 12. Chip Enable Controlled, Write AC Waveforms tAVAV VALID A0-A16 tAVEH tAVEL tELEH tEHAX E1 E2 tAVWL tWLEH W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI05479 12/20 M68AW127B Table 8. Write Mode AC Characteristics M68AW127B Symbol Parameter Unit 70 100 tAVAV Write Cycle Time Min 70 100 ns tAVEH Address Valid to Chip Enable High Min 60 80 ns tAVEL Address valid to Chip Enable Low Min 0 0 ns tAVWH Address Valid to Write Enable High Min 60 80 ns tAVWL Address Valid to Write Enable Low Min 0 0 ns tDVEH Input Valid to Chip Enable High Min 30 40 ns tDVWH Input Valid to Write Enable High Min 30 40 ns tEHAX Chip Enable High to Address Transition Min 0 0 ns tEHDX Chip enable High to Input Transition Min 0 0 ns tELEH Chip Enable Low to Chip Enable High Min 60 80 ns tELWH Chip Enable Low to Write Enable High Min 60 80 ns tWHAX Write Enable High to Address Transition Min 0 0 ns tWHDX Write Enable High to Input Transition Min 0 0 ns tWHQX (1) Write Enable High to Output Transition Min 5 5 ns tWLEH Write Enable Low to Chip Enable High Min 60 70 ns Write Enable Low to Output Hi-Z Max 20 30 ns Write Enable Low to Write Enable High Min 60 70 ns tWLQZ (1,2) tWLWH Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 13/20 M68AW127B Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V (1) tCDR tR E1 ≥ VDR – 0.2V E1 AI05980 Note: 1. For 100ns speed class VDR ≥ 2.0V. Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V (1) tCDR tR E2 E2 ≤ 0.2V AI05957B Note: 1. For 100ns speed class VDR ≥ 2.0V. Table 9. Low VCC Data Retention Characteristics Symbol ICCDR (1) Parameter Supply Current (Data Retention) Test Condition VCC = 1.5V, E1 ≥ VCC –0.2V or E2 ≤ 0.2V, f = 0 Min VDR (1) Supply Voltage (Data Retention) E1 ≥ VCC –0.2V or E2 ≤ 0.2V, f = 0 4.5 µA 5 µA ns 70 tAVAV ns 100 5 ms 70 1.5 V 100 2.0 V Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V. 2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V. 14/20 Unit 70 0 Operation Recovery Time Max 100 Chip Deselected to Data tCDR (1,2) Retention Time tR (2) Typ M68AW127B PACKAGE MECHANICAL Figure 15. SO32 - 32 lead Plastic Small Outline, Package Outline D 16 1 E 17 E1 32 A A2 B A1 e C CP L L1 SO-C Note: Drawing is not to scale. Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 2.997 Max 0.118 A1 0.102 A2 2.565 2.819 0.101 0.111 b 0.356 0.508 0.014 0.020 c 0.152 0.305 0.006 0.012 D 20.142 20.752 0.793 0.817 E 11.176 11.430 0.440 0.450 E1 13.868 14.376 0.546 0.566 – – – – L 0.584 0.991 0.023 0.039 L1 1.194 1.600 0.047 0.063 e CP 1.270 0.004 0.10 0.050 0.004 15/20 M68AW127B Figure 16. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C A1 TSOP-a α L Note: Drawing is not to scale. Table 11. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.200 Max 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.950 1.050 0.0374 0.0413 B 0.170 0.250 0.0067 0.0098 C 0.100 0.210 0.0039 0.0083 CP 0.100 0.0039 D 19.800 20.200 0.7795 0.7953 D1 18.300 18.500 0.7205 0.7283 E 7.900 8.100 0.3110 0.3189 – – – – L 0.500 0.700 0.0197 0.0276 α 0° 5° 0° 5° N 32 e 16/20 Max 0.500 0.0197 32 M68AW127B Figure 17. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C A1 TSOP-a α L Note: Drawing is not to scale. Table 12. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.20 Max 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.91 1.05 0.0358 0.0413 0.0039 0.0083 B 0.22 C 0.0087 0.10 0.21 D 13.40 – – 0.5276 – – D1 11.80 – – 0.4646 – – E 8.00 – – 0.3150 – – e 0.50 – – 0.0197 – – L 0.40 0.60 0.0157 0.0236 α 0 5 0 5 N CP 32 32 0.10 0.0039 17/20 M68AW127B PART NUMBERING Table 13. Ordering Information Scheme Example: M68AW127 B L 70 N 6 T Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 127 = 1Mbit (128K x8) Option 1 B = 2 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 70 = 70ns 10 = 100ns Package MC = SO32 N = TSOP32 (8 x 20 mm) NK = TSOP32 (8 x 13.4 mm) Operative Temperature 1 = 0 to 70°C 6 = –40 to 85 °C Shipping T = Tape & Reel Packing For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 18/20 M68AW127B REVISION HISTORY Table 14. Document Revision History Date Version Revision Details January 2002 1.0 First Issue 09-May-2002 2.0 DC Characteristics table clarified (Table 5) E1 Controlled, Low VCC Data Retention AC Waveforms clarified (Figure 13) Low VCC Data Retention Characteristics table clarified (Table 9) Ordering Information Scheme clarified (Table 13) 01-Jul-2002 3.0 70ns speed class added SO32 and TSOP32 8x13.4mm package options added 11-Sep-2002 4.0 Commercial code clarified 02-Oct-2002 4.1 Title and header layout modified. 09-Oct-2002 4.2 Commercial code modified. 16-Apr-2003 4.3 Label corrected on “E2 Controlled, Low VCC Data Retention AC Waveforms” figure 21-Aug-2003 4.4 TSOP Package connections modified (Figure 5) 19/20 M68AW127B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 20/20