STMICROELECTRONICS ST10F167

ST10F167
16-BIT MCU WITH 128K BYTE FLASH MEMORY
PRELIMINARY DATASHEET
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Interrupt Controller
16
8
Port 6
8
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■
■
■
■
■
■
■
Port 5
16
BR G
BRG
Port 3
15
Port 7
Port 2
16
CAPCOM1
16
CAPCOM2
CAN
PWM
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OSC.
16
XRA M
SSC
■
PEC
ASC usart
■
W atchdog
16
GPT1
■
Internal
R AM
16
C PU-C ore
GPT2
■
32
10-Bit ADC
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16
Internal
FLASH
Memory
External Bus
Controller
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High Performance 16-bit CPU with 4-Stage
Pipeline
100 ns Instruction Cycle Time at 20MHz CPU
Clock
500 ns Multiplication (16 × 16 bit), 1 µs Division
(32 / 16 bit)
Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and
Operating Systems
Register-Based Design with Multiple Variable
Register Banks
Single-Cycle Context Switching Support
Clock Generation via on-chip PLL or via direct
clock input
Up to 16 MBytes Linear Address Space for
Code and Data
2K Bytes On-Chip Internal RAM (IRAM)
2K Bytes On-Chip Extension RAM (XRAM)
128K Bytes On-Chip FLASH memory
FLASH Memory organized into 4 banks
independently erasable
Programmable External Bus Characteristics for
Different Address Ranges
8-Bit or 16-Bit External Data Bus
Multiplexed or Demultiplexed External Address/
Data Buses
Five Programmable Chip-Select Signals
Hold- and Hold-Acknowledge Bus Arbitration
Support
1024 Bytes On-Chip Special Function Register
Area
Idle and Power Down Modes
8-Channel Interrupt-Driven Single-Cycle Data
Transfer Facilities via Peripheral Event
Controller (PEC)
16-Priority-Level Interrupt System with 56
Sources, Sample-Rate down to 50 ns
16-Channel 10-bit A/D Converter with 9.7µs
Conversion Time
Two 16-Channel Capture/Compare Units
Port 4 Port 1 Port 0
■
16
Port 8
8
8
4-Channel PWM Unit
Two Multi-Functional General Purpose Timer
Units with 5 Timers
Two
Serial
Channels
(Synchronous/
Asynchronous and High-Speed-Synchronous)
On-Chip CAN 2.0B Interface with 15 Message
Objects (Full-CAN/Basic-CAN)
Programmable Watchdog Timer
Up to 111 General Purpose I/O Lines, partly
with Selectable Input Thresholds and
Hysteresis
Supported by development tools: C-Compilers,
Macro-Assembler
Packages,
Emulators,
Evaluation
Boards,
HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers,
Programming Boards
On-Chip Bootstrap Loader
144-Pin PQFP Package
May 1997
This is preliminary information on a new product indevelopment or undergoing evaluation. Details are subject to change without notice.
1/69
1
Table of Contents
1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
PIN DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
Flash Memory Programming And Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
Flash Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3
Flash Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
CENTRAL PROCESSING UNIT (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
INTERRUPT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
CAPTURE/COMPARE (CAPCOM) UNITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10 GENERAL PURPOSE TIMER (GPT) UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11 PWM MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13 A/D CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
15 CAN-MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
17 INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
18 BOOTSTRAP LOADER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
19 SPECIAL FUNCTION REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
20 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2/62
2
20.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
20.2
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
20.3
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
20.4
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
20.5
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
20.5.1
Test Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
20.5.2
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
20.5.3
Direct Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
20.5.4
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
20.5.5
External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
20.5.6
Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . 50
20.5.7
Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
20.5.8
Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
20.5.9
CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
20.5.10 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
21 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
22 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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ST10F167
1
INTRODUCTION
The ST10F167 is a flash derivative of the
SGS-THOMSON ST10 family of full featured single-chip CMOS microcontrollers. It combines high
CPU performance with high peripheral functionali-
Figure 1.1
ty and enhanced IO-capabilities. It also provides
on-chip high-speed RAM and clock generation via
PLL.
Logic Symbol
VDD
VSS
XTAL1
Port 0
16-bit
XTAL2
RSTIN
RSTOUT
Port 1
16-bit
VAREF
Port 2
16-bit
VAGND
NMI
EA
READY
ALE
ST10F167
Port 3
15-bit
Port 4
8-bit
Port 6
8-bit
RD
WR/WRL
Port 5
16-bit
4/69
3
Port 7
8-bit
Port 8
8-bit
P6.0/CS0
P6.1/CS1
P6.2/CS2
P6.3/CS3
P6.4/CS4
P6.5/HOLD
P6.6/HLDA
P6.7/BREQ
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
VDD
VSS
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28I0
P7.5/CC29I0
P7.6/CC30I0
P7.7/CC31I0
P5.0AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
VSS
NMI
RSTOUT
RSTIN
VSS
XTAL1
XTAL2
VDD
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
VSS
VDD
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
POH.7/AD15
POH.6/AD14
POH.5/AD13
POH.4/AD12
POH.3/AD11
POH.2/AD10
POH.1/AD9
VSS
VDD
2
VAREF
VAGND
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
VSS
VDD
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
VSS
VDD
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IOEX2IN
P2.11/CC11IOEX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
VSS
VDD
ST10F167
PIN DATA
ST10F167
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
POH.0/AD8
POL.7/AD7
POL.6/AD6
POL.5/AD5
POL.4/AD4
POL.3/AD3
POL.2AD2
POL.A/AD1
POL.0/AD0
EA
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7/A23
P4.6/A22/CAN_T XD
P4.5/A21/CAN_R X D
P4.4/A20
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
VPP
VSS
VDD
P3.15/CLKOUT
P3.13/SCLK
P3.12/BHE/WRH
P3.11/RXD0
P3.10/TXD0
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
5/69
3
ST10F167
Table 2.1
Pin Definitions and Functions
Symbol
Pin
Number
Input (I)
Output
(O)
P6.0 – P6.7
1-8
I/O
1
...
5
6
7
8
O
...
O
I
O
O
9 - 16
I/O
9
...
16
I/O
...
I/O
19 - 26
I/O
19
...
22
23
...
26
O
...
O
I/O
...
I/O
P8.0 – P8.7
P7.0 –P7.7
6/69
3
Function
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state. Port 6 outputs
can be configured as push/pull or open drain drivers.
The following Port 6 pins also serve for alternate functions:
P6.0
CS0
Chip Select 0 Output
...
...
...
P6.4
CS4
Chip Select 4 Output
P6.5
HOLD
External Master Hold Request Input
P6.6
HLDA
Hold Acknowledge Output
P6.7
BREQ
Bus Request Output
Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state. Port 8 outputs
can be configured as push/pull or open drain drivers. The input
threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
P8.0
CC16IO
CAPCOM2: CC16 Cap.-In/Comp.Out
...
...
...
P8.7
CC23IO
CAPCOM2: CC23 Cap.-In/Comp.Out
Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state. Port 7 outputs
can be configured as push/pull or open drain drivers. The input
threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
P7.0
POUT0
PWM Channel 0 Output
...
...
...
P7.3
POUT3
PWM Channel 3 Output
P7.4
CC28IO
CAPCOM2: CC28 Cap.-In/Comp.Out
...
...
...
P7.7
CC31IO
CAPCOM2: CC31 Cap.-In/Comp.Out
ST10F167
Table 2.1
Symbol
P5.0-P5.15
P2.0-P2.15
Pin Definitions and Functions (cont’d)
Pin
Number
Input (I)
Output
(O)
27 – 36
39 – 44
I
I
39
40
41
42
43
44
I
I
I
I
I
I
47 – 54
57 - 64
I/O
47
...
54
57
I/O
...
I/O
I/O
I
...
I/O
I
I
...
64
Function
Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input
channels for the A/D converter, where P5.x equals ANx (Analog
input channel x), or they serve as timer inputs:
P5.10
T6EUD
GPT2 Timer T6 Ext.Up/Down Ctrl.Input
P5.11
T5EUD
GPT2 Timer T5 Ext.Up/Down Ctrl.Input
P5.12
T6IN
GPT2 Timer T6 Count Input
P5.13
T5IN
GPT2 Timer T5 Count Input
P5.14
T4EUD
GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.15
T2EUD
GPT1 Timer T2 Ext.Up/Down Ctrl.Input
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state. Port 2 outputs
can be configured as push/pull or open drain drivers. The input
threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
P2.0
CC0IO
CAPCOM: CC0 Cap.-In/Comp.Out
...
...
...
P2.7
CC7IO
CAPCOM: CC7 Cap.-In/Comp.Out
P2.8
CC8IO
CAPCOM: CC8 Cap.-In/Comp.Out,
EX0IN
Fast External Interrupt 0 Input
...
...
...
P2.15
CC15IO
CAPCOM: CC15 Cap.-In/Comp.Out,
EX7IN
Fast External Interrupt 7 Input
T7IN
CAPCOM2 Timer T7 Count Input
7/69
3
ST10F167
Table 2.1
Symbol
P3.0P3.13,
P3.15
P4.0 –P4.7
Pin Definitions and Functions (cont’d)
Pin
Number
Input (I)
Output
(O)
65 – 70,
73 – 80,
81
I/O
I/O
I/O
65
66
67
68
69
70
I
O
I
O
I
I
73
74
I
I
75
76
77
78
79
I/O
I/O
O
I/O
O
O
I/O
O
I/O
80
81
85 - 92
85
90
92
O
O
I
O
O
O
95
O
91
RD
8/69
3
Function
Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bitwise programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-impedance
state. Port 3 outputs can be configured as push/pull or open drain
drivers. The input threshold of Port 3 is selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
P3.0
T0IN
CAPCOM Timer T0 Count Input
P3.1
T6OUT
GPT2 Timer T6 Toggle Latch Output
P3.2
CAPIN
GPT2 Register CAPREL Capture Input
P3.3
T3OUT
GPT1 Timer T3 Toggle Latch Output
P3.4
T3EUD
GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.5
T4IN
GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P3.6
T3IN
GPT1 Timer T3 Count/Gate Input
P3.7
T2IN
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
P3.8
MRST
SSC Master-Rec./Slave-Transmit I/O
P3.9
MTSR
SSC Master-Transmit/Slave-Rec. O/I
P3.10
T×D0
ASC0 Clock/Data Output (Asyn./Syn.)
P3.11
R×D0
ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12
BHE
Ext. Memory High Byte Enable Signal,
WRH
Ext. Memory High Byte Write Strobe
P3.13
SCLK
SSC Master Clock Outp./Slave Cl. Inp.
P3.15
CLKOUT System Clock Output (=CPU Clock)
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
In case of an external bus configuration, Port 4 can be used to output the segment address lines:
P4.0
A16
Least Significant Segment Addr. Line
P4.5
A21
Segment Address Line,
CAN_RxD CAN Receive Data Input
P4.6
A22
Segment Address Line,
CAN_TxD CAN Transmit Data Output
P4.7
A23
Most Significant Segment Addr. Line
External Memory Read Strobe. RD is activated for every external
instruction or data read access.
ST10F167
Table 2.1
Pin Definitions and Functions (cont’d)
Pin
Number
Input (I)
Output
(O)
WR/WRL
96
O
READY
97
I
ALE
98
O
EA
99
I
Symbol
PORT0:
P0L.0P0L.7,
P0H.0P0H.7
I/O
100-107
108,
111-117
Function
External Memory Write Strobe. In WR-mode this pin is activated
for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
Ready Input. When the Ready function is enabled, a high level at
this pin during an external memory access will force the insertion
of memory cycle time waitstates until the pin returns to a low level.
Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed
bus modes.
External Access Enable pin. A low level at this pin during and after
Reset forces the ST10F167 to begin instruction execution out of
external memory. A high level forces execution out of the internal
Flash Memory.
PORT0 consists of the two 8-bit bidirectional I/O ports P0L and
P0H. It is bit-wise programmable for input or output via direction
bits. For a pin configured as input, the output driver is put into highimpedance state.
In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes
and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width:8-bit 16-bit
P0L.0 – P0L.7:D0 – D7D0 - D7
P0H.0 – P0H.7:I/O
D8 - D15
Multiplexed bus modes:
Data Path Width:8-bit 16-bit
P0L.0 – P0L.7:AD0 – AD7AD0 - AD7
P0H.0 – P0H.7:A8 - A15AD8 - AD15
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3
ST10F167
Table 2.1
Symbol
PORT1:
P1L.0 –
P1L.7,
P1H.0 P1H.7
Pin Definitions and Functions (cont’d)
Pin
Number
Input (I)
Output
(O)
I/O
118 –
125
128 –
135
Function
PORT1 consists of the two 8-bit bidirectional I/O ports P1L and
P1H. It is bit-wise programmable for input or output via direction
bits. For a pin configured as input, the output driver is put into highimpedance state. PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.
The following PORT1 pins also serve for alternate functions:
P1H.4
CC24IO
CAPCOM2: CC24 Capture Input
P1H.5
CC25IO
CAPCOM2: CC25 Capture Input
P1H.6
CC26IO
CAPCOM2: CC26 Capture Input
P1H.7
CC27IO
CAPCOM2: CC27 Capture Input
132
133
134
135
I
I
I
I
XTAL1
138
I
XTAL2
137
O
RSTIN
140
I
RSTOUT
141
O
NMI
142
I
VAREF
37
-
Reference voltage for the A/D converter.
VAGND
VPP
38
84
-
Reference ground for the A/D converter.
Flash programming voltage. This pin accepts the programming
voltage for the on-chip flash EPROM of the ST10F167.
10/69
3
XTAL1:
Input to the oscillator amplifier and input to the internal
clock generator
XTAL2:
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while
leaving XTAL2 unconnected. Minimum and maximum high/low
and rise/fall times specified in the AC Characteristics must be observed.
Reset Input with Schmitt-Trigger characteristics. A low level at this
pin for a specified duration while the oscillator is running resets the
ST10F167. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS.
Internal Reset Indication Output. This pin is set to a low level when
the part is executing, either a hardware, a software or a watchdog
timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this pin
causes the CPU to vector to the NMI trap routine. When the
PWRDN (power down) instruction is executed, the NMI pin must
be low in order to force the ST10F167 to go into power down
mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
ST10F167
Table 2.1
Symbol
VDD
VSS
Pin Definitions and Functions (cont’d)
Pin
Number
Input (I)
Output
(O)
Function
46, 82,
136
-
Digital Supply Voltage for internal circuitry:
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode
17, 56,
72, 93,
109,126,
144
45, 83,
139
-
Digital Supply Voltage for port drivers:
+ 5 V during normal operation and idle mode
-
Digital Ground for internal circuitry.
18, 55,
71, 94,
110,127,
143
-
Digital Ground for port drivers.
11/69
3
ST10F167
3
FUNCTIONAL DESCRIPTION
The architecture of the ST10F167 combines the
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The following block diagram gives an overview of the dif-
Figure 3.1
ferent on-chip components and of the advanced,
high bandwidth internal bus structure of the
ST10F167.
Block Diagram
16
Internal
FLASH
Memory
32
16
Internal
RAM
CPU-Core
16
Watchdog
16
XRAM
PEC
OSC.
Interrupt Controller
16
CAN
Module
8
8
12/69
3
T2
T3
T4
ASC
(USART)
SSC
CAPCOM CAPCOM
2
1
PWM
T7
T8
T0
T1
...
...
16
GPT2
T5
T6
...
Port 6
GPT1
Port 2
Port 0
Ext.
Bus
Controller
Port 1
16
10-Bit
ADC
Port 4
16
Port 5
16
BRG
BRG
Port 3
15
Port 7
Port 8
8
8
VR02060C
ST10F167
4
MEMORY ORGANIZATION
The memory space of the ST10F167 is configured
in a Von-Neumann architecture. Code memory,
data memory, registers and I/O ports are organized within the same linear address space which
includes 16 MBytes. The entire memory space can
be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally
been made directly bit addressable.
The ST10F167 provides 128KBytes of on-chip
flash memory.
2 KBytes of on-chip Internal RAM are provided as
a storage for user defined variables, for the system
stack, general purpose register banks and even
for code. A register bank can consist of up to 16
wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
5
1024 bytes (2 * 512 bytes) of the address space
are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are
wordwide registers which are used for controlling
and monitoring functions of the different on-chip
units. Unused SFR addresses are reserved for
other/future members of the ST10 family.
2 KBytes of on-chip Extension RAM (XRAM) are
provided to store user data, user stacks or code.
The XRAM is accessed like external memory and
cannot be used for the system stack or register
banks, and is not bit-addressable. The XRAM allows 16-bit accesses with maximum speed.
In order to meet the needs of designs where more
memory is required than is provided on chip, up to
16 MBytes of external RAM and/or ROM can be
connected to the microcontroller.
EXTERNAL BUS CONTROLLER
All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory
access modes, which are as follows:
•
16-/18-/20-/24-bit Addresses, 16-bit Data,
Demultiplexed
•
16-/18-/20-/24-bit Addresses, 16-bit Data,
Multiplexed
•
16-/18-/20-/24-bit Addresses, 8-bit Data,
Multiplexed
•
16-/18-/20-/24-bit Addresses, 8-bit Data,
Demultiplexed
In the demultiplexed bus modes, addresses are
output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.
Important timing characteristics of the external bus
interface (Memory Cycle Time, Memory Tri-State
Time, Length of ALE and Read Write Delay) have
been made programmable. This gives the choice
of a wide range of different types of memories and
external peripherals. In addition, different address
ranges may be accessed with different bus characteristics. Up to 5 external CS signals (4 windows
plus default) can be generated in order to save external glue logic. Access to very slow memories is
supported via a particular ‘Ready’ function. A
HOLD/HLDA protocol is available for bus arbitration.
For applications which require less than 16
MBytes of external memory space, this address
space can be restricted to 1 MByte, 256 KByte or
to 64 KByte. In this case Port 4 outputs four, two or
no address lines. If an address space of 16
MBytes is used, it outputs all 8 address lines.
13/69
3
ST10F167
6
FLASH MEMORY
The ST10F167 provides 128KBytes of on-chip,
electrically erasable and re-programmable Flash
EPROM. The flash memory is organized in 32 bit
wide blocks. This allows double word instructions
to be fetched in one machine cycle. The flash
memory can be used for both code and data storage. The flash memory is organised into four
banks of sizes 8K, 24K, 48K and 48Kbytes (table
6.1). Each of these banks can be erased independently. This prevents unnecessary re-programming of the whole flash memory when only a
partial re-programming is required.
Table 6.1
FLASH Memory Bank Organisation
Bank
Addresses (Segment 0)
Size (bytes)
000000h to 07FFFh and 018000h to 01BFFFh
01C000h to 027FFFh
028000h to 02DFFFh
02E000h to 02FFFFh
0
1
2
3
6.1
The first 32K bytes of the FLASH memory are located in segment 0 (0h to 007FFFh) during reset,
and include the reset and interrupt vectors. The
rest of the FLASH memory is mapped in segments
1 and 2 (018000h to 02FFFFh). For flexibility, the
first 32K bytes of the FLASH memory may be remapped to segment 1 (010000h to 017FFFh) during
initialization. This allows the interrupt vectors to be
programmed from the external memory, while retaining the common routines and constants that
are programmed into the FLASH memory.
48K
48K
24K
8K
Flash Memory Programming And Erasure
The FLASH memory is programmed using the
PRESTO F Program Write algorithm. Erasure of
the FLASH memory is performed in the program
mode using the PRESTO F Erase algorithm.
tion is indicated by a flag. A second flag indicates
that the V PP voltage was correct for the whole programming cycle. This guarantees that a good
write/erase operation has been carried out.
Timing of the Write/Erase cycles is automatically
generated by a programmable timer and comple-
The FLASH parameters are detailed below.
Table 6.2
Flash Parameters
Parameter
Units
Min
Typical
Max
Word Programming Time
µsec
12.8
12.8
1250
0.5
1000
30
Bank Erasing Time
Endurance
Flash Vpp
14/69
3
sec
cycles
volts
11.4
12.6
ST10F167
6.2
Flash Control Register (FCR)
In the standard operation mode, the FLASH memory can be accessed in the same way as the normal mask-programmable on-chip ROM. All, appropriate, direct and indirect addressing modes can
be used for reading the FLASH memory.
All programming or erase operations are controlled via a 16-bit register, the FCR. The FCR is not
an SFR or GPR. To prevent inadvertent writing to
the FLASH memory, the FCR is locked and inactive during the standard operation mode. The
FLASH memory writing mode must be entered,
before a valid access to the FCR is provided. This
is done via a special key code instruction sequence.
The FCR is virtually mapped into the active address space of the Flash memory. It can only be
accessed with direct 16-bit (mem) addressing
modes. Since the FCR is neither byte, nor bit-addressable, only word operand instructions can be
used for FCR accesses. By default, the FCR can
be accessed with any even address from 000000h
to 07FFFEh and 018000h to 02FFFEh. If the first
32K byte Block of the FLASH memory is mapped
to segment 1, the corresponding even FCR addresses are 010000h to 017FFEh. Note that DPP
referencing and DPP contents must be considered
for FCR accesses. If an FCR access is attempted
via an odd address, an illegal operand access
hardware trap will occur.
FCR
Flash Control Register
Reset Condition: 0000h (Read)
b15 = FWMSET: Flash Writing Mode Set. This bit
is set to ”1” automatically once the Flash writing
mode is entered. To exit from the Flash writing
mode, FWMSET must be set to ”0”. Since only
word values can be written to FCR, care must be
taken that FWMSET is not cleared inadvertently.
Therefore, for any command written to FCR (except for the return to the Flash standard mode),
FWMSET must be set to ”1”. Reset condition of
FWMSET is ”0”.
b14-b10 = Reserved: these bits are reserved for
future development, they must be written to ”0”.
b9-b8 = BE0,1: Bank erase select. These bits select the Flash memory bank to be erased. The
physical addresses of bank 0 depends on the
which Flash memory map has been chosen. In
Flash operating modes, other than the erasing
mode, these bits are not significant. At reset BE1,0
are set to ”00”.
b7 = WDWW: Word/double word write. This bit determines the word width used for programming operations: 16-bit (WDWW = 0) or 32-bit (WDWW =
”1”). In Flash operation modes, other than the programming mode, this bit is not significant. At reset,
WDWW is set to “0”.
b6-b5 = CKCTL0,1: Flash Timer Clock Control.
These two bits control the width (TPRG) of the programming or erase pulses applied to the Flash
memory cells during the operation. TPRG varies in
an inverse ratio to the clock frequency. To avoid
putting the Flash memory under critical stress conditions, the width of one single programming or
erase pulse and the programming or erase time,
must not exceed defined values. Thus the maximum number of programming or erase attempts,
depends on the system clock frequency.
RESET state: 00.
b4 = VPPRIV: VPP Revelation bit. This read-only bit
reflects the state of the VPP voltage in the Flash
writing mode. If VPPRIV is set to ”0”, this indicates
that VPP is below the threshold necessary for reliable programming. The normal reaction to this indication is to check the VPP power supply and to then
repeat the intended operation. If the VPP voltage is
above a sufficient margin, VPPRIV will be set to
”1”. The reset state of the VPPRIV bit depends on
the state of the external VPP voltage at the VPP pin.
15/69
3
ST10F167
b3 = FCVPP: Flash VPP control bit. This read-only
bit indicates that the VPP voltage fell below the valid threshold value during a Flash programming or
erase operation. If FCVPP is set to ”1” after such
an operation has finished, it can mean that the operation was not successful. The VPP power supply
should be checked and the operation repeated. If
FCVPP is set to ”0”, no critical discontinuity in VPP
occurred. At reset FCVPP is set to ”0”.
b2 = FBUSY: Flash busy bit. This read-only bit indicates that a Flash programming or erase operation is in progress. FBUSY is set to ”1” by hardware, as soon as the programming or erase command is given. At reset FBUSY is set to ”0”. Note
that this bit position is also occupied by the writeonly bit RPROT.
b2 = RPROT: Protection enable bit. This bit set at
1, anded with the OTP protection bit, disables any
access to the Flash, by instructions fetched from
the external memory space, or from the internal
RAM. This write-only bit, is only significant if the
general Flash memory protection is enabled. If the
protection is enabled, the setting of RPROT determines whether the Flash protection is active
(RPROT=”1”) or inactive (RPROT=”0”). RPROT is
the only FCR bit which can be modified even in the
Flash standard operation mode, but only by an in-
6.3
3
b1 = FEE: Flash erase/program selection. This bit
selects the Flash write operation to be performed:
erase (FEE=”1”) or programming (FEE=”0”). Together with bits FWE and FWMSET, bit FEE determined the operation mode of the Flash memory.
Note that setting bits FWE and FEE causes the
corresponding Flash operation mode to be selected but does not launch the execution of the selected operation. If bit FWE was set to ”0”, the setting
of FEE is insignificant. At reset, FEE is set to ”0”.
b0 = FWE: Flash write/read enable. This bit determines whether FLASH write operations are enabled (FWE=1) or disabled (FWE=0). By definition,
a FLASH write operation can be either programming or erasure. Together with bits FEE and
FWMSET, bit FWE determines the operation
mode of the Flash memory. Note that setting bits
FWE and FEE causes the corresponding Flash
operation mode to be selected but does not launch
the execution of the selected operation. If bit FWE
was set to ”1”, any read access on a Flash memory location means a particular program-verify or
erase-verify read operation. Flash write operations
are disabled at reset.
Flash Memory Security
Security and reliability have been enhanced by
built-in features: a key code sequence is used to
enter the Write/Erase mode preventing false write
cycles, a programmable option (set by the programming board) prevents access to the FLASH
memory from the internal RAM or from External
16/69
struction executed from the Flash memory itself.
At reset, RPROT is set to ”1”. Note that this bit position is also occupied by the read-only bit FBUSY.
Memory. If the security option is set, the FLASH
memory can only be accessed from a program
within the FLASH memory area. This protection
can only be disabled by instructions executed from
the FLASH memory.
ST10F167
Figure 6.1
PRESTO F Write Algorithm
=0
PCOUNT=PNmax?
PCOUNT=PCOUNT+1
VR02057A
17/69
3
ST10F167
Figure 6.2
PRESTO F Erase Algorithm
=0
PCOUNT=ENmax?
PCOUNT=PCOUNT+1
VR02057B
18/69
3
ST10F167
7
CENTRAL PROCESSING UNIT (CPU)
Figure 7.1
CPU Block Diagram
CPU
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
FLASH
ROM
32
MDH
MLD
16
R15
Internal
RAM
2KByte
Mul./Div.-HW
Bit-Mask Gen.
General
4-Stage
Pipeline
ALU
16-Bit
PSW
Purpose
Registers
R15
Barrel-Shift
SYSCON
Context Ptr
R0
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSE L 1
ADDRSE L 2
ADDRSE L 3
ADDRSE L 4
Data Pg. Ptrs
Code Seg. Ptr.
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. has been added for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the
ST10F167’s instructions can be executed in one
machine cycle. This requires 100ns at 20MHz
CPU clock. For example, shift and rotate instructions are always processed during one machine
cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized for speed: branches in 2 cycles, a 16 × 16
bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. The ‘Jump Cache’ pipeline optimization, reduces the execution time of repeatedly
performed jumps in a loop, from 2 cycles to 1 cycle.
16
R0
The CPU includes an actual register context. This
consists of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area.
A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a
register bank may overlap others.
A system stack of up to 2048 bytes is provided as
a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN,
are implicitly compared against the stack pointer
value upon each stack access for the detection of
a stack overflow or underflow.
19/69
3
ST10F167
An efficient instruction set allows maximum use of
the CPU. The instruction set is classified into the
following groups:
•
Arithmetic Instructions
•
Logical Instructions
•
Boolean Bit Manipulation Instructions
•
Compare and Loop Control Instructions
•
Shift and Rotate Instructions
•
Prioritize Instruction
8
The architecture of the ST10F167 supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In a standard interrupt service, program execution
is suspended and a branch to the interrupt vector
table is performed. For a PEC service, just one cycle is ‘stolen’ from the current CPU activity. A PEC
service is a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter
is decremented for each PEC service, except for
the continuous transfer mode. When this counter
reaches zero, a standard interrupt is performed to
the corresponding source related vector location.
PEC services are suited to, for example, the transmission or reception of blocks of data. The
3
Data Movement Instructions
•
System Stack Instructions
•
Jump and Call Instructions
•
Return Instructions
•
System Control Instructions
•
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes.
Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes exist.
INTERRUPT SYSTEM
With an interrupt response time from 250ns to
600ns (in the case of internal program execution),
the ST10F167 reacts quickly to the occurrence of
non-deterministic events
20/69
•
ST10F167 has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and
an interrupt priority bitfield, exists for each of the
possible interrupt sources. Via its related register,
each source can be programmed to one of sixteen
interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request.
For the standard interrupt processing, each of the
possible interrupt sources has a dedicated vector
location.
Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the
‘TRAP’ instruction in combination with an individual trap (interrupt) number.
Table 8.1 shows all of the possible ST10F167 interrupt sources and the corresponding hardwarerelated interrupt flags, vectors, vector locations
and trap (interrupt) numbers
ST10F167
Table 8.1
Interrupt Sources, Flags, Vector and Trap Numbers
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0
CAPCOM Register 1
CC0IR
CC1IR
CC0IE
CC1IE
CC0INT
CC1INT
00’0040h
00’0044h
10h
11h
CAPCOM Register 2
CC2IR
CC2IE
CC2INT
00’0048h
12h
CAPCOM Register 3
CC3IR
CC3IE
CC3INT
00’004Ch
13h
CAPCOM Register 4
CAPCOM Register 5
CC4IR
CC5IR
CC4IE
CC5IE
CC4INT
CC5INT
00’0050h
00’0054h
14h
15h
CAPCOM Register 6
CAPCOM Register 7
CC6IR
CC7IR
CC6IE
CC7IE
CC6INT
CC7INT
00’0058h
00’005Ch
16h
17h
CAPCOM Register 8
CC8IR
CC8IE
CC8INT
00’0060h
18h
CAPCOM Register 9
CC9IR
CC9IE
CC9INT
00’0064h
19h
CAPCOM Register 10
CAPCOM Register 11
CC10IR
CC11IR
CC10IE
CC11IE
CC10INT
CC11INT
00’0068h
00’006Ch
1Ah
1Bh
CAPCOM Register 12
CAPCOM Register 13
CC12IR
CC13IR
CC12IE
CC13IE
CC12INT
CC13INT
00’0070h
00’0074h
1Ch
1Dh
CAPCOM Register 14
CC14IR
CC14IE
CC14INT
00’0078h
1Eh
CAPCOM Register 15
CC15IR
CC15IE
CC15INT
00’007Ch
1Fh
CAPCOM Register 16
CAPCOM Register 17
CC16IR
CC17IR
CC16IE
CC17IE
CC16INT
CC17INT
00’00C0h
00’00C4h
30h
31h
CAPCOM Register 18
CAPCOM Register 19
CC18IR
CC19IR
CC18IE
CC19IE
CC18INT
CC19INT
00’00C8h
00’00CCh
32h
33h
CAPCOM Register 20
CC20IR
CC20IE
CC20INT
00’00D0h
34h
CAPCOM Register 21
CC21IR
CC21IE
CC21INT
00’00D4h
35h
CAPCOM Register 22
CAPCOM Register 23
CC22IR
CC23IR
CC22IE
CC23IE
CC22INT
CC23INT
00’00D8h
00’00DCh
36h
37h
CAPCOM Register 24
CAPCOM Register 25
CC24IR
CC25IR
CC24IE
CC25IE
CC24INT
CC25INT
00’00E0h
00’00E4h
38h
39h
CAPCOM Register 26
CC26IR
CC26IE
CC26INT
00’00E8h
3Ah
CAPCOM Register 27
CC27IR
CC27IE
CC27INT
00’00ECh
3Bh
CAPCOM Register 28
CAPCOM Register 29
CC28IR
CC29IR
CC28IE
CC29IE
CC28INT
CC29INT
00’00E0h
00’0110h
3Ch
44h
CAPCOM Register 30
CAPCOM Register 31
CC30IR
CC31IR
CC30IE
CC31IE
CC30INT
CC31INT
00’0114h
00’0118h
45h
46h
CAPCOM Timer 0
T0IR
T0IE
T0INT
00’0080h
20h
CAPCOM Timer 1
T1IR
T1IE
T1INT
00’0084h
21h
CAPCOM Timer 7
CAPCOM Timer 8
T7IR
T8IR
T7IE
T8IE
T7INT
T8INT
00’00F4h
00’00F8h
3Dh
3Eh
21/69
3
ST10F167
Table 8.1
Interrupt Sources, Flags, Vector and Trap Numbers (cont’d)
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
GPT1 Timer 2
GPT1 Timer 3
T2IR
T3IR
T2IE
T3IE
T2INT
T3INT
00’0088h
00’008Ch
22h
23h
GPT1 Timer 4
GPT2 Timer 5
T4IR
T5IR
T4IE
T5IE
T4INT
T5INT
00’0090h
00’0094h
24h
25h
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098h
26h
GPT2 CAPREL Register
CRIR
CRIE
CRINT
00’009Ch
27h
A/D Conversion Complete
A/D Overrun Error
ADCIR
ADEIR
ADCIE
ADEIE
ADCINT
ADEINT
00’00A0h
00’00A4h
28h
29h
ASC0 Transmit
ASC0 Transmit Buffer
S0TIR
S0TBIR
S0TIE
S0TBIE
S0TINT
S0TBINT
00’00A8h
00’011Ch
2Ah
47h
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACh
2Bh
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0h
2Ch
SSC Transmit
SSC Receive
SCTIR
SCRIR
SCTIE
SCRIE
SCTINT
SCRINT
00’00B4h
00’00B8h
2Dh
2Eh
SSC Error
PWM Channel 0...3
SCEIR
PWMIR
SCEIE
PWMIE
SCEINT
PWMINT
00’00BCh
00’00FCh
2Fh
3Fh
CAN Interface
XP0IR
XP0IE
XP0INT
00’0100h
40h
X-Peripheral Node
XP1IR
XP1IE
XP1INT
00’0104h
41h
X-Peripheral Node
PLL Unlock
XP2IR
XP3IR
XP2IE
XP3IE
XP2INT
XP3INT
00’0108h
00’010Ch
42h
43h
Note: Two X-Peripheral nodes can accept interrupt requests from integrated X-Bus peripherals. Nodes, where no XPeripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
The ST10F167 provides an excellent mechanism
to identify and to process exceptions or error conditions that arise during run-time, ‘Hardware
Traps’. Hardware traps cause an immediate nonmaskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except
22/69
3
when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual
program execution. In turn, hardware trap services
can normally not be interrupted by standard or
PEC interrupts
Table 8.2 shows all of the possible exceptions or
error conditions that can arise during run-time.
ST10F167
Table 8.2
Exceptions or Error Conditions During Runtime
Exception Condition
Trap
Flag
Reset Functions:
•Hardware Reset
•Software Reset
•Watchdog Timer Overflow
Class A Hardware Traps:
•Non-Maskable Interrupt
•Stack Overflow
•Stack Underflow
Class B Hardware Traps:
•Undefined Opcode
•Protected Instruction Fault
•Illegal Word Operand Access
•Illegal Instruction Access
•Illegal External Bus Access
Reserved
Software Traps
•TRAP Instruction
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
III
III
III
NMI
STKOF
STKUF
NMITRAP
STOTRP
STUTRP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[2Ch – 3Ch]
0Ah
0Ah
0Ah
0Ah
0Ah
[0Bh – 0Fh]
I
I
I
I
I
Any
[00’0000h –
00’01FCh]
in steps of
4h
Any
[00h – 7Fh]
Current
CPU
Priority
23/69
3
ST10F167
9
CAPTURE/COMPARE (CAPCOM) UNITS
The CAPCOM units support generation and control of timing sequences on up to 32 channels. It
has a maximum resolution of 400 ns at 20MHz
system clock. The CAPCOM units are typically
used to handle high speed I/O tasks such as pulse
and waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external
events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers, provide two independent time bases for the
capture/compare register array.
The input clock for the timers is programmable to
several pre-scaled values of the internal system
clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a
wide range of variation for the timer period and
resolution and allows precise adjustments to the
application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7
allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays
contain 16 dual purpose capture/compare regis-
Table 9.1
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;
only one compare event per timer period is generated
Two registers operate on one pin; pin toggles on each compare match;
several compare events per timer period are possible.
Mode 3
Double
Register Mode
3
When a capture/compare register has been selected for capture mode, the current contents of
the allocated timer will be latched (‘captured) into
the capture/compare register in response to an external event at the port pin which is associated with
this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive
and a negative external signal transition at the pin
can be selected as the triggering event. The contents of all registers which have been selected for
one of the five compare modes are continuously
compared with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken, based on the selected
compare mode.
Compare Mode Function
Compare Modes
24/69
ters, each of which may be individually allocated to
either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare
function. Each register has one port pin associated
with it which serves as an input pin for triggering
the capture function, or as an output pin (except
for CC24...CC27) to indicate the occurrence of a
compare event.
ST10F167
Figure 9.1
CAPCOM Unit Block Diagram
),
*) 12 outputs on CAPCOM2
25/69
3
ST10F167
10
GENERAL PURPOSE TIMER (GPT) UNIT
The GPT unit is a flexible multifunctional timer/
counter structure. It may be used for many different time-related tasks such as: event timing and
counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication.
The GPT unit incorporates five 16-bit timers which
are organized in two separate modules, GPT1 and
GPT2. Each timer, in each module may operate independently in a number of different modes, or
may be concatenated with another timer of the
same module.
Each of the three timers T2, T3, T4 of module
GPT1 can be configured individually for one of
three basic modes of operation: Timer, Gated Timer, and Counter Mode. In Timer Mode, the input
clock for a timer is derived from the CPU clock, divided by a programmable prescaler. Counter
Mode allows a timer to be clocked in reference to
external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode where
the operation of a timer is controlled by the ‘gate’
level on an external input pin. Each timer has one
associated port pin (TxIN) which serves as gate or
clock input. The maximum resolution of the timers
in module GPT1 is 400ns (@ 20MHz CPU clock).
The count direction (up/down) for each timer is
programmable by software or may be altered dynamically by an external signal on a port pin (TxEUD) to facilitate, for example, position tracking.
Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer overflow/underflow. The state of these latches may be
output on port pins (TxOUT) for time-out monitoring by external hardware components, or may be
used internally to clock timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers
T2 and T4 may be configured as reload or capture
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3
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 are captured into T2 or T4 in
response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of
T2 or T4, triggered, either by an external signal, or
by a selectable state transition of its toggle latch
T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of
T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.
With its maximum resolution of 160 ns (@
20MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a
programmable prescaler or with external signals.
The count direction (up/down) for each timer is
programmable by software or may additionally be
altered dynamically by an external signal on a port
pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer
T6, which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer
T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionally be cleared after the capture procedure. This allows absolute time differences to be
measured or pulse multiplication to be performed
without software overhead.
ST10F167
Figure 10.1
Block Diagram of GPT1
T2EUD
U/D
Interrupt
Request
GPT1 Timer T2
CPU Clock
2n n=3...10
T2IN
CPU Clock
2n n=3...10
T3EUD
T2
Mode
Control
Reload
Capture
T3OUT
T3
Mode
Control
GPT1 Timer T3
T3OTL
U/D
T3IN
Capture
T4
Mode
Control
T4IN
CPU Clock
Reload
Interrupt
Request
2n n=3...10
GPT1 Timer T4
T4EUD
Interrupt
Request
U/D
27/69
3
ST10F167
Figure 10.2
Block Diagram of GPT2
T5EUD
U/D
CPU Clock
2n n=2...9
T5IN
T5
Mode
Control
Interrupt
Request
GPT2 Timer T5
Clear
Capture
Interrupt
Request
CAPIN
GPT2 CAPREL
Reload
T4IN
CPU Clock
2n n=2...9
T6
Mode
Control
Toggle FF
GPT1 Timer T6
U/D
T4EUD
11
3
T60TL
T6OUT
to CAPCOM
Timers
PWM MODULE
The Pulse Width Modulation Module can generate
up to four PWM output signals using edge-aligned
or centre-aligned PWM. In addition the PWM module can generate PWM burst signals and single
shot outputs. The frequency range of the PWM
28/69
Interrupt
Request
signals is from 4.8 Hz to 1 MHz (referred to a CPU
clock of 20 MHz), depending on the resolution of
the PWM output signal. The level of the output signals is selectable and the PWM module can generate interrupt requests.
ST10F167
12
WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism. It
limits the maximum malfunction time of the controller
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the
time interval until the EINIT (end of initialization)
instruction has been executed. In this way the
chip’s start-up procedure is always monitored. The
software must be designed to service the Watchdog Timer before it overflows. If, due to hardware
or software related failures, the software fails to do
so, the Watchdog Timer overflows and generates
an internal hardware reset and pulls the RSTOUT
13
pin low in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with
the system clock divided either by 2 or by 128. The
high byte of the Watchdog Timer register can be
set to a pre-specified reload value (stored in
WDTREL) in order to allow further variation of the
monitored time interval. Each time it is serviced by
the application software, the high byte of the
Watchdog Timer is reloaded. Therefore, time intervals between 25µs and 420ms can be monitored
(@ 20 MHz). The default Watchdog Timer interval
after reset is 6.55 ms (@ 20 MHz).
A/D CONVERTER
A 10-bit A/D converter with 16 multiplexed input
channels and a sample and hold circuit has been
integrated on-chip for analog signal measurement. It uses a successive approximation method.
The sample time (for loading the capacitors) and
conversion time is programmable and can be
modified for the external circuitry.
Overrun error detection/protection is provided for
the conversion result register (ADDAT). When the
result of a previous conversion has not been read
from the result register at the time the next conversion is complete, either an interrupt request is generated, or the next conversion is suspended, until
the previous result has been read.
For applications which require less than 16 analog
input channels, the remaining channel inputs can
be used as digital input port pins.
The A/D converter of the ST10F167 supports four
different conversion modes. In the standard Single
Channel conversion mode, the analog level on a
specified channel is sampled once and converted
to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel
is repeatedly sampled and converted without soft-
ware intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels
are sequentially sampled and converted. In the
Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific
channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is
called Channel Injection Mode.
The Peripheral Event Controller (PEC) may be
used to automatically store the conversion results
into a table in memory for later evaluation, without
the overhead of interrupt routines for each data
transfer.
After each reset and also during normal operation,
the ADC automatically performs calibration cycles.
This automatic self-calibration constantly adjusts
the converter to the changing operating conditions
(e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion
cycle. They do not affect the normal operation of
the A/D converter.
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ST10F167
14
SERIAL CHANNELS
Serial communication with other microcontrollers,
processors, terminals or external peripheral components is provided by two serial interfaces. An
Asynchronous/Synchronous
Serial
Channel
(ASC0) and a High-Speed Synchronous Serial
Channel (SSC).
ASC0 supports full-duplex asynchronous communication up to 625 KBaud and half-duplex synchronous communication up to 2.5 Mbaud @ 20MHz
system clock.
The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20MHz system clock.
Two dedicated baud rate generators are used to
set up standard baud rates without oscillator tuning. For transmission, reception, and erroneous
reception, 3 separate interrupt vectors are provided for each serial channel.
In asynchronous mode, 8- or 9-bit data frames are
transmitted or received, preceded by a start bit
and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distin-
15
guish address from data bytes has been included
(8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length
synchronously to a shift clock. The shift clock can
be generated by the SSC (master mode) or by an
external master (slave mode). The SSC can start
shifting with the LSB or with the MSB, while the
ASC0 always shifts the LSB first. A loop back option is available for testing purposes.
A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on
reception. ‘framing error detection’ recognizes
data frames with missing stop bits. An overrun error is generated if the last character received was
not read out of the receive buffer register, on the
reception of a new character.
CAN-MODULE
The integrated CAN-Module performs the autonomous transmission and reception of CAN frames
in accordance with the CAN specification V2.0 part
B (active). The on-chip CAN-Module can receive
and transmit standard frames with 11-bit identifiers
as well as extended frames with 29-bit identifiers.
tering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard
a number of identifiers in Basic CAN mode. All
message objects can be updated independent
from the other objects and are equipped for the
maximum message length of 8 bytes.
The module provides full CAN functionality for up
to 15 message objects. Message object 15 may be
configured for Basic CAN functionality. Both
modes provide separate masks for acceptance fil-
The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The
CAN-Module uses two pins to interface to a bus
transceiver.
30/69
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ST10F167
16
PARALLEL PORTS
The ST10F167 provides up to 77 I/O lines which
are organized into eight input/output ports and one
input port. All port lines are bit-addressable, and all
input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when
configured as inputs. The output drivers of three I/
O ports can be configured (pin by pin) for push/pull
operation or open-drain operation via control registers. During the internal reset, all port pins are
configured as inputs.
The input threshold of Port 2, Port 3, Port 7 and
Port 8 is selectable (TTL or CMOS like). The special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input
threshold may be selected individually for each
byte of the respective ports.
All port lines have programmable alternate input or
output functions associated with them. PORT0
and PORT1 may be used as address and data
lines when accessing external memory, while Port
4 outputs the additional segment address bits A23/
19/17...A16 in systems where segmentation is enabled to access more than 64KBytes of memory.Port 2, Port 8 and Port 7 are associated with the
capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM
module. Port 6 provides optional bus arbitration
signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers,
serial interfaces, the optional bus control signal
BHE and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the
A/D converter or timer control signals.
All port lines that are not used for these alternate
functions may be used as general purpose IO
lines.
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ST10F167
17
INSTRUCTION SET SUMMARY
The table below lists the instruction set of the
ST10F167. More detailed information such as address modes, instruction operation, parameters for
Table 17.1
conditional execution of instructions, opcodes and
a detailed description of each instruction can be
found in the “ST10 Programming Manual”..
Instruction Set
Mnemonic
Description
Bytes
ADD(B)
Add word (byte) operands
2/4
ADDC(B)
SUB(B)
Add word (byte) operands with Carry
Subtract word (byte) operands
2/4
2/4
SUBC(B)
MUL(U)
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
2/4
2
DIV(U)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
2
DIVL(U)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
2
CPL(B)
NEG(B)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
2
2
AND(B)
OR(B)
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
2/4
2/4
XOR(B)
Bitwise XOR, (word/byte operands)
2/4
BCLR
Clear direct bit
2
BSET
BMOV(N)
Set direct bit
Move (negated) direct bit to direct bit
2
4
BAND, BOR, BXOR
BCMP
AND/OR/XOR direct bit with direct bit
Compare direct bit to direct bit
4
4
BFLDH/L
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B)
Compare word (byte) operands
2/4
CMPD1/2
Compare word data to GPR and decrement GPR by 1/2
2/4
CMPI1/2
PRIOR
2/4
2
SHL / SHR
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
ROL / ROR
ASHR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
MOV(B)
Move word (byte) data
2/4
MOVBS
Move byte operand to word operand with sign extension
2/4
MOVBZ
JMPA, JMPI, JMPR
Move byte operand to word operand. with zero extension
Jump absolute/indirect/relative if condition is met
2/4
4
JMPS
J(N)B
Jump absolute to a code segment
Jump relative if direct bit is (not) set
32/69
3
2
2
2
4
4
ST10F167
Table 17.1
Instruction Set (cont’d)
JBC
Mnemonic
Description
Jump relative and clear bit if direct bit is set
JNBS
Jump relative and set bit if direct bit is not set
4
CALLA, CALLI, CALLR
Call absolute/indirect/relative subroutine if condition is met
4
CALLS
PCALL
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
4
4
2
4
RET
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update
register with word operand
Return from intra-segment subroutine
RETS
Return from inter-segment subroutine
2
RETP
Return from intra-segment subroutine and pop direct
word register from system stack
2
RETI
SRST
Return from interrupt service subroutine
Software Reset
2
4
IDLE
PWRDN
Enter Idle Mode
Enter Power Down Mode (assumes NMI-pin low)
4
4
SRVWDT
Service Watchdog Timer
4
DISWDT
Disable Watchdog Timer
4
EINIT
ATOMIC
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
4
2
EXTR
EXTP(R)
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
2
2/4
EXTS(R)
Begin EXTended Segment (and Register) sequence
2/4
NOP
Null operation
TRAP
PUSH, POP
SCXT
18
Bytes
4
2
2
2
BOOTSTRAP LOADER
To activate the Boot-strap loader, a hardware reset with RSTIN pin low and an external pull-up resistor connected to the ALE pin, is applied. This
forces the chip into a special test mode. The program execution starts from 1K bytes ROM,
mapped from 0 to 3FF hex which is not accessible
in normal execution mode.
strap loader mode is activated, an instruction fetch
is performed from the test ROM regardless of the
configuration selected with the EBC0, EBC1 and
BUSACT pins. The reset vector in the test ROM
branches to the self-test program, while the NonMaskable Interrupt vector (NMI) branches to the
Boot-strap loader routine.
This test ROM contains a one-time programmable
flash EPROM, loaded with a self-test program plus
the Boot-strap loader program. When the Boot-
The self-test routine execution time is approximately 10ms. It terminates with a software reset
instruction (SRST), where the chip is restarted ac-
33/69
3
ST10F167
cording to the EBC0, EBC1 and BUSACT pin configurations. The state of the ALE pin is not taken
into account for software reset. To trigger the
Boot-strap loader program, it is necessary to activate the Non Maskable Interrupt by forcing a low
level on the NMI pin before the end of the self-test
routine
19
The identification byte sent by the ST10F167 is
D5h. Note that the bootstrap loader of all ST10 devices which include identification registers will return D5h as the identification byte. The startup
code loaded with bootstrap loader will dump identification registers for complete chip identification
from the host.
SPECIAL FUNCTION REGISTER OVERVIEW
The following table lists all ST10F167 SFRs in alphabetical order.
Bit-addressable SFRs are marked with the letter
“b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter
“E” in column “Physical Address”.
Table 19.1
An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical
address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page
Pointers).
Special Function Register List
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
ADCIC
b
FF98h
CCh
A/D Converter End of Conversion Interrupt Cont Reg
0000h
ADCON
b
FFA0h
D0h
A/D Converter Control Register
0000h
ADDAT
FEA0h
50h
A/D Converter Result Register
0000h
ADDAT2
F0A0h E
50h
A/D Converter 2 Result Register
0000h
ADDRSEL1
FE18h
0Ch
Address Select Register 1
0000h
ADDRSEL2
FE1Ah
0Dh
Address Select Register 2
0000h
ADDRSEL3
FE1Ch
0Eh
Address Select Register 3
0000h
ADDRSEL4
FE1Eh
0Fh
Address Select Register 4
0000h
ADEIC
b
FF9Ah
CDh
A/D Converter Overrun Error Interrupt Control Reg
0000h
BUSCON0 b
FF0Ch
86h
Bus Configuration Register 0
0XX0h
BUSCON1 b
FF14h
8Ah
Bus Configuration Register 1
0000h
BUSCON2 b
FF16h
8Bh
Bus Configuration Register 2
0000h
BUSCON3 b
FF18h
8Ch
Bus Configuration Register 3
0000h
BUSCON4 b
FF1Ah
8Dh
Bus Configuration Register 4
0000h
CAPREL
FE4Ah
25h
GPT2 Capture/Reload Register
0000h
FE80h
40h
CAPCOM Register 0
0000h
FF78h
BCh
CAPCOM Register 0 Interrupt Control Register
0000h
FE82h
41h
CAPCOM Register 1
0000h
FF7Ah
BDh
CAPCOM Register 1 Interrupt Control Register
0000h
FE84h
42h
CAPCOM Register 2
0000h
FF7Ch
BEh
CAPCOM Register 2 Interrupt Control Register
0000h
CC0
CC0IC
b
CC1
CC1IC
b
CC2
CC2IC
34/69
3
b
ST10F167
Table 19.1
Special Function Register List (cont’d)
Name
CC3
CC3IC
b
CC4
CC4IC
b
CC5
CC5IC
b
CC6
CC6IC
b
CC7
CC7IC
b
CC8
CC8IC
b
CC9
CC9IC
b
CC10
CC10IC
b
CC11
CC11IC
b
CC12
CC12IC
b
CC13
CC13IC
b
CC14
CC14IC
b
CC15
CC15IC
b
CC16
CC16IC
b
CC17
CC17IC
b
CC18
CC18IC
b
CC19
CC19IC
b
CC20
CC20IC
b
Physical
Address
8-Bit
Address
FE86h
43h
CAPCOM Register 3
0000h
FF7Eh
BFh
CAPCOM Register 3 Interrupt Control Register
0000h
FE88h
44h
CAPCOM Register 4
0000h
FF80h
C0h
CAPCOM Register 4 Interrupt Control Register
0000h
FE8Ah
45h
CAPCOM Register 5
0000h
FF82h
C1h
CAPCOM Register 5 Interrupt Control Register
0000h
FE8Ch
46h
CAPCOM Register 6
0000h
FF84h
C2h
CAPCOM Register 6 Interrupt Control Register
0000h
FE8Eh
47h
CAPCOM Register 7
0000h
FF86h
C3h
CAPCOM Register 7 Interrupt Control Register
0000h
FE90h
48h
CAPCOM Register 8
0000h
FF88h
C4h
CAPCOM Register 8 Interrupt Control Register
0000h
FE92h
49h
CAPCOM Register 9
0000h
FF8Ah
C5h
CAPCOM Register 9 Interrupt Control Register
0000h
FE94h
4Ah
CAPCOM Register 10
0000h
FF8Ch
C6h
CAPCOM Register 10 Interrupt Control Register
0000h
FE96h
4Bh
CAPCOM Register 11
0000h
FF8Eh
C7h
CAPCOM Register 11 Interrupt Control Register
0000h
FE98h
4Ch
CAPCOM Register 12
0000h
FF90h
C8h
CAPCOM Register 12 Interrupt Control Register
0000h
FE9Ah
4Dh
CAPCOM Register 13
0000h
FF92h
C9h
CAPCOM Register 13 Interrupt Control Register
0000h
FE9Ch
4Eh
CAPCOM Register 14
0000h
FF94h
CAh
CAPCOM Register 14 Interrupt Control Register
0000h
FE9Eh
4Fh
CAPCOM Register 15
0000h
FF96h
CBh
CAPCOM Register 15 Interrupt Control Register
0000h
FE60h
30h
CAPCOM Register 16
0000h
F160h E
B0h
CAPCOM Register 16 Interrupt Control Register
0000h
FE62h
31h
CAPCOM Register 17
0000h
F162h E
B1h
CAPCOM Register 17 Interrupt Control Register
0000h
FE64h
32h
CAPCOM Register 18
0000h
F164h E
B2h
CAPCOM Register 18 Interrupt Control Register
0000h
FE66h
33h
CAPCOM Register 19
0000h
F166h E
B3h
CAPCOM Register 19 Interrupt Control Register
0000h
FE68h
34h
CAPCOM Register 20
0000h
F168h E
B4h
CAPCOM Register 20 Interrupt Control Register
0000h
Description
Reset
Value
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3
ST10F167
Table 19.1
Special Function Register List (cont’d)
Name
CC21
CC21IC
b
CC22
CC22IC
b
CC23
CC23IC
b
CC24
CC24IC
b
CC25
CC25IC
b
CC26
CC26IC
b
CC27
CC27IC
b
CC28
CC28IC
b
CC29
CC29IC
b
CC30
CC30IC
b
CC31
Physical
Address
8-Bit
Address
FE6Ah
35h
CAPCOM Register 21
0000h
F16Ah E
B5h
CAPCOM Register 21 Interrupt Control Register
0000h
FE6Ch
36h
CAPCOM Register 22
0000h
F16Ch E
B6h
CAPCOM Register 22 Interrupt Control Register
0000h
FE6Eh
37h
CAPCOM Register 23
0000h
F16Eh E
B7h
CAPCOM Register 23 Interrupt Control Register
0000h
FE70h
38h
CAPCOM Register 24
0000h
F170h E
B8h
CAPCOM Register 24 Interrupt Control Register
0000h
FE72h
39h
CAPCOM Register 25
0000h
F172h E
B9h
CAPCOM Register 25 Interrupt Control Register
0000h
FE74h
3Ah
CAPCOM Register 26
0000h
F174h E
BAh
CAPCOM Register 26 Interrupt Control Register
0000h
FE76h
3Bh
CAPCOM Register 27
0000h
F176h E
BBh
CAPCOM Register 27 Interrupt Control Register
0000h
Description
Reset
Value
FE78h
3Ch
CAPCOM Register 28
0000h
F178h E
BCh
CAPCOM Register 28 Interrupt Control Register
0000h
FE7Ah
3Dh
CAPCOM Register 29
0000h
F184h E
C2h
CAPCOM Register 29 Interrupt Control Register
0000h
FE7Ch
3Eh
CAPCOM Register 30
0000h
F18Ch E
C6h
CAPCOM Register 30 Interrupt Control Register
0000h
FE7Eh
3Fh
CAPCOM Register 31
0000h
CC31IC
b
F194h E
CAh
CAPCOM Register 31 Interrupt Control Register
0000h
CCM0
b
FF52h
A9h
CAPCOM Mode Control Register 0
0000h
CCM1
b
FF54h
AAh
CAPCOM Mode Control Register 1
0000h
CCM2
b
FF56h
ABh
CAPCOM Mode Control Register 2
0000h
CCM3
b
FF58h
ACh
CAPCOM Mode Control Register 3
0000h
CCM4
b
FF22h
91h
CAPCOM Mode Control Register 4
0000h
CCM5
b
FF24h
92h
CAPCOM Mode Control Register 5
0000h
CCM6
b
FF26h
93h
CAPCOM Mode Control Register 6
0000h
CCM7
b
FF28h
94h
CAPCOM Mode Control Register 7
0000h
FE10h
08h
CPU Context Pointer Register
FC00h
FF6Ah
B5h
GPT2 CAPREL Interrupt Control Register
0000h
FE08h
04h
CPU Code Segment Pointer Register (read only)
0000h
CP
CRIC
b
CSP
DP0L
b
F100h E
80h
P0L Direction Control Register
00h
DP0H
b
F102h E
81h
P0H Direction Control Register
00h
DP1L
b
F104h E
82h
P1L Direction Control Register
00h
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3
ST10F167
Table 19.1
Special Function Register List (cont’d)
Name
Physical
Address
8-Bit
Address
Description
Reset
Value
DP1H
b
F106h E
83h
P1H Direction Control Register
00h
DP2
b
FFC2h
E1h
Port 2 Direction Control Register
0000h
DP3
b
FFC6h
E3h
Port 3 Direction Control Register
0000h
DP4
b
FFCAh
E5h
Port 4 Direction Control Register
00h
DP6
b
FFCEh
E7h
Port 6 Direction Control Register
00h
DP7
b
FFD2h
E9h
Port 7 Direction Control Register
00h
DP8
b
FFD6h
EBh
Port 8 Direction Control Register
00h
DPP0
FE00h
00h
CPU Data Page Pointer 0 Register (10 bits)
0000h
DPP1
FE02h
01h
CPU Data Page Pointer 1 Register (10 bits)
0001h
DPP2
FE04h
02h
CPU Data Page Pointer 2 Register (10 bits)
0002h
DPP3
FE06h
03h
CPU Data Page Pointer 3 Register (10 bits)
0003h
EXICON
b
F1C0h E
E0h
External Interrupt Control Register
0000h
MDC
b
FF0Eh
87h
CPU Multiply Divide Control Register
0000h
FE0Ch
06h
CPU Multiply Divide Register – High Word
0000h
MDH
MDL
FE0Eh
07h
CPU Multiply Divide Register – Low Word
0000h
ODP2
b
F1C2h E
E1h
Port 2 Open Drain Control Register
0000h
ODP3
b
F1C6h E
E3h
Port 3 Open Drain Control Register
0000h
ODP6
b
F1CEh E
E7h
Port 6 Open Drain Control Register
00h
ODP7
b
F1D2h E
E9h
Port 7 Open Drain Control Register
00h
ODP8
b
F1D6h E
EBh
Port 8 Open Drain Control Register
00h
FF1Eh
8Fh
Constant Value 1’s Register (read only)
FFFFh
ONES
P0L
b
FF00h
80h
Port 0 Low Register (Lower half of PORT0)
00h
P0H
b
FF02h
81h
Port 0 High Register (Upper half of PORT0)
00h
P1L
b
FF04h
82h
Port 1 Low Register (Lower half of PORT1)
00h
P1H
b
FF06h
83h
Port 1 High Register (Upper half of PORT1)
00h
P2
b
FFC0h
E0h
Port 2 Register
0000h
P3
b
FFC4h
E2h
Port 3 Register
0000h
P4
b
FFC8h
E4h
Port 4 Register (8 bits)
00h
P5
b
FFA2h
D1h
Port 5 Register (read only)
XXXXh
P6
b
FFCCh
E6h
Port 6 Register (8 bits)
00h
P7
b
FFD0h
E8h
Port 7 Register (8 bits)
00h
P8
b
FFD4h
EAh
Port 8 Register (8 bits)
00h
PECC0
FEC0h
60h
PEC Channel 0 Control Register
0000h
PECC1
FEC2h
61h
PEC Channel 1 Control Register
0000h
PECC2
FEC4h
62h
PEC Channel 2 Control Register
0000h
PECC3
FEC6h
63h
PEC Channel 3 Control Register
0000h
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ST10F167
Table 19.1
Special Function Register List (cont’d)
Physical
Address
8-Bit
Address
Description
Reset
Value
PECC4
FEC8h
64h
PEC Channel 4 Control Register
0000h
PECC5
FECAh
65h
PEC Channel 5 Control Register
0000h
PECC6
FECCh
66h
PEC Channel 6 Control Register
0000h
PECC7
FECEh
67h
PEC Channel 7 Control Register
0000h
PICON
F1C4h E
E2h
Port Input Threshold Control Register
0000h
PP0
F038h E
1Ch
PWM Module Period Register 0
0000h
PP1
F03Ah E
1Dh
PWM Module Period Register 1
0000h
PP2
F03Ch E
1Eh
PWM Module Period Register 2
0000h
PP3
F03Eh E
1Fh
PWM Module Period Register 3
0000h
FF10h
88h
CPU Program Status Word
0000h
PT0
F030h E
18h
PWM Module Up/Down Counter 0
0000h
PT1
F032h E
19h
PWM Module Up/Down Counter 1
0000h
PT2
F034h E
1Ah
PWM Module Up/Down Counter 2
0000h
PT3
F036h E
1Bh
PWM Module Up/Down Counter 3
0000h
PW0
FE30h
18h
PWM Module Pulse Width Register 0
0000h
PW1
FE32h
19h
PWM Module Pulse Width Register 1
0000h
PW2
FE34h
1Ah
PWM Module Pulse Width Register 2
0000h
PW3
FE36h
1Bh
PWM Module Pulse Width Register 3
0000h
PWMCON0b
FF30h
98h
PWM Module Control Register 0
0000h
PWMCON1b
FF32h
99h
PWM Module Control Register 1
0000h
PWMIC
b
F17Eh E
BFh
PWM Module Interrupt Control Register
0000h
RP0H
b
F108h E
84h
System Startup Configuration Register (Rd. only)
XXh
FEB4h
5Ah
Serial Channel 0 Baud Rate Generator Reload Reg
0000h
Name
PSW
b
S0BG
S0CON
b
FFB0h
D8h
Serial Channel 0 Control Register
0000h
S0EIC
b
FF70h
B8h
Serial Channel 0 Error Interrupt Control Register
0000h
S0RBUF
FEB2h
59h
Serial Channel 0 Receive Buffer Register (read only)
XXh
S0RIC
b
FF6Eh
B7h
Serial Channel 0 Receive Interrupt Control Register
0000h
S0TBIC
b
F19Ch E
CEh
Serial Channel 0 Transmit Buffer Interrupt Control
Register
0000h
FEB0h
58h
Serial Channel 0 Transmit Buffer Register (write only)
00h
S0TBUF
S0TIC
FF6Ch
B6h
Serial Channel 0 Transmit Interrupt Control Register
0000h
SP
FE12h
09h
CPU System Stack Pointer Register
FC00h
SSCBR
F0B4h E
5Ah
SSC Baudrate Register
0000h
SSCCON b
FFB2h
D9h
SSC Control Register
0000h
SSCEIC
FF76h
BBh
SSC Error Interrupt Control Register
0000h
F0B2h E
59h
SSC Receive Buffer (read only)
XXXXh
SSCRB
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3
b
b
ST10F167
Table 19.1
Special Function Register List (cont’d)
Physical
Address
8-Bit
Address
FF74h
BAh
SSC Receive Interrupt Control Register
0000h
F0B0h E
58h
SSC Transmit Buffer (write only)
0000h
FF72h
B9h
SSC Transmit Interrupt Control Register
0000h
STKOV
FE14h
0Ah
CPU Stack Overflow Pointer Register
FA00h
STKUN
FE16h
0Bh
CPU Stack Underflow Pointer Register
FC00h
SYSCON b
FF12h
89h
CPU System Configuration Register
0xx0h1)
T0
FE50h
28h
CAPCOM Timer 0 Register
0000h
Name
SSCRIC
b
SSCTB
SSCTIC
b
Description
Reset
Value
T01CON
b
FF50h
A8h
CAPCOM Timer 0 and Timer 1 Control Register
0000h
T0IC
b
FF9Ch
CEh
CAPCOM Timer 0 Interrupt Control Register
0000h
T0REL
FE54h
2Ah
CAPCOM Timer 0 Reload Register
0000h
T1
FE52h
29h
CAPCOM Timer 1 Register
0000h
FF9Eh
CFh
CAPCOM Timer 1 Interrupt Control Register
0000h
T1REL
FE56h
2Bh
CAPCOM Timer 1 Reload Register
0000h
T2
FE40h
20h
GPT1 Timer 2 Register
0000h
T1IC
b
T2CON
b
FF40h
A0h
GPT1 Timer 2 Control Register
0000h
T2IC
b
FF60h
B0h
GPT1 Timer 2 Interrupt Control Register
0000h
FE42h
21h
GPT1 Timer 3 Register
0000h
T3
T3CON
b
FF42h
A1h
GPT1 Timer 3 Control Register
0000h
T3IC
b
FF62h
B1h
GPT1 Timer 3 Interrupt Control Register
0000h
FE44h
22h
GPT1 Timer 4 Register
0000h
T4
T4CON
b
FF44h
A2h
GPT1 Timer 4 Control Register
0000h
T4IC
b
FF64h
B2h
GPT1 Timer 4 Interrupt Control Register
0000h
FE46h
23h
GPT2 Timer 5 Register
0000h
T5
T5CON
b
FF46h
A3h
GPT2 Timer 5 Control Register
0000h
T5IC
b
FF66h
B3h
GPT2 Timer 5 Interrupt Control Register
0000h
T6
FE48h
24h
GPT2 Timer 6 Register
0000h
T6CON
b
FF48h
A4h
GPT2 Timer 6 Control Register
0000h
T6IC
b
FF68h
B4h
GPT2 Timer 6 Interrupt Control Register
0000h
F050h E
28h
CAPCOM Timer 7 Register
0000h
T7
T78CON
b
FF20h
90h
CAPCOM Timer 7 and 8 Control Register
0000h
T7IC
b
F17Ah E
BEh
CAPCOM Timer 7 Interrupt Control Register
0000h
T7REL
F054h E
2Ah
CAPCOM Timer 7 Reload Register
0000h
T8
F052h E
29h
CAPCOM Timer 8 Register
0000h
F17Ch E
BFh
CAPCOM Timer 8 Interrupt Control Register
0000h
F056h E
2Bh
CAPCOM Timer 8 Reload Register
0000h
FFACh
D6h
Trap Flag Register
0000h
T8IC
b
T8REL
TFR
b
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ST10F167
Table 19.1
Special Function Register List (cont’d)
Physical
Address
8-Bit
Address
WDT
FEAEh
57h
Watchdog Timer Register (read only)
0000h
WDTCON
FFAEh
D7h
Watchdog Timer Control Register
000Xh2)
Name
Description
Reset
Value
XP0IC
b
F186h E
C3h
CAN Module Interrupt Control Register
0000h
XP1IC
b
F18Eh E
C7h
X-Peripheral 1 Interrupt Control Register
0000h
XP2IC
b
F196h E
CBh
X-Peripheral 2 Interrupt Control Register
0000h
XP3IC
b
F19Eh E
CFh
PLL Interrupt Control Register
0000h
ZEROS
b
FF1Ch
8Eh
Constant Value 0’s Register (read only)
0000h
Notes 1:The system configuration is selected during reset.
2:Bit WDTR indicates a watchdog timer triggered reset.
3:The Interrupt Control Registers XPnIC, control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
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ST10F167
20
ELECTRICAL CHARACTERISTICS
20.1 Absolute Maximum Ratings
Ambient temperature under bias (TA): ST10F167.................................................................. –40to +85 °C
– to +150 °C
Storage temperature (TST)................................................................................................... 65
Voltage on VDD pins with respect to ground (VSS).................................................................. –0.5 to +6.5 V
Voltage on any pin with respect to ground (VSS) ............................................................. –0.3to VDD +0.3 V
Input current on any pin during overload condition.............................................................. –10 to +10 mA
Absolute sum of all input currents during overload condition........................................................ |100 mA|
Power dissipation............................................................................................................................... 1.5 W
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN<VSS)
the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum
Ratings.
20.2 Parameter Interpretation
The parameters listed in the Electrical Characteristics tables, 20.1 to 20.9, represent the characteristics of the ST10F167 and its demands on the
system.
Where the ST10F167 logic provides signals with
their respective timing characteristics, the symbol
“CC” for Controller Characteristics, is included in
the “Symbol” column.
Where the external system must provide signals
with their respective timing characteristics to the
ST10F167, the symbol “SR” for System Requirement, is included in the “Symbol” column.
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ST10F167
20.3 DC Characteristics
VDD = 5 V ± 5%, VSS = 0, fCPU = 20MHz, Reset active, T A = -40 to +85 °C
Table 20.1
DC Parametric
Symbol
Parameter
Limit Values
min.
max.
Unit
Test Condition
Input low voltage (TTL)
VILSR
– 0.5
0.2 VDD
– 0.1
V
–
Input low voltage
(Special Threshold)
VILSSR
– 0.5
2.0
V
–
Input high voltage, all except RSTIN
and XTAL1 (TTL)
VIHSR
0.2 VDD
+ 0.9
VDD + 0.5
V
–
Input high voltage RSTIN
VIH1SR
0.6 VDD
VDD + 0.5
V
–
Input high voltage XTAL1
VIH2SR
0.7 VDD
VDD + 0.5
V
–
Input high voltage
(Special Threshold)
VIHSSR
0.8 VDD
- 0.2
VDD + 0.5
V
–
Input Hysteresis
(Special Threshold)
HYS
400
-
mV
–
Output low voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
VOLCC
–
0.45
V
IOL = 2.4 mA
Output low voltage
(all other outputs)
VOL1CC
–
0.45
V
IOL1 = 1.6 mA
Output high voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
VOHCC
0.9 VDD
2.4
–
V
IOH = – 500 µA
IOH = – 2.4 mA
VOH1CC
0.9 VDD
2.4
–
V
V
IOH = – 250 µA
IOH = – 1.6 mA
Input leakage current (Port 5)
IOZ1CC
–
±1
µA
0.45V < VIN < VDD
Input leakage current (all other)
IOZ2CC
–
±1
µA
0.45V < VIN < VDD
Overload current
IOVSR
–
±5
mA
5) 8)
RRSTCC
1)
Output high voltage
(all other outputs)
RSTIN pullup resistor
Read/Write inactive current
Read/Write active current
ALE inactive current
ALE active current
4)
4)
Port 6 inactive current
Port 6 active current
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3
4)
4)
4)
4)
50
250
kΩ
–
IRWH
2)
–
-40
µA
VOUT = 2.4 V
IRWL
3)
-500
–
µA
VOUT = VOLmax
IALEL
2)
–
30
µA
VOUT = VOLmax
IALEH
3)
500
–
µA
VOUT = 2.4 V
IP6H
2)
–
-40
µA
VOUT = 2.4 V
IP6L
3)
-500
–
µA
VOUT = VOL1max
ST10F167
Table 20.1
DC Parametric (cont’d)
Symbol
Parameter
Limit Values
min.
max.
Unit
Test Condition
IP0H
2)
–
-10
µA
VIN = VIHmin
IP0L
3)
-100
–
µA
VIN = VILmax
IIL CC
–
±20
µA
0 V < VIN < VDD
Pin capacitance
(digital inputs/outputs)
CIO CC
–
10
pF
f = 1MHz
TA = 25 °C
Power supply current
ICC
–
120 +
5 * fCPU
mA
RSTIN = VIL
fCPU in [MHz] 6)
Idle mode supply current
IID
–
40 +
2 * fCPU
mA
RSTIN = VIH1
fCPU in [MHz] 6)
Power-down mode supply current
IPD
–
100
µA
VDD = 5.25 V 7)
VPP Read Current
VPP Write Current
IPPR
-
200
µA
VPP < VDD
IPPW
-
50
mA
at 20MHz 32-Bit
programming
VPP = 12V
VPP during Write/Read
VPP
11.4
12.6
V
PORT0 configuration current
4)
XTAL1 input current
5)
Notes 1:This specification is not valid for outputs which are switched to open drain mode. In this case
the respective output will float and the voltage results from the external circuitry.
2:The maximum current may be drawn while the respective signal line remains inactive.
3:The minimum current must be drawn in order to drive the respective signal line active.
4:This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only
affected, if they are used for CS output and the open drain function is not enabled.
5:Not 100% tested, guaranteed by design characterization.
6:The supply current is a function of the operating frequency. This dependency is illustrated in the
figure below.
These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected
and all inputs at V IL or VIH.
7:This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD – 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured
as outputs) disconnected.
8:Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on
any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < VSS-0.5V). The absolute
sum of input overload currents on all port pins may not exceed 50 mA.
9:Power Down Current is to be defined.
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ST10F167
Supply/Idle Current as a Function of Operating Frequency
I [mA]
Figure 20.1
150
ICCmax
100
ICCtyp
IIDmax
50
IIDtyp
10
5
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3
10
15
20
fCPU [MHz]
ST10F167
20.4 A/D Converter Characteristics
VDD = 5 V ± 5%, VSS = 0 V, TA = -40 to +85 °C
4.0 V ≤ VAREF ≤ VDD+0.1 V, VSS-0.1 V ≤ VAGND ≤ VSS+0.2 V
Table 20.2
A/D Converter Characteristics
Parameter
Limit Values
Symbol
min.
max.
Unit
Analog input voltage range
VAIN
SR
VAGND
VAREF
Sample time
tS
tC
CC
–
2 tSC
2) 4)
CC
–
14 tCC + tS
+ 4TCL
3) 4)
TUE CC
RAREF SR
–
–
+3
Conversion time
Total unadjusted error
Internal resistance of reference
voltage source
Internal resistance of analog
source
ADC input capacitance
RASRC SR
–
CC
–
CAIN
Sample time and conversion time of the
ST10F167’s ADC are programmable. Table 20.3
Table 20.3
ADCON.15|14
(ADCTC)
tCC / 165
- 0.25
tS / 330
- 0.25
33
V
Test Condition
1)
LSB
kΩ
5)
tCC in [ns] 6) 7)
kΩ
tS in [ns] 2) 7)
pF
7)
shows the timing calculations.
Sample and Conversion Time Calculations
Conversion clock tCC
ADCON.13|12
(ADSTC)
Sample clock tSC
00
01
TCL * 24
Reserved, do not use
00
01
tCC
tCC * 2
10
TCL * 96
10
tCC * 4
11
TCL * 48
11
tCC * 8
Notes 1:VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FF H, respectively.
2:During the sample time the input capacitance CI can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within tS. After the end of the sample time tS, changes of the analog input voltage
have no effect on the conversion result.
Values for the sample clock tSC depend on programming and can be taken from the table above.
3:This parameter includes the sample time tS, the time for determining the digital result and the
time to load the result register with the conversion result.
Values for the conversion clock tCC depend on programming and can be taken from the table
above.
4:This parameter depends on the ADC control logic. It is not a real maximum value, but rather a
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ST10F167
fixum.
5:TUE is tested at VAREF=5.0V, VAGND=0V, VDD=4.9V. It is guaranteed by design characterization
for all other voltages within the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see I OV specification) occurs on
maximum 2 not selected analog input pins and the absolute sum of input overload currents on
all analog input pins does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±4 LSB.
6:During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The
internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed
conversion timing.
7:Not 100% tested, guaranteed by design characterization.
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ST10F167
20.5
AC Characteristics
20.5.1 Test Waveforms
Figure 20.2
Input Output Waveforms
2.4V
0.2VDD+0.9
0.2VDD+0.9
Test Points
0.45V
0.2V DD-0.1
0.2VDD-0.1
AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
Figure 20.3
Float Waveforms
V OH
V Load +0.1V
V Load
VLoad -0.1V
VOH -0.1V
Timing
Reference
Points
V OL +0.1V
VOL
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs,but begins to float whena 100 mV change from the loaded VOH/VOL level occurs
(IOH/IOL = 20 mA).
47/69
3
ST10F167
20.5.2 Definition of Internal Timing
The internal operation of the ST10F167 is controlled by the internal CPU clock fCPU. Both edges of
the CPU clock can trigger internal (e.g. pipeline) or
external (e.g. bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock,
called “TCL” (see Figure 20.4).
Figure 20.4
The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their
variation (and also the derived external timing) depends on the mechanism used to generate fCPU.
This influence must be taken into consideration
when calculating the timings for the ST10F167.
Generation Mechanisms for the CPU Clock
Phase Locked Loop Operation
fXTAL
fCPU
TCL TCL
Direct Clock Drive
fXTAL
fCPU
TCL TCL
20.5.3 Direct Drive
When pin P0.15 (P0H.7) is low (‘0’) during reset
the on-chip phase locked loop is disabled and the
CPU clock is directly driven from the oscillator with
the input clock signal.
The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the
duty cycle of the input clock f XTAL.
The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:
48/69
3
TCL
min
= 1 ⁄ f X TA L *DC
min
DC = duty cycle
For two consecutive TCLs the deviation caused by
the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum
value TCLmin therefore has to be used only once
for timings that require an odd number of TCLs
(1,3,...). Timings that require an even number of
TCLs (2,4,...) may use the formula:
2TCL = 1/fXTAL.
Note:The address float timings in Multiplexed bus mode
(t11 and t45) use the maximum duration of TCL
(TCLmax = 1/fXTAL * DCmax) instead of TCLmin.
ST10F167
20.5.4 Phase Locked Loop
When pin P0.15 (P0H.7) is high (‘1’) during reset
the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input
frequency by 4 (i.e. fCPU = fXTAL * 4). With every
fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
For a period of N * TCL the minimum value is computed using the corresponding deviation DN:
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight variation causes a jitter
of f CPU which also effects the duration of individual
TCLs.
So for a period of 3 TCLs (i.e. N = 3):
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective
circumstances.
The actual minimum value for TCL depends on the
jitter of the PLL. As the PLL is constantly adjusting
its output frequency so that it remains locked to the
applied input frequency (crystal or oscillator) the
relative deviation for periods of more than one TCL
is lower than for one single TCL (see formula and
figure below).
Figure 20.5
TCLmi n = TCL NOM * ( 1 – lD N l ) § 100
D N = ± ( 4 – N ⁄ 15 ) [ % ]
where N = number of consecutive TCLs and
1 ≤ N ≤ 40.
D 3 = 4 – 3 ⁄ 15
= 3.8%
TCLmin = TCLN OM × ( 1 – 3.8 ⁄ 100 )
= TCL NOM × 0.962
( 24.1 [email protected] CP U = 20 MHz )
This is especially important for bus cycles using
waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and
longer periods (e.g. pulse train generation or
measurement, lower baudrates, etc.) the deviation
caused by the PLL jitter is negligible.
Approximated Maximum PLL Jitter
Max.jitter [%]
This approximated formula is valid for
1 ≤ N ≤ 40 and 10MHz ≤ fCPU ≤ 20MHz.
±4
±3
±2
±1
2
4
8
16
32
N
49/69
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ST10F167
20.5.5 External Clock Drive XTAL1
VDD = 5 V ± 5%, VSS = 0 V, TA = -40 to +85 °C
Table 20.4
External Clock Drive Characteristics
Parameter
tOSC
t1
t2
t3
t4
Oscillator period
High time
Low time
Rise time
Fall time
1)
Direct Drive 1:1
Symbol
PLL 1:4
Unit
SR
min.
50 1)
max.
1000
min.
200
max.
333
SR
25
–
6
–
ns
SR
25
–
6
–
ns
SR
SR
–
–
10
10
–
–
10
10
ns
ns
ns
Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.
Figure 20.6
External Clock Drive XTAL1
t3
t1
t4
VIL
VIH2
t2
tOSC
20.5.6 Memory Cycle Variables
The timing tables below use three variables which
are derived from the BUSCONx registers and represent the special characteristics of the pro-
Table 20.5
Memory Cycle Variable Definition
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
50/69
3
grammed memory cycle. The following table describes, how these variables are to be computed.
Symbol
tA
tC
tF
Values
TCL * <ALECTL>
2TCL * (15 - <MCTC>)
2TCL * (1 - <MTTC>)
ST10F167
20.5.7 Multiplexed Bus
VDD = 5 V ± 5%,VSS = 0 V, TA = -40 to +85 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Table 20.6
Multiplexed Bus Characteristics
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
–
–
TCL - 10 + tA
TCL - 25 + tA
–
–
ns
ns
ALE high time
Address setup to ALE
t5 CC
t6 CC
15 + tA
0 + tA
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD, WR
(with RW-delay)
t7 CC
t8 CC
15 + tA
15 + tA
–
–
TCL - 10 + tA
TCL - 10 + tA
–
–
ns
ns
t9 CC
-10 + tA
–
-10 + tA
–
ns
t10 CC
–
5
–
5
ns
Address float after RD, WR
(no RW-delay)
t11 CC
–
30
–
TCL + 5
ns
RD, WR low time
(with RW-delay)
t12 CC
25 + tC
–
2TCL - 25
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13 CC
65 + tC
–
3TCL - 10
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14 SR
–
5 + tC
–
2TCL - 45
+ tC
ns
RD to valid data in
(no RW-delay)
t15 SR
–
55 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16 SR
–
40 + tA + tC
–
3TCL - 35
+ tA + tC
ns
Address to valid data in
t17 SR
–
–
t18 SR
0
0
4TCL - 40
+ 2tA + tC
–
ns
Data hold after RD
rising edge
Data float after RD
60
+ 2tA + tC
–
–
35 + tF
–
2TCL - 15 + tF
ns
Data valid to WR
t19 SR
t22 SR
15 + tC
–
2TCL - 35
+ tC
–
ns
Data hold after WR
t23 CC
35 + tF
–
–
ns
ALE rising edge after RD,
t25 CC
WR
Address hold after RD, WR t27 CC
35 + tF
–
–
ns
35 + tF
–
2TCL - 15
+ tF
2TCL - 15
+ tF
2TCL - 15 + tF
–
ns
ns
51/69
3
ST10F167
Table 20.6
Multiplexed Bus Characteristics (cont’d)
Parameter
ALE falling edge to CS
CS low to Valid Data In
Symbol
t38 CC
t39 SR
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
min.
-5 - tA
max.
10 - tA
min.
-5 - tA
max.
10 - tA
–
–
ns
3TCL - 15 + tF
3TCL - 30
+ tC + 2tA
–
Unit
ns
t40 CC
t42 CC
60 + tF
45
+ tC + 2tA
–
20 + tA
–
TCL - 5 + tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43 CC
-5 + tA
–
-5 + tA
–
ns
Address float after RdCS,
WrCS (with RW delay)
t44 CC
–
0
–
0
ns
Address float after RdCS,
WrCS (no RW delay)
t45 CC
–
25
–
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46 SR
–
15 + tC
–
2TCL - 35
+ tC
ns
RdCS to Valid Data In
(no RW delay)
t47 SR
–
50 + tC
–
3TCL - 25
+ tC
ns
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
t48 CC
40 + tC
–
–
ns
t49 CC
65 + tC
–
–
ns
t50 CC
35 + tC
–
–
ns
Data hold after RdCS
t51 SR
t52 SR
t54 CC
0
–
2TCL - 10
+ tC
3TCL - 10
+ tC
2TCL - 15
+ tC
0
–
30 + tF
30 + tF
–
t56 CC
30 + tF
–
CS hold after RD, WR
ALE fall. edge to RdCS,
WrCS (with RW delay)
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
52/69
3
–
ns
ns
–
2TCL - 20 + tF
2TCL - 20 + tF
–
ns
ns
2TCL - 20 + tF
ns
–
ST10F167
Figure 20.7
External Memory Cycle:Multiplexed Bus, With Read/Write Delay, Normal
ALE
t5
t16
t25
ALE
t38
t39
t40
CSx
t17
A23-A16
(A15-A8)
BHE
t27
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t8
Data In
t10
t14
RD
t42
t44
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
t8
Data Out
WR,
WRL, WRH
t42
t56
t10
t44
t22
t12
t50
WrCSx
t48
53/69
3
ST10F167
Figure 20.8
External Memory Cycle:Multiplexed Bus,
Extended ALE
t5
With
Read/Write
t16
t25
t39
t40
t17
t27
ALE
t38
CSx
A23-A16
(A15-A8)
BHE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
Data In
t8
t10
t14
RD
t42
t44
t12
t51
t52
t46
RdCSx
t48
Write Cycle
BUS
t23
Address
t8
Data Out
WR,
WRL, WRH
t42
t56
t10
t44
t22
t12
t50
WrCSx
t48
54/69
3
Delay,
ST10F167
Figure 20.9
External Memory Cycle:Multiplexed Bus, No Read/Write Delay, Normal
ALE
t5
t16
t25
ALE
t38
t39
t40
CSx
t17
A23-A16
(A15-A8)
BHE
t27
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t9
Data In
t11
RD
t43
t15
t13
t45
RdCSx
t51
t52
t47
t49
Write Cycle
BUS
t23
Address
t9
Data Out
t56
t11
WR,
WRL, WRH
t43
t22
t13
t45
t50
WrCSx
t49
55/69
3
ST10F167
Figure 20.10 External Memory Cycle:Multiplexed Bus, No Read/Write Delay, Extended
ALE
t5
t16
t25
t39
t40
t17
t27
ALE
t38
CSx
A23-A16
(A15-A8)
BHE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t9
Data In
t11
RD
t15
t13
t43
t45
RdCSx
t51
t52
t47
t49
Write Cycle
BUS
t23
Address
Data Out
t56
t9
t11
WR,
WRL, WRH
t22
t13
t43
t45
t50
WrCSx
t49
56/69
3
ST10F167
20.5.8 Demultiplexed Bus
VDD = 5 V ± 5%,VSS = 0 V, TA = -40 to +85 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Table 20.7
Demultiplexed Bus Characteristics
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
15 + tA
0 + tA
–
–
TCL - 10 + tA
TCL - 25 + tA
–
–
ns
ns
ALE high time
Address setup to ALE
t5
t6
CC
CC
ALE falling edge to RD,
WR (with RW-delay)
t8
CC
15 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC
-10 + tA
–
-10 + tA
–
ns
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
t12 CC
25 + tC
–
–
ns
t13
CC
65 + tC
–
–
ns
t14
SR
–
5 + tC
2TCL - 25
+ tC
3TCL - 10
+ tC
–
2TCL - 45
+ tC
ns
RD to valid data in
(no RW-delay)
t15
SR
–
55 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16
SR
–
40
+ tA + tC
–
3TCL - 35
+ tA + tC
ns
Address to valid data in
t17
SR
–
60
+ 2tA + tC
–
4TCL - 40
+ 2tA + tC
ns
Data hold after RD
rising edge
t18
SR
0
–
0
–
ns
Data float after RD rising
edge (with RW-delay)
t20
SR
–
35 + tF
–
2TCL - 15
+ tF
ns
Data float after RD rising
edge (no RW-delay)
t21
SR
–
15 + tF
–
TCL - 10
+ tF
ns
Data valid to WR
t22
CC
15 + tC
–
2TCL - 35
+ tC
–
ns
Data hold after WR
ALE rising edge after RD,
WR
t24
t26
CC
CC
15 + tF
-10 + tF
–
–
TCL - 10 + tF
-10
+ tF
–
–
ns
ns
Address hold after RD, WR t28
ALE falling edge to CS
t38
CC
CC
-2.5 + tF
-5 - tA
–
10 - tA
-2.5 + tF
-5 - tA
–
10 - tA
ns
ns
t39
SR
–
45
+ tC + 2tA
–
3TCL - 30
+ tC + 2tA
ns
CS low to Valid Data In
57/69
3
ST10F167
Table 20.7
Demultiplexed Bus Characteristics (cont’d)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
t41
t42
CC
min.
10 + tF
max.
–
min.
TCL - 15 + tF
max.
–
ns
CC
20 + tA
–
TCL - 5 + tA
–
ns
t43
CC
-5 + tA
–
-5 + tA
–
ns
t46
SR
–
15 + tC
–
2TCL - 35
+ tC
ns
RdCS to Valid Data In
(no RW-delay)
t47
SR
–
50 + tC
–
3TCL - 25
+ tC
ns
RdCS, WrCS Low Time
(with RW-delay)
t48
CC
40 + tC
–
2TCL - 10
+ tC
–
ns
RdCS, WrCS Low Time
(no RW-delay)
t49
CC
65 + tC
–
3TCL - 10
+ tC
–
ns
Data valid to WrCS
t50
t51
t53
CC
35 + tC
–
2TCL - 15 + tC
–
ns
SR
SR
0
–
–
30 + tF
0
–
ns
ns
t68
SR
–
5 + tF
–
–
2TCL - 20
+ tF
TCL - 20
+ tF
Address hold after
RdCS, WrCS
t55
CC
-10 + tF
–
-10
+ tF
–
ns
Data hold after WrCS
t57
CC
10 + tF
–
TCL - 15 + tF
–
ns
CS hold after RD, WR
ALE falling edge to RdCS,
WrCS (with RW-delay)
ALE falling edge to RdCS,
WrCS (no RW-delay)
RdCS to Valid Data In
(with RW-delay)
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
58/69
3
ns
ST10F167
Figure 20.11 External Memory Cycle:Demultiplexed
Normal ALE
t5
t16
Bus,
With
Read/Write
Delay,
t26
ALE
t38
t39
t41
CSx
t17
A23-A16
A15-A0
BHE
t28
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
t14
RD
t12
t42
RdCSx
t51
t53
t46
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL, WRH
t24
Data Out
t57
t8
t22
t12
t42
t50
WrCSx
t48
59/69
3
ST10F167
Figure 20.12 External Memory Cycle:Demultiplexed
Extended ALE
t5
Bus,
With
t16
Read/Write
t26
ALE
t38
t39
t41
CSx
t17
A23-A16
A15-A0
BHE
t28
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
RD
t14
t12
t42
RdCSx
t51
t53
t46
t48
Write Cycle
BUS
(D15-D8)
D7-D0
WR,
WRL, WRH
t24
Data Out
t57
t8
t22
t12
t42
t50
WrCSx
t48
60/69
3
Delay,
ST10F167
Figure 20.13 External Memory Cycle:Demultiplexed Bus, No Read/Write Delay, Normal
ALE
t5
t16
t26
ALE
t38
t39
t41
CSx
t17
A23-A16
A15-A0
BHE
t28
Address
t6
t55
t21
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t9
t15
RD
t43
t13
t51
t68
t47
RdCSx
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t9
WR,
WRL, WRH
t43
t57
t22
t13
t50
WrCSx
t49
61/69
ST10F167
Figure 20.14 External Memory Cycle:Demultiplexed
Extended ALE
t5
Bus,
No
t16
Read/Write
t26
ALE
t38
t39
t41
CSx
t17
A23-A16
A15-A0
BHE
t28
Address
t6
t55
t21
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t9
RD
t15
t13
t43
RdCSx
t51
t68
t47
t49
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
WR,
WRL, WRH
t22
t13
t43
t50
WrCSx
t49
62/69
Delay,
ST10F167
20.5.9 CLKOUT and READY
VDD = 5 V ± 5%, VSS = 0 V, T A = -40 to +85 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF
Table 20.8
CLKOUT and READY Characteristics
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
t29
t30
t31
t32
t33
t34
CC
CC
50
20
50
–
2TCL
TCL – 5
2TCL
–
ns
ns
CC
CC
15
–
–
5
TCL – 10
–
–
5
ns
ns
CC
–
10
–
10
ns
CC
-5 + tA
10 + tA
-5 + tA
10 + tA
ns
Synchronous READY
setup time to CLKOUT
t35
SR
30
–
30
–
ns
Synchronous READY
hold time after CLKOUT
t36
SR
0
–
0
–
ns
Asynchronous READY
low time
Asynchronous READY
setup time 1)
Asynchronous READY
hold time 1)
t37
SR
65
–
2TCL + 15
–
ns
t58
SR
15
–
15
–
ns
t59
SR
0
–
0
–
ns
Async. READY hold time
after RD, WR high (Demultiplexed Bus) 2)
t60
SR
0
0 + tc
+ 2tA + tF
0
TCL - 25
+ tc + 2tA + tF
ns
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to
ALE falling edge
2)
2)
Notes 1:These timings are given for test purposes only, in order to assure recognition at a specific clock
edge.
2:Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum
values. This adds even more time for deactivating READY.
The 2tA and 2tc refer to the next bus cycle, tF refers to the current bus cycle.
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ST10F167
Figure 20.15 CLKOUT and READY
READY
waitstate
Running cycle 1)
CLKOUT
t32
MUX/Tristate 6)
t33
t30
t29
t31
t34
ALE
7)
Command
RD, WR
2)
t35
Sync
READY
t59
t58
3)
t35
t36
3)
3)
t58
Async
READY
t36
t59
t60
4)
3)
5)
t37
see 6)
Notes 1:Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2:The leading edge of the respective command depends on RW-delay.
3:READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4:READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR).
5:If the Asynchronous READY signal does not fulfil the indicated setup and hold times with respect
to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfil t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)).
6:Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC
waitstate may be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed
bus without MTTC waitstate this delay is zero.
7:The next external bus cycle may start here.
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ST10F167
20.5.10 External Bus Arbitration
VDD = 5 V ± 5%, VSS = 0 V, T A = -40 to +85 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF, CL (for Port 6, CS) = 100 pF
Table 20.9
External Bus Arbitration Characteristics
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
HOLD input setup time
to CLKOUT
CLKOUT to HLDA high
or BREQ low delay
CLKOUT to HLDA low
or BREQ high delay
CSx release
t61
SR
35
–
35
–
ns
t62
CC
–
20
–
20
ns
t63
CC
–
20
–
20
ns
t64
CC
–
20
–
20
ns
CSx drive
Other signals release
t65
t66
CC
CC
-5
–
25
20
-5
–
25
20
ns
ns
Other signals drive
t67
CC
-5
25
-5
25
ns
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ST10F167
Figure 20.16 External Bus Arbitration, Releasing the Bus
CLKOUT
t61
HOLD
t63
HLDA
1)
t62
2)
BREQ
t64
3)
CSx
(On P6.x)
t66
Other
Signals
1)
Notes 1:The ST10F167 will complete the currently running bus cycle before granting bus access.
2:This is the first possibility for BREQ to get active.
3:The CS outputs will be resistive high (pullup) after t64.
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ST10F167
Figure 20.17 External Bus Arbitration (Regaining the Bus)
2)
CLKOUT
t61
HOLD
t62
HLDA
t62
BREQ
t62
t63
1)
t65
CSx
(On P6.x)
t67
Other
Signals
Notes 1:This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the ST10F167 requesting the bus.
2:The next ST10F167 driven bus cycle may start here.
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ST10F167
21
PACKAGE MECHANICAL DATA
Figure 21.1
Package Outline PQFP144 (28 x 28 mm)
mm
inches
D im
min
ty
A
max
min
ty
4.07
A1
0.25
A2
3.17
B
0.010
3.67
0.125
0.22
0.38
0.009
C
0.13
0.23
0.005
D
30.95
31.20
31.45
1.129
1.228
1.238
D1
27.90
28.00
28.10
1.098
1.120
1.106
D3
3.42
22.75
e
0.315
0.015
0.009
0.896
0.65
0.02-
30.95
31.20
31.45
1.219
1.228
1.238
E1
27.90
28.00
28.10
1.098
1.102
1.106
L
L1
22.75
0.65
0.80
0.896
0.95
0.026
1.60
K
0.031
0.063
0°(min), 7°(max)
Number of Pins
22
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0.144
E
E3
VR02061A
max
0.106
N1
144
ORDERING INFORMATION
Salestype
Temperature range
Package
ST10F167-Q6
-40°C to 85°C
PQFP144 (28 x 28)
0.037
Notes
Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-TH OMSON Microelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
without the express written approval of SGS-THO MSON Microelectronics.
1997 SGS-TH OMSON Microelectronics - All rights reserved.
SGS-THOMSON Microelectronics Group of Companies
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco
The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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