STMICROELECTRONICS ST72324J6

ST72324
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,
4 TIMERS, SPI, SCI INTERFACE
■
■
■
■
■
Memories
– 8 to 32K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and InCircuit Programming for HDFlash devices
– 384 to 1K bytes RAM
– HDFlash endurance: 100 cycles, data retention: 20 years at 55°C
Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for
main supply with 3 programmable reset
thresholds and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security
system and bypass for external clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
Interrupt Management
– Nested interrupt controller
– 10 interrupt vectors plus TRAP and RESET
– 9/6 external interrupt lines (on 4 vectors)
Up to 32 I/O Ports
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
4 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– 16-bit Timer A with: 1 input capture, 1 output
compare, external clock input, PWM and
pulse generator modes
– 16-bit Timer B with: 2 input captures, 2 output
compares, PWM and pulse generator modes
TQFP44
10 x 10
SDIP42
600 mil
■
■
TQFP32
7x7
SDIP32
400 mil
2 Communication Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface (LIN compatible)
1 Analog Peripheral
– 10-bit ADC with up to 12 input pins
■
Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
■
Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range (ROM)
Temp. Range (Flash)
Packages
ST72324(J/K)6
ST72324(J/K)4
ST72324(J/K)2
32K
16K
8K
1024 (256)
512 (256)
384 (256)
3.8V to 5.5V (low voltage Flash version planned with 3.0 to 3.6V range)
up to -40°C to +125°C
up to -40°C to +125°C
-40°C to +85 °C
SDIP42 (JxB), TQFP44 10x10 (JxT),SDIP32 (KxB), TQFP32 7x7 (KxT)
Rev. 1.9
August 2003
1/161
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
4.3
STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5
ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7
RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0
5.3
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2
MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3
RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
26
26
27
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
29
29
30
31
31
7.2
MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3
INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4
CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5
INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.6
EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 38
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
161
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.2
SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2/161
2
Table of Contents
8.3
WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4
ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
42
43
45
45
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
45
48
9.4
LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . .
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) .
51
51
51
52
54
54
54
54
54
56
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
56
56
56
57
57
57
59
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
59
59
71
71
71
72
78
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
78
78
82
83
3/161
1
Table of Contents
10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
85
86
89
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
103
104
104
104
105
107
107
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
108
108
108
108
109
109
110
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
113
113
113
113
114
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
114
114
115
115
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3.2 General Operating Conditions for low voltage Flash devices (planned) . . . . . . . . 116
12.3.3 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 117
12.3.4 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
161
12.4.1 RUN and SLOW Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.4.2 WAIT and SLOW WAIT Modes (Flash devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4/161
1
Table of Contents
12.4.3 RUN and SLOW Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.4 WAIT and SLOW WAIT Modes (ROM devices) . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.5 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.6 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.7 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
121
122
122
123
124
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
124
125
127
128
128
129
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
130
131
133
135
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 140
12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
143
143
144
145
145
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 149
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 151
14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5/161
1
Table of Contents
15.1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.2 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.2.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.2 CSS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.3 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.5 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2.6 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3 FLASH REV “X” AND ALL ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
157
157
157
157
157
158
15.3.1 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.3 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.4 LVD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.4 ALL ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
158
158
158
158
15.4.1 AVD not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
15.4.2 Internal RC oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet.
Please also pay special attention to the Section “IMPORTANT NOTES” on page 157
6/161
1
ST72324
1 INTRODUCTION
The ST72324K and ST72324J devices are members of the ST7 microcontroller family. They can
be grouped as follows:
– The 32-pin ST72324K devices are designed for
mid-range applications
– The 42/44-pin ST72324J devices target the
same range of applications requiring more than
24 I/O ports.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH or ROM program memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram
8-BIT CORE
ALU
RESET
VPP
VSS
VDD
PROGRAM
MEMORY
(8K - 60K Bytes)
CONTROL
RAM
(384 - 2048 Bytes)
LVD
WATCHDOG
OSC1
OSC2
OSC
PORT F
PF7:6,4,2:0
(6 bits on J devices)
(5 bits on K devices)
TIMER A
BEEP
ADDRESS AND DATA BUS
MCC/RTC/BEEP
PORT A
PA7:3
(5 bits on J devices)
(4 bits on K devices)
PORT B
PB4:0
(5 bits on J devices)
(3 bits on K devices)
PORT E
PE1:0
(2 bits)
PORT C
SCI
TIMER B
PC7:0
(8 bits)
PORT D
PD5:0
(6 bits on J devices)
(2 bits on K devices)
SPI
10-BIT ADC
VAREF
VSSA
7/161
3
ST72324
2 PIN DESCRIPTION
PE0 / TDO
VDD_2
OSC1
OSC2
VSS_2
RESET
VPP / ICCSEL
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
ei0
31
ei2
4
30
5
29
ei3
6
28
7
27
8
26
9
25
ei1
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
VSS_1
VDD_1
PA3 (HS)
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
AIN5 / PD5
VAREF
VSSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
(HS) PF2
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
VDD_0
VSS_0
RDI / PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
1
2
ei3
ei2
3
4
42
41
PB3
PB2
40
39
PB1
PB0
AIN3 / PD3
5
38
PE1 / RDI
AIN4 / PD4
AIN5 / PD5
6
7
37
36
PE0 / TDO
VDD_2
VAREF
8
35
34
OSC1
VSSA
MCO / AIN8 / PF0
9
10
BEEP / (HS) PF1
11
(HS) PF2
AIN10 / OCMP1_A / PF4
12
13
31
30
VPP / ICCSEL
PA7 (HS)
29
28
PA6 (HS)
ICAP1_A / (HS) PF6
14
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
15
16
AIN13 / OCMP1_B / PC1
17
ICAP2_B/ (HS) PC2
ICAP1_B / (HS) PC3
18
19
ICCDATA / MISO / PC4
AIN14 / MOSI / PC5
33
32
ei1
27
26
25
ei0
OSC2
VSS_2
RESET
PA5 (HS)
PA4 (HS)
VSS_1
VDD_1
PA3 (HS)
20
24
23
PC7 / SS / AIN15
21
22
PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector
8/161
ST72324
PIN DESCRIPTION (Cont’d)
Figure 3. 32-Pin SDIP Package Pinout
(HS) PB4
1
ei3
32
ei2
PB3
AIN0 / PD0
2
31
PB0
AIN1 / PD1
3
30
PE1 / RDI
VAREF
4
29
PE0 / TDO
VSSA
5
28
VDD_2
MCO / AIN8 / PF0
6
27
OSC1
BEEP / (HS) PF1
7
26
OSC2
OCMP1_A / AIN10 / PF4
8
25
VSS_2
ICAP1_A / (HS) PF6
9
24
RESET
ei1
EXTCLK_A / (HS) PF7
10
23
VPP / ICCSEL
AIN12 / OCMP2_B / PC0
11
22
PA7 (HS)
AIN13 / OCMP1_B / PC1
12
21
PA6 (HS)
ICAP2_B / (HS) PC2
13
20
PA4 (HS)
ICAP1_B / (HS) PC3
14
ICCDATA/ MISO / PC4
AIN14 / MOSI / PC5
19
PA3 (HS)
15
18
PC7 / SS / AIN15
16
17
PC6 / SCK / ICCCLK
ei0
(HS) 20mA high sink capability
eix associated external interrupt vector
PD1 / AIN1
PD0 / AIN0
PB4 (HS)
PB3
PB0
PE1 / RDI
PE0 / TDO
VDD_2
Figure 4. 32-Pin TQFP 7x7 Package Pinout
32 31 30 29 28 27 26 25
24
1
ei3 ei2
23
2
22
3
ei1
21
4
20
5
19
6
18
7
ei0 17
8
9 10 11 12 13 14 15 16
AIN13 / OCMP1_B / PC1
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA / MISO / PC4
AIN14 / MOSI / PC5
ICCCLK / SCK / PC6
AIN15 / SS / PC7
(HS) PA3
VAREF
VSSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
OSC1
OSC2
VSS_2
RESET
VPP / ICCSEL
PA7 (HS)
PA6 (HS)
PA4 (HS)
(HS) 20mA high sink capability
eix associated external interrupt vector
9/161
ST72324
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 113.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output:
OD = open drain 2), PP = push-pull
Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
1 30 1
PB4 (HS)5)
I/O CT
HS
X
X
X
Port B4
7
2 31 2
PD0/AIN0
X
X
X
X
X
Port D0
ADC Analog Input 0
8
3 32 3
PD1/AIN1
I/O CT
I/O CT
X
X
X
X
X
Port D1
ADC Analog Input 1
9
4
PD2/AIN2
X
X
X
X
X
Port D2
ADC Analog Input 2
10 5
PD3/AIN3
I/O CT
I/O CT
X
X
X
X
X
Port D3
ADC Analog Input 3
11 6
PD4/AIN4
I/O CT
X
X
X
X
X
Port D4
ADC Analog Input 4
12 7
PD5/AIN5
I/O CT
S
X
X
X
X
X
Port D5
ADC Analog Input 5
13 8
1
4
VAREF
14 9
2
5
VSSA
15 10 3
6
PF0/MCO/AIN8
I/O CT
16 11 4
7
PF1 (HS)/BEEP
I/O CT
PF2 (HS)
I/O CT
17 12
ei3
Alternate Function
PP
ana
int
Input
wpu
Pin Name
OD
float
6
SDIP32
Output
Main
function
Output
(after
reset)
Input
Port
SDIP42
Type
Level
TQFP44
TQFP32
Pin n°
Analog Reference Voltage for ADC
S
Analog Ground Voltage
X
ei1
HS
X
ei1
HS
X
X
ei1
X
X
Port F0
Main clock
out (fOSC/2)
X
X
Port F1
Beep signal output
X
X
Port F2
X
X
Port F4
Timer A OutADC Analog
put ComInput 10
pare 1
ADC Analog
Input 8
18 13 5
8
PF4/OCMP1_A/
AIN10
I/O CT
19 14 6
9
PF6 (HS)/ICAP1_A
I/O CT
20 15 7 10
PF7 (HS)/
EXTCLK_A
I/O CT
21
VDD_0
S
Digital Main Supply Voltage
22
VSS_0
S
Digital Ground Voltage
23 16 8 11
PC0/OCMP2_B/
AIN12
10/161
I/O CT
X
X
HS
X
X
X
X
Port F6
Timer A Input Capture 1
HS
X
X
X
X
Port F7
Timer A External Clock
Source
X
X
X
X
X
X
Port C0
Timer B OutADC Analog
put ComInput 12
pare 2
ST72324
X
HS
X
X
Port C1
Timer B OutADC Analog
put ComInput 13
pare 1
X
X
X
Port C2
Timer B Input Capture 2
X
X
X
X
Port C3
Timer B Input Capture 1
X
X
Port C4
SPI Master
In / Slave
Out Data
ICC Data Input
X
X
Port C5
SPI Master
Out / Slave
In Data
ADC Analog
Input 14
X
X
Port C6
SPI Serial
Clock
ICC Clock
Output
X
X
Port C7
SPI Slave
Select (active low)
ADC Analog
Input 15
X
X
Port A3
26 19 11 14 PC3 (HS)/ICAP1_B
I/O CT
I/O CT
PC4/MISO/ICCDATA
I/O CT
X
X
28 21 13 16 PC5/MOSI/AIN14
I/O CT
X
X
29 22 14 17 PC6/SCK/ICCCLK
I/O CT
X
X
30 23 15 18 PC7/SS/AIN15
I/O CT
X
X
31 24 16 19 PA3 (HS)
I/O CT
S
27 20 12 15
32 25
VDD_1
33 26
VSS_1
HS
X
X
X
X
ei0
Digital Main Supply Voltage
S
Digital Ground Voltage
34 27 17 20 PA4 (HS)
I/O CT
HS
X
X
X
X
Port A4
35 28
HS
X
X
X
X
Port A5
36 29 18 21 PA6 (HS)
I/O CT
I/O CT
HS
X
T
Port A6 1)
37 30 19 22 PA7 (HS)
I/O CT
HS
X
T
Port A7 1)
PA5 (HS)
38 31 20 23 VPP /ICCSEL
39 32 21 24 RESET
40 33 22 25 VSS_2
41 34 23 26 OSC2
Alternate Function
PP
HS
Main
function
Output
(after
reset)
OD
X
ana
X
I/O CT
int
Output
Input
wpu
25 18 10 13 PC2 (HS)/ICAP2_B
Port
float
PC1/OCMP1_B/
AIN13
Type
SDIP32
TQFP32
SDIP42
TQFP44
24 17 9 12
Pin Name
Input
Level
Pin n°
Must be tied low. In the flash programming mode, this pin acts as the
programming voltage input VPP. See
Section 12.9.2 for more details. High
voltage must not be applied to ROM
devices.
I
I/O CT
Top priority non maskable interrupt.
S
Digital Ground Voltage
O
Resonator oscillator inverter output
42 35 24 27 OSC1
I
External clock input or Resonator oscillator inverter input
43 36 25 28 VDD_2
44 37 26 29 PE0/TDO
S
Digital Main Supply Voltage
1 38 27 30 PE1/RDI
2 39 28 31 PB0
I/O CT
X
X
X
X
Port E0
SCI Transmit Data Out
I/O CT
I/O CT
X
X
X
X
Port E1
SCI Receive Data In
X
ei2
X
X
Port B0
X
ei2
X
X
Port B1
X
ei2
X
X
Port B2
X
X
X
Port B3
3 40
PB1
4 41
PB2
I/O CT
I/O CT
5 42 29 32 PB3
I/O CT
ei2
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
11/161
ST72324
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See See “I/O PORTS” on page 45. and Section 12.8 I/O PORT PIN CHARACTERISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current
consumption.
5. In ROM devices, there is no weak pull-up on PB4.
12/161
ST72324
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, up to 1024 bytes of
RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for
the stack from 0100h to 01FFh.
The highest address bytes contain the user reset
and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the
device.
Figure 5. Memory Map
0000h
007Fh
0080h
HW Registers
(see Table 2)
087Fh
0880h
Reserved
0FFFh
1000h
Program Memory
(32K, 16K or 8K)
FFFFh
Short Addressing
RAM (zero page)
00FFh
0100h
RAM
(1024,
512 or 384 Bytes)
FFDFh
FFE0h
0080h
Interrupt & Reset Vectors
(see Table 7)
256 Bytes Stack
01FFh
0200h
16-bit Addressing
RAM
027Fh
or 047Fh
8000h
C000h
32 KBytes
16 KBytes
E000h
8 Kbytes
FFFFh
13/161
ST72324
Table 2. Hardware Register Map
Register
Label
Block
0000h
0001h
0002h
Port A2)
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h1)
00h
00h
R/W
R/W
R/W
0003h
0004h
0005h
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h1)
00h
00h
R/W
R/W
R/W
0006h
0007h
0008h
Port C
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h1)
00h
00h
R/W
R/W
R/W
D2)
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h1)
00h
00h
R/W
R/W
R/W
0009h
000Ah
000Bh
Port
Register Name
Reset
Status
Address
Remarks
000Ch
000Dh
000Eh
Port E
2)
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h1)
00h
00h
R/W
R/W2)
R/W2)
000Fh
0010h
0011h
Port F 2)
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h1)
00h
00h
R/W
R/W
R/W
0012h
to
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
Reserved Area (15 Bytes)
SPI
ITC
0028h
0029h
FLASH
002Ah
WATCHDOG
002Bh
002Ch
002Dh
002Eh
to
0030h
14/161
MCC
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt
Interrupt
Interrupt
Interrupt
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
EICR
External Interrupt Control Register
00h
R/W
FCSR
Flash Control/Status Register
00h
R/W
WDGCR
Watchdog Control Register
7Fh
R/W
SICSR
System Integrity Control/Status Register
MCCSR
MCCBCR
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
Software Priority
Software Priority
Software Priority
Software Priority
Register 0
Register 1
Register 2
Register 3
Reserved Area (3 Bytes)
000x 000x b R/W
00h
00h
R/W
R/W
ST72324
Address
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Block
TIMER A
Register
Label
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
Register Name
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register5
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Reserved3
Reserved3
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
Reset
Status
Remarks
00h
00h
xxx0 x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
80h
00h
Write Only4
Write Only4
Reserved Area (1 Byte)
TIMER B
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCI
0070h
0071h
0072h
ADC
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
00h
00h
xxxx x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
C0h
xxh
00h
x000 0000b
00h
00h
--00h
Read Only
R/W
R/W
R/W
R/W
R/W
SCIETPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read Only
Read Only
0073h
007Fh
R/W
Reserved Area (13 Bytes)
Legend: x=undefined, R/W=read/write
15/161
ST72324
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. These registers and the ICF2 and OCF2 flags are not present in the ST72324 but are present in the
emulator. For compatibility with the emulator, it is recommended to perform a dummy access (read or
write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.
4. The registers can be written, but reading them will return undefined values.
5. Bits 2 and 4 of this register (ICF2 and OCF2) are forced by hardware to 0. Consequently, the corresponding interrupts cannot be used.
16/161
ST72324
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).
Table 3. Sectors available in Flash devices
Flash Size (bytes)
Available Sectors
4K
Sector 0
4.2 Main Features
■
■
■
■
Three Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be programmed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be programmed or erased without removing the device from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the
application is running.
ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Read-out protection against piracy
Register Access Security System (RASS) to
prevent accidental programming or erasing
4.3 Structure
8K
Sectors 0,1
> 8K
Sectors 0,1, 2
4.3.1 Read-out Protection
Read-out protection, when selected, makes it impossible to extract the memory content from the
microcontroller, thus preventing piracy. Even ST
cannot access the user code.
In flash devices, this protection is removed by reprogramming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
Read-out protection selection depends on the device type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
The Flash memory is organised in sectors and can
be used for both code and data storage.
Figure 6. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
1000h
FLASH
MEMORY SIZE
3FFFh
7FFFh
9FFFh
SECTOR 2
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
2 Kbytes
8 Kbytes
16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
17/161
ST72324
FLASH PROGRAM MEMORY (Cont’d)
–
–
–
–
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/VPP: programming voltage
OSC1(or OSCIN): main clock input for external source (optional)
– VDD: application board power supply (optional, see Figure 7, Note 3)
4.4 ICC Interface
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 7).
These pins are:
– RESET: device reset
– VSS: device power supply ground
Figure 7. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
OPTIONAL
(See Note 3)
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
APPLICATION
RESET SOURCE
See Note 2
10kΩ
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the application RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
18/161
ICCDATA
ICCCLK
ST7
RESET
See Note 1
ICCSEL/VPP
OSC1
CL1
OSC2
VDD
CL2
VSS
APPLICATION
POWER SUPPLY
APPLICATION
I/O
agement IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
ST72324
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the specific microcontroller device, the user needs only to
implement the ICP hardware interface on the application board (see Figure 7). For more details on
the pin locations, refer to the device pinout description.
4.6 IAP (In-Application Programming)
Register
Label
0029h
FCSR
Reset Value
4.7 Related Documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.7.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read /Write
Reset Value: 0000 0000 (00h)
7
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
Address
(Hex.)
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
0
0
0
0
0
0
0
0
0
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations. Flash Control/Status Register Address and Reset Value
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
19/161
ST72324
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
5.2 MAIN FEATURES
■
■
■
■
■
■
■
■
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect
addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power HALT and WAIT modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
Figure 8. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
20/161
ST72324
CENTRAL PROCESSING UNIT (Cont’d)
Bit 1 = Z Zero.
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
7
1
0
1
I1
H
I0
N
Z
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative .
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
I1
1
0
0
1
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
21/161
ST72324
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15
0
8
0
0
0
0
0
0
7
SP7
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
CC
A
CC
A
X
X
X
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
22/161
SP
PCH
SP
@ 01FFh
Y
CC
A
SP
SP
ST72324
6 SUPPLY, RESET AND CLOCK MANAGEMENT
6.1 PHASE LOCKED LOOP
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An
overview is shown in Figure 11.
For more details, refer to dedicated parametric
section.
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for applications where timing accuracy is required. See
“PLL Characteristics” on page 128.
Main features
■ Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
– Clock Security System (CSS) with Clock Filter
and Backup Safe Oscillator (enabled by option byte)
Figure 10. PLL Block Diagram
PLL x 2
0
/2
1
fOSC
fOSC2
PLL OPTION BIT
Figure 11. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT
CLOCK SECURITY SYSTEM
(CSS)
OSC2
MULTI-
fOSC
OSCILLATOR
OSC1
(MO)
RESET SEQUENCE
RESET
MANAGER
(RSM)
fOSC2
PLL
(option)
CLOCK
SAFE
FILTER
OSC
fOSC2
AVD Interrupt Request
SICSR
AVD AVD LVD
0
IE
F RF
MAIN CLOCK
fCPU
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
WATCHDOG
TIMER (WDG)
0
CSS CSS WDG
IE D RF
CSS Interrupt Request
LOW VOLTAGE
VSS
DETECTOR
VDD
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
23/161
ST72324
6.2 MULTI-OSCILLATOR (MO)
24/161
Table 4. ST7 Clock Sources
External Clock
Hardware Configuration
Crystal/Ceramic Resonators
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Note: External clock source is not supported with
the PLL enabled.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 14.1 on page 149 for more details on
the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscillator pins in order to minimize output distortion and
start-up stabilization time. The loading capacitance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has
the drawback of a lower frequency accuracy and
should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied
to ground.
Internal RC Oscillator
The main clock of the ST7 can be generated by
three different source types coming from the multioscillator block:
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 4. Refer to the
electrical characteristics section for more details.
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered
undefined when the OSC pins are left unconnected.
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
CL1
OSC2
LOAD
CAPACITORS
ST7
OSC1
OSC2
CL2
ST72324
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 13:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 12:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see Section 14.1 on page 149).
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 12. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
“CONTROL PIN CHARACTERISTICS” on
page 138 for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
Figure 13. Reset Block Diagram
VDD
RON
RESET
INTERNAL
RESET
Filter
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
25/161
ST72324
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
If the external RESET pulse is shorter than
tw(RSTL)out (see short ext. Reset in Figure 14), the
signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see long ext.
Reset in Figure 14). Starting from the external RESET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
tw(RSTL)out.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency.
(see “OPERATING CONDITIONS” on page 115)
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC network connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 14.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 14. RESET Sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
RUN
SHORT EXT.
RESET
RUN
ACTIVE PHASE
tw(RSTL)out
th(RSTL)in
LONG EXT.
RESET
RUN
ACTIVE
PHASE
ACTIVE
PHASE
WATCHDOG
RESET
RUN
ACTIVE
PHASE
RUN
tw(RSTL)out
tw(RSTL)out
th(RSTL)in
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU )
VECTOR FETCH
26/161
ST72324
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD), Auxiliary Voltage
Detector (AVD) functions and Clock Security System (CSS). It is managed by the SICSR register.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is
below a VIT- reference value. This means that it
secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
– VIT+ when VDD is rising
– VIT- when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
If the medium or low thresholds are selected, the
detection may occur outside the specified operating voltage range. Below 3.8V, device operation is
not guaranteed.
The LVD is an optional function which can be selected by option byte.
Figure 15. Low Voltage Detector vs Reset
VDD
Vhys
VIT+
VIT-
RESET
27/161
ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a VIT-(AVD) and
VIT+(AVD) reference value and the VDD main supply. The VIT- reference value for falling voltage is
lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
6.4.2.1 Monitoring the VDD Main Supply
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see Section 14.1 on page 149).
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or
VIT-(AVD) threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcontroller. See Figure 16.
The interrupt on the rising edge is used to inform
the application that the VDD warning state is over.
If the voltage rise time trv is less than 256 or 4096
CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles then:
– If the AVD interrupt is enabled before the
VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
– If the AVD interrupt is enabled after the VIT+(AVD)
threshold is reached then only one AVD interrupt
will occur.
Figure 16. Using the AVD to Monitor VDD
VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
AVDF bit
trv VOLTAGE RISE TIME
0
1
RESET VALUE
1
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
LVD RESET
28/161
INTERRUPT PROCESS
ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Clock Security System (CSS)
The Clock Security System (CSS) protects the
ST7 against breakdowns, spikes and overfrequencies occurring on the main clock source (fOSC). It
is based on a clock filter and a clock detection control with an internal safe oscillator (fSFOSC).
Caution: The CSS function is not guaranteed. Refer to Section 15
6.4.3.1 Clock Filter Control
The PLL has an integrated glitch filtering capability
making it possible to protect the internal clock from
overfrequencies created by individual spikes. This
feature is available only when the PLL is enabled.
If glitches occur on fOSC (for example, due to loose
connection or noise), the CSS filters these automatically, so the internal CPU frequency (fCPU)
continues deliver a glitch-free signal (see Figure
17).
6.4.3.2 Clock detection Control
If the clock signal disappears (due to a broken or
disconnected resonator...), the safe oscillator delivers a low frequency clock signal (fSFOSC) which
allows the ST7 to perform some rescue operations.
Automatically, the ST7 clock source switches back
from the safe oscillator (fSFOSC) if the main clock
source (fOSC) recovers.
When the internal clock (fCPU) is driven by the safe
oscillator (fSFOSC), the application software is notified by hardware setting the CSSD bit in the SIC-
SR register. An interrupt can be generated if the
CSSIE bit has been previously set.
These two bits are described in the SICSR register
description.
6.4.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.
The CRSR register is frozen.
The CSS (including the safe oscillator) is
disabled until HALT mode is exited. The
previous CSS configuration resumes when
the MCU is woken up by an interrupt with
“exit from HALT mode” capability or from
the counter reset value when the MCU is
woken up by a RESET.
6.4.4.1 Interrupts
The CSS or AVD interrupt events generate an interrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).
Interrupt Event
Enable
Event
Control
Flag
Bit
CSS event detection
(safe oscillator acti- CSSD
vated as main clock)
AVD event
AVDF
Exit
from
Wait
Exit
from
Halt
CSSIE
Yes
No
AVDIE
Yes
No
Figure 17. Clock Filter Function
PLL ON
Clock Filter Function
fOSC2
fCPU
Clock Detection Function
fOSC2
fSFOSC
fCPU
29/161
ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.5 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read /Write
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
Reset Value: 000x 000x (00h)
CSSIE bit has no effect.
7
0
AVD
IE
AVD
F
LVD
RF
0
CSS
IE
CSS WDG
D
RF
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt information is automatically cleared when software enters
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to
Figure 16 and to Section 6.4.2.1 for additional details.
0: VDD over VIT+(AVD) threshold
1: VDD under VIT-(AVD) threshold
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bits 3 = Reserved, must be kept cleared.
Bit 2 = CSSIE Clock security syst interrupt enable
This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
.
30/161
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
Clock Security System block has been selected by
hardware due to a disturbance on the main clock
signal (fOSC). It is set by hardware and cleared by
reading the SICSR register when the original oscillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET Sources
LVDRF
WDGRF
External RESET pin
Watchdog
LVD
0
0
1
0
1
X
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
ST72324
7 INTERRUPTS
7.1 INTRODUCTION
The ST7 enhanced interrupt management provides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nested) ST7 interrupt controller.
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 5. Interrupt Software Priority Levels
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The processing flow is shown in Figure 18
Level
Low
I1
1
0
0
1
High
I0
0
1
0
1
Figure 18. Interrupt Processing Flowchart
N
FETCH NEXT
INSTRUCTION
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
Y
TRAP
Interrupt has the same or a
lower software priority
than current one
THE INTERRUPT
STAYS PENDING
Y
N
I1:0
Interrupt has a higher
software priority
than current one
PENDING
INTERRUPT
RESET
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
31/161
ST72324
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is determined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software priority then the interrupt with the highest hardware
priority is serviced first.
Figure 19 describes this decision process.
Figure 19. Priority Decision Process
PENDING
INTERRUPTS
Same
SOFTWARE
PRIORITY
Different
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its
software priority combined with the hardware priority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET and TRAP can be considered as
having the highest software priority in the decision
process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 18). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
32/161
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
■ TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced according to the flowchart in Figure 18.
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear sequence is executed.
ST72324
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exiting HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision process shown in Figure 19.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
The following Figure 20 and Figure 21 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in
Figure 21. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.
Warning: A stack overflow may occur without notifying the software of the failure.
IT0
TRAP
IT3
IT4
IT1
SOFTWARE
PRIORITY
LEVEL
TRAP
IT0
IT1
IT1
IT2
IT3
I1
I0
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
USED STACK = 10 BYTES
HARDWARE PRIORITY
IT2
Figure 20. Concurrent Interrupt Management
RIM
IT4
MAIN
MAIN
11 / 10
3/0
10
IT0
TRAP
IT3
IT4
IT1
SOFTWARE
PRIORITY
LEVEL
TRAP
IT0
IT1
IT1
IT2
IT2
IT3
I1
I0
3
1 1
3
1 1
2
0 0
1
0 1
3
1 1
3
1 1
RIM
IT4
MAIN
11 / 10
IT4
MAIN
USED STACK = 20 BYTES
HARDWARE PRIORITY
IT2
Figure 21. Nested Interrupt Management
3/0
10
33/161
ST72324
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read /Write
Reset Value: 111x 1010 (xAh)
7
1
0
1
I1
H
I0
N
Z
Level
Low
High
I1
1
0
0
1
7
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TRAP and RESET events can interrupt a
level 3 program.
0
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
ISPR2
I1_11 I0_11 I1_10 I0_10 I1_9
I0_9
I1_8
I0_8
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This correspondance is shown in the following table.
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
FFE1h-FFE0h
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
I1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)
The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the interrupt x).
34/161
ST72324
INTERRUPTS (Cont’d)
Table 6. Dedicated Interrupt Instruction Set
Instruction
HALT
New Description
Function/Example
Entering Halt mode
I1
H
1
I0
N
Z
C
0
IRET
Interrupt routine return
Pop CC, A, X, PC
JRM
Jump if I1:0=11 (level 3)
I1:0=11 ?
I1
H
I0
N
Z
C
JRNM
Jump if I1:0<>11
I1:0<>11 ?
POP CC
Pop CC from the Stack
Mem => CC
RIM
Enable interrupt (level 0 set)
Load 10 in I1:0 of CC
I1
H
I0
N
Z
C
SIM
Disable interrupt (level 3 set)
Load 11 in I1:0 of CC
1
1
TRAP
Software trap
Software NMI
1
1
WFI
Wait for interrupt
1
0
1
0
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
35/161
ST72324
INTERRUPTS (Cont’d)
Table 7. Interrupt Mapping
N°
Source
Block
RESET
TRAP
Register
Label
Description
Reset
N/A
Software interrupt
0
Priority
Order
Exit
from
HALT1)
yes
FFFEh-FFFFh
no
FFFCh-FFFDh
Not used
1
MCC/RTC
CSS
2
ei0
External interrupt port A3..0
3
ei1
External interrupt port F2..0
4
ei2
External interrupt port B3..0
5
ei3
External interrupt port B7..4
7
SPI
SPI peripheral interrupts
8
TIMER A
9
TIMER B
Address
Vector
FFFAh-FFFBh
Main clock controller time base interrupt
Safe oscillator activation interrupt
MCCSR
SICSR
Higher
Priority
N/A
yes
FFF8h-FFF9h
yes
FFF6h-FFF7h
yes
FFF4h-FFF5h
yes
FFF2h-FFF3h
yes
FFF0h-FFF1h
SPICSR
yes2
FFECh-FFEDh
TIMER A peripheral interrupts
TASR
no
FFEAh-FFEBh
TIMER B peripheral interrupts
TBSR
no
FFE8h-FFE9h
no
FFE6h-FFE7h
no
FFE4h-FFE5h
10
SCI
SCI Peripheral interrupts
SCISR
11
AVD
Auxiliary Voltage detector interrupt
SICSR
Lower
Priority
Notes:
1. Valid for HALT mode except for the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT
mode.
2. Exit from HALT possible when SPI is in slave mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 22). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
36/161
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the
EICR.
■
■
ST72324
INTERRUPTS (Cont’d)
Figure 22. External Interrupt Control bits
PORT A3 INTERRUPT
PAOR.3
PADDR.3
EICR
IS20
IS21
ei0 INTERRUPT SOURCE
SENSITIVITY
PA3
CONTROL
IPA BIT
PORT F [2:0] INTERRUPTS
EICR
IS20
PFOR.2
PFDDR.2
IS21
SENSITIVITY
PF2
CONTROL
PORT B [3:0] INTERRUPTS
PBOR.3
PBDDR.3
IS10
IS11
SENSITIVITY
CONTROL
IPB BIT
PBOR.7
PBDDR.7
PB7
ei1 INTERRUPT SOURCE
EICR
PB3
PORT B [7:4] INTERRUPTS
PF2
PF1
PF0
PB3
PB2
PB1
PB0
ei2 INTERRUPT SOURCE
EICR
IS10
IS11
SENSITIVITY
CONTROL
PB7
PB6
PB5
PB4
ei3 INTERRUPT SOURCE
37/161
ST72324
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
Read /Write
Reset Value: 0000 0000 (00h)
7
IS11
0
IS10
IPB
IS21
IS20
IPA
0
0
- ei0 (port A3..0)
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
External Interrupt Sensitivity
IS21 IS20
Falling edge &
low level
Rising edge
& high level
0
IPB bit =1
0
1
Rising edge only
Falling edge only
1
0
Falling edge only
Rising edge only
1
1
IS11 IS10
0
0
Falling edge &
low level
Rising edge
& high level
0
1
Rising edge only
Falling edge only
1
0
Falling edge only
Rising edge only
1
1
Rising and falling edge
Rising and falling edge
- ei1 (port F2..0)
IS21 IS20
- ei3 (port B4)
IS11 IS10
IPA bit =1
0
External Interrupt Sensitivity
IPB bit =0
IPA bit =0
External Interrupt Sensitivity
0
0
Falling edge & low level
External Interrupt Sensitivity
0
1
Rising edge only
0
0
Falling edge & low level
1
0
Falling edge only
0
1
Rising edge only
1
1
Rising and falling edge
1
0
Falling edge only
1
1
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
38/161
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.
ST72324
INTERRUPTS (Cont’d)
Table 8. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
0024h
ISPR0
Reset Value
I1_3
1
6
5
I0_3
1
I1_2
1
ei1
4
3
I0_2
1
I1_1
1
ei0
ISPR1
Reset Value
I1_7
1
0026h
ISPR2
Reset Value
0027h
ISPR3
Reset Value
EICR
Reset Value
I0_1
1
1
ei3
I0_7
1
I1_6
1
I1_11
1
I0_11
1
1
IS11
0
1
IS10
0
0
1
ei2
I0_6
1
I1_5
1
I1_10
1
I0_10
1
TIMER B
I1_9
I0_9
1
1
TIMER A
I1_8
I0_8
1
1
1
IPB
0
1
IS21
0
I1_13
1
IS20
0
I1_12
1
I0_12
1
0
0
AVD
0028h
1
MCC + SI
SPI
0025h
2
SCI
I0_5
1
I0_13
1
IPA
0
I1_4
1
I0_4
1
39/161
ST72324
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the application in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 23): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT.
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(fOSC2).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU) to
the available supply voltage.
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2)
can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency
(fCPU).
Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in
SLOW mode.
Figure 23. Power Saving Mode Transitions
Figure 24. SLOW Mode Clock Transitions
High
fOSC2/2
fOSC2/4
fCPU
RUN
fOSC2
MCCSR
SLOW
WAIT
CP1:0
00
01
SMS
SLOW WAIT
NEW SLOW
FREQUENCY
REQUEST
ACTIVE HALT
HALT
Low
POWER CONSUMPTION
40/161
fOSC2
NORMAL RUN MODE
REQUEST
ST72324
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 25.
Figure 25. WAIT Mode Flow-chart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
10
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
41/161
ST72324
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending on option byte). Otherwise, the ST7
enters HALT mode for the remaining tDELAY period.
Figure 26. ACTIVE-HALT Timing Overview
RUN
MCCSR
OIE bit
Power Saving Mode entered when HALT
instruction is executed
0
HALT mode
1
ACTIVE-HALT mode
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section
10.2 on page 56 for more details on the MCCSR
register).
The MCU can exit ACTIVE-HALT mode on reception of an MCC/RTC interrupt or a RESET. When
exiting ACTIVE-HALT mode by means of an MCC/
RTC interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the
interrupt or by fetching the reset vector which
woke it up (see Figure 27).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION: When exiting ACTIVE-HALT mode following an MCC/RTC interrupt, OIE bit of MCCSR
register must not be cleared before tDELAY after
42/161
ACTIVE 256 OR 4096 CPU
HALT
CYCLE DELAY 1)
HALT
INSTRUCTION
[MCCSR.OIE=1]
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
Figure 27. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=1)
OSCILLATOR
PERIPHERALS 2)
CPU
I[1:0] BITS
N
N
INTERRUPT 3)
Y
ON
OFF
OFF
10
RESET
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt can exit the MCU
from ACTIVE-HALT mode.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
ST72324
POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 10.2 on page 56 for more details on the MCCSR register).
The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 36) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 29).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see
Section 14.1 on page 149 for more details).
Figure 29. HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WDGHALT 1)
WATCHDOG
0
DISABLE
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2) OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
Figure 28. HALT Timing Overview
RUN
HALT
HALT
INSTRUCTION
[MCCSR.OIE=0]
256 OR 4096 CPU
CYCLE DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RUN
RESET
OR
INTERRUPT
FETCH
VECTOR
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Refer to Table 7, “Interrupt Mapping,” on page 36 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
43/161
ST72324
POWER SAVING MODES (Cont’d)
8.4.2.1 Halt Mode Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to external interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.
44/161
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memory. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
ST72324
9 I/O PORTS
9.1 INTRODUCTION
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is
shown in Figure 30
9.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external interrupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description
and interrupt section). If several input pins are selected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
DR
0
1
Push-pull
VSS
VDD
Open-drain
Vss
Floating
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over the
standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
45/161
ST72324
I/O PORTS (Cont’d)
Figure 30. I/O Port General Block Diagram
ALTERNATE
OUTPUT
REGISTER
ACCESS
1
P-BUFFER
(see table below)
VDD
0
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
VDD
DDR
PULL-UP
CONDITION
DATA BUS
OR
PAD
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)
Table 9. I/O Port Mode Options
Configuration Mode
Input
Output
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
46/161
Pull-Up
P-Buffer
Off
On
Off
Off
NI
On
Off
NI
Diodes
to VDD
On
to VSS
On
NI (see note)
Note: The diode to VDD is not implemented in the
true open drain pads. A local protection between
the pad and VSS is implemented to protect the device against positive stress.
ST72324
I/O PORTS (Cont’d)
Table 10. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
PULL-UP
CONDITION
DR
REGISTER
PAD
W
DATA BUS
INPUT 1)
R
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (eix)
INTERRUPT
CONDITION
PUSH-PULL OUTPUT 2)
OPEN-DRAIN OUTPUT 2)
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
DR
REGISTER
PAD
ALTERNATE
ENABLE
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
R/W
DATA BUS
ALTERNATE
OUTPUT
DR REGISTER ACCESS
VDD
RPU
PAD
DR
REGISTER
ALTERNATE
ENABLE
R/W
DATA BUS
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
47/161
ST72324
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be activated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maximum ratings.
Figure 31. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
XX
= DDR, OR
9.4 LOW POWER MODES
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
48/161
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Interrupt Event
External interrupt on
selected external
event
Enable
Event
Control
Flag
Bit
-
DDRx
ORx
Exit
from
Wait
Exit
from
Halt
Yes
Yes
ST72324
I/O PORTS (Cont’d)
9.5.1 I/O Port Implementation
The I/O port register configurations are summarised as follows.
PA3, PB3, PF2 (without pull-up)
MODE
floating input
floating interrupt input
open drain output
push-pull output
Standard Ports
PA5:4, PC7:0, PD5:0,
PE1:0, PF7:6, 4
MODE
floating input
pull-up input
open drain output
push-pull output
DDR
0
0
1
1
OR
0
1
0
1
MODE
floating input
open drain (high sink ports)
DDR
0
0
1
1
OR
0
1
0
1
True Open Drain Ports
PA7:6
Interrupt Ports
PB4, PB2:0, PF1:0 (with pull-up)
MODE
floating input
pull-up interrupt input
open drain output
push-pull output
DDR
0
0
1
1
DDR
0
1
OR
0
1
0
1
Table 11. Port Configuration
Port
Pin name
Input
PA7:6
Port A
Output
OR = 0
OR = 1
OR = 0
floating
OR = 1
true open-drain
PA5:4
PA3
floating
floating
pull-up
floating interrupt
open drain
open drain
push-pull
push-pull
Port B
PB3
PB4, PB2:0
floating
floating
floating interrupt
pull-up interrupt
open drain
open drain
push-pull
push-pull
Port C
Port D
PC7:0
PD5:0
floating
floating
pull-up
pull-up
open drain
open drain
push-pull
push-pull
Port E
PE1:0
PF7:6, 4
floating
floating
pull-up
pull-up
open drain
open drain
push-pull
push-pull
Port F
PF2
PF1:0
floating
floating
floating interrupt
pull-up interrupt
open drain
open drain
push-pull
push-pull
49/161
ST72324
I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
Reset Value
of all I/O port registers
0000h
PADR
0001h
PADDR
0002h
PAOR
0003h
PBDR
0004h
PBDDR
0005h
PBOR
0006h
PCDR
0007h
PCDDR
0008h
PCOR
0009h
PDDR
000Ah
PDDDR
000Bh
PDOR
000Ch
PEDR
000Dh
PEDDR
000Eh
PEOR
000Fh
PFDR
0010h
PFDDR
0011h
PFOR
50/161
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
ST72324
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
10.1.2 Main Features
■ Programmable free-running downcounter
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte
10.1.3 Functional Description
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 fOSC2 cycles (approx.), and the
length of the timeout period can be programmed
by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 33. Approximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writing to the WDGCR register (see Figure 34).
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 32. Watchdog Block Diagram
RESET
fOSC2
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)
DIV 64
WDGA
T6
T5
T4
T3
T2
T1
T0
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC
RTC COUNTER
MSB
11
LSB
6 5
0
TB[1:0] bits
(MCCSR
Register)
WDG PRESCALER
DIV 4
51/161
ST72324
WATCHDOG TIMER (Cont’d)
10.1.4 How to Program the Watchdog Timeout
Figure 33 shows the linear relationship between
the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation
without taking the timing variations into account. If
more precision is needed, use the formulae in Figure 34.
Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 33. Approximate Timeout Duration
3F
38
CNT Value (hex.)
30
28
20
18
10
08
00
1.5
18
34
50
65
82
Watchdog timeout (ms) @ 8 MHz. fOSC2
52/161
98
114
128
ST72324
WATCHDOG TIMER (Cont’d)
Figure 34. Exact Timeout Duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2=8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
(MCCSR Reg.) (MCCSR Reg.)
0
0
0
1
1
0
1
1
Selected MCCSR
Timebase
MSB
LSB
2ms
4ms
10ms
25ms
4
8
20
49
59
53
35
54
To calculate the minimum Watchdog Timeout (tmin):
IF CNT < MSB
------------4
THEN
tm in = tmin0 + 16384 × CNT × t osc2
CNT
ELSE t min = tmin0 + 16384 ×  CN T – 4---------------MSB


+ ( 192 + LS B) × 64 × -----------------
4CNT
MSB
× t osc2
4CNT
+ ( 192 + LSB ) × 64 × -----------------
× t osc2
To calculate the maximum Watchdog Timeout (tmax):
IF CNT ≤ MSB
------------4
THEN
t ma x = tmax0 + 16384 × C NT × tosc2
ELSE t max = tmax0 + 16384 × C NT – 4CNT
----------------
MSB


MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Value of T[5:0] Bits in
WDGCR Register (Hex.)
00
3F
Min. Watchdog
Timeout (ms)
tmin
1.496
128
Max. Watchdog
Timeout (ms)
tmax
2.048
128.552
53/161
ST72324
WATCHDOG TIMER (Cont’d)
10.1.5 Low Power Modes
Mode
SLOW
WAIT
Description
No effect on Watchdog.
No effect on Watchdog.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
0
0
0
1
1
x
HALT
No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external interrupt or a reset.
If an external interrupt is received, the Watchdog restarts counting after 256
or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 10.1.7 below.
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
10.1.6 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
10.1.7 Using Halt Mode with the WDG
(WDGHALT option)
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcontroller.
10.1.8 Interrupts
None.
54/161
10.1.9 Register Description
CONTROL REGISTER (WDGCR)
Read /Write
Reset Value: 0111 1111 (7Fh)
7
WDGA
0
T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
ST72324
Table 13. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
002Ah
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
55/161
ST72324
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three different functions:
■ a programmable CPU clock prescaler
■ a clock-out signal to supply external devices
■ a real time clock timer with interrupt capability
Each function can be used independently and simultaneously.
10.2.1 Programmable CPU Clock Prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See
Section 8.2 SLOW MODE for more details).
The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
10.2.2 Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f OSC2 clock to drive
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.
10.2.3 Real Time Clock Timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depending directly on fOSC2 are available. The whole
functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 8.4 ACTIVE-HALT AND HALT MODES for more details.
10.2.4 Beeper
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
Figure 35. Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0
MCCBCR
BEEP
BEEP SIGNAL
SELECTION
MCO
12-BIT MCC RTC
COUNTER
DIV 64
MCO CP1 CP0 SMS TB1 TB0
MCCSR
fOSC2
DIV 2, 4, 8, 16
OIF
MCC/RTC INTERRUPT
1
0
56/161
OIE
TO
WATCHDOG
TIMER
fCPU
CPU CLOCK
TO CPU AND
PERIPHERALS
ST72324
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.5 Low Power Modes
Mode
WAIT
ACTIVEHALT
HALT
Description
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
10.2.6 Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Interrupt Event
Time base overflow
event
Enable
Event
Control
Flag
Bit
OIF
OIE
Exit
from
Wait
Exit
from
Halt
Yes
No 1)
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
10.2.7 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read /Write
Reset Value: 0000 0000 (00h )
7
MCO
0
CP1
CP0
SMS
TB1
TB0
OIE
Bit 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
fCPU in SLOW mode
CP1
CP0
fOSC2 / 2
0
0
fOSC2 / 4
0
1
fOSC2 / 8
1
0
fOSC2 / 16
1
1
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC2
1: Slow mode. fCPU is given by CP1, CP0
See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC) for more details.
Bit 3:2 = TB[1:0] Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
Time Base
Counter
Prescaler f
OSC2 =4MHz fOSC2=8MHz
TB1
TB0
16000
4ms
2ms
0
0
32000
8ms
4ms
0
1
80000
20ms
10ms
1
0
200000
50ms
25ms
1
1
A modification of the time base is taken into account at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
OIF
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (fCPU on I/O
port)
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVEHALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode.
57/161
ST72324
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC BEEP CONTROL REGISTER (MCCBCR)
Read /Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
BC1
BC0
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with fOSC2=8MHz
0
0
Off
0
1
~2-KHz
1
0
~1-KHz
1
1
~500-Hz
Output
Beep signal
~50% duty cycle
The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the
consumption.
Table 14. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
002Bh
002Ch
002Dh
58/161
Register
Label
SICSR
Reset Value
MCCSR
Reset Value
MCCBCR
Reset Value
7
6
5
4
3
2
1
0
0
MCO
0
AVDIE
0
CP1
0
AVDF
0
CP0
0
LVDRF
x
SMS
0
0
TB1
0
CSSIE
0
TB0
0
0
0
0
0
0
0
CSSD
0
OIE
0
BC1
0
WDGRF
x
OIF
0
BC0
0
ST72324
10.3 16-BIT TIMER
10.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
10.3.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
■ 1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 36.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
10.3.3 Functional Description
10.3.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most significant byte (MS Byte).
– Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 15 Clock
Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8
or an external frequency.
Caution: Timer A functionality has the following
restrictions:
– TAOC2HR and TAOC2LR registers are write
only
– Input Capture 2 is not implemented
– The corresponding interrupts cannot be used
(ICF2, OCF2 forced by hardware to zero)
59/161
ST72324
16-BIT TIMER (Cont’d)
Figure 36. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 low
8
8
8
low
8
high
8
low
8
high
EXEDG
8
low
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
REGISTER
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Control/Status Register)
CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note)
TIMER INTERRUPT
60/161
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
ST72324
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +∆t LS Byte
Returns the buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
10.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
61/161
ST72324
16-BIT TIMER (Cont’d)
Figure 37. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000
COUNTER REGISTER
0001
0002
0003
TIMER OVERFLOW FLAG (TOF)
Figure 38. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
TIMER OVERFLOW FLAG (TOF)
Figure 39. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
62/161
ST72324
16-BIT TIMER (Cont’d)
10.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition is detected on the
ICAPi pin (see figure 5).
ICiR
MS Byte
ICiHR
LS Byte
ICiLR
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 15
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pullup without interrupt if this configuration is available).
When an input capture occurs:
– ICFi bit is set.
– The IC iR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 41).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the IC iHR (see note
1).
6. The TOF bit can be used with interrupt generation in order to measure events that go beyond
the timer range (FFFFh).
7. The ICAP2 registers (TAIC2HR, TAIC2LR) are
not available on Timer A. The corresponding
interrupts cannot be used (ICF2 is forced by
hardware to 0).
63/161
ST72324
16-BIT TIMER (Cont’d)
Figure 40. Input Capture Block Diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R Register
IC1R Register
ICF1
ICF2
0
16-BIT FREE RUNNING
COUNTER
CC1
CC0 IEDG2
Figure 41. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: The rising edge is the active edge.
64/161
0
(Control Register 2) CR2
16-BIT
COUNTER REGISTER
0
FF03
ST72324
16-BIT TIMER (Cont’d)
10.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
OCiR
MS Byte
OCiHR
LS Byte
OCiLR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the timer clock (CC[1:0]) (see Table 15
Clock Control Bits).
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMP i pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
fCPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 15
Clock Control Bits)
If the timer clock is an external clock, the formula
is:
∆ OCiR = ∆t * fEXT
Where:
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
fEXT
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
65/161
ST72324
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 43 on page
67). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OC iR register value plus 1 (see Figure 44 on page 67).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
6. The TAOC2HR, TAOC2LR registers are "writeonly" in Timer A. The corresponding event cannot be generated (OCF2 is forced by hardware
to 0).
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
Figure 42. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
16-bit
Latch
2
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
66/161
Latch
1
OCMP1
Pin
OCMP2
Pin
ST72324
16-BIT TIMER (Cont’d)
Figure 43. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCRi)
2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 44. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
2ED3
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
67/161
ST72324
16-BIT TIMER (Cont’d)
10.3.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 15
Clock Control Bits).
One pulse mode cycle
When
event occurs
on ICAP1
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
68/161
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
t * fCPU
-5
OCiR Value =
PRESC
Where:
t
= Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 15
Clock Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Pulse period (in seconds)
fEXT
= External timer clock frequency (in hertz)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 45).
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
6. On timer A, the OCF2 bit is forced by hardware
to 0.
ST72324
16-BIT TIMER (Cont’d)
Figure 45. One Pulse Mode Timing Example
COUNTER
2ED3
01F8
IC1R
01F8
FFFC FFFD FFFE
2ED0 2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OLVL2
OCMP1
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 46. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
COUNTER 34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
34E2
FFFC
OLVL2
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
69/161
ST72324
16-BIT TIMER (Cont’d)
10.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R register, and so this functionality can not be used when
PWM mode is activated.
In PWM mode, double buffering is implemented on
the output compare registers. Any new values written in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 15
Clock Control Bits).
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
70/161
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula:
t * fCPU - 5
OCiR Value =
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 15)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
fEXT
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 46)
Notes:
1. After a write instruction to the OC iHR register,
the output compare function is inhibited until the
OCiLR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
6. The TAOC2HR, TAOC2LR registers in Timer A
are "write only". A read operation returns an
undefined value.
7. The ICAP2 registers (TAIC2HR, TAIC2LR) are
not available in Timer A. The ICF2 bit is forced by
hardware to 0.
ST72324
16-BIT TIMER (Cont’d)
10.3.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.3.5 Interrupts
Event
Flag
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2*
OCF1
OCF2*
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
* The ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no interrupt event for
these flags.
10.3.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
Input Capture 1
Yes
Yes
One Pulse Mode
No
PWM Mode
No
TIMER RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
Yes2)5)
Yes
Yes4)
5)
Yes
Yes
Yes4)
Not
No
Partially 2)
Recommended1)5)
Not
No
No
Recommended3)5)
1) See note 4 in Section 10.3.3.5 One Pulse Mode
2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode
3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode
4) The TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event cannot be generated, OCF2 is forced by hardware to 0.
5) Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.
71/161
ST72324
16-BIT TIMER (Cont’d)
10.3.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
72/161
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
ST72324
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: This bit is not available in Timer A. It must
be kept at its reset value.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 15. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
Note: If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
73/161
ST72324
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only (except bit 2 R/W)
Reset Value: xxxx x0xx (xxh)
7
ICF1
0
OCF1
TOF
ICF2
OCF2 TIMD
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
74/161
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Note: This bit is not available in Timer A and is
forced by hardware to 0.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) register.
Note: This bit is not available in Timer A and is
forced by hardware to 0.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
ST72324
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the input capture 1 event).
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
75/161
ST72324
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
Note: This register is write-only in Timer A.
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
Note: This register is write-only in Timer A.
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
7
0
MSB
LSB
0
LSB
Note: This register is not implemented in Timer A.
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the Input Capture 2 event).
7
0
MSB
LSB
Note: This register is not implemented in Timer A.
76/161
ST72324
16-BIT TIMER (Cont’d)
Table 16. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32
Timer B: 42
Timer A: 31
Timer B: 41
Timer A: 33
Timer B: 43
Timer A: 34
Timer B: 44
Timer A: 35
Timer B: 45
Timer A: 36
Timer B: 46
Timer A: 37
Timer B: 47
Timer B: 4E
Timer B: 4F
Timer A: 38
Timer B: 48
Timer A: 39
Timer B: 49
Timer A: 3A
Timer B: 4A
Timer A: 3B
Timer B: 4B
Timer B: 4C
Timer B: 4D
CR1
Reset Value
CR2
Reset Value
CSR
Reset Value
IC1HR
Reset Value
IC1LR
Reset Value
OC1HR
Reset Value
OC1LR
Reset Value
OC2HR
Reset Value
OC2LR
Reset Value
CHR
Reset Value
CLR
Reset Value
ACHR
Reset Value
ACLR
Reset Value
IC2HR
Reset Value
IC2LR
Reset Value
ICIE
0
OC1E
0
ICF1
x
MSB
x
MSB
x
MSB
1
MSB
0
MSB
1
MSB
0
MSB
1
MSB
1
MSB
1
MSB
1
MSB
x
MSB
x
OCIE
0
OC2E1
0
OCF1
x
TOIE
0
OPM
0
TOF
x
FOLV21
0
PWM
0
ICF22
x
FOLV1
0
CC1
0
OCF22
x
OLVL2
0
CC0
0
TIMD
0
IEDG1
0
IEDG21
0
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
OLVL1
0
EXEDG
0
x
LSB
x
LSB
x
LSB
0
LSB
0
LSB
0
LSB
0
LSB
1
LSB
0
LSB
1
LSB
0
LSB
x
LSB
x
1
These bits are not used in Timer A and must be kept cleared.
These bits are forced by hardware to 0 in Timer A
2
77/161
ST72324
10.4 SERIAL PERIPHERAL INTERFACE (SPI)
10.4.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.4.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
■ Six master mode frequencies (fCPU/4 max.)
■ fCPU/2 max. slave mode frequency
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision, Master Mode Fault and Overrun
flags
10.4.3 General Description
Figure 47 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and input by SPI slaves
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves individually and to avoid contention on the data
lines. Slave SS inputs can be driven by standard I/O ports on the master MCU.
Figure 47. Serial Peripheral Interface Block Diagram
Data/Address Bus
SPIDR
Read
Interrupt
request
Read Buffer
MOSI
MISO
8-Bit Shift Register
SPICSR
7
SPIF WCOL OVR MODF
SOD
bit
SS
SPI
STATE
CONTROL
7
SPIE
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
78/161
SOD SSM
SSI
Write
SCK
SS
0
0
1
0
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 48.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communication with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 51) but master and slave
must be programmed with the same timing mode.
Figure 48. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
MSBit
MISO
MISO
MOSI
MOSI
SCK
SS
LSBit
8-BIT SHIFT REGISTER
SCK
+5V
SS
Not used if SS is managed
by software
79/161
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR register (see Figure 50)
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
– SS internal must be held high continuously
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see Figure 49):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.4.5.3).
Figure 49. Generic SS Timing Diagram
MOSI/MISO
Byte 1
Byte 2
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 50. Hardware/Software Slave Select Management
SSM bit
80/161
SSI bit
1
SS external pin
0
SS internal
Byte 3
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.3 Master Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in master mode, perform the
following two steps in order (if the SPICSR register
is not written first, the SPICR register setting may
be not taken into account):
1. Write to the SPICSR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
51 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
2. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
10.4.3.4 Master Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
10.4.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 51).
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Manage the SS pin as described in Section
10.4.3.2 and Figure 49. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
10.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.4.5.2).
81/161
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 51).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 51, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
Figure 51. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
82/161
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5 Error Flags
10.4.5.1 Master Mode Fault (MODF)
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
– The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
10.4.5.2 Overrun Condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
When an Overrun occurs:
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
The OVR bit is cleared by reading the SPICSR
register.
10.4.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode. See also Section 10.4.3.2 Slave Select
Management.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 52).
Figure 52. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
Read SPIDR
SPIF =0
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
Read SPIDR
WCOL=0
Note: Writing to the SPIDR register instead of reading it does not
reset the WCOL bit
83/161
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5.4 Single Master Systems
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 53).
The master device selects the individual slave devices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with command fields.
Figure 53. Single Master / Multiple Slave Configuration
SS
SCK
Slave
MCU
Slave
MCU
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
84/161
SS
Ports
MOSI MISO
SS
SS
SCK
SS
SCK
Slave
MCU
SCK
Slave
MCU
MOSI MISO
MOSI MISO
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.6 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wakeup event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
10.4.6.1 Using the SPI to wakeup the MCU from
Halt mode
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to perform an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selection is configured as external (see Section
10.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
10.4.7 Interrupts
Interrupt Event
SPI End of Transfer
Event
Master Mode Fault
Event
Overrun Error
Event
Flag
Enable
Control
Bit
SPIF
MODF
OVR
SPIE
Exit
from
Wait
Exit
from
Halt
Yes
Yes
Yes
No
Yes
No
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
85/161
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
7
SPIE
0
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 17 SPI Master
mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.4.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
86/161
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by resetting the SPE bit.
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 17. SPI Master mode SCK Frequency
Serial Clock
SPR2
SPR1
SPR0
fCPU/4
1
0
0
fCPU/8
0
0
0
fCPU/16
0
0
1
fCPU/32
1
1
0
fCPU/64
0
1
0
fCPU/128
0
1
1
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
7
SPIF
Bit 3 = Reserved, must be kept cleared.
0
WCOL
OVR
MODF
-
SOD
SSM
SSI
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR register is read.
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see
Figure 52).
0: No write collision occurred
1: A write collision has been detected
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
10.4.3.2 Slave Select Management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O)
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.4.5.2). An interrupt is generated if
SPIE = 1 in SPICSR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
D7
0
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of the shift
register (see Figure 47).
87/161
ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 18. SPI Register Map and Reset Values
Address
(Hex.)
0021h
0022h
0023h
88/161
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
SPICR
Reset Value
SPICSR
Reset Value
MSB
x
SPIE
0
SPIF
0
x
SPE
0
WCOL
0
x
SPR2
0
OR
0
x
MSTR
0
MODF
0
x
CPOL
x
x
CPHA
x
SOD
0
x
SPR1
x
SSM
0
LSB
x
SPR0
x
SSI
0
0
ST72324
10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.5.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two
baud rate generator systems.
10.5.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently
programmable transmit and
receive baud rates up to 500K baud.
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting function for multiprocessor configurations
■ Separate enable bits for Transmitter and
Receiver
■ Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
10.5.3 General Description
The interface is externally connected to another
device by two pins (see Figure 55):
– TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data recovery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
This interface uses two types of baud rate generator:
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
89/161
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 54. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Received Shift Register
Transmit Shift Register
RDI
CR1
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8
SCID
M WAKE PCE PS
PIE
RECEIVER
CLOCK
RECEIVER
CONTROL
CR2
SR
TIE TCIE RIE
ILIE
TE
RE RWU SBK
TDRE TC RDRF IDLE OR
NF
FE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
fCPU
CONTROL
/16
/PR
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
90/161
PE
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in Figure 54. It contains 6 dedicated registers:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIERPR)
– An extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section
10.5.7for the definitions of each bit.
10.5.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 register (see Figure 54).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 55. Word Length Programming
9-bit Word length (M bit is set)
Possible
Parity
Bit
Data Frame
Start
Bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Start
Bit
Break Frame
Extra
’1’
Possible
Parity
Bit
Data Frame
Bit0
Bit8
Next
Stop Start
Bit
Bit
Idle Frame
8-bit Word length (M bit is reset)
Start
Bit
Bit7
Next Data Frame
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Start
Bit
Next Data Frame
Stop
Bit
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame
Extra Start
Bit
’1’
91/161
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.2 Transmitter
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 54).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
– Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first
transmission.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR register without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write instruction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
92/161
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 55).
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
Idle Characters
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the SCIDR.
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.3 Receiver
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 54).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during reception.
Clearing the RDRF bit is performed by the following
software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
Break Character
When a break character is received, the SPI handles it as a framing error.
Idle Character
When a idle frame is detected, there is the same
procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
Overrun Error
An overrun error occurs when a character is received when RDRF has not been reset. Data can
not be transferred from the shift register to the
RDR register as long as the RDRF bit is not
cleared.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.
Noise Error
Oversampling techniques are used for data recovery by discriminating between valid incoming data
and noise.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– Data is transferred from the Shift register to the
SCIDR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The NF bit is reset by a SCISR register read operation followed by a SCIDR register read operation.
Framing Error
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchronization or excessive noise.
– A break is received.
When the framing error is detected:
– the FE bit is set by hardware
– Data is transferred from the Shift register to the
SCIDR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation.
93/161
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 56. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
fCPU
TRANSMITTER RATE
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
94/161
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.4 Conventional Baud Rate Generation
with:
The baud rate for the receiver and transmitter (Rx
ETPR = 1,..,255 (see SCIETPR register)
and Tx) are set independently and calculated as
ERPR = 1,.. 255 (see SCIERPR register)
follows:
10.5.4.6 Receiver Muting and Wake-up Feature
fCPU
fCPU
In multiprocessor configurations it is often desiraRx =
Tx =
ble that only the intended message recipient
(16*PR)*RR
(16*PR)*TR
should actively receive the full message contents,
with:
thus reducing redundant SCI service overhead for
all non addressed receivers.
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
The non addressed devices may be placed in
TR = 1, 2, 4, 8, 16, 32, 64,128
sleep mode by means of the muting function.
(see SCT[2:0] bits)
Setting the RWU bit by software puts the SCI in
RR = 1, 2, 4, 8, 16, 32, 64,128
sleep mode:
(see SCR[2:0] bits)
All the reception status bits can not be set.
All these bits are in the SCIBRR register.
All the receive interrupts are inhibited.
Example: If fCPU is 8 MHz (normal mode) and if
A muted receiver may be awakened by one of the
PR=13 and TR=RR=1, the transmit and receive
following two ways:
baud rates are 38400 baud.
– by Idle Line detection if the WAKE bit is reset,
Note: the baud rate registers MUST NOT be
– by Address Mark detection if the WAKE bit is set.
changed while the transmitter or the receiver is enabled.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
10.5.4.5 Extended Baud Rate Generation
Then the RWU bit is reset by hardware but the
The extended prescaler option gives a very fine
IDLE bit is not set.
tuning on the baud rate, using a 255 value prescalReceiver wakes-up by Address Mark detection
er, whereas the conventional Baud Rate Generawhen it received a “1” as the most significant bit of
tor retains industry standard software compatibilia word, thus indicating that the message is an adty.
dress. The reception of this particular word wakes
The extended baud rate generator block diagram
up the receiver, resets the RWU bit and sets the
is described in the Figure 56.
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
Caution: In Mute mode, do not write to the
divided by a factor ranging from 1 to 255 set in the
SCICR2 register. If the SCI is in Mute mode during
SCIERPR or the SCIETPR register.
the read operation (RWU=1) and a address mark
wake up event occurs (RWU is reset) before the
Note: the extended prescaler is activated by setwrite operation, the RWU bit will be set again by
ting the SCIETPR or SCIERPR register to a value
this write operation. Consequently the address
other than zero. The baud rates are calculated as
byte is lost and the SCI is not woken up from Mute
follows:
mode.
fCPU
fCPU
Rx =
Tx =
16*ERPR*(PR*RR)
16*ETPR*(PR*TR)
95/161
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.7 Parity Control
Parity control (generation of parity bit in trasmission and and parity chencking in reception) can be
enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by
the M bit, the possible SCI frame formats are as
listed in Table 19.
Table 19. Frame Formats
M bit
0
0
1
1
PCE bit
0
1
0
1
SCI frame
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte has an
even number of “1s” if even parity is selected
96/161
(PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register.
10.5.5 Low Power Modes
Mode
Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit
from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
10.5.6 Interrupts
Interrupt Event
Enable Exit
Event
Control from
Flag
Bit
Wait
Transmit Data Register
TDRE
Empty
Transmission ComTC
plete
Received Data Ready
RDRF
to be Read
Overrun Error Detected OR
Idle Line Detected
IDLE
Parity Error
PE
Exit
from
Halt
TIE
Yes
No
TCIE
Yes
No
Yes
No
Yes
Yes
Yes
No
No
No
RIE
ILIE
PIE
The SCI interrupt events are connected to the
same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.7 Register Description
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line ocSTATUS REGISTER (SCISR)
curs).
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
Bit 7 = TDRE Transmit data register empty.
access to the SCISR register followed by a read to
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
the SCIDR register).
0: No Overrun error
register. An interrupt is generated if the TIE bit=1
1: Overrun error is detected
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register folNote: When this bit is set RDR register content will
lowed by a write to the SCIDR register).
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data will not be transferred to the shift regThis bit is set by hardware when noise is detected
ister unless the TDRE bit is cleared.
on a received frame. It is cleared by a software sequence (an access to the SCISR register followed
Bit 6 = TC Transmission complete.
by a read to the SCIDR register).
0: No noise is detected
This bit is set by hardware when transmission of a
1: Noise is detected
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
Note: This bit does not generate interrupt as it apthe SCICR2 register. It is cleared by a software sepears at the same time as the RDRF bit which itquence (an access to the SCISR register followed
self generates an interrupt.
by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchronizaNote: TC is not set after the transmission of a Pretion, excessive noise or a break character is deamble or a Break.
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
Bit 5 = RDRF Received data ready flag.
the SCIDR register).
This bit is set by hardware when the content of the
0: No Framing error is detected
RDR register has been transferred to the SCIDR
1: Framing error or break character is detected
register. An interrupt is generated if RIE=1 in the
Note: This bit does not generate interrupt as it apSCICR2 register. It is cleared by a software sepears at the same time as the RDRF bit which itquence (an access to the SCISR register followed
self generates an interrupt. If the word currently
by a read to the SCIDR register).
being transferred causes both frame error and
0: Data is not received
overrun error, it will be transferred and only the OR
1: Received data is ready to be read
bit will be set.
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
97/161
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Bit 3 = WAKE Wake-Up method.
Read/Write
This bit determines the SCI Wake-Up method, it is
Reset Value: x000 0000 (x0h)
set or cleared by software.
0: Idle Line
7
0
1: Address Mark
R8
T8
SCID
M
WAKE
PCE
PS
PIE
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M=1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte transfer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
98/161
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled.
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Notes:
Read/Write
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
Reset Value: 0000 0000 (00 h)
after the current word.
7
0
– When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 2 = RE Receiver enable.
1: An SCI interrupt is generated whenever
This bit enables the receiver. It is set and cleared
TDRE=1 in the SCISR register
by software.
0: Receiver is disabled
Bit 6 = TCIE Transmission complete interrupt ena1: Receiver is enabled and begins searching for a
ble
start bit
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 1 = RWU Receiver wake-up.
1: An SCI interrupt is generated whenever TC=1 in
This bit determines if the SCI is in mute mode or
the SCISR register
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
Bit 5 = RIE Receiver interrupt enable.
recognized.
This bit is set and cleared by software.
0: Receiver in Active mode
0: Interrupt is inhibited
1: Receiver in Mute mode
1: An SCI interrupt is generated whenever OR=1
Note: Before selecting Mute mode (setting the
or RDRF=1 in the SCISR register
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
Bit 4 = ILIE Idle line interrupt enable.
wakeup by idle line detection.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 0 = SBK Send break.
1: An SCI interrupt is generated whenever IDLE=1
This bit set is used to send break characters. It is
in the SCISR register.
set and cleared by software.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
99/161
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift register (see Figure 54).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 54).
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1 SCR0
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
0
0
3
0
1
4
1
0
13
1
1
100/161
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR dividing factor
SCT2
SCT1
SCT0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR Dividing factor
SCR2
SCR1
SCR0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
Read/Write
Reset Value: 0000 0000 (00 h)
Allows setting of the Extended Prescaler rate division factor for the receive circuit.
7
0
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Reset Value:0000 0000 (00h)
Allows setting of the External Prescaler rate division factor for the transmit circuit.
7
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
7
6
5
4
3
2
1
0
ETPR
7
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 56) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended baud rate generator is not used after a reset.
0
ETPR
6
ETPR
5
ETPR
4
ETPR
3
ETPR
2
ETPR ETPR
1
0
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 56) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used after a reset.
Table 20. Baudrate Selection
Conditions
Symbol
Parameter
fCPU
Accuracy
vs. Standard
~0.16%
fTx
fRx
Communication frequency
8MHz
~0.79%
Prescaler
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
Standard
Baud
Rate
Unit
~300.48
300
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
Hz
14400 ~14285.71
101/161
ST72324
SERIAL COMMUNICATION INTERFACE (Cont’d)
Table 21. SCI Register Map and Reset Values
Address
(Hex.)
0050h
0051h
0052h
0053h
0054h
0055h
0057h
102/161
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
SCIDR
Reset Value
SCIBRR
Reset Value
SCICR1
Reset Value
SCICR2
Reset Value
SCIERPR
Reset Value
SCIPETPR
Reset Value
TDRE
1
MSB
x
SCP1
0
R8
x
TIE
0
MSB
0
MSB
0
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
x
SCP0
0
T8
0
TCIE
0
x
SCT2
0
SCID
0
RIE
0
x
SCT1
0
M
0
ILIE
0
x
SCT0
0
WAKE
0
TE
0
x
SCR2
0
PCE
0
RE
0
x
SCR1
0
PS
0
RWU
0
0
0
0
0
0
0
0
0
0
0
0
0
PE
0
LSB
x
SCR0
0
PIE
0
SBK
0
LSB
0
LSB
0
ST72324
10.6 10-BIT A/D CONVERTER (ADC)
10.6.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
10.6.2 Main Features
■ 10-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 57.
Figure 57. ADC Block Diagram
fCPU
DIV 4
0
DIV 2
fADC
1
EOC SPEEDADON
0
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
AINx
ADCDRH
D9
D8
ADCDRL
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
103/161
ST72324
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.6.3 Functional Description
The conversion is monotonic, meaning that the result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VAREF
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.6.3.1 A/D Converter Configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
10.6.3.2 Starting the Conversion
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
104/161
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
automatically.
Note: The data is not latched, so both the low and
the high data register must be read before the next
conversion is complete, so it is recommended to
disable interrupts while reading the conversion result.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRH register. This clears EOC
automatically.
10.6.3.3 Changing the conversion channel
The application can change channels during conversion. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.
10.6.4 Low Power Modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Mode
WAIT
HALT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
tSTAB (see Electrical Characteristics)
before accurate conversions can be
performed.
10.6.5 Interrupts
None.
ST72324
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.6.6 Register Description
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
CONTROL/STATUS REGISTER (ADCCSR)
Read /Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
7
EOC SPEED ADON
0
0
CH3
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
1: fADC = fCPU/2
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = Reserved. Must be kept cleared.
Channel Pin*
CH3
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
7
D9
0
D8
D7
D6
D5
D4
D3
D2
Bit 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
D1
D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Converted Analog Value
105/161
ST72324
10-BIT A/D CONVERTER (Cont’d)
Table 22. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0070h
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
0
CH3
0
CH2
0
CH1
0
CH0
0
0071h
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0072h
ADCDRL
Reset Value
0
0
0
0
0
0
D1
0
D0
0
106/161
ST72324
11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two sub-modes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 23. CPU Addressing Mode Overview
Mode
Syntax
Destination
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+0
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Relative
Direct
jrne loop
PC+/-127
Relative
Indirect
jrne [$10]
PC+/-127
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip
00..FF
+1
00..FF
byte
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
107/161
ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask (level 3)
RIM
Reset Interrupt Mask (level 0)
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte contains the operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
108/161
11.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
11.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 24. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Available Relative
Direct/Indirect
Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset is following the opcode.
Relative (Indirect)
The offset is defined in memory, which address
follows the opcode.
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Additions/Substractions operations
BCP
Bit Compare
Short Instructions
Only
CLR
11.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Function
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
109/161
ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
be subdivided into 13 main groups as illustrated in
the following table:
RSP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
Using a pre-byte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
opcode
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the effective address
110/161
RET
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
I1
H
I0
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
jrf *
JRIH
Jump if ext. INT pin = 1
(ext. INT pin high)
JRIL
Jump if ext. INT pin = 0
(ext. INT pin low)
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I1:0 = 11
I1:0 = 11 ?
JRNM
Jump if I1:0 <> 11
I1:0 <> 11 ?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
reg, M
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
1
I1
reg, M
0
H
I0
C
111/161
ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
MUL
I1
H
I0
N
Z
N
Z
dst <= src
reg, M
M, reg
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2's compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
PUSH
Push onto the Stack
push Y
M
reg, CC
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I1:0 = 10 (level 0)
RLC
Rotate left true C
C <= A <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => A => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Substract with Carry
A=A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I1:0 = 11 (level 3)
0
I1
H
C
0
I0
N
Z
N
Z
N
Z
C
C
0
1
A
0
M
1
1
1
SLA
Shift left Arithmetic
C <= A <= 0
reg, M
N
Z
C
SLL
Shift left Logic
C <= A <= 0
reg, M
N
Z
C
SRL
Shift right Logic
0 => A => C
reg, M
0
Z
C
SRA
Shift right Arithmetic
A7 => A => C
reg, M
N
Z
C
SUB
Substraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
A7-A4 <=> A3-A0
reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
WFI
Wait for Interrupt
XOR
Exclusive OR
N
Z
112/161
A = A XOR M
A
M
M
1
1
1
0
ST72324
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are referred to VSS.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the minimum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V. They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by
characterization of a batch of samples from a
standard diffusion lot over the full temperature
range, where 95% of the devices have an error
less than or equal to the value indicated
(mean±2Σ).
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 58.
12.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 59.
Figure 59. Pin input voltage
ST7 PIN
VIN
Figure 58. Pin loading conditions
ST7 PIN
CL
113/161
ST72324
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these condi12.2.1 Voltage Characteristics
Symbol
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
Ratings
Maximum value
VDD - VSS
Supply voltage
6.5
VPP - VSS
Programming Voltage
13
VIN
1) & 2)
Input Voltage on true open drain pin
VSS-0.3 to 6.5
|VSSA - VSSx|
V
VSS-0.3 to VDD+0.3
Input voltage on any other pin
|∆VDDx| and |∆VSSx|
Unit
Variations between different digital power pins
50
Variations between digital and analog ground pins
50
VESD(HBM)
Electro-static discharge voltage (Human Body Model)
VESD(MM)
Electro-static discharge voltage (Machine Model)
mV
see Section 12.7.3 on page 131
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
IVDD
Total current into VDD power lines
(source) 3)
32-pin devices
75
44-pin devices
150
IVSS
Total current out of VSS ground lines
(sink) for 3)
32-pin devices
75
44-pin devices
150
Output current sunk by any standard I/O and control pin
25
IIO
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
IINJ(PIN) 2) & 4)
±5
±2
Injected current on any other pin
ΣIINJ(PIN) 2)
Total injected current (sum of all I/O and control pins) 5)
mA
50
Injected current on VPP pin
5) & 6)
mA
- 25
Injected current on RESET pin
Injected current on OSC1 and OSC2 pins
Unit
mA
±5
±5
± 25
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 144.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
114/161
ST72324
12.2.3 Thermal Characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
Parameter
Conditions
fCPU
Internal clock frequency
VDD
Standard voltage devices (except Flash
Write/Erase)
Operating Voltage for Flash Write/Erase
VPP = 11.4 to 12.6V
1 Suffix Version
TA
Ambient temperature range
Min
Max
Unit
0
8
MHz
3.8
5.5
4.5
5.5
0
70
5 Suffix Version
-10
85
6 or A Suffix Versions
-40
85
7 or B Suffix Versions
-40
105
C Suffix Version
-40
125
V
°C
Figure 60. fCPU Max Versus VDD for Standard Voltage Devices
fCPU [MHz]
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
6
4
2
1
0
3.5
3.8 4.0
4.5
5.5
FUNCTIONALITY
GUARANTEED
IN THIS AREA
IN STANDARD
VOLTAGE
DEVICES (UNLESS
OTHERWISE
SPECIFIED
IN THE TABLES
OF PARAMETRIC
DATA)
SUPPLY VOLTAGE [V]
Note: Some temperature ranges are only available with a specific package and memory size. Refer to Ordering Information .
115/161
ST72324
12.3.2 General Operating Conditions for low voltage Flash devices (planned)
Symbol
Parameter
Conditions
fCPU
Internal clock frequency
VDD
Low voltage devices (except Flash Write/
Erase)1)
Operating Voltage for Flash Write/Erase
TA
Ambient temperature range
Min
Max
Unit
0
4
MHz
3.0
3.6
3.0
3.6
1 Suffix Version
0
70
5 Suffix Version
-10
85
6 Suffix Version
-40
85
VPP = 11.4 to 12.6V
Figure 61. fCPU Max Versus VDD for Low Voltage Devices
FUNCTIONALITY
GUARANTEED
IN THIS AREA
IN LOW
VOLTAGE
DEVICES UNLESS
OTHERWISE
SPECIFIED
IN THE TABLES
OF PARAMETRIC
DATA
fCPU [MHz]
6
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
1
0
2.5
3.0
3.5 3.6
SUPPLY VOLTAGE [V]
116/161
4
V
°C
ST72324
OPERATING CONDITIONS (Cont’d)
12.3.3 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA.
Symbol
Parameter
VIT+(LVD)
Reset release threshold
(VDD rise)
VIT-(LVD)
Reset generation threshold
(VDD fall)
Vhys(LVD)
LVD voltage threshold hysteresis 1)
1)2)
VtPOR
VDD rise time
tg(VDD)
VDD glitches filtered (not detected)
by LVD 1)
Conditions
Min
Typ
Max
VD level = High in option byte
4.0 1)
4.2
4.5
VD level = Med. in option byte3) 3.55 1)
VD level = Low in option byte3) 2.95 1)
3.75
3.15
4.01)
3.351)
VD level = High in option byte
4.0
4.25 1)
VD level = Med. in option byte3) 3.351)
VD level = Low in option byte3) 2.81)
3.55
3.0
3.751)
3.15 1)
VIT+(LVD)-VIT-(LVD)
200
250
mV
∝
µs/V
40
ns
3.8
150
6
Unit
V
Notes:
1. Data based on characterization results, not tested in production.
2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the
VIT+(LVD) threshold.
3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
Below 3.8V, device operation is not guaranteed.
117/161
ST72324
12.3.4 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
Symbol
Parameter
Conditions
Min
Typ
Max
4.41)
4.6
4.9
VD level = Med. in option byte2)
VD level = Low in option byte2)
3.95 1)
3.4 1)
4.15
3.6
4.4
3.8
4.2
3.75
3.2
4.4
4.0
3.4
4.65 1)
4.2 1)
3.6 1)
VD level = High in option byte
Unit
VIT+(AVD)
1⇒0 AVDF flag toggle threshold
(VDD rise)
VIT-(AVD)
0⇒1 AVDF flag toggle threshold
(VDD fall)
VD level = High in option byte
VD level = Med. in option byte2)
VD level = Low in option byte2)
Vhys(AVD)
AVD voltage threshold hysteresis
VIT+(AVD)-VIT-(AVD)
200
mV
∆VIT-
Voltage drop between AVD flag set
VIT-(AVD)-VIT-(LVD)
and LVD reset activated
450
mV
1. Data based on characterization results, not tested in production.
2. Applicable only in low voltage devices (planned).
118/161
V
ST72324
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
12.4.1 RUN and SLOW Modes (Flash devices)
Symbol
Parameter
Typ
Max 1)
Unit
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
1.3
2.0
3.6
7.1
3.0
5.0
8.0
15.0
mA
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500kHz
0.6
0.7
0.8
1.1
2.7
3.0
3.6
4.0
mA
fOSC=2MHz,
fOSC=4MHz,
fOSC=8MHz,
fCPU=1MHz
fCPU=2MHz
fCPU=4MHz
fOSC=2MHz,
fOSC=4MHz,
fOSC=8MHz,
fCPU=62.5kHz
fCPU=125kHz
fCPU=250kHz
0.8
1.2
2.0
0.33
0.37
0.44
TBD
TBD
TBD
TBD
TBD
TBD
Conditions
3.8V≤VDD≤5.5V
Supply current in RUN mode 2)
(see Figure 62)
IDD
3V≤VDD≤3.6V
Supply current in SLOW mode 2)
(see Figure 63)
Supply current in RUN mode 2)
IDD
Supply current in SLOW mode 2)
Figure 62. Typical IDD in RUN vs. fCPU
8
7
1.20
500kHz
250kHz
1.00
125kHz
62.5kHz
0.80
Idd (mA)
6
Idd (mA)
mA
Figure 63. Typical IDD in SLOW vs. fCPU
8MHz
4MHz
2MHz
1MHz
9
mA
5
4
3
0.60
0.40
2
0.20
1
0
0.00
3.2
3.6
4
4.4
Vdd (V)
4.8
5.2
5.5
3.2
3.6
4
4.4
4.8
5.2
5.5
Vdd (V)
Notes:
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- CSS and LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.5.3 and Section 12.5.4) and the
peripheral power consumption (Section 12.4.7).
119/161
ST72324
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 WAIT and SLOW WAIT Modes (Flash devices)
Typ
Max 1)
Unit
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
1.0
1.5
2.5
4.5
3.0
4.0
5.0
7.0
mA
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500kHz
0.58
0.65
0.77
1.05
1.2
1.3
1.8
2.0
mA
fOSC=2MHz,
fOSC=4MHz,
fOSC=8MHz,
fCPU=1MHz
fCPU=2MHz
fCPU=4MHz
0.6
0.8
1.6
TBD
TBD
TBD
mA
fOSC=2MHz,
fOSC=4MHz,
fOSC=8MHz,
fCPU=62.5kHz
fCPU=125kHz
fCPU=250kHz
0.33
0.37
0.44
TBD
TBD
TBD
mA
Conditions
Supply current in WAIT mode 2)
(see Figure 64)
IDD
Supply current in SLOW WAIT mode 2)
(see Figure 65)
Supply current in WAIT mode 2)
IDD
Supply current in SLOW WAIT mode 2)
3.8V≤VDD≤5.5V
Parameter
3V≤VDD≤3.6V
Symbol
Figure 64. Typical IDD in WAIT vs. fCPU
Figure 65. Typical IDD in SLOW-WAIT vs. fCPU
8MHz
4MHz
2MHz
1MHz
6
5
250kHz
125kHz
62.5kHz
1.00
4
)
0.80
3
(
Idd (mA)
500kHz
1.20
2
0.60
0.40
1
0.20
0
3.2
3.6
4
4.4
Vdd (V)
4.8
5.2
5.5
0.00
3.2
3.6
4
4.4
4.8
5.2
5.5
Vdd (V)
Notes:
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- CSS and LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.5.3 and Section 12.5.4) and the
peripheral power consumption (Section 12.4.7).
120/161
ST72324
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.3 RUN and SLOW Modes (ROM devices)
Typ
Max 1)
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
1.3
2.0
3.6
7.1
2.0
3.0
5.0
10.0
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500kHz
0.6
0.7
0.8
1.1
1.8
2.1
2.4
3.0
Typ
Max 1)
fOSC=2MHz, fCPU=1MHz
fOSC=4MHz, fCPU=2MHz
fOSC=8MHz, fCPU=4MHz
fOSC=16MHz, fCPU=8MHz
1.0
1.5
2.5
4.5
1.3
2.0
3.3
6.0
fOSC=2MHz, fCPU=62.5kHz
fOSC=4MHz, fCPU=125kHz
fOSC=8MHz, fCPU=250kHz
fOSC=16MHz, fCPU=500kHz
0.07
0.1
0.2
0.35
0.2
0.3
0.6
1.2
Parameter
Supply current in RUN mode 2)
IDD
Supply current in SLOW mode 2)
Conditions
3.8V≤VDD≤5.5V
Symbol
Unit
mA
12.4.4 WAIT and SLOW WAIT Modes (ROM devices)
Parameter
Supply current in WAIT mode 2)
IDD
Supply current in SLOW WAIT mode 2)
Conditions
3.8V≤VDD≤5.5V
Symbol
Unit
mA
Notes:
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Progam executed from RAM, CPU running with RAM access. There is no increase in consumption if programs are executed in ROM
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state.
- CSS and LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.
To obtain the total current consumption of the device, add the clock source (Section 12.5.3 and Section 12.5.4) and the
peripheral power consumption (Section 12.4.7).
121/161
ST72324
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.5 HALT and ACTIVE-HALT Modes
Symbol
Parameter
Conditions
Max
Unit
-40°C≤TA≤+85°C
10
-40°C≤TA≤+125°C
50
µA
IDD
Supply current in HALT mode 1)
VDD=5.5V
IDD
Supply current in ACTIVE-HALT mode 2)
fOSC = 16 MHz, VDD= 5V
Typ
650
No max.
guaranteed
µA
Notes:
1. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), CSS and LVD disabled.
Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with
a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, CSS and LVD disabled. To
obtain the total current consumption of the device, add the clock source consumption (Section 12.5.3 and Section 12.5.4).
12.4.6 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Symbol
Parameter
Conditions
IDD(RCINT) Supply current of internal RC oscillator
IDD(RES)
Typ
Max 1)
Unit
625
see Section
12.5.3 on page
125
Supply current of resonator oscillator 2) & 3)
IDD(PLL)
PLL supply current
IDD(CSS)
Clock security system supply current
VDD= 5V
250
IDD(LVD)
LVD supply current
HALT mode, VDD= 5V
150
VDD= 5V
µA
360
300
Notes:
1. Data based on characterisation results, not tested in production.
2. Data based on characterization results done with the external components specified in Section 12.5.3, not tested in
production.
3. As the oscillator is based on a current source, the consumption does not depend on the voltage.
122/161
ST72324
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.7 On-Chip Peripherals
Measured on S72F521R9T3 on TQFP64 generic board T A = 25°C fCPU=4MHz.
Symbol
Typ
Unit
IDD(TIM)
16-bit Timer supply current 1)
VDD=5.0V
50
µA
IDD(SPI)
SPI supply current 3)
VDD=5.0V
400
µA
VDD=5.0V
400
µA
IDD(ADC)
Parameter
ADC supply current when converting
Conditions
6)
Notes:
1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (only TIMD bit set). Data valid for one timer.
3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master
communicationat maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.
6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
123/161
ST72324
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for VDD, fCPU, and TA.
12.5.1 General Timings
Symbol
tc(INST)
tv(IT)
Parameter
Conditions
Instruction cycle time
Interrupt reaction time
tv(IT) = ∆tc(INST) + 10
fCPU=8MHz
2)
fCPU=8MHz
Min
Typ 1)
Max
Unit
2
3
12
tCPU
250
375
1500
ns
10
22
tCPU
1.25
2.75
µs
12.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
VOSC1H
OSC1 input pin high level voltage
VDD-1
VDD
VOSC1L
OSC1 input pin low level voltage
VSS
VSS+1
tw(OSC1H)
tw(OSC1L)
tr(OSC1)
tf(OSC1)
IL
OSC1 high or low time 3)
see Figure 66
Unit
V
5
ns
OSC1 rise or fall time 3)
15
VSS≤VIN≤VDD
OSCx Input leakage current
±1
µA
Figure 66. Typical Application with an External Clock Source
90%
VOSC1H
10%
VOSC1L
tr(OSC1)
tf(OSC1)
OSC2
tw(OSC1H)
tw(OSC1L)
Not connected internally
fOSC
EXTERNAL
CLOCK SOURCE
OSC1
IL
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
124/161
ST72324
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the resonator and the load capacitors have to be placed as
Symbol
Parameter
fOSC
Oscillator Frequency 1)
RF
Feedback resistor
CL1
CL2
Recommended load capacitance versus equivalent serial resistance of the
crystal or ceramic resonator (RS)
Symbol
i2
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
Min
Max
Unit
LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
Conditions
1
>2
>4
>8
2
4
8
16
MHz
20
40
kΩ
RS=200Ω
RS=200Ω
RS=200Ω
RS=100Ω
22
22
18
15
56
46
33
33
pF
Typ
Max
Unit
80
160
310
610
150
250
460
910
µA
Parameter
LP oscillator
MP oscillator
MS oscillator
HS oscillator
Conditions
VDD=5V
VIN=VSS
OSC2 driving current
LP oscillator
MP oscillator
MS oscillator
HS oscillator
Figure 67. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i2
fOSC
CL1
OSC1
RESONATOR
CL2
RF
OSC2
ST72XXX
Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details.
125/161
ST72324
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Typical Ceramic Resonators (information for guidance only)
LP
MP
MS
HS
Reference3)
MURATA
Ceramic
Oscil.
Freq.
CSA2.00MG
CSA4.00MG
CSA8.00MTZ
4)
CSA16.00MXZ040
Characteristic 1)
CL1 CL2 tSU(osc)
[pF] [pF] [ms] 2)
2MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 22
4MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 22
8MHz ∆fOSC=[±0.5%tolerance,±0.5%∆Ta,±0.3%aging,±x.x%correl] 33
22
22
4
2
33
1
16MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging,±x.x%correl] 33
33
0.7
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. Resonators all have different characteristics. Contact the manufacturer to obtain the appropriate values of external
components and to verify oscillator performance.
4. 3rd overtone resonators require specific validation by the resonator manufacturer.
126/161
ST72324
CLOCK CHARACTERISTICS (Cont’d)
12.5.4 RC Oscillators
Symbol
fOSC (RCINT)
Parameter
Conditions
Internal RC oscillator frequency
TA=25°C, VDD=5V
See Figure 68
Min
Typ
Max
Unit
2
3.5
5.6
MHz
Figure 68. Typical fOSC(RCINT) vs TA
fOSC(RCINT) (MHz)
4
Vdd = 5V
3.8
Vdd = 5.5V
3.6
3.4
3.2
3
-45
0
25
70
130
TA(°C)
127/161
ST72324
CLOCK CHARACTERISTICS (Cont’d)
12.5.5 Clock Security System (CSS)
Symbol
Parameter
Conditions
Min
Typ
Safe Oscillator Frequency 1)
fSFOSC
Max
3
Unit
MHz
Note:
1. Data based on characterization results.
12.5.6 PLL Characteristics
Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C1) or VDD 4.5 to 5.5V @ TA -40 to 125°C
Symbol
Parameter
VDD(PLL)
PLL Operating Range
fOSC
PLL input frequency range
∆ fCPU/ fCPU
Instantaneous PLL jitter 1)
Conditions
Min
Typ
Max
TA 0 to 70°C
3.8
5.5
TA -40 to +125°C
4.5
5.5
2
Unit
V
4
MHz
fOSC = 4 MHz.
1.0
2.5
%
fOSC = 2 MHz.
2.5
4.0
%
Note:
1. Data characterized but not tested.
Figure 69. PLL Jitter vs. Signal frequency1
0.8
+/-Jitter (%)
0.7
0.6
PLL ON
0.5
PLL OFF
0.4
0.3
0.2
0.1
0
2000
The user must take the PLL jitter into account in
the application (for example in serial communication or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore the longer the
period of the application signal, the less it will be
impacted by the PLL jitter.
Figure 69 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequencies of less than 125KHz, the jitter is negligible.
1000
500
250
125
Application Signal Frequency (KHz)
Note 1: Measurement conditions: fCPU = 4MHz, TA= 25°C
128/161
ST72324
12.6 MEMORY CHARACTERISTICS
12.6.1 RAM and Hardware Registers
Symbol
VRM
Parameter
Data retention mode
1)
Conditions
HALT mode (or RESET)
Min
Typ
Max
1.6
Unit
V
12.6.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY
Symbol
Parameter
fCPU
Operating frequency
VPP
Programming voltage 3)
IDD
Supply current4)
IPP
tVPP
tRET
NRW
TPROG
TERASE
VPP current4)
Internal VPP stabilization time
Data retention
Write erase cycles
Programming or erasing temperature range
Conditions
Read mode
Write / Erase mode
4.5V ≤ VDD ≤ 5.5V
RUN mode (fCPU = 4MHz)
Write / Erase
Power down mode / HALT
Read (VPP=12V)
Write / Erase
Min 2)
0
1
11.4
Typ
0
1
Max 2)
8
8
12.6
3
10
200
30
10
TA=55°C
TA=25°C
20
100
-40
25
85
Unit
MHz
V
mA
µA
mA
µs
years
cycles
°C
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons.
4. Data based on simulation results, not tested in production.
Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.
129/161
ST72324
12.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample basis during product characterization.
12.7.1 Functional EMS
(Electro Magnetic Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-44 standard.
A device reset allows normal operations to be resumed.
■
Symbol
Parameter
Conditions
Neg 1)
Pos 1)
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-2
-1
>1.5
VFFTB
Fast transient voltage burst limits to be apVDD=5V, TA=+25°C, fOSC=8MHz
plied through 100pF on VDD and VDD pins
conforms to IEC 1000-4-4
to induce a functional disturbance
-1.7
1.7
Unit
kV
12.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product
is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies
the board and the loading of each pin.
Symbol
Parameter
Conditions
Monitored
Frequency Band
0.1MHz to 30MHz
SEMI
SEMI
Peak level
Peak level
8/4MHz
16/8MHz
20
21
26
31
Unit
VDD=5V, TA=+25°C,
30MHz to 130MHz
TQFP44 package
conforming to SAE J 1752/3 130MHz to 1GHz
SAE EMI Level
22
28
3.5
4.0
0.1MHz to 30MHz
25
27
30
18
36
23
dBµV
3.0
3.5
-
VDD=5V, TA=+25°C,
30MHz to 130MHz
TQFP32 package
conforming to SAE J 1752/3 130MHz to 1GHz
SAE EMI Level
Notes:
1. Data based on characterization results, not tested in production.
130/161
Max vs. [fOSC/fCPU]
dBµV
-
ST72324
EMC CHARACTERISTICS (Cont’d)
12.7.3 Absolute Electrical Sensitivity
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note.
12.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 70 and the following test sequences.
Machine Model Test Sequence
– CL is loaded through S1 by the HV pulse generator.
– S1 switches position from generator to ST7.
– A discharge from CL to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
– R (machine resistance), in series with S2, ensures a slow discharge of the ST7.
Human Body Model Test Sequence
– C L is loaded through S1 by the HV pulse generator.
– S1 switches position from generator to R.
– A discharge from CL through R (body resistance)
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
Symbol
Ratings
Maximum value 1) Unit
Conditions
VESD(HBM)
Electro-static discharge voltage
(Human Body Model)
TA=+25°C
2000
VESD(MM)
Electro-static discharge voltage
(Machine Model)
TA=+25°C
200
V
Figure 70. Typical Equivalent ESD Circuits
S1
CL=100pF
ST7
S2
HIGH VOLTAGE
PULSE
GENERATOR
R=10k~10MΩ
HIGH VOLTAGE
PULSE
GENERATOR
S1
R=1500Ω
ST7
CL=200pF
HUMAN BODY MODEL
S2
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
131/161
ST72324
EMC CHARACTERISTICS (Cont’d)
12.7.3.2 Static and Dynamic Latch-Up
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the AN1181 ST7
application note.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 71. For
more details, refer to the AN1181 ST7
application note.
12.7.3.3 Designing hardened software to avoid
noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electrical Sensitivities
Symbol
LU
DLU
Parameter
Class 1)
Conditions
Static latch-up class
TA=+25°C
TA=+85°C
TA=+125°C
A
A
A
Dynamic latch-up class
VDD=5.5V, fOSC=4MHz, TA=+25°C
A
Figure 71. Simplified Diagram of the ESD Generator for DLU
RCH=50MΩ
CS=150pF
ESD
GENERATOR 2)
RD=330Ω
DISCHARGE TIP
VDD
VSS
HV RELAY
ST7
DISCHARGE
RETURN CONNECTION
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
132/161
ST72324
EMC CHARACTERISTICS (Cont’d)
12.7.4 ESD Pin Protection Strategy
To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to
prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be protected must not receive excessive current, voltage
or heating within their structure.
An ESD network combines the different input and
output ESD protections. This network works, by allowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 72 and Figure 73 for standard
pins and in Figure 74 and Figure 75 for true open
drain pins.
Standard Pin Protection
To protect the output structure the following elements are added:
– A diode to VDD (3a) and a diode from VSS (3b)
– A protection device between VDD and VSS (4)
To protect the input structure the following elements are added:
– A resistor in series with the pad (1)
– A diode to VDD (2a) and a diode from VSS (2b)
– A protection device between VDD and VSS (4)
Figure 72. Positive Stress on a Standard Pad vs. VSS
VDD
VDD
(2a)
(3a)
(1)
OUT
(4)
IN
Main path
(2b)
(3b)
Path to avoid
VSS
VSS
Figure 73. Negative Stress on a Standard Pad vs. VDD
VDD
VDD
(2a)
(3a)
(1)
OUT
(4)
IN
Main path
(3b)
VSS
(2b)
VSS
133/161
ST72324
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
diode to VDD are not implemented. An additional
local protection between the pad and VSS (5a &
5b) is implemented to completely absorb the positive ESD discharge.
Multisupply Configuration
When several types of ground (VSS, VSSA, ...) and
power supply (VDD, VAREF, ...) are available for
any reason (better noise immunity...), the structure
shown in Figure 76 is implemented to protect the
device against ESD.
Figure 74. Positive Stress on a True Open Drain Pad vs. VSS
VDD
VDD
Main path
(1)
Path to avoid
OUT
(5a)
(4)
IN
(3b)
(5b)
(2b)
VSS
VSS
Figure 75. Negative Stress on a True Open Drain Pad vs. VDD
VDD
VDD
Main path
(1)
OUT
(3b)
(4)
IN
(3b)
(2b)
(3b)
VSS
VSS
Figure 76. Multisupply Configuration
VDD
VAREF
VAREF
VSS
BACK TO BACK DIODE
BETWEEN GROUNDS
VSSA
134/161
VSSA
ST72324
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
VIL
Input low level voltage
VIH
Input high level voltage 1)
Vhys
Schmitt trigger voltage hysteresis 2)
IINJ(PIN)3)
ΣIINJ(PIN)3)
Min
Typ
1)
Max
0.3xVDD
CMOS ports
0.7xVDD
0.7
Injected Current on an I/O pin
±4
Total injected current (sum of all I/O VDD=5V
and control pins)
± 25
IL
Input leakage current
VSS≤VIN≤VDD
±1
IS
Static current consumption
Floating input mode4)
200
RPU
Weak pull-up equivalent resistor 5)
VIN=VSS
CIO
I/O pin capacitance
tf(IO)out
Unit
VDD=5V
50
120
V
mA
µA
250
kΩ
5
Output high to low level fall time 1)
tr(IO)out
CL=50pF
Output low to high level rise time 1) Between 10% and 90%
tw(IT)in
External interrupt pulse time 6)
Figure 77. Connecting Unused I/O Pins
pF
25
ns
25
1
tCPU
Figure 78. Typical IPU vs. VDD with VIN=VSS
90
VDD
ST72XXX
Ta=1 40°C
80
Ta=9 5°C
10kΩ
70
UNUSED I/O PORT
Ta=2 5°C
Ta=-45 °C
Ip u(uA)
60
50
40
30
10kΩ
UNUSED I/O PORT
20
10
ST72XXX
0
2
2 .5
3
3 .5
4
4.5
V dd(V )
5
5 .5
6
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to Section 12.2.2
on page 114 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 77). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 78).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
135/161
ST72324
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.8.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol
Parameter
Conditions
VOL 1)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 80 and Figure 82)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 81 and Figure 84)
VOH 2)
Figure 79. Typical VOL at VDD=5V (standard)
1.2
IIO=+2mA
0.5
IIO=+20mA, TA≤85°C
TA≥85°C
1.3
1.5
IIO=+8mA
IIO=-5mA, TA≤85°C VDD-1.4
TA≥85°C VDD-1.6
0.6
IIO=-2mA
5
Vdd-Vo h (V) at Vd d=5V
1.2
0.6
Ta =14 0°C "
0.4
Ta =95 °C
V
VDD-0.7
4.5
4
3.5
V dd= 5V 1 40°C m in
3
V dd= 5v 95°C m in
V dd= 5v 25°C m in
Ta =25 °C
0.2
Unit
Figure 81. Typical VOH at VDD=5V
5.5
0.8
Max
IIO=+5mA
1.4
1
V ol (V ) at Vdd=5V
VDD=5V
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 79)
Min
2.5
V dd= 5v -4 5°C m in
Ta =-45 °C
2
0
0
0.005
0.0 1
0.01 5
Iio(A)
-0.01
-0.008 -0.006 -0.004
-0.002
0
Iio (A)
Figure 80. Typical VOL at VDD=5V (high-sink)
1
0.9
Vol(V ) at V dd=5V
0.8
0.7
0.6
0.5
0.4
Ta= 140 °C
0.3
Ta= 95 °C
0.2
Ta= 25 °C
0.1
Ta= -45°C
0
0
0.01
0.02
0.03
Iio(A)
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.
136/161
ST72324
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 82. Typical VOL vs. VDD (standard)
1
0.45
Ta= -4 5°C
0.9
0.8
Ta=2 5°C
Ta= 95°C
Ta=9 5°C
0.35
Ta= 140 °C
0.7
Ta=1 40°C
Vo l(V ) a t Iio=2 mA
Vol(V ) at Iio =5m A
Ta=-4 5°C
0.4
Ta= 25°C
0.6
0.5
0.4
0.3
0.3
0.25
0.2
0.15
0.2
0.1
0.1
0.05
0
2
2.5
3
3.5
4
4.5
5
5.5
0
6
2
Vd d(V )
2 .5
3
3.5
4
4.5
5
5.5
6
Vd d(V )
Figure 83. Typical VOL vs. VDD (high-sink)
1 .6
0 .6
Ta= 140 °C
1 .4
0 .5
Ta=95 °C
1 .2
Ta=25 °C
Ta=-45°C
Vol(V ) at Iio=20m A
Vol(V ) at Iio=8m A
0 .4
0 .3
0 .2
1
0 .8
0 .6
Ta= 14 0°C
0 .4
Ta=9 5°C
0 .1
Ta=2 5°C
0 .2
Ta=-45 °C
0
0
2
2.5
3
3.5
4
4.5
5
5.5
2
6
2.5
3
3.5
4
4.5
5
5.5
6
V dd(V )
Vdd (V )
Figure 84. Typical VDD-VOH vs. VDD
5.5
6
Ta= -4 5°C
5
Vdd-Voh(V) at Iio=-5m A
Vdd-Voh(V ) at Iio =-2m A
5
4.5
4
3.5
Ta= -4 5°C
3
Ta= 25°C
Ta= 25°C
Ta= 95°C
Ta= 140°C
4
3
2
Ta= 95°C
2.5
1
Ta= 140°C
2
0
2
2.5
3
3.5
4
Vdd(V)
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
137/161
ST72324
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol
Parameter
Conditions
VIL
Input low level voltage
VIH
Input high level voltage 1)
Vhys
Schmitt trigger voltage hysteresis 2)
VOL
Output low level voltage 3)
IIO
RON
tg(RSTL)in
Max
Unit
0.16xVDD
V
2.5
VDD=5V
IIO=+2mA
0.2
0.5
2
TBD
mA
30
120
kΩ
0
429)
µs
20
429)
µs
Input current on RESET pin
Weak pull-up equivalent resistor
20
External pin
Internal reset sources
External reset pulse hold time 4)
Filtered glitch duration
Typ
0.85xVDD
tw(RSTL)out Generated reset pulse duration
th(RSTL)in
Min
1)
30
µs
2.5
5)
200
ns
Figure 85. Typical Application with RESET pin 6)7)8)
Recommended
if LVD is disabled
VDD
USER
EXTERNAL
RESET
CIRCUIT 5)
VDD
ST72XXX
VDD
0.01µF
4.7kΩ
RON
INTERNAL
RESET
Filter
0.01µF
PULSE
GENERATOR
WATCHDOG
LVD RESET
Required if LVD is disabled
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below th(RSTL)in can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in Section 12.9.1 . Otherwise the reset will not be taken into account internally.
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for IINJ(RESET) in Section 12.2.2 on page 114.
9. Data guaranteed by design, not tested in production.
138/161
ST72324
CONTROL PIN CHARACTERISTICS (Cont’d)
12.9.2 ICCSEL/VPP Pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol
Parameter
VIL
Input low level voltage 1)
VIH
Input high level voltage 1)
IL
Input leakage current
Conditions
FLASH versions
Min
Max
VSS
0.2
ROM versions
FLASH versions
VSS 0.3xVDD
VDD-0.1 12.6
ROM versions
0.7xVDD
Unit
V
VDD
VIN=VSS
±1
µA
Figure 86. Two typical Applications with ICCSEL/VPP Pin 2)
ICCSEL/V PP
VPP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.
12.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).
12.10.1 16-Bit Timer
Symbol
Parameter
Conditions
tw(ICAP)in Input capture pulse time
tres(PWM) PWM resolution time
fCPU=8MHz
Min
Typ
Max
Unit
1
tCPU
2
tCPU
250
ns
fEXT
Timer external clock frequency
0
fCPU/4
MHz
fPWM
PWM repetition rate
0
fCPU/4
MHz
16
bit
ResPWM
PWM resolution
139/161
ST72324
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V DD,
fCPU, and TA unless otherwise specified.
Symbol
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Parameter
Conditions
Master
fSCK
1/tc(SCK)
fCPU=8MHz
SPI clock frequency
Slave
fCPU=8MHz
Min
Max
fCPU/128
0.0625
fCPU/4
2
0
fCPU/2
4
tr(SCK)
tf(SCK)
SPI clock rise and fall time
tsu(SS)
th(SS)
SS setup time
SS hold time
Slave
Slave
120
120
SCK high and low time
Master
Slave
100
90
Data input setup time
Master
Slave
100
100
Data input hold time
Master
Slave
100
100
0
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
ta(SO)
Data output access time
Slave
Data output disable time
Slave
Data output valid time
Data output hold time
tv(MO)
th(MO)
Data output valid time
Data output hold time
MHz
see I/O port pin description
tdis(SO)
tv(SO)
th(SO)
Unit
ns
120
240
90
Slave (after enable edge)
0
Master (before capture edge)
0.25
0.25
tCPU
Figure 87. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
SCK INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
MISO OUTPUT
tw(SCKH)
tw(SCKL)
MSB OUT
see note 2
tsu(SI)
MOSI INPUT
tv(SO)
th(SO)
BIT6 OUT
tdis(SO)
tr(SCK)
tf(SCK)
LSB OUT
see
note 2
th(SI)
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
140/161
ST72324
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 88. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
SCK INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO OUTPUT
see
note 2
tv(SO)
th(SO)
MSB OUT
HZ
tsu(SI)
BIT6 OUT
LSB OUT
see
note 2
th(SI)
MSB IN
MOSI INPUT
tdis(SO)
tr(SCK)
tf(SCK)
Figure 89. SPI Master Timing Diagram
BIT1 IN
LSB IN
1)
SS INPUT
tc(SCK)
SCK INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tsu(MI)
MISO INPUT
MOSI OUTPUT see note 2
th(MI)
MSB IN
tv(MO)
tr(SCK)
tf(SCK)
BIT6 IN
LSB IN
th(MO)
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
141/161
ST72324
12.12 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
ADC clock frequency
fADC
VAREF
VAIN
Analog reference
0.7*VDD≤VAREF≤VDD
voltage 2)
Conversion voltage range
3)
Max
Unit
0.4
2
MHz
3.8
5.5
VSSA
VAREF
-40°C≤TA≤85°C range
Input leakage current
for analog input
IL
Typ 1)
External input impedance
CAIN
External capacitor on analog input
fAIN
Variation freq. of analog input signal
CADC
Internal sample and hold capacitor
12
tSTAB
Stabilization time after ADC enable
0 5)
Conversion time (Sample+Hold)
7.5
fCPU=8MHz, SPEED=0
- No of sample capacitor loading cycles fADC=2MHz
- No. of Hold conversion cycles
tADC
Figure 90. RAIN max. vs fADC with CAIN=0pF4)
nA
±1
µA
see
Figure 90
and
Figure
913)4)5)
kΩ
pF
Hz
pF
µs
4
11
1/fADC
Figure 91. Recommended CAIN & RAIN values.5)
45
1000
40
Cain 10 nF
2 MHz
30
1 MHz
25
Cain 22 nF
100
Max. R AIN (Kohm)
35
Max. R AIN (Kohm)
±250
Other TA ranges
RAIN
V
20
15
10
Cain 47 nF
10
1
5
0
0.1
0
10
30
70
0.01
0.1
CPARASITIC (pF)
1
10
f AIN(KHz)
Figure 92. Typical A/D Converter Application
VDD
RAIN
AINx
ST72XXX
VT
0.6V
2kΩ(max)
VAIN
CAIN
VT
0.6V
IL
±1µA
10-Bit A/D
Conversion
CADC
12pF
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
5. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).
142/161
ST72324
ADC CHARACTERISTICS (Cont’d)
12.12.1 Analog Power Supply and Reference
Pins
Depending on the MCU pin count, the package
may feature separate VAREF and VSSA analog
power supply pins. These pins supply power to the
A/D converter cell and function as the high and low
reference voltages for the conversion. In some
packages, VAREF and VSSA pins are not available
(refer to Table 1). In this case the analog supply
and reference pads are internally bonded to the
VDD and VSS pins.
Separation of the digital and analog power pins allow board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see Section
12.12.2 General PCB Design Guidelines).
12.12.2 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Use separate digital and analog planes. The analog ground plane should be connected to the
digital ground plane via a single point on the
PCB.
– Filter power to the analog power planes. It is recommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines, placing 0.1µF and optionally, if
needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10µF capacitor close to the power source (see Figure
93).
– The analog and digital power supplies should be
connected in a star nework. Do not use a resistor, as VAREF is used as a reference voltage by
the A/D converter and any resistance would
cause a voltage drop and a loss of accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being
converted.
Figure 93. Power Supply Filtering
10pF
(if needed) 0.1µF
1 to 10µF
ST7
DIGITAL NOISE
FILTERING
ST72XXX
VSS
VDD
VDD
POWER
SUPPLY
SOURCE
10pF
(if needed) 0.1µF
EXTERNAL
NOISE
FILTERING
VAREF
VSSA
143/161
ST72324
10-BIT ADC CHARACTERISTICS (Cont’d)
12.12.3 ADC Accuracy
Conditions: VDD=5V
Symbol
|ET|
EO
EG
Parameter
Conditions
Typ
1)
Gain
3
3.52)
-0.5
-22)
CPU in run mode @ fADC 2 MHz.
1.5
4.5
2)
CPU in run mode @ fADC 2 MHz.
1.5
4.52)
1)
Error 1)
error 1)
|ED|
Differential linearity
|EL|
Integral linearity error 1)
Unit
4
Total unadjusted error
Offset error
Max
LSB
Notes:
1. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC
accuracy.
2. Data based on characterization results, monitored in production.
Figure 94. ADC Accuracy Characteristics
Digital Result ADCDR
EG
1023
1022
1LSB
1021
IDEAL
V
–V
A REF
SS A
= --------------------------------------------
1024
(2)
ET
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
(3)
7
(1)
6
5
EO
4
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
144/161
Vin (LSBIDEAL)
2
3
4
5
6
7
1021 1022 1023 1024
VAREF
ST72324
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 95. 44-Pin Thin Quad Flat Package
Dim.
A
A2
D
D1
b
e
c
L1
A1
0.05
A2
1.35
1.40
b
0.30
0.37
C
0.09
inches
Max
Min
Typ
Max
1.60
0.063
0.15 0.002
0.006
1.45 0.053 0.055 0.057
0.45 0.012 0.015 0.018
0.20 0.004 0.000 0.008
D
12.00
0.472
D1
10.00
0.394
E
12.00
0.472
E1
10.00
0.394
e
0.80
0.031
θ
0°
3.5°
L
0.45
0.60
L1
L
Typ
A
A1
E1 E
mm
Min
7°
0°
3.5°
7°
0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
h
N
44
Figure 96. 32-Pin Thin Quad Flat Package
Dim.
mm
Min
Typ
D
A
A
D1
A2
A1
0.05
A2
1.35
1.40
b
0.30
0.37
C
0.09
A1
e
E1 E
b
c
L1
L
h
inches
Max
Min
Typ
0.063
0.15 0.002
0.006
1.45 0.053 0.055 0.057
0.45 0.012 0.015 0.018
0.20 0.004
0.008
D
9.00
0.354
D1
7.00
0.276
E
9.00
0.354
E1
7.00
0.276
e
0.80
θ
0°
3.5°
L
0.45
0.60
L1
Max
1.60
0.031
7°
0°
3.5°
7°
0.75 0.018 0.024 0.030
1.00
0.039
Number of Pins
N
32
145/161
ST72324
PACKAGE MECHANICAL DATA (Cont’d)
Figure 97. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
Dim.
E
mm
Min
Typ
A
A
A2
A1
b2
L
c
e
b
E1
eA
eB
D
E
0.015
GAGE PLANE
eC
inches
Max
Min
Typ
5.08
Max
0.200
A1
0.51
0.020
A2
3.05
3.81
4.57 0.120 0.150 0.180
b
0.38
0.46
0.56 0.015 0.018 0.022
b2
0.89
1.02
1.14 0.035 0.040 0.045
c
0.23
0.25
0.38 0.009 0.010 0.015
D
36.58 36.83 37.08 1.440 1.450 1.460
E
15.24
E1
12.70 13.72 14.48 0.500 0.540 0.570
16.00 0.600
0.630
e
1.78
0.070
eA
15.24
0.600
eB
18.54
0.730
eC
1.52 0.000
0.060
eB
L
2.54
3.30
3.56 0.100 0.130 0.140
Number of Pins
N
42
Figure 98. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
Dim.
E
A2 A
A1
L
C
b
b2
D
e
mm
inches
Min
Typ
Max
A
3.56
3.76
5.08 0.140 0.148 0.200
A1
0.51
A2
3.05
3.56
4.57 0.120 0.140 0.180
eC
Min
Typ
0.020
b
0.36
0.46
0.58 0.014 0.018 0.023
E1
b1
0.76
1.02
1.40 0.030 0.040 0.055
eA
eB
C
0.20
0.25
D
27.43
E
9.91 10.41 11.05 0.390 0.410 0.435
E1
7.62
0.36 0.008 0.010 0.014
28.45 1.080 1.100 1.120
8.89
9.40 0.300 0.350 0.370
e
1.78
0.070
eA
10.16
0.400
eB
12.70
0.500
eC
1.40
0.055
L
2.54
3.05
3.81 0.100 0.120 0.150
Number of Pins
N
146/161
Max
32
ST72324
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
RthJA
Package thermal resistance (junction to ambient)
TQFP44 10x10
TQFP32 7x7
SDIP42 600mil
SDIP32 200mil
52
70
55
50
Power dissipation 1)
500
mW
150
°C
PD
TJmax
Maximum junction
temperature 2)
Unit
°C/W
Notes:
1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
147/161
ST72324
13.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines.
Figure 99. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
150
SOLDERING
PHASE
80°C
Temp. [°C]
100
50
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
PREHEATING
PHASE
Time [sec]
0
20
40
60
80
100
120
140
160
Figure 100. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=235+/-5°C
for 25 sec
200
150
90 sec at 125°C
150 sec above 183°C
Temp. [°C]
100
50
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
Recommended glue for SMD plastic packages dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
148/161
ST72324
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
ST72324 devices are ROM versions. ST72P324
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are factory-programmed HDFlash devices. FLASH devices are
shipped to customers with a default content (FFh),
while ROM/FASTROM factory coded parts contain
the code supplied by the customer. This implies
that FLASH devices have to be configured by the
customer using the Option Bytes while the ROM/
FASTROM devices are factory-configured.
14.1 FLASH OPTION BYTES
STATIC OPTION BYTE 0
STATIC OPTION BYTE 1
FMP_R
PKG1
RSTC
SW
CSS
HALT
1
1
0
0
1
1
1
1
1
The option bytes allows the hardware configuration of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. To program directly the FLASH devices using ICP,
FLASH devices are shipped to customers with the
internal RC clock source. In masked ROM devices, the option bytes are fixed in hardware by the
ROM code (see option list).
OPTION BYTE 0
OPT7= WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OSCTYPE
OSCRANGE
1
0
2
1
0
PLLOFF
0
VD
1
0
1
WDG
Default
7
Reserved
0
Reserved
7
1
0
1
1
1
1
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+AVD).
Selected Low Voltage Detector
LVD and AVD Off
Lowest Threshold: (VDD~3V)
Med. Threshold (VDD~3.5V)
Highest Threshold (VDD~4V)
VD1
VD0
1
1
0
0
1
0
1
0
Caution: If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
AVD and LVD threshold levels refer to Section
12.3.3 on page 117
OPT2:1 = Reserved, must be kept at default value.
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = CSS Clock security system on/off
This option bit enables or disables the clock security system function (CSS) which includes the
clock filter and the backup safe oscillator.
0: CSS enabled
1: CSS disabled
Caution: The CSS function is not guaranteed. Refer to Section 15.
OPT0= FMP_R Flash memory read-out protection
This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. Erasing the
option bytes when the FMP_R option is selected
causes the whole user memory to be erased first,
and the device can be reprogrammed. Refer to
Section 4.3.1 and the ST7 Flash Programming
Reference Manual for more details.
0: Read-out protection enabled
1: Read-out protection disabled
149/161
ST72324
ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPTION BYTE 1
OPT7= PKG1 Pin package selection bit
This option bit selects the package.
OSCRANGE
Typ. Freq. Range
Version
Selected Package
PKG1
J
TQFP44 / SDIP42
1
K
TQFP32 / SDIP32
0
Note: On the chip, each I/O port has 8 pads. Pads
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration
of these pads must be kept at reset state to avoid
added current consumption.
OPT6 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OSCTYPE
Clock Source
1
0
Resonator Oscillator
0
0
Reserved
0
1
Internal RC Oscillator
1
0
External Source
1
1
OPT3:1 = OSCRANGE[2:0] Oscillator range
When the resonator oscillator type is selected,
these option bits select the resonator oscillator
current source corresponding to the frequency
range of the used resonator. Otherwise, these bits
are used to select the normal operating frequency
150/161
2
1
0
LP
1~2MHz
0
0
0
MP
2~4MHz
0
0
1
MS
4~8MHz
0
1
0
HS
8~16MHz
0
1
1
OPT0 = PLLOFF PLL activation
This option bit activates the PLL which allows multiplication by two of the main input clock frequency.
The PLL is guaranteed only with an input frequency between 2 and 4MHz.
0: PLL x2 enabled
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT3:1) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionality is not guaranteed.
ST72324
ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
ROM devices can be ordered in any combination
of memory size and temperature range with the
types given in Figure 101 and by completing the
option list on the next page. Flash devices are
available only in the types listed in Table 25.
ROM customer code is made up of the ROM contents and the list of the selected options (if any).
The ROM contents are to be sent with the S19
hexadecimal file generated by the development
tool. All unused bytes must be set to FFh.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.The STMicroelectronics
Sales Organization will be pleased to provide detailed information on contractual points.
Figure 101. ROM Factory Coded Device Types
DEVICE PACKAGE VERSION / XXX
Code name (defined by STMicroelectronics)
1 = Standard 0 to +70 °C
5 = Standard -10 to +85 °C
6 = Standard -40 to +85 °C
A = Automotive -40 to +85 °C
B = Automotive -40 to +105 °C
C = Automotive -40 to +125 °C
T= Plastic Thin Quad Flat Pack
B= Plastic Dual in Line
ST72324J6, ST72324J4, ST72324J2
ST72324K6, ST72324K4, ST72324K2
151/161
ST72324
ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
Table 25. Orderable Flash Device Types
Part Number
Version
Package
Flash
Memory
(KBytes)
ST72F324K2TA
8
ST72F324K4TA
16
TQFP32
ST72F324K6TA
ST72F324K6TC
ST72F324J6TA
ST72F324J2TA
ST72F324J6TC
16
ST72F324K2T6
8
ST72F324K4T6
16
TQFP32
32
ST72F324K2B5
8
ST72F324K6B5
ST72F324J2T6
ST72F324J4T6
ST72F324J6T6
SDIP32
16
-10°C +85°C
8
TQFP44
16
-40°C +85°C
32
32
ST72F324J2B5
8
SDIP42
ST72F324J6B5
14.2.1 Version-Specific Sales Conditions
To satisfy the different customer requirements and
to ensure that ST Standard Microcontrollers will
consistently meet or exceed the expectations of
each Market Segment, the Codification System for
Standard Microcontrollers clearly distinguishes
products intended for use in automotive environments, from products intended for use in non-automotive environments.
It is the responsibility of the Customer to select the
appropriate product for his application.
152/161
-40°C +85°C
32
Standard
ST72F324J6T5
ST72F324J4B5
-40°C +125°C
32
ST72F324K6T5
ST72F324K4B5
-40°C +85°C
32
32
ST72F324K6T6
-40°C +125°C
8
TQFP44
ST72F324J4TA
-40°C +85°C
32
32
Automotive
Temp. Range
16
32
-10°C +85°C
ST72324
ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
ST72324 MICROCONTROLLER OPTION LIST
................................
................................
................................
Contact:
................................
Phone No:
................................
Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . .
*The ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Customer:
Address:
Device Type/Memory Size/Package (check only one option):
--------------------------------- | ------------------------------------- ------------------------------------- ----------------------------------||
||
32K
ROM DEVICE:
16K
8K
--------------------------------- | ------------------------------------- ------------------------------------- ----------------------------------TQFP32:
|
[ ] ST72324K6T
|
[ ] ST72324K4T
|
[ ] ST72324K2T
DIP32:
|
[ ] ST72324K6B
|
[ ] ST72324K4B
|
[ ] ST72324K2B
TQFP44 :
|
[ ] ST72324J6T
|
[ ] ST72324J4T
|
[ ] ST72324J2T
DIP42:
|
[ ] ST72324J6B
|
[ ] ST72324J4B
|
[ ] ST72324J2B
--------------------------------- | -------------------------------------- -------------------------------------- ----------------------------------DIE FORM:
32K
||
16K
||
8K
--------------------------------- | -------------------------------------- -------------------------------------- -----------------------------------32-pin:
|
[]
|
[]
|
[]
44-pin:
|
[]
|
[]
|
[]
Conditioning (check only one option):
------------------------------------------------------------------------ ----------------------------------------------------| Die Product (dice tested at 25°C only)
Packaged Product
---------------------------------------------------------------------------------------------------------------------------[ ] Tape & Reel
[ ] Tray
| [ ] Tape & Reel
| [ ] Inked wafer
| [ ] Sawn wafer on sticky foil
Version/Temp. Range (do not check for die product). Please refer to datasheet for specific sales conditions:
-------------------- || ------------------- --------------------------------------Standard
Automotive || --------------------------------------Temp. Range
-------------------------------------[]
|
| 0°C to +70°C
[]
|
| -10°C to +85°C
[]
|
[]
| -40°C to +85°C
|
[]
|
-40°C to +105°C
|
[]
|
-40°C to +125°C
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ " (TQFP32 7 char., other pkg. 10 char. max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock Source Selection:
[ ] Resonator:
PLL2
CSS4
LVD Reset
[ ] Internal RC1
[ ] External Clock
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Disabled
[ ] Disabled
[ ] Disabled
Reset Delay
Watchdog Selection:
Halt when Watchdog on:
[ ] Enabled
[ ] Enabled
[ ] High threshold
[ ] Med. threshold5 [ ] Low threshold5
[ ] 256 Cycles
[ ] 4096 Cycles
[ ] Software Activation
[ ] Hardware Activation
[ ] Reset
[ ] No reset
[ ] Disabled
Readout Protection3:
Date
Signature
................................
1LVD must be enabled when internal RC is selected.
2PLL must not be enabled if internal RC or External Clock
3
is selected.
[ ] Enabled
4Not guaranteed
5Device operation
below 3.8V not guaranteed
Readout protection is not supported if LVD is enabled.
153/161
ST72324
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST7 microcontroller family. Full details of tools available for
the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
Tools from these manufacturers include C compliers, emulators and gang programmers.
ST Emulators
The emulator is delivered with everything (probes,
TEB, adapters etc.) needed to start emulating the
devices. To configure the emulator to emulate different ST7 subfamily devices, the active probe for
the ST7 EMU3 can be changed and the ST7EMU3
probe is designed for easy interchange of TEBs
(Target Emulation Board). See Table 26 for more
details.
14.3.1
Socket
and
Emulator
Adapter
Information
For information on the type of socket that is supplied with the emulator, refer to the suggested list
of sockets in Table 27.
Note: Before designing the board layout, it is recommended to check the overall dimensions of the
socket as they may be greater than the dimensions of the device.
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet (www.yamaichi.de for
TQFP44 10 x 10 and www.ironwoodelectronics.com for TQFP32 7 x 7)
Table 26. STMicroelectronics Development Tools
Supported Products
ST72324J, ST72F324J
ST72324K, ST72F324K
ST7 Evaluation
Board
ST7 Emulator
N/A
ST7MDT20JEMU3
Active Probe &
T.E.B.
ST7 Programming Board
ST7MDT20J-EPB/EU
ST7MDT20J-TEB
ST7MDT20J-EPB/US
ST7MDT20J-EPB/UK
Note:
1. Flash Programming interface for FLASH devices.
Table 27. Suggested List of Socket Types
154/161
Device
Socket (supplied with
ST7MDT20J-EMU3)
Emulator Adapter (supplied with
ST7MDT20J-EMU3)
TQFP32 7 X 7
IRONWOOD SF-QFE32SA-L-01
IRONWOOD SK-UGA06/32A-01
TQFP44 10 X10
YAMAICHI IC149-044-*52-*5
YAMAICHI ICP-044-5
ST72324
14.4 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
EXAMPLE DRIVERS
AN 969
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
AN 972
ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
AN1042
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
AN1044
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
AN1046
UART EMULATION SOFTWARE
AN1047
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048
ST7 SOFTWARE LCD DRIVER
AN1078
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
AN1083
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105
ST7 PCAN PERIPHERAL DRIVER
AN1129
PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
AN1130
WITH THE ST72141
AN1148
USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149
HANDLING SUSPEND MODE ON A USB MOUSE
AN1180
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
AN1475
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910
PERFORMANCE BENCHMARKING
AN 990
ST7 BENEFITS VERSUS INDUSTRY STANDARD
AN1077
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1150
BENCHMARK ST72 VS PC16
AN1151
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
155/161
ST72324
IDENTIFICATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1324
AN1477
AN1502
AN1529
DESCRIPTION
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILAN1530
LATOR
PROGRAMMING AND TOOLS
AN 978
KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
AN 983
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985
EXECUTING CODE IN ST7 RAM
AN 986
USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987
ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN 989
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
AN1039
ST7 MATH UTILITY ROUTINES
AN1064
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
AN1071
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
AN1106
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179
GRAMMING)
AN1446
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
AN1478
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
AN1527
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
AN1575
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
156/161
ST72324
15 IMPORTANT NOTES
15.1 Silicon Identification
15.2 ALL FLASH AND ROM DEVICES
This document refers to ST72F324/ST72324 devices shown in Table 28 and Table 29. They are
identifiable both by the last letter of the Trace
code marked on the device package and by the
last 3 digits of the Internal Sales Type printed on
the box label.
15.2.1 External RC option
The External RC clock source option described in
previous datasheet revisions is no longer supported and has been removed from this specification.
15.2.2 CSS Function
The Clock Security System function is not guaranteed. The features described in Section 6.4.3 are
subject to revision.
15.2.3 Safe Connection of OSC1/OSC2 Pins
The OSC1 and/or OSC2 pins must not be left unconnected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed
maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. Refer to Section 6.2 on page
24.
15.2.4 Unexpected Reset Fetch
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.2.5 Internal RC Oscillator with LVD
The internal RC can only be used if LVD is enabled.
15.2.6 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
Table 28. Flash Device Identification
Part
Number
ST72F324
xxxx
ST72F324
xxxx
Trace Code
marked on device
“xxxxxxxxxW”
(current revision)
“xxxxxxxxxX”
Internal Sales Type
on box label
72F324xxxx$A5
72F324xxxx$U5
72F324xxxx$A4
72F324xxxx$U4
Table 29. ROM Device Identification
Part
Number
ST72324xx
xx
ST72324xx
xx
Trace Code
Internal Sales Type
marked on device on box label
“xxxxxxxxxY”
72324xxxx/xxx$A3
“xxxxxxxxxA”
72324xxxx/xxx$U1
157/161
ST72324
15.3 FLASH REV “X” and ALL ROM DEVICES
15.3.1 Read-out protection with LVD
The LVD is not supported if the read-out protection
is enabled.
15.3.2 External clock source with PLL
External clock source is not supported with the
PLL enabled.
15.3.3 I/O Port A and F Configuration
When using an external quartz crystal or ceramic
resonator, the fOSC2 clock may be disturbed because the device goes into reserved mode controlled by Port A and F.
This happens with either one of the following configurations:
PA3=0, PF4=1, PF1=0 while CSS and PLL options are both disabled and PF0 is toggling
PA3=0, PF4=1, PF1=0, PF0=1 while CSS or PLL
options are enabled
This is detailed in the following table:
Clock
Disturbance
Max. 2 clock
Tog cycles lost at
glin each rising or
g falling edge of
PF0
Max. 1 clock
1 cycle lost out
of every 16
CSS PLL PA3 PF4 PF1 PF0
OFF OFF
x
ON
ON
x
0
1
0
0
1
0
As a consequence, for cycle-accurate operations,
these configurations are prohibited in either input
or output mode.
Workaround:
To avoid this occurring, it is recommended to connect one of these pins to GND (PF4 or PF0) or
VDD (PA3 or PF1).
158/161
15.3.4 LVD Operation
Depending on the operating conditions, especially
the VDD ramp up speed and ambient temperature,
in some cases the LVD may not start. When this
occurs, the MCU may operate outside the guaranteed functional area (see datasheet Figure 76)
without being forced into reset state.
In this case, proper use of the watchdog may
make it possible to recover through a watchdog reset and allow normal operations to resume.
Consequently, the LVD function is not guaranteed
in the current silicon revision. For complete security, an external reset circuit must be added.
15.4 ALL ROM DEVICES
15.4.1 AVD not supported
On some devices with a specific VDD ramp up
speed the AVD may not start. As a result it cannot
generate interrupts when VDD rises and falls.
15.4.2 Internal RC oscillator operation
Internal RC oscillator operation is not supported in
ROM devices.
ST72324
Table 30. Product Evolution Summary
Section
Limitation
Silicon Rev.
FLASH Devices
ROM Devices
Previous
Current
Current
Current
Rev “X”
Rev“W”
Rev “Y”
Rev “A”
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
15.2.6
15.3.1
EXTERNAL RC OPTION
CSS FUNCTION
SAFE CONNECTION OF OSC1/OSC2 PINS
UNEXPECTED RESET FETCH
INTERNAL RC OSCILLATOR WITH LVD
16-BIT TIMER PWM MODE
READ-OUT PROTECTION WITH LVD
●
●
●
●
●
●
●
15.3.2
EXTERNAL CLOCK WITH PLL
●
15.3.3
I/O PORT A & F CONFIGURATION
15.3.4
15.4.1
15.4.2
LVD OPERATION
AVD NOT SUPPORTED
INTERNAL RC OSCILLATOR OPERATION
●
●
Legend: Limitation present =
●;
❍
❍
●
●
●
●
●
●
❍
❍
❍
❍
❍
❍
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Limitation not present = ❍.
159/161
1
ST72324
16 SUMMARY OF CHANGES
Revision
Main Changes
Date
Modified “ACTIVE-HALT AND HALT MODES” on page 42: wakeup from active halt by reset
or MCC/RTC interrupt only
Changed references to planned low voltage version to refer to flash only
1.7
Reset pin IINJMAX for changed to 2 mA in Section 12.9.1 and Section 12.2
Mar 03
Updated ordering information Section 18.2 on page 230
Updated EMI data in “EMC CHARACTERISTICS” on page 130
Added “IMPORTANT NOTES” on page 157
1.8
Updated Errata sheet
July 03
Changed document name from ST72324J/K to ST72324
Removed External RC option from Section 6.2 on page 24 and throughout document
Added Caution ‘CSS function is not guaranteed’ to Section 6.4 on page 27 and Section 14.1
on page 149
Removed restrictions on PWM mode in 16-bit timer A. Added notes on Timer A IC2 and OC2
registers and interrupts in Table 2. and throughout Section 10.3
Modified description of internal RC oscillator in Section 6.2.
Added note to “MULTI-OSCILLATOR (MO)” on page 24 External clock source not supported if PLL is enabled
Added Caution about disconnecting OSC pins in Section 6.2 on page 24
Moved LVD startup behaviour diagram from Section 12.3.3 on page 117 to Section 15
1.9
Modified notes in table of Murata resonators in Section 12.5.3
August 03
Modified description of VAREF/VSSA pins in Section 12.12.1 on page 143
Added phrase “can be reprogrammed” in Section 4.3.1 on page 17 and Section 14.1 on
page 149
Added heading “Related Documentation” on page 19
Updated “EMC CHARACTERISTICS” on page 130
Added FASTROM information to Section 14 on page 149
Added note under VD option bit table in Section 14.1 on page 149
Updated option list in Section 14.2 on page 151
Removed Errata sheet and put information in “IMPORTANT NOTES” on page 157
Please read carefully the “IMPORTANT NOTES” on page 157
160/161
1
ST72324
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
161/161