STMICROELECTRONICS ST72T511R9T6S

ST72311R, ST72511R,
ST72512R, ST72532R
8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC,
16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
DATASHEET
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Memories
– 16K to 60K bytes Program memory
(ROM,OTP and EPROM)
with read-out protection
– 256 bytes E2PROM Data memory
(only on ST72532R4)
– 1024 to 2048 bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system
– Low voltage supply supervisor
– Clock sources: crystal/ceramic resonator oscillator or external clock
– Beep and Clock-out capability
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
Interrupt Management
– Nested interrupt controller
– 13 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
– TLI dedicated top level interrupt pin
48 I/O Ports
– 48 multifunctional bidirectional I/O lines
– 32 alternate function lines
– 12 high sink outputs
5 Timers
– Configurable watchdog timer
– Real time clock timer
– One 8-bit auto-reload timer with 4 independent PWM output channels, 2 input captures,
output compares and external clock with
event detector (except on ST725x2R4)
– Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes
TQFP64
14 x 14
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3 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
– CAN interface (except on ST72311Rx)
1 Analog peripheral
– 8-bit ADC with 8 input channels
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
Development Tools
– Full hardware/software development package
Device Summary
Features
ST72511R9 ST72511R7 ST72511R6
ST72311R9 ST72311R7 ST72311R6 ST72512R4
ST72532R4
Program memory - bytes
60K
48K
32K
60K
48K
32K
16K
16K
RAM (stack) - bytes
2048 (256) 1536 (256) 1024 (256) 2048 (256) 1536 (256) 1024 (256) 1024 (256)
1024 (256)
EEPROM - bytes
256
watchdog, two 16-bit timers, 8-bit PWM watchdog, two 16-bit timers, 8-bit PWM watchdog, two 16-bit timers,
Peripherals
ART, SPI, SCI, CAN, ADC
ART, SPI, SCI, ADC
SPI, SCI, CAN, ADC
Operating Supply
3.0V to 5.5V
3.0 to 5.5V 1)
CPU Frequency
2 to 8 MHz (with 4 to 16 MHz oscillator)
2 to 4 MHz 1)
Operating Temperature
-40°C to +85°C (-40°C to +105/125°C optional)
Packages
TQFP64
Note 1. See Section 12.3.1 on page 133 for more information on VDD versus fOSC.
Rev. 2.1
February 2000
1/164
1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
15
16
16
16
3.3
MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
3.6
ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
4.3
MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
26
26
26
27
6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2
MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3
INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4
6.5
CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3
WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4
ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
2/164
2
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
...
8.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
37
38
38
38
38
38
38
Table of Contents
8.3
I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4
8.5
LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.5.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2
9.3
I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . .
49
49
49
50
50
50
50
52
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
52
52
53
53
53
54
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
55
58
61
61
61
61
73
73
73
74
79
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
79
79
81
88
88
89
3/164
3
ST72311R, ST72511R, ST72512R, ST72532R
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.7 CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
105
105
111
121
10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
121
121
122
122
123
125
125
126
126
126
126
126
127
127
128
131
131
131
131
131
131
131
132
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
132
132
132
133
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . .
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
133
134
135
135
136
4/164
ST72311R, ST72511R, ST72512R, ST72532R
12.4.3 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4.5 On-Chip Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
137
137
138
138
138
138
139
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.2 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6.3 EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
139
139
140
12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
141
143
145
145
146
147
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.9.2 VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.10.28-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.10.316-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . .
148
148
148
149
12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.11.2SCI - Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.11.3CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
149
151
151
152
154
154
155
13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 158
14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 159
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15 ST7 GENERIC APPLICATION NOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5/164
ST72311R, ST72511R, ST72512R, ST72532R
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72311R, ST72511R, ST72512R and
ST72532R devices are members of the ST7 microcontroller family. They can be grouped as follows:
– ST725xxR devices are designed for mid-range
applications with a CAN bus interface (Controller
Area Network)
– ST72311R devices target the same range of applications but without CAN interface.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram
8-BIT CORE
ALU
RESET
VPP
TLI
CONTROL
RAM
(1024, 2048 Bytes)
VDD
VSS
LVD
OSC1
OSC2
OSC
PORT F
PF7:0
(8-BIT)
TIMER A
BEEP
PORT E
PE7:0
(8-BIT)
CAN
SCI
PORT D
PD7:0
(8-BIT)
8-BIT ADC
6/164
4
EEPROM
(256 Bytes)
ADDRESS AND DATA BUS
MCC/RTC
VDDA
VSSA
PROGRAM
MEMORY
(16K - 60K Bytes)
WATCHDOG
PORT A
PA7:0
(8-BIT)
PORT B
PB7:0
(8-BIT)
PWM ART
PORT C
TIMER B
SPI
PC7:0
(8-BIT)
ST72311R, ST72511R, ST72512R, ST72532R
1.2 PIN DESCRIPTION
PA4 (HS)
PA6 (HS)
PA5 (HS)
PA7 (HS)
RESET
VPP
OSC2
VSS_2
OSC1
PE0 / TDO
VDD_2
TLI
nc
VSS_1
VDD_1
PA3
PA2
PA1
PA0
PC7 / SS
PC6 / SCK
PC5 / MOSI
PC4 / MISO
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
VSS_0
VDD_0
ICAP2_A / PF5
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
OCMP1_A / PF4
PF2
OCMP2_A / PF3
BEEP / PF1
AIN2 / PD2
AIN3 / PD3
37
36
35
ei1
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
12
13
14
VSS_3
MCO / PF0
AIN0 / PD0
AIN1 / PD1
VDD_3
PB5
PB6
PB7
AIN7 / PD7
VDDA
VSSA
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / PB4
AIN6 / PD6
(HS) PE7
PWM3 / PB0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
2
46
3
45
4
ei0
44
5
43
6
ei2
42
7
41
8
40
9
39
10
38
11 ei3
1
AIN4 / PD4
AIN5 / PD5
(HS) PE4
(HS) PE5
(HS) PE6
PE1 / RDI
PE3 / CANRX
PE2 / CANTX
Figure 2. 64-Pin TQFP Package Pinout
(HS) 20mA high sink capability
eix associated external interrupt vector
7/164
5
ST72311R, ST72511R, ST72512R, ST72532R
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 12 ”ELECTRICAL CHARACTERISTICS” on page
131.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
– Output:
OD = open drain 2), PP = push-pull
Refer to Section 8 ”I/O PORTS” on page 38 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
I/O CT HS
X
X
X
X
Port E4
2
PE5 (HS)
I/O CT HS
X
X
X
X
Port E5
3
PE6 (HS)
I/O CT HS
X
X
X
X
Port E6
4
PE7 (HS)
I/O CT HS
X
X
X
X
Port E7
5
PB0/PWM3
I/O
CT
X
ei2
X
X
Port B0
PWM Output 3
6
PB1/PWM2
I/O
CT
X
ei2
X
X
Port B1
PWM Output 2
7
PB2/PWM1
I/O
CT
X
ei2
X
X
Port B2
PWM Output 1
8
PB3/PWM0
I/O
CT
X
ei2
X
X
Port B3
PWM Output 0
ei3
PWM-ART External Clock
ana
PE4 (HS)
int
PP
Alternate function
OD
Output
wpu
Inpu t
Main
function
(after
reset)
float
Output
Input
Port
1
9
PB4/ARTCLK
I/O
CT
X
X
X
Port B4
10
PB5
I/O
CT
X
ei3
X
X
Port B5
11
PB6
I/O
CT
X
ei3
X
X
Port B6
12
PB7
I/O
CT
X
ei3
X
X
Port B7
13
PD0/AIN0
I/O
CT
X
X
X
X
X
Port D0
ADC Analog Input 0
14
PD1/AIN1
I/O
CT
X
X
X
X
X
Port D1
ADC Analog Input 1
15
PD2/AIN2
I/O
CT
X
X
X
X
X
Port D2
ADC Analog Input 2
16
PD3/AIN3
I/O
CT
X
X
X
X
X
Port D3
ADC Analog Input 3
17
PD4/AIN4
I/O
CT
X
X
X
X
X
Port D4
ADC Analog Input 4
18
PD5/AIN5
I/O
CT
X
X
X
X
X
Port D5
ADC Analog Input 5
19
PD6/AIN6
I/O
CT
X
X
X
X
X
Port D6
ADC Analog Input 6
20
PD7/AIN7
I/O
CT
X
X
X
X
X
Port D7
ADC Analog Input 7
21
V DDA
S
Analog Power Supply Voltage
22
V SSA
S
Analog Ground Voltage
23
V DD_3
S
Digital Main Supply Voltage
8/164
6
Pin Name
Type
Level
TQFP64
Pin n°
ST72311R, ST72511R, ST72512R, ST72532R
Port
PP
OD
Output
ana
int
wpu
Inpu t
float
Input
Type
TQFP64
Pin Name
Output
Level
Pin n°
S
Main
function
(after
reset)
Alternate function
Digital Ground Voltage
24
V SS_3
25
PF0/MCO
I/O
CT
X
ei1
X
X
Port F0
Main clock output (fOSC/2)
26
PF1/BEEP
I/O
CT
X
ei1
X
X
Port F1
Beep signal output
27
PF2
I/O
CT
X
X
X
Port F2
28
PF3/OCMP2_A
I/O
CT
X
X
ei1
X
X
Port F3
Timer A Output Compare 2
29
PF4/OCMP1_A
I/O
CT
X
X
X
X
Port F4
Timer A Output Compare 1
30
PF5/ICAP2_A
I/O
CT
X
X
X
X
Port F5
Timer A Input Capture 2
31
PF6 (HS)/ICAP1_A
I/O CT HS
X
X
X
X
Port F6
Timer A Input Capture 1
32
PF7 (HS)/EXTCLK_A I/O CT HS
X
X
X
X
Port F7
Timer A External Clock Source
33
V DD_0
34
V SS_0
35
PC0/OCMP2_B
I/O
CT
X
X
X
X
Port C0
Timer B Output Compare 2
36
PC1/OCMP1_B
I/O
CT
X
X
X
X
Port C1
Timer B Output Compare 1
37
PC2 (HS)/ICAP2_B
I/O CT HS
X
X
X
X
Port C2
Timer B Input Capture 2
38
PC3 (HS)/ICAP1_B
I/O CT HS
X
X
X
X
Port C3
Timer B Input Capture 1
39
PC4/MISO
I/O
CT
X
X
X
X
Port C4
SPI Master In / Slave Out Data
40
PC5/MOSI
I/O
CT
X
X
X
X
Port C5
SPI Master Out / Slave In Data
41
PC6/SCK
I/O
CT
X
X
X
X
Port C6
SPI Serial Clock
42
PC7/SS
I/O
CT
X
X
X
X
Port C7
SPI Slave Select (active low)
43
PA0
I/O
CT
X
ei0
X
X
Port A0
44
PA1
I/O
CT
X
ei0
X
X
Port A1
45
PA2
I/O
CT
X
ei0
X
X
Port A2
46
PA3
I/O
CT
X
X
X
Port A3
S
Digital Main Supply Voltage
S
Digital Ground Voltage
ei0
47
V DD_1
S
48
V SS_1
S
Digital Main Supply Voltage
49
PA4 (HS)
I/O CT HS
X
X
X
X
50
PA5 (HS)
I/O CT HS
X
X
X
X
51
PA6 (HS)
I/O CT HS
X
T
Port A6
52
PA7 (HS)
I/O CT HS
X
T
Port A7
53
V PP
54
RESET
I/O
55
NC
Not Connected
56
NMI
I
57
V SS_3
S
58
OSC2 3)
I/O
External clock mode input pull-up or crystal/ceramic resonator oscillator inverter output
59
OSC1 3)
I
External clock input or crystal/ceramic resonator oscillator inverter input
60
V DD_3
S
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
Port A5
Must be tied low in user mode. In programming
mode when available, this pin acts as the programming voltage input V PP .
I
C
CT
X
X
X
Top priority non maskable interrupt (active low)
Non maskable interrupt input pin
Digital Ground Voltage
9/164
ST72311R, ST72511R, ST72512R, ST72532R
Port
PP
X
X
X
X
X
X
PE0/TDO
I/O
CT
62
PE1/RDI
I/O
CT
X
63
PE2/CANTX
I/O
CT
64
PE3/CANRX
I/O
CT
ana
X
61
int
OD
Output
wpu
Inpu t
float
Output
Pin Name
Input
Level
Type
TQFP64
Pin n°
X
X
X
X
X
Main
function
(after
reset)
Port E0
Alternate function
SCI Transmit Data Out
Port E1
SCI Receive Data In
Port E2
CAN Transmit Data Output
Port E3
CAN Receive Data Input
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD
are not implemented). See Section 8 ”I/O PORTS” on page 38 and Section 12.8 ”I/O PORT PIN CHARACTERISTICS” on page 145 for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator
see Section 1.2 ”PIN DESCRIPTION” on page 7 and Section 12.5 ”CLOCK AND TIMING CHARACTERISTICS” on page 138 for more details.
10/164
ST72311R, ST72511R, ST72512R, ST72532R
1.3 REGISTER & MEMORY MAP
As shown in the Figure 3, the MCU is capable of
addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register location, up to 2Kbytes of RAM,
up to 256 bytes of data EEPROM and up to
60Kbytes of user program memory. The RAM
space includes up to 256 bytes for the stack from
0100h to 01FFh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 3. Memory Map
0000h
007Fh
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
1024 Bytes RAM
1536 Bytes RAM
087Fh
0880h
0080h
2048 Bytes RAM
00FFh
0100h
01FFh
0200h
16-bit Addressing
RAM
Reserved
0BFFh
0C00h
Optional EEPROM
(256 Bytes)
0CFFh
0D00h
Stack
(256 Bytes)
047Fh
or 067Fh
or 087Fh
1000h
60 KBytes
Reserved
4000h
0FFFh
1000h
48 KBytes
Program Memory
(60K, 48K, 32K, 16K Bytes)
FFDFh
FFE0h
FFFF h
8000h
32 KBytes
C000h
Interrupt & Reset Vectors
(see Table 7 on page 32)
16 KBytes
FFFF h
11/164
ST72311R, ST72511R, ST72512R, ST72532R
Table 2. Hardware Register Map
Address
Block
0000h
0001h
0002h
Port A
Register
Label
PADR
PADDR
PAOR
Register Name
Reset
Status
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h 1)
00h
00h
R/W
R/W
R/W 2)
00h 1)
00h
00h
R/W
R/W
R/W
00h 1)
00h
00h
R/W
R/W
R/W
00h 1)
00h
00h
R/W
R/W 2)
R/W 2)
00h 1)
00h
00h
R/W
R/W
R/W
00h 1)
00h
00h
R/W
R/W
R/W
0003h
0004h
0005h
0006h
Reserved Area (1 Byte)
Port C
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
0007h
0008h
0009h
000Ah
Reserved Area (1 Byte)
Port B
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
000Bh
000Ch
000Dh
000Eh
Reserved Area (1 Byte)
Port E
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
000Fh
0010h
0011h
0012h
Reserved Area (1 Byte)
Port D
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
0013h
0014h
0015h
0016h
Reserved Area (1 Byte)
Port F
PFDR
PFDDR
PFOR
0017h
to
001Fh
0024h
0025h
0026h
0027h
MISCR1
Miscellaneous Register 1
00h
R/W
SPI
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
ITC
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt
Interrupt
Interrupt
Interrupt
0
1
2
3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
Main Clock Control / Status Register
01h
R/W
0028h
0029h
12/164
Port F Data Register
Port F Data Direction Register
Port F Option Register
Reserved Area (9 Bytes)
0020h
0021h
0022h
0023h
Remarks
Software
Software
Software
Software
Priority
Priority
Priority
Priority
Register
Register
Register
Register
Reserved Area (1 Byte)
MCC
MCCSR
ST72311R, ST72511R, ST72512R, ST72532R
Register
Label
Address
Block
Register Name
002Ah
002Bh
WATCHDOG
WDGCR
WDGSR
Watchdog Control Register
Watchdog Status Register
002Ch
EEPROM
EECSR
Data EEPROM Control/Status Register
002Dh
to
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Reset
Status
Remarks
7Fh
000x 000x
R/W
R/W
00h
R/W
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read
Read
Read
R/W
R/W
Read
Read
Read
Read
Read
Read
R/W
R/W
Reserved Area (4 Bytes)
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
0040h
MISCR2
Miscellaneous Register 2
00h
R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read
Read
Read
R/W
R/W
Read
Read
Read
Read
Read
Read
R/W
R/W
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
TIMER A
TIMER B
SCI
SCIETPR
A Control Register 2
A Control Register 1
A Status Register
A Input Capture 1 High Register
A Input Capture 1 Low Register
A Output Compare 1 High Register
A Output Compare 1 Low Register
A Counter High Register
A Counter Low Register
A Alternate Counter High Register
A Alternate Counter Low Register
A Input Capture 2 High Register
A Input Capture 2 Low Register
A Output Compare 2 High Register
A Output Compare 2 Low Register
B Control Register 2
B Control Register 1
B Status Register
B Input Capture 1 High Register
B Input Capture 1 Low Register
B Output Compare 1 High Register
B Output Compare 1 Low Register
B Counter High Register
B Counter Low Register
B Alternate Counter High Register
B Alternate Counter Low Register
B Input Capture 2 High Register
B Input Capture 2 Low Register
B Output Compare 2 High Register
B Output Compare 2 Low Register
C0h
xxh
00xx xxxx
xxh
00h
00h
00h
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
13/164
ST72311R, ST72511R, ST72512R, ST72532R
Address
Block
Register
Label
0058h
0059h
CAN
0070h
0071h
ADC
0077h
0078h
0079h
007Ah
to
007Fh
Remarks
Reserved Area (2 Bytes)
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
to
006Fh
0072h
0073h
0074h
0075h
0076h
Reset
Status
Register Name
PWM ART
CANISR
CANICR
CANCSR
CANBRPR
CANBTR
CANPSR
CAN Interrupt Status Register
CAN Interrupt Control Register
CAN Control / Status Register
CAN Baud Rate Prescaler Register
CAN Bit Timing Register
CAN Page Selection Register
First address
to
Last address of CAN page X
00h
00h
00h
00h
23h
00h
R/W
R/W
R/W
R/W
R/W
R/W
See CAN
Description
ADCDR
ADCCSR
Data Register
Control/Status Register
xxh
00h
Read Only
R/W
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
PWM
PWM
PWM
PWM
PWM
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
ARTCSR
ARTCAR
ARTARR
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
00h
00h
00h
R/W
R/W
R/W
AR Timer Duty Cycle Register
AR Timer Duty Cycle Register
AR Timer Duty Cycle Register
AR Timer Duty Cycle Register
AR Timer Control Register
3
2
1
0
Reserved Area (6 Bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
14/164
ST72311R, ST72511R, ST72512R, ST72532R
2 EPROM PROGRAM MEMORY
The program memory of the OTP and EPROM devices can be programmed with EPROM programming tools available from STMicroelectronics
EPROM Erasure
EPROM devices are erased by exposure to high
intensity UV light admitted through the transparent
window. This exposure discharges the floating
gate to its initial state through induced photo current.
It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under these lighting conditions. Covering the window also reduces IDD in
power-saving modes due to photo-diode leakage
currents.
15/164
ST72311R, ST72511R, ST72512R, ST72532R
3 DATA EEPROM
3.1 INTRODUCTION
3.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■
■
■
■
■
■
Up to 16 Bytes programmed in the same cycle
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
Internal control of the global programming cycle
duration
End of programming cycle interrupt flag
WAIT mode management
Figure 4. EEPROM Block Diagram
FALLING
EDGE
DETECTOR
EEPROM INTERRUPT
HIGH VOLTAGE
PUMP
RESERVED
EECSR
0
0
0
0
ADDRESS
DECODER
EEPROM
0
IE
4
LAT PGM
EEPROM
ROW
MEMORY MATRIX
DECODER
(1 ROW = 16 x 8 BITS)
128
4
128
DATA
16 x 8 BITS
MULTIPLEXER
DATA LATCHES
4
ADDRESS BUS
16/164
DATA BUS
ST72311R, ST72511R, ST72512R, ST72532R
DATA EEPROM (Cont’d)
3.3 MEMORY ACCESS
The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 5 describes these different memory
access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to execute machine code.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEPROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.
Note: Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit.
It is not possible to read the latched data.
This note is ilustrated by the Figure 6.
Figure 5. Data EEPROM Programming Flowchart
READ MODE
LAT=0
PGM=0
READ BYTES
IN EEPROM AREA
WRITE MODE
LAT=1
PGM=0
WRITE UP TO 16 BYTES
IN EEPROM AREA
(with the same 12 MSB of the address)
START PROGRAMMING CYCLE
LAT=1
PGM=1 (set by software)
INTERRUPT GENERATION
IF IE=1
0
LAT
1
CLEARED BY HARDWARE
17/164
ST72311R, ST72511R, ST72512R, ST72532R
DATA EEPROM (Cont’d)
3.4 POWER SAVING MODES
3.5 ACCESS ERROR HANDLING
Wait mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a read access occurs while LAT=1, then the data
bus will not be driven.
If a write access occurs while LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guaranteed.
Halt mode
The DATA EEPROM immediatly enters HALT
mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Figure 6. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE OF
DATA LATCHES
WRITE CYCLE
t PROG
LAT
PGM
EEPROM INTERRUPT
18/164
ST72311R, ST72511R, ST72512R, ST72532R
DATA EEPROM (Cont’d)
Bit 1 = LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode
3.6 REGISTER DESCRIPTION
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
IE
LAT
PGM
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 = IE Interrupt enable
This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when the software enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled
Bit 0 = PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware and an interrupt is generated
if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed
Table 3. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
002Ch
Register
Label
7
6
5
4
3
2
1
0
0
0
0
0
0
IE
0
RWM
0
PGM
0
EECSR
Reset Value
19/164
ST72311R, ST72511R, ST72512R, ST72532R
4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION
4.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 7 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
4.2 MAIN FEATURES
■
■
■
■
■
■
■
■
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect
addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power HALT and WAIT modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
Figure 7. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
CONDITIO N CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
20/164
X = Undefined Value
ST72311R, ST72511R, ST72512R, ST72532R
CENTRAL PROCESSING UNIT (Cont’d)
Bit 1 = Z Zero.
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
7
1
0
1
I1
H
I0
N
Z
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: An half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt management bits
Bit 5,3 = I1, I0 Interrupt.
The combination of the Iand I0 bits gives the current interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
I1
1
0
0
1
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
21/164
ST72311R, ST72511R, ST72512R, ST72532R
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15
0
8
0
0
0
0
0
0
7
SP7
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 8. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
CC
A
CC
A
X
X
X
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
22/164
SP
PCH
SP
@ 01FFh
Y
CC
A
SP
SP
ST72311R, ST72511R, ST72512R, ST72532R
5 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72311R, ST72511R, ST72512R and
ST72532R microcontrollers include a range of utility features for securing the application in critical
situations (for example in case of a power brownout), and reducing the number of external components. An overview is shown in Figure 9.
Main features
■ Main supply low voltage detection (LVD)
■ RESET Manager (RSM)
■ Low consumption resonator oscillator
Figure 9. Clock, RESET, Option and Supply Management Overview
OSC2
OSCILLATOR
OSC1
RESET
VDD
RESET
f OSC
TO
MAIN CLOCK
CONTROLLER
FROM
WATCHDOG
PERIPHERAL
LOW VOLTAGE
DETECTOR
VSS
(LVD)
23/164
ST72311R, ST72511R, ST72512R, ST72532R
5.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detector function (LVD) generates a static reset when
the VDD supply voltage is below a VIT- reference
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
– VIT+ when VDD is rising
– VIT- when VDD is falling
The LVD function is illustrated in Figure 10.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is below VIT-, the MCU
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be selected when ordering the device (ordering information).
Figure 10. Low Voltage Detector vs Reset
VDD
Vhys
VIT+
VIT-
RESET
24/164
ST72311R, ST72511R, ST72512R, ST72532R
5.2 RESET SEQUENCE MANAGER (RSM)
5.2.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 12:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 11:
■ Delay depending on the RESET source
■ 4096 CPU clock cycle delay
■ RESET vector fetch
The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. RESET Sequence Phases
RESET
DELAY
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
Figure 12. Reset Block Diagram
VDD
INTERNAL
RESET
RON
COUNTER
f CPU
RESET
WATCHDOG RESET
LVD RESET
25/164
ST72311R, ST72511R, ST72512R, ST72532R
RESET SEQUENCE MANAGER (Cont’d)
5.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 13.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
5.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized as shown in Figure 13. This
detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
5.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 13.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during tw(RSTL)out.
CAUTION: this output signal as not enought energy to be used to drive external devices.
Figure 13. RESET Sequences
VDD
VIT+
VIT-
WATCHDOG
RESET
LVD
RESET
RUN
SHORT EXT.
RESET
RUN
DELAY
RUN
RUN
DELAY
DELAY
tw(RSTL)out
th(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (4096 TCP U)
FETCH VECTOR
26/164
ST72311R, ST72511R, ST72512R, ST72532R
5.3 LOW CONSUMPTION OSCILLATOR
Hardware Configuration
External Clock
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillator
This oscillator (based on constant current source)
is optimized in terms of consumption and has the
advantage of producing a very accurate rate on
the main clock of the ST7.
When using this oscillator, the resonator and the
load capacitances have to be connected as shown
in Table 4 and have to be mounted as close as
possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time.
This oscillator is not stopped during the RESET
phase to avoid losing time in the oscillator start-up
phase.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Table 4. ST7 Clock Sources
Crystal/Ceramic Resonators
The fOSC main clock of the ST7 can be generated
by two different source types:
■ an external source
■ a crystal or ceramic resonator oscillators
The associated hardware configuration are shown
in Table 4. Refer to the electrical characteristics
section for more details.
ST7
OSC1
VDD
OSC2
R OBP
EXTERNAL
SOURCE
ST7
OSC1
C L1
OSC2
LOAD
CAPACITORS
CL2
27/164
ST72311R, ST72511R, ST72512R, ST72532R
6 INTERRUPTS
6.1 INTRODUCTION
The ST7 enhanced interrupt management provides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: TLI, RESET, TRAP
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nested) ST7 interrupt controller.
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 5. Interrupt Software Priority Levels
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
6.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The processing flow is shown in Figure 14
Level
Low
I1
1
0
0
1
High
I0
0
1
0
1
Figure 14. Interrupt Processing Flowchart
PENDIN G
INTERRUPT
FETCH NEXT
INSTRUC TION
“IRET”
N
RESTORE PC, X, A, CC
FROM STAC K
TLI
EXECUTE
INSTRUCTI ON
THE INTE RRUPT
STAYS PENDING
Y
N
Interrupt has the same or a
lower software priority
than current one
N
Y
Y
I1:0
Interrupt has a higher
software priority
than current one
RESET
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
28/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is determined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software priority then the interrupt with the highest hardware
priority is serviced first.
Figure 15 describes this decision process.
Figure 15. Priority Decision Process
PENDING
INTE RRUPTS
Same
SOFTWARE
PRIORITY
Different
HIGHEST SOFTWAR E
PRIORITY SERVIC ED
HIGHES T HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its
software priority combined with the hardware priority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI are non maskable
and they can be considered as having the highest
software priority in the decision process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (external or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 14). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
■ TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. Its detailed specification is given in the Miscellaneous
register chapter.
■ TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced according to the flowchart on Figure 14 as a TLI.
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the Miscellaneous registers (MISCRx).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear sequence is executed.
29/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
6.3 INTERRUPTS AND LOW POWER MODES
6.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit the HALT modes (see column “Exit from
HALT” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting HALT
mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is
selected through the same decision process
shown in Figure 15
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
The following Figure 16 and Figure 17 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in
Figure 17 The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without notifying the software of the failure.
IT0
TLI
IT3
IT4
IT1
SOFTWARE
PRIORITY
LEVEL
TLI
IT0
IT1
IT1
IT2
IT3
RIM
IT4
MAIN
MAIN
11 / 10
I1
I0
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
3
1 1
USED STACK = 10 BYTES
HARDWARE PRIORITY
IT2
Figure 16. Concurrent interrupt management
3/0
10
IT0
TLI
IT3
IT4
IT1
TLI
IT0
IT1
IT1
IT2
IT2
IT3
RIM
IT4
MAIN
11 / 10
30/164
SOFTWARE
PRIORITY
LEVEL
IT4
MAIN
10
I1
I0
3
1 1
3
1 1
2
0 0
1
0 1
3
1 1
3
1 1
3/0
USED STACK = 20 BYTES
HARDWARE PRIORITY
IT2
Figure 17. Nested interrupt management
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
6.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Values: 1111 1111 (FFh)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Reset Value: 111x 1010 (xAh)
7
1
7
0
1
I1
H
I0
N
Z
Level
Low
High
I1
1
0
0
1
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
I1_7
I0_7
I1_6
I0_6
I1_5
I0_5
I1_4
I0_4
ISPR2
I1_11 I0_11 I1_10 I0_10 I1_9
I0_9
I1_8
I0_8
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt software priority.
Interrupt Software Priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable*)
0
I0
0
1
0
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TLI, TRAP and RESET events are non
maskable sources and can interrupt a level 3 program.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
These four registers contain the interrupt software
priority of each interrupt vector.
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This correspondance is shown in the following table.
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FF F8h
...
FFE1h-FFE0h
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
I1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they
are not significant in the interrupt process management.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the interrupt x).
31/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
Table 6. Dedicated Interrupt Instruction Set
Instruction
New Description
Function/Example
I1
H
I0
I1
H
H
1
N
Z
C
I0
N
Z
C
I0
N
Z
C
HALT
Entering Halt mode
IRET
Interrupt routine return
Pop CC, A, X, PC
0
JRM
Jump if I1:0=11
I1:0=11 ?
JRNM
Jump if I1:0<>11
I1:0<>11 ?
POP CC
Pop CC from the Stack
Mem => CC
I1
RIM
Enable interrupt (level 0 set)
Load 10 in I1:0 of CC
1
0
SIM
Disable interrupt (level 3 set)
Load 11 in I1:0 of CC
1
1
TRAP
Software trap
Software NMI
1
1
WFI
Wait for interrupt
1
0
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never
be used in an interrupt routine.
Table 7. Interrupt Mapping
N°
Source
Block
RESET
TRAP
Description
Reset
Software Interrupt
Register
Label
Priority
Order
N/A
Highest
Priority
0
TLI
1
MCC/RTC
2
ei0
External Interrupt Port A3..0
3
ei1
External Interrupt Port F2..0
4
ei2
External Interrupt Port B3..0
5
ei3
External Interrupt Port B7..4
6
CAN
CAN Peripheral Interrupts
CANISR
SPI Peripheral Interrupts
SPISR
TIMER A Peripheral Interrupts
TASR
7
SPI
8
TIMER A
9
TIMER B
10
SCI
11
EEPROM
12
13
32/164
External Top Level Interrupt
MISCR2
Main Clock Controller Time Base Interrupt
MCCSR
Address
Vector
yes
FFFEh-FFFFh
no
FFFCh-FFFDh
yes
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
N/A
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFE Fh
no
FFECh-FFEDh
FFEAh-FFEBh
TIMER B Peripheral Interrupts
TBSR
FFE8h-FFE9h
SCI Peripheral Interrupts
SCISR
FFE6h-FFE7h
EEPROM Interrupt
EECSR
FFE4h-FFE5h
Not Used
PWM ART
Exit
from
HALT
PWM ART Overflow Interrupt
ARTCSR
Lowest
Priority
FFE2h-FFE3h
Yes
FFE0h-FFE1h
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
Table 8. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
ei1
0024h
ISPR0
Reset Value
I1_3
1
ei0
I0_3
1
I1_2
1
SPI
0025h
ISPR1
Reset Value
I1_7
1
ISPR2
Reset Value
I1_11
1
3
2
I0_7
1
I0_2
1
I1_6
1
I1_10
1
I1_1
1
I0_1
1
ISPR3
Reset Value
1
1
1
TLI
1
1
I0_6
1
I1_5
1
ei2
I0_5
1
TIMER B
I0_10
1
I1_9
1
I0_9
1
PWMART
0027h
0
ei3
SCI
I0_11
1
1
MCC/RTC
CAN
EEPROM
0026h
4
1
I1_13
1
I0_13
1
I1_4
1
I0_4
1
TIMER A
I1_8
1
I0_8
1
Not Used
I1_12
1
I0_12
1
33/164
ST72311R, ST72511R, ST72512R, ST72532R
7 POWER SAVING MODES
7.1 INTRODUCTION
7.2 SLOW MODE
To give a large measure of flexibility to the application in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 18): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT.
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (fCPU).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscillator status.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU) to
the available supply voltage.
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (fCPU).
In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enterring the WAIT mode while the device is already in
SLOW mode.
Figure 18. Power Saving Mode Transitions
High
Figure 19. SLOW Mode Clock Transitions
fOSC/4
RUN
fOSC/8
fOSC/2
fCPU
SLOW
MISCR1
fOSC/2
WAIT
CP1:0
00
01
SMS
SLOW WAIT
NEW SLOW
FREQU ENCY
REQUEST
ACTIVE HALT
HALT
Low
POWER CONSUMPTION
34/164
NORMAL RUN MODE
REQUEST
ST72311R, ST72511R, ST72512R, ST72532R
POWER SAVING MODES (Cont’d)
7.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 20.
Figure 20. WAIT Mode Flow-chart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
10
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
35/164
ST72311R, ST72511R, ST72512R, ST72532R
POWER SAVING MODES (Cont’d)
7.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
MCCSR
OIE bit
Power Saving Mode entered when HALT
instruction is executed
0
HALT mode
1
ACTIVE-HALT mode
7.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see Section
10.2 on page 52 for more details on the MCCSR
register).
The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 7, “Interrupt Mapping,” on
page 32) or a RESET. When exiting ACTIVEHALT mode by means of a RESET or an interrupt,
a 4096 CPU cycle delay occurs. After the start up
delay, the CPU resumes operation by servicing
the interrupt or by fetching the reset vector which
woke it up (see Figure 22).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10’ to enable interrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
36/164
Figure 21. ACTIVE-HALT Timing Overview
RUN
ACTIVE
HALT
HALT
INSTRUCTION
[MCCSR.OIE=1]
4096 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
Figure 22. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=1)
OSCILLATOR
ON
PERIPHERALS 1) OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
Y
N
INTERRUPT 2)
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX 3)
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 3)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. Peripheral clocked with an external clock source
can still be active.
2. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 7, “Interrupt Mapping,” on page 32 for more
details.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
ST72311R, ST72511R, ST72512R, ST72532R
POWER SAVING MODES (Cont’d)
7.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 10.2 on page 52 for more details on the MCCSR register).
The MCU can exit HALT mode on reception of either a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 32) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 24).
When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see
Section 14.1 on page 158 for more details).
Figure 23. HALT Timing Overview
RUN
HALT
HALT
INSTRUCTION
[MCCSR.OIE=0]
4096 CPU CYCLE
DELAY
RUN
RESET
OR
INTERRUPT
FETCH
VECTOR
Figure 24. HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WDGHALT 1)
WATCHDOG
0
DISABLE
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2) OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
XX 4)
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Refer to Table 7, “Interrupt Mapping,” on page 32 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
37/164
ST72311R, ST72511R, ST72512R, ST72532R
8 I/O PORTS
8.1 INTRODUCTION
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
8.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is
shown in Figure 25
8.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external interrupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
38/164
programmable using the sensitivity bits in the Miscellaneous register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description
and interrupt section). If several input pins are selected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
In case of a floating input with interrupt configuration, special care must be taken when changing
the configuration (see Figure 26).
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellaneous register must be modified.
8.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
DR
0
1
Push-pu ll
VSS
V DD
Open-drain
Vss
Floating
8.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over the
standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
Figure 25. I/O Port General Block Diagram
ALTERNATE
OUTPUT
REGISTER
ACCESS
1
P-BUFFER
(see table below)
VDD
0
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
VDD
DDR
PULL-UP
CONDITION
DATA BUS
OR
PAD
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
EXTERNAL
INTERRUPT
SOURCE (eix)
POLARITY
SELECTION
ALTERNATE
INPUT
FROM
OTHER
BITS
Table 9. I/O Port Mode Options
Configuration Mode
Input
Output
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Pull-Up
P-Buffer
Off
On
Off
Off
NI
On
Off
NI
Diodes
to VDD
On
to VSS
On
NI (see note)
Note: The diode to VDD is not implemented in the
true open drain pads. A local protection between
the pad and VSS is implemented to protect the device against positive stress.
39/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
Table 10. I/O Port Configurations
Hardware Configu ration
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
PULL-UP
CONDITIO N
DR
REGISTER
PAD
W
DATA BUS
INPUT 1)
R
ALTERNATE INPUT
FROM
OTHER
PINS
INTERRUPT
CONDITION
EXTERNAL INTERRU PT
SOURCE (eix)
POLARITY
SELECTION
PUSH-PULL OUTPUT 2)
OPEN-DRAIN OUTPUT 2)
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGIST ER ACCESS
VDD
RPU
DR
REGIST ER
PAD
ALTERNATE
ENABLE
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DATA BUS
ALTERNATE
OUTPUT
DR REGIST ER ACCESS
VDD
RPU
PAD
R/W
DR
REGIST ER
ALTERNATE
ENABLE
R/W
DATA BUS
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
40/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be activated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maximum ratings.
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3
MODE
floating input
pull-up input
open drain output
push-pull output
DDR
OR
0
0
1
1
0
1
0
1
Interrupt Ports
PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
MODE
floating input
pull-up interrupt input
open drain output
push-pull output
DDR
OR
0
0
1
1
0
1
0
1
PA3, PB4, PB3, PF2 (without pull-up)
8.3 I/O PORT IMPLEMENTATION
MODE
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 26 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 26. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
floating input
floating interrupt input
open drain output
push-pull output
DDR
OR
0
0
1
1
0
1
0
1
True Open Drain Ports
PA7:6
MODE
floating input
open drain (high sink ports)
DDR
0
1
Pull-up Input Port (CANTX requirement)
PE2
MODE
XX
= DDR, OR
pull-up input
The I/O port register configurations are summarized as follows.
41/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
8.4 LOW POWER MODES
Mode
WAIT
HALT
8.5 INTERRUPTS
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Interrupt Event
External interrupt on
selected external
event
Enable
Event
Control
Flag
Bit
-
DDRx
ORx
Exit
from
Wait
Exit
from
Halt
Yes
Yes
Table 11. Port Configuration
Input
Port
OR = 0
Port A
Port B
Port C
Port D
Port E
Port F
Outpu t
Pin name
PA7:6
PA5:4
PA3
PA2:0
PB4, PB3
PB7:5, PB2:0
PC7:0
PD7:0
PE7:3, PE1:0
PE2
PF7:3
PF2
PF1:0
OR = 1
OR = 0
floating
true open-drain
drain
push-pull
drain
push-pull
drain
push-pull
drain
push-pull
floating
floating
floating
floating
pull-up
floating interrupt
pull-up interrupt
floating interrupt
floating
floating
floating
floating
pull-up interrupt
open drain
pull-up
open drain
pull-up
open drain
pull-up
open drain
pull-up input only *
pull-up
open drain
floating interrupt
open drain
pull-up interrupt
open drain
floating
floating
floating
open
open
open
open
OR = 1
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
* Note: when the CANTX alternate function is selected the IO port operates in output push-pull mode.
42/164
High-Sink
Yes
No
PC3:2 only
No
PE7:4 only
No
PF7:6 only
No
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
8.5.1 Register Description
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
7
D7
D6
D5
D4
D3
D2
D1
0
7
D0
O7
Bit 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
7
DD7
0
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: pull-up input with or without interrupt
Output mode:
0: output open drain (with P-Buffer unactivated)
1: output push-pull
0
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
43/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
Reset Value
of all IO port registers
0000h
PADR
0001h
PADDR
0002h
PAOR
0004h
PCDR
0005h
PCDDR
0006h
PCOR
0008h
PBDR
0009h
PBDDR
000Ah
PBOR
000Ch
PEDR
000Dh
PEDDR
000Eh
PEOR
0010h
PDDR
0011h
PDDDR
0012h
PDOR
0014h
PFDR
0015h
PFDDR
0016h
PFOR
44/164
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
ST72311R, ST72511R, ST72512R, ST72532R
9 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several features such as the external interrupts or
the I/Oalternate functions.
9.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the Miscellaneous
registers (Figure 27). This control allows to have
up to 4 fully independent external interrupt source
sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the MISCR registers must be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). See I/O port register and Miscellaneous register descriptions for more details on
the programming.
9.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers allow to manage four I/O port
miscellaneous alternate functions:
■ Main clock signal (fOSC/2) output on PF0
■ A Beep signal output on PF1 (with three
selectable audio frequencies)
■ A TLI management on a dedicated pin
■ A SPI SS pin internal control to use the PC7 I/O
port function while the SPI is active.
These functions are described in details in the
Section 9.3 ”MISCELLANEOUS REGISTERS” on
page 46.
Figure 27. External Interrupt Sources vs MISCR
ei0
INTER RUPT
SOURCE
PA3
SOURCES
PA2
PA1
MISCR1
IS20
IS21
PA0
SENSI TIVITY
MISCR2.IPA
PF2
SOURCES
PF1
ei1
INTERRUPT
SOURCE
CONTROL
PF0
ei2
INTERRUPT
SOURCE
PB3
SOURCES
PB2
PB1
PB0
MISCR1
IS10
IS11
SENSI TIVITY
MISCR2.IPB
PB7
SOURCES
PB6
ei3
INTERRUPT
SOURCE
CONTROL
PB5
PB4
45/164
ST72311R, ST72511R, ST72512R, ST72532R
MISCELLANEOUS REGISTERS (Cont’d)
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
- ei0 (port A3..0)
9.3 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Reset Value: 0000 0000 (00h)
External Interrupt Sensitivity
7
IS11
0
IS10 MCO IS21
IS20
CP1
CP0
SMS
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
External Interrupt Sensitivity
IS11 IS10
MISCR2.IPB=0
MISCR2.IPB=1
Rising edge
& high level
0
0
Falling edge &
low level
0
1
Rising edge only
Falling edge only
1
0
Falling edge only
Rising edge only
1
1
Rising and falling edge
- ei3 (port B7..4)
IS11 IS10
External Interrupt Sensitivity
IS21 IS20
MISCR2.IPA=0
MISCR2.IPA=1
0
0
Falling edge &
low level
Rising edge
& high level
0
1
Rising edge only
Falling edge only
1
0
Falling edge only
Rising edge only
1
1
Rising and falling edge
- ei1 (port F2..0)
IS21 IS20
External Interrupt Sensitivity
0
0
0
1
Falling edge & low level
Rising edge only
1
0
Falling edge only
1
1
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
0
0
Falling edge & low level
0
1
Rising edge only
1
0
Falling edge only
fCPU in SLOW mode
CP1
CP0
1
1
Rising and falling edge
fOSC / 4
0
0
fOSC / 8
1
0
fOSC / 16
0
1
fOSC / 32
1
1
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (fOSC/2on I/O
port)
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
46/164
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC / 2
1: Slow mode. fCPU is given by CP1, CP0
See Section 7.2 ”SLOW MODE” on page 34 and
Section 10.2 ”MAIN CLOCK CONTROLLER
WITH REAL TIME CLOCK TIMER (MCC/RTC)”
on page 52 for more details.
ST72311R, ST72511R, ST72512R, ST72532R
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
IPA
IPB
BC1
BC0
TLIS
TLIE
SSM
SSI
Bit 7 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSITIVITY” on page 45 and the description of the IS2x
bits of the MISCR1 register for more details.
Bit 6 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSITIVITY” on page 45 and the description of the IS1x
bits of the MISCR1 register for more details.
Bit 3 = TLIS TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
Bit 2 = TLIE TLI enable
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
Bit 1 = SSM SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode (PC7), the level of the SPI SS signal is
read from the SSI bit.
Bit 0 = SSI SS internal mode
This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.
Bit 5:4 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with fOSC=16MHz
0
0
Off
0
1
~2-KHz
1
0
~1-KHz
1
1
~500-Hz
Output
Beep signal
~50% duty cycle
The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the
consumption.
47/164
ST72311R, ST72511R, ST72512R, ST72532R
MISCELLANEOUS REGISTERS (Cont’d)
Table 13. Miscellaneous Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0020h
MISCR1
Reset Value
IS11
0
IS10
0
MCO
0
IS21
0
IS20
0
CP1
0
CP0
0
SMS
0
0040h
MISCR2
Reset Value
IPA
0
IPB
0
BC1
0
BC0
0
TLIS
0
TLIE
0
SSM
0
SSI
0
(Hex.)
48/164
ST72311R, ST72511R, ST72512R, ST72532R
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
10.1.2 Main Features
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
■
■
Hardware Watchdog selectable by option byte
Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)
10.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
Figure 28. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
WDGA
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷12288
49/164
ST72311R, ST72511R, ST72512R, ST72532R
WATCHDOG TIMER (Cont’d)
The application program must write in the CR register at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 14 .Watchdog Timing (fCPU = 8 MHz)):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Table 14.Watchdog Timing (fCPU = 8 MHz)
CR Register
initial value
WDG timeout period
(ms)
Max
FFh
98.304
Min
C0h
1.536
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
10.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Refer to the device-specific Option Byte description.
10.1.5 Low Power Modes
Mode
WAIT
Description
No effect on Watchdog.
HALT
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
10.1.6 Interrupts
None.
50/164
10.1.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
STATUS REGISTER (SR)
Read/Write
Reset Value*: 0000 0000 (00h)
7
-
0
-
-
-
-
-
-
WDOGF
Bit 0 = WDOGF Watchdog flag.
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred
* Only by software and power on/off reset
Note: This register is not used in versions without
LVD Reset.
ST72311R, ST72511R, ST72512R, ST72532R
WATCHDOG TIMER (Cond’t)
Table 15. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
002Ah
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Bh
WDGSR
Reset Value
0
0
0
0
0
0
0
WDOGF
0
51/164
ST72311R, ST72511R, ST72512R, ST72532R
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)
The Main Clock Controller consists of three different functions:
■ a programmable CPU clock prescaler
■ a clock-out signal to supply external devices
■ a real time clock timer with interrupt capability
Each function can be used independently and simultaneously.
10.2.1 Programmable CPU Clock Prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See
Section 7.2 ”SLOW MODE” on page 34 for more
details).
The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MISCR1
register: CP[1:0] and SMS.
CAUTION: The prescaler does not act on the CAN
peripheral clock source. This peripheral is always
supplied by the fOSC/2 clock source.
10.2.2 Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a fOSC/2 clock to drive
external devices. It is controlled by the MCO bit in
the MISCR1 register.
CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.
10.2.3 Real Time Clock Timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depending directly on fOSC are available. The whole functionality is controlled by four bits of the MCCSR
register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 7.4
”ACTIVE-HALT AND HALT MODES” on page 36
for more details.
Figure 29. Main Clock Controller (MCC/RTC) Block Diagram
CLOCK TO CAN
PERIPHERAL
PORT
ALTERNATE
FUNCTION
MCO
f OSC/2
MISCR1
-
fOSC
-
MCO
MCCSR
0
0
MCC/RTC INTERRUPT
52/164
-
CP1 CP0 SMS
DIV2, 4, 8, 16
DIV 2
RTC
COUNTER
0
-
0
TB1 TB0 OIE OIF
fCPU
CPU CLOCK
TO CPU AND
PERIPHERALS
ST72311R, ST72511R, ST72512R, ST72532R
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)
10.2.4 Register Description
MISCELLANEOUS REGISTER 1 (MISCR1)
See “MISCELLANEOUS REGISTERS” Section.
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read/Write
Reset Value: 0000 0001 (01h)
7
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
0
10.2.5 Low Power Modes
0
0
0
0
TB1
TB0
OIE
OIF
Mode
Bit 7:4 = Reserved, always read as 0.
WAIT
Bit 3:2 = TB[1:0] Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
ACTIVEHALT
Counter
Prescaler
Time Base
TB1
TB0
fOSC =8MHz
fOSC=16MHz
32000
4ms
2ms
0
0
64000
8ms
4ms
0
1
160000
20ms
10ms
1
0
400000
50ms
25ms
1
1
HALT
Description
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
10.2.6 Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
A modification of the time base is taken into account at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVEHALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode.
Interrupt Event
Time base overflow
event
Enable
Event
Control
Flag
Bit
OIF
OIE
Exit
from
Wait
Exit
from
Halt
Yes
No 1)
Note:
1. The MCC/RTC interrupt allows to exit from ACTIVE-HALT mode, not from HALT mode.
Table 16. MCC/RTC Register Map and Reset Values
Address
(Hex.)
0029h
Register
Label
MCCSR
Reset Value
7
6
5
4
3
2
1
0
0
0
0
0
TB1
0
TB0
0
OIE
0
OIF
1
53/164
ST72311R, ST72511R, ST72512R, ST72532R
10.3 PWM AUTO-RELOAD TIMER (ART)
10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare capabilities and of a 7-bit
prescaler clock source.
These resources allow three possible operating
modes:
– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
– External event detector
The two first modes can be used together with a
single counter frequency.
The timer can be used to wake up the MCU from
WAIT and HALT modes.
Figure 30. PWM Auto-Reload Timer Block Diagram
OEx
PWMCR
OCRx
DCRx
REGIST ER
REGISTER
OPx
LOAD
PWMx
ARTCLK
PORT
ALTERNATE
FUNCT ION
POLARITY
CONTROL
COMPARE
ARR
8-BIT COUNTER
REGISTER
(CAR REGISTE R)
LOAD
fEXT
fCPU
fCOUNTER
MUX
fINPUT
EXCL
PROGRAMMABLE
PRESCALER
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR
OVF INTERRUPT
54/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every rising edge of the clock signal.
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (CAR).
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARR register (the prescaler is not affected).
Counter clock and prescaler
The counter clock frequency is given by:
fCOUNTER = fINPUT / 2CC[2:0]
The timer counter’s input clock (f INPUT) feeds the
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(CSR). Thus the division factor of the prescaler
can be set to 2n (where n = 0, 1,..7).
This fINPUT frequency source is selected through
the EXCL bit of the CSR register and can be either
the fCPU or an external input frequency fEXT.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the CSR register. When TCE is reset, the counter is stopped and
the prescaler and counter contents are frozen.
When TCE is set, the counter runs at the rate of
the selected clock source.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
cleared and fINPUT = fCPU.
The counter can be initialized by:
– Writing to the ARR register and then setting the
FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the CSR register.
– Writing to the CAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Direct access to the prescaler is not possible.
Output compare control
The timer compare function is based on four different comparisons with the counter (one for each
PWMx output). Each comparison is made between the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cycle register (DCRx) at each overflow of the counter.
This double buffering method avoids glitch generation when changing the duty cycle on the fly.
Figure 31. Output compare control
f COUNTER
ARR=FDh
COUNTER
FDh
FEh
FFh
OCRx
DCRx
FDh
FEh
FFh
FDh
FFh
FEh
FDh
FDh
FEh
FEh
PWMx
55/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as output push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARR register value.
fPWM = fCOUNTER / (256 - ARR)
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARR register.
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (256 - ARR)
Note: To get the maximum resolution (1/256), the
ARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing
the polarity.
Figure 32. PWM Auto-reload Timer Function
COUNTER
255
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ARR)
PWMx OUTPUT
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 33. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER
ARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
FEh
PWMx OUTPUT
WITH OEx=1
AND OPx=0
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
56/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the CSR register is
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OIE, in the CSR
register, is set. The OVF flag must be reset by the
user software. This interrupt can be used as a time
base in the application.
External clock and event detector mode
Using the fEXT external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARR register is
used to select the nEVENT number of events to be
counted before setting the OVF flag.
nEVENT = 256 - ARR
When entering HALT mode while fEXT is selected,
all the timer control registers are frozen but the
counter continues to increment. If the OIE bit is
set, the next overflow of the counter will generate
an interrupt which wakes up the MCU.
Figure 34. External Event Detector Example (3 counts)
fEXT =fCOUNTER
ARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
CSR READ
CSR READ
INTERRUPT
IF OIE=1
INTERRUPT
IF OIE=1
t
57/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.3 Register Description
COUNTER ACCESS REGISTER (CAR)
Read/Write
Reset Value: 0000 0000 (00h)
CONTROL / STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
EXCL
CC2
CC1
CC0
TCE
FCRL
OIE
0
7
OVF
CA7
Bit 7 = EXCL External Clock
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
1: External clock.
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from fINPUT.
fCOUNTER
fINPUT
fINPUT / 2
fINPUT / 4
fINPUT / 8
fINPUT / 16
fINPUT / 32
fINPUT / 64
fINPUT / 128
With fINPUT=8 MHz CC2 CC1 CC0
8 MHz
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 3 = TCE Timer Counter Enable
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
Bit 2 = FCRL Force Counter Re-Load
This bit is write-only and any attempt to read it will
yield a logical zero. When set, it causes the contents
of ARR register to be loaded into the counter, and
the content of the prescaler register to be cleared in
order to initialize the timer before starting to count.
Bit 1 = OIE Overflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.
Bit 0 = OVF Overflow Flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates the transition
of the counter from FFh to the ARR value.
0: New transition not yet reached
1: Transition reached
58/164
0
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Bit 7:0 = CA[7:0] Counter Access Data
These bits can be set and cleared either by hardware or by software. The CAR register is used to
read or write the auto-reload counter “on the fly”
(while it is counting).
AUTO-RELOAD REGISTER (ARR)
Read/Write
Reset Value: 0000 0000 (00h)
7
AR7
0
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Bit 7:0 = AR[7:0] Counter Auto-Reload Data
These bits are set and cleared by software. They
are used to hold the auto-reload value which is automatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
This register has two PWM management functions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
PWM Frequency vs. Resolution:
ARR value
0
[ 0..127 ]
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
f PWM
Resolution
8-bit
> 7-bit
> 6-bit
> 5-bit
> 4-bit
Min
Max
~0.244-KHz
~0.244-KHz
~0.488-KHz
~0.977-KHz
~1.953-KHz
31.25-KHz
62.5-KHz
125-KHz
250-KHz
500-KHz
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
DUTY CYCLE REGISTERS (DCRx)
Read/Write
Reset Value: 0000 0000 (00h)
PWM CONTROL REGISTER (PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
7
OE3
OE2
OE1
OE0
OP3
OP2
OP1
0
7
OP0
DC7
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels independently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
0
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A DCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARR register). These DCR registers allow
the duty cycle to be set independently for each
PWM channel.
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
59/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
Table 17. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
60/164
Register
Label
PWMDCR3
Reset Value
PWMDCR2
Reset Value
PWMDCR1
Reset Value
PWMDCR0
Reset Value
PWMCR
Reset Value
ARTCSR
Reset Value
ARTCAR
Reset Value
ARTARR
Reset Value
7
6
5
4
3
2
1
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
OIE
0
OVF
0
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
ST72311R, ST72511R, ST72512R, ST72532R
10.4 16-BIT TIMER
10.4.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
10.4.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
10.4.3 Functional Description
10.4.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most significant byte (MS Byte).
– Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 18 Clock
Control Bits. The value in the counter register repeats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU /4, fCPU/8
or an external frequency.
The Block Diagram is shown in Figure 35.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
61/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 35. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 low
8
8
8
low
low
8
high
8
8
high
EXEDG
8
low
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
REGISTER
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2
0
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note)
TIMER INTERRUPT
62/164
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +∆t LS Byte
Returns the buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
10.4.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
63/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 36. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000
COUNTER REGISTER
0001
0002
0003
TIMER OVERFLOW FLAG (TOF)
Figure 37. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
TIMER OVERFLOW FLAG (TOF)
Figure 38. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
64/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition detected by the
ICAP i pin (see figure 5).
ICiR
MS Byte
ICiHR
LS Byte
ICiLR
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 18
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 40).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input capture function.
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
65/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 39. Input Capture Block Diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R Register
ICF1
IC1R Register
ICF2
0
16-BIT FREE RUNNING
CC1
CC0
COUNTER
Figure 40. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.
66/164
0
(Control Register 2) CR2
16-BIT
COUNTER REGISTER
0
FF03
IEDG2
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
OCiR
MS Byte
OCiHR
LS Byte
OCiLR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0] ).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the timer clock (CC[1:0]) (see Table 18
Clock Control Bits).
And select the following in the CR1 register:
– Select the OLVL i bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
fCPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 18
Clock Control Bits)
If the timer clock is an external clock, the formula
is:
∆ OCiR = ∆t * fEXT
Where:
∆t
= Output compare period (in seconds)
fEXT
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
67/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCi HR register, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 42 on page
68). This behaviour is the same in OPM or
PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR register value plus 1 (see Figure 43 on page 68).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
Figure 41. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
16-bit
Latch
2
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
68/164
Latch
1
OCMP1
Pin
OCMP2
Pin
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 42. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCR i)
2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 43. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCR i)
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
2ED3
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
69/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 18
Clock Control Bits).
One pulse mode cycle
When
event occurs
on ICAP1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
70/164
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 18
Clock Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t * f EXT -5
Where:
t
= Pulse period (in seconds)
fEXT
= External timer clock frequency (in hertz)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 44).
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 44. One Pulse Mode Timing Example
COUNTER
FFFC FFFD FFFE
2ED0
2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OLVL2
OCMP1
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 45. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
34E2
FFFC
OLVL2
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
71/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The pulse width modulation mode uses the complete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 18
Clock Control Bits).
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
72/164
The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 18 Clock
Control Bits)
If the timer clock is an external clock the formula is:
OCiR = t * f EXT -5
Where:
t
= Signal or pulse period (in seconds)
fEXT
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 45)
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.4.5 Interrupts
Event
Flag
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2
OCF1
OCF2
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
10.4.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
1)
2)
3)
Input Capture 1
Yes
Yes
No
No
AVAILABLE RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
Yes
Yes
Yes
Yes
Yes
Yes
Not Recommended 1)
Not Recommended 3)
No
No
Partially 2)
No
See note 4 in Section 10.4.3.5 ”One Pulse Mode” on page 69
See note 5 in Section 10.4.3.5 ”One Pulse Mode” on page 69
See note 4 in Section 10.4.3.6 ”Pulse Width Modulation Mode” on page 71
73/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
74/164
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 18. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
Note: If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
75/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
ICF1
0
OCF1
TOF
ICF2
OCF2
0
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) register.
Bit 2-0 = Reserved, forced by hardware to 0.
76/164
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
7
0
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the input capture 1 event).
7
0
MSB
LSB
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
MSB
LSB
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
7
0
MSB
LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the Input Capture 2 event).
7
0
MSB
LSB
77/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Table 19. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
Timer A: 32 CR1
Timer B: 42 Reset Value
Timer A: 31 CR2
Timer B: 41 Reset Value
Timer A: 33 SR
Timer B: 43 Reset Value
Timer A: 34 ICHR1
Timer B: 44 Reset Value
Timer A: 35 ICLR1
Timer B: 45 Reset Value
Timer A: 36 OCHR1
Timer B: 46 Reset Value
Timer A: 37 OCLR1
Timer B: 47 Reset Value
Timer A: 3E OCHR2
Timer B: 4E Reset Value
Timer A: 3F OCLR2
Timer B: 4F Reset Value
Timer A: 38 CHR
Timer B: 48 Reset Value
Timer A: 39 CLR
Timer B: 49 Reset Value
Timer A: 3A ACHR
Timer B: 4A Reset Value
Timer A: 3B ACLR
Timer B: 4B Reset Value
Timer A: 3C ICHR2
Timer B: 4C Reset Value
Timer A: 3D ICLR2
Timer B: 4D Reset Value
78/164
7
6
5
4
3
2
1
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
0
0
0
0
0
0
0
0
OC1E
OC2E
OPM
PWM
CC1
CC0
IEDG2
EXEDG
0
0
0
0
0
0
0
0
ICF1
OCF1
TOF
ICF2
OCF2
-
-
-
0
0
0
0
0
0
0
0
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
1
1
1
1
1
1
1
LSB
1
MSB
1
1
1
1
1
1
0
LSB
0
MSB
1
1
1
1
1
1
1
LSB
1
MSB
1
1
1
1
1
1
0
LSB
0
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
ST72311R, ST72511R, ST72512R, ST72532R
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.3 General description
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
10.5.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is normally used for communication between the microcontroller and external peripherals
or another microcontroller.
Refer to the Pin Description chapter for the devicespecific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 46.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master device via the SCK pin).
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is complete.
Four possible data/clock timing relationships may
be chosen (see Figure 49) but master and slave
must be programmed with the same timing mode.
10.5.2 Main Features
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/2.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
Figure 46. Serial Peripheral Interface Master/Slave
SLAVE
MASTER
MSBit
LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
MSBit
MISO
MISO
MOSI
MOSI
SCK
SS
LSBit
8-BIT SHIFT REGISTER
SCK
+5V
SS
79/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 47. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
MISO
SR
8-Bit Shift Register
SPIF WCOL - MODF
-
-
-
-
Write
SPI
STATE
CONTROL
SCK
SS
CR
SPIE
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
80/164
SPE
SPR2 MSTR CPOL CPHA SPR1 SPR0
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4 Functional Description
Figure 46 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
10.5.7for the bit definitions.
10.5.4.1 Master Configuration
In a master configuration, the serial clock is generated on the SCK pin.
Procedure
– Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register).
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 49).
– The SS pin must be connected to a high level
signal during the complete byte transmit sequence.
– The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a
high level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is written the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
2. A write or a read of the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
81/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.2 Slave Configuration
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure
49.
– The SS pin must be connected to a low level
signal during the complete byte transmit sequence.
– Clear the MSTR bit and set the SPE bit to assign the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
82/164
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
2. A write or a read of the DR register.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 10.5.4.6).
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
10.5.4.4).
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not selected do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Figure 49, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 48).
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the occurrence of the first clock transition.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 48).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 48. CPHA / SS Timing Diagram
MOSI/MISO
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
83/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 49. Data Clock Timing Diagram
CPHA =1
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
MSBit
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
84/164
VR02131B
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.4 Write Collision Error
A write collision occurs when the software tries to
write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the external MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write collision.
In Master mode
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 50).
Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SR
OR
Read SR
THEN
THEN
2nd Step
Read DR
SPIF =0
WCOL=0
Write DR
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SR
THEN
2nd Step
Read DR
WCOL=0
Note: Writing in DR register instead of reading in it do not reset
WCOL bit
85/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
86/164
may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a reset or default system state using an interrupt routine.
10.5.4.6 Overrun Condition
An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripheral.
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
For more security, the slave device may respond
to the master with the received data byte. Then the
– Single Master System
master will receive the previous byte back from the
– Multimaster System
slave device if all MISO and MOSI pins are connected and the slave has not written its DR register.
Single Master System
Other transmission security methods can use
A typical single master system may be configured,
ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as
mand fields.
slaves (see Figure 51).
Multi-master System
The master device selects the individual slave deA multi-master system may also be configured by
vices by using four pins of a parallel port to control
the user. Transfer of master control could be imthe four SS pins of the slave devices.
plemented using a handshake method through the
The SS pins are pulled high during reset since the
I/O ports or by an exchange of code messages
master device ports will be forced to be inputs at
through the serial peripheral interface system.
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
Note: To prevent a bus conflict on the MISO line
in the SR register.
the master allows only one active slave device
during a transmission.
Figure 51. Single Master Configuration
SS
SCK
SS
SS
SCK
Slave
MCU
Slave
MCU
MOSI MISO
MOSI MISO
SS
SCK
Slave
MCU
SCK
Slave
MCU
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
Ports
MOSI MISO
SS
87/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
10.5.6 Interrupts
Interrupt Event
SPI End of Transfer Event
Master Mode Fault Event
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
88/164
Event
Flag
Enable
Control
Bit
SPIF
MODF
SPIE
Exit
from
Wait
Yes
Yes
Exit
from
Halt
No
No
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000xxxx (0xh)
7
SPIE
0
SPE SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.4.5 ”Master Mode Fault” on
page 85).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins.
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
These 2 bits have no effect in slave mode.
Table 20. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable.
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 20.
0: Divider by 2 enabled
1: Divider by 2 disabled
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.4.5 ”Master Mode Fault” on
page 85).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
Serial Clock
SPR2
SPR1
SPR0
fCPU/2
1
0
0
fCPU/8
0
0
0
fCPU/16
0
0
1
fCPU/32
1
1
0
fCPU/64
0
1
0
fCPU/128
0
1
1
89/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
7
SPIF
WCOL
-
MODF
-
-
-
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
0
7
-
D7
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register).
0: Data transfer is in progress or has been approved by a clearing sequence.
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 50).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.5.4.5
”Master Mode Fault” on page 85). An SPI interrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
90/164
0
D6
D5
D4
D3
D2
D1
D0
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/reception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value located in the buffer and not the contents of the shift
register (See Figure 47 ).
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 21. SPI Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0021h
SPIDR
Reset Value
MSB
x
x
x
x
x
x
x
LSB
x
0022h
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0023h
SPISR
Reset Value
SPIF
0
WCOL
0
0
MODF
0
0
0
0
0
(Hex.)
91/164
ST72311R, ST72511R, ST72512R, ST72532R
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.6.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two
baud rate generator systems.
10.6.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently
programmable transmit and
receive baud rates up to 250K baud.
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting functionfor multiprocessor configurations
■ Separate
enable bits for Transmitter and
Receiver
■ Three error detection flags:
– Overrun error
– Noise error
– Frame error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
92/164
10.6.3 General Description
The interface is externally connected to another
device by two pins (see Figure 53):
– TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO
pin is at high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data recovery by discriminating between valid incoming
data and noise.
Through this pins, serial data is transmitted and received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
This interface usestwo types of baud rate generator:
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 52. SCI Block Diagram
Write
Read
(DATA REGIST ER) DR
Received Data Register (RDR)
Transmit Data Register (TDR)
TDO
Received Shift Register
Transmit Shift Register
RDI
CR1
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8
-
M
WAKE
-
-
-
RECEIVER
RECEIVE R
CONTROL
CLOCK
SR
CR2
TIE TCIE RIE
ILIE
TE
RE RWU SBK
TDRE TC RDRF IDLE OR
NF
FE
-
SCI
INTERRUPT
CONTROL
TRANSMIT TER
CLOCK
TRANS MITTER RATE
fCPU
CONTROL
/16
/2
/PR
BRR
SCP1 SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVEN TIONAL BAUD RATE GENERATOR
93/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in Figure 52. It contains 6 dedicated registers:
– Two control registers (CR1 & CR2)
– A status register (SR)
– A baud rate register (BRR)
– An extended prescaler receiver register (ERPR)
– Anextendedprescalertransmitter register (ETPR)
Refer to the register descriptions in Section
10.6.7for the definitions of each bit.
10.6.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see Figure 52).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 53. Word length programming
9-bit Word length (M bit is set)
Possible
Parity
Bit
Data Frame
Start
Bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Start
Bit
Break Frame
Extra
’1’
Possible
Parity
Bit
Data Frame
94/164
Bit0
Bit8
Next
Stop Start
Bit
Bit
Idle Frame
8-bit Word length (M bit is reset)
Start
Bit
Bit7
Next Data Frame
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Start
Bit
Next Data Frame
Stop
Bit
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame
Extra Start
Bit
’1’
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.2 Transmitter
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 52).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the BRR and
the ETPR registers.
– Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first
transmission.
– Access the SR register and write the data to
send in the DR register (this sequence clears the
TDRE bit). Repeat this sequence for each data to
be transmitted.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write instruction to the DR register stores the data in the
TDR register and which is copied in the shift register at the end of the current transmission.
When no transmission is taking place, a write instruction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 53).
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
Idle Characters
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.
95/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.3 Receiver
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the internal bus and the received shift register (see Figure 52).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the BRR and
the ERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during reception.
Clearing the RDRF bit is performed by the following
software sequence done by:
1. An access to the SR register
2. A read to the DR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
Break Character
When a break character is received, the SPI handles it as a framing error.
Idle Character
When a idle frame is detected, there is the same
procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
96/164
Overrun Error
An overrun error occurs when a character is received when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SR register
followed by a DR register read operation.
Noise Error
Oversampling techniques are used for data recovery by discriminating between valid incoming data
and noise.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– Data is transferred from the Shift register to the
DR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The NF bit is reset by a SR register read operation
followed by a DR register read operation.
Framing Error
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchronization or excessive noise.
– A break is received.
When the framing error is detected:
– the FE bit is set by hardware
– Data is transferred from the Shift register to the
DR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram
EXTE NDED PRESCALER TRANSMITTE R RATE CONTROL
ETPR
EXTE NDED TRANS MITTER PRESCALE R REGISTER
ERPR
EXTE NDED RECEIVER PRESCALER REGISTER
EXTE NDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
fCPU
TRANSMI TTER
CLOCK
TRANSMIT TER RATE
CONTROL
/16
/2
/PR
BRR
SCP1 SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER
CLOCK
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
97/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.4 Conventional Baud Rate Generation
than zero. The baud rates are calculated as follows:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
fCPU
fCPU
follows:
Rx =
Tx =
fCPU
fCPU
16*ERPR
16*ETPR
Rx =
Tx =
(32*PR)*RR
(32*PR)*TR
with:
with:
ETPR = 1,..,255 (see ETPR register)
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
ERPR = 1,.. 255 (see ERPR register)
TR = 1, 2, 4, 8, 16, 32, 64,128
10.6.4.6 Receiver Muting and Wake-up Feature
(see SCT0, SCT1 & SCT2 bits)
In multiprocessor configurations it is often desirable that only the intended message recipient
RR = 1, 2, 4, 8, 16, 32, 64,128
should actively receive the full message contents,
(see SCR0,SCR1 & SCR2 bits)
thus reducing redundant SCI service overhead for
All this bits are in the BRR register.
all non addressed receivers.
Example: If fCPU is 8 MHz (normal mode) and if
The non addressed devices may be placed in
PR=13 and TR=RR=1, the transmit and receive
sleep mode by means of the muting function.
baud rates are 19200 baud.
Setting the RWU bit by software puts the SCI in
Note: the baud rate registers MUST NOT be
sleep mode:
changed while the transmitter or the receiver is enAll the reception status bits can not be set.
abled.
All the receive interrupt are inhibited.
10.6.4.5 Extended Baud Rate Generation
A muted receiver may be awakened by one of the
The extended prescaler option gives a very fine
following two ways:
tuning on the baud rate, using a 255 value prescal– by Idle Line detection if the WAKE bit is reset,
er, whereas the conventional Baud Rate Generator retains industry standard software compatibili– by Address Mark detection if the WAKE bit is set.
ty.
Receiver wakes-up by Idle Line detection when
The extended baud rate generator block diagram
the Receive line has recognised an Idle Frame.
is described in the Figure 54.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
Receiver wakes-up by Address Mark detection
divided by a factor ranging from 1 to 255 set in the
when it received a “1” as the most significant bit of
ERPR or the ETPR register.
a word, thus indicating that the message is an address. The reception of this particular word wakes
Note: the extended prescaler is activated by setup the receiver, resets the RWU bit and sets the
ting the ETPR or ERPR register to a value other
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
98/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.5 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
10.6.6 Interrupts
Interrupt Event
Transmit Data Register Empty
Transmission Complete
Received Data Ready to be Read
Overrrun Error Detected
Idle Line Detected
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
Event
Flag
TDRE
TC
RDRF
OR
IDLE
Enable
Control
Bit
TIE
TCIE
RIE
ILIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
99/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.7 Register Description
STATUS REGISTER (SR)
Read Only
Reset Value: 1100 0000 (C0h)
7
TDRE
0
TC
RDRF
IDLE
OR
NF
FE
-
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a
write to the DR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: data will not be transferred to the shift register as long as the TDRE bit is not reset.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a
write to the DR register).
0: Transmission is not complete
1: Transmission is complete
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SR register followed by a read to the DR register).
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the
SR register followed by a read to the DR register).
0: No Idle Line is detected
1: Idle Line is detected
100/164
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line occurs). This bit is not set by an idle line when the receiver wakes up from wake-up mode.
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 register. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
Bit 2 = NF Noise flag.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SR register followed by a read to the DR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
Bit 0 = Unused.
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)
1: An SCI interrupt is generated whenever TC=1 in
the SR register
Read/Write
Reset Value: Undefined
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
7
0
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
R8
T8
M
WAK E
or RDRF=1 in the SR register
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M=1.
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Address Mark
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
TIE
0
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 6 = TCIE Transmission complete interrupt enable
This bit is set and cleared by software.
0: interrupt is inhibited
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SR register.
1: Receiver is enabled and begins searching for a
start bit.
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
101/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift register (see Figure 52).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 52).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1 SCR0
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
0
0
3
0
1
4
1
0
13
1
1
102/164
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR dividi ng factor
SCT2
SCT1
SCT0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
RR dividi ng factor
SCR2
SCR1
SCR0
1
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)
Read/Write
Reset Value: 0000 0000 (00h)
Allows setting of the Extended Prescaler rate division factor for the receive circuit.
7
0
ERPR ERPR
7
6
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)
Read/Write
Reset Value:0000 0000 (00h)
Allows setting of the External Prescaler rate division factor for the transmit circuit.
7
ERPR ERPR ERPR ERPR ERPR ERPR
5
4
3
2
1
0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 54) is divided by
the binary factor set in the ERPR register (in the
range 1 to 255).
The extended baud rate generator is not used after a reset.
ETPR
7
0
ETPR ETPR
6
5
ETPR ETPR
4
3
ETPR ETPR ETPR
2
1
0
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 54) is divided by
the binary factor set in the ETPR register (in the
range 1 to 255).
The extended baud rate generator is not used after a reset.
Table 22. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0050h
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
0
0051h
SCIDR
Reset Value
MSB
x
x
x
x
x
x
x
LSB
x
0052h
SCIBRR
Reset Value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
0053h
SCICR1
Reset Value
R8
x
T8
x
0
M
x
WAKE
x
0
0
0
0054h
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
0055h
SCIERPR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
0057h
SCIETPR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
103/164
ST72311R, ST72511R, ST72512R, ST72532R
10.7 CONTROLLER AREA NETWORK (CAN)
10.7.1 Introduction
This peripheral is designed to support serial data
exchanges using a multi-master contention based
priority scheme as described in CAN specification
Rev. 2.0 part A. It can also be connected to a 2.0 B
network without problems, since extended frames
are checked for correctness and acknowledged
accordingly although such frames cannot be transmitted nor received. The same applies to overload
frames which are recognized but never initiated.
Figure 55. CAN Block Diagram
ST7 Internal Bus
ST7 Interface
TX/RX
Buffer 1
TX/RX
Buffer 2
TX/RX
Buffer 3
ID
Filter 0
ID
Filter 1
10 Bytes
10 Bytes
10 Bytes
4 Bytes
4 Bytes
PSR
BRPR
BTR
RX
BTL
ICR
SHREG
BCDL
ISR
TX
EML
CRC
CSR
CAN 2.0B passive Core
TECR
RECR
104/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.2 Main Features
– Support of CAN specification 2.0A and 2.0B passive
– Three prioritized 10-byte Transmit/Receive message buffers
– Two programmable global 12-bit message acceptance filters
– Programmable baud rates up to 1 MBit/s
– Buffer flip-flopping capability in transmission
– Maskable interrupts for transmit, receive (one
per buffer), error and wake-up
– Automatic low-power mode after 20 recessive
bits or on demand (standby mode)
– Interrupt-driven wake-up from standby mode
upon reception of dominant pulse
– Optional dominant pulse transmission on leaving
standby mode
– Automatic message queuing for transmission
upon writing of data byte 7
– Programmable loop-back mode for self-test operation
– Advanced error detection and diagnosis functions
– Software-efficient buffer mapping at a unique address space
– Scalable architecture.
10.7.3 Functional Description
10.7.3.1 Frame Formats
A summary of all the CAN frame formats is given
in Figure 56 for reference. It covers only the standard frame format since the extended one is only
acknowledged.
A message begins with a start bit called Start Of
Frame (SOF). This bit is followed by the arbitration
field which contains the 11-bit identifier (ID) and
the Remote Transmission Request bit (RTR). The
RTR bit indicates whether it is a data frame or a remote request frame. A remote request frame does
not have any data byte.
The control field contains the Identifier Extension
bit (IDE), which indicates standard or extended
format, a reserved bit (ro) and, in the last four bits,
a count of the data bytes (DLC). The data field
ranges from zero to eight bytes and is followed by
the Cyclic Redundancy Check (CRC) used as a
frame integrity check for detecting bit errors.
The acknowledgement (ACK) field comprises the
ACK slot and the ACK delimiter. The bit in the ACK
slot is placed on the bus by the transmitter as a recessive bit (logical 1). It is overwritten as a dominant bit (logical 0) by those receivers which have
at this time received the data correctly. In this way,
the transmitting node can be assured that at least
one receiver has correctly received its message.
Note that messages are acknowledged by the receivers regardless of the outcome of the acceptance test.
The end of the message is indicated by the End Of
Frame (EOF). The intermission field defines the
minimum number of bit periods separating consecutive messages. If there is no subsequent bus
access by any station, the bus remains idle.
10.7.3.2 Hardware Blocks
The CAN controller contains the following functional blocks (refer to Figure 55):
– ST7 Interface: buffering of the ST7 internal bus
and address decoding of the CAN registers.
– TX/RX Buffers: three 10-byte buffers for transmission and reception of maximum length messages.
– ID Filters: two 12-bit compare and don’t care
masks for message acceptance filtering.
– PSR: page selection register (see memory map).
– BRPR: clock divider for different data rates.
– BTR: bit timing register.
– ICR: interrupt control register.
– ISR: interrupt status register.
– CSR: general purpose control/status register.
– TECR: transmit error counter register.
– RECR: receive error counter register.
– BTL: bit timing logic providing programmable bit
sampling and bit clock generation for synchronization of the controller.
– BCDL: bit coding logic generating a NRZ-coded
datastream with stuff bits.
– SHREG: 8-bit shift register for serialization of
data to be transmitted and parallelisation of received data.
– CRC: 15-bit CRC calculator and checker.
– EML: error detection and management logic.
– CAN Core: CAN 2.0B passive protocol controller.
105/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Figure 56. CAN Frames
Inter-Frame Space
Inter-Frame Space
or Overload Frame
Data Frame
44 + 8 * N
Arbitration Field Control Field Data Field
12
6
ID
Ack Field
2
CRC Field
8 *N
16
EOF
CRC
ACK
SOF
RTR
IDE
r0
DLC
7
Inter-Frame Space
Inter-Frame Space
or Overload Frame
Remote Frame
44
Arbitration Field Control Field
12
CRC Field
6
ID
16
End Of Frame
7
CRC
ACK
RTR
IDE
r0
DLC
SOF
Data Frame or
Remote Frame
Ack Field
2
Inter-Frame Space
or Overload Frame
Error Frame
Error Flag Flag Echo Error Delimiter
6
≤6
8
Inter-Frame Space
Any Frame
Data Frame or
Remote Frame
Notes:
•0
<= N
<= 8
• SOF = Start Of Frame
Suspend
Intermission
Transmission
3
8
Bus Idle
• ID = Identifier
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
End Of Frame or
Error Delimiter or
Overload Delimiter
• DLC = Data Length Code
Overload Frame
Inter-Frame Space
or Error Frame
• CRC = Cyclic Redundancy Code
•Error flag: 6 dominant bits if node is error
active else 6 recessive bits.
Overload Flag Overload Delimiter
6
8
• Suspend transmission: applies to error
passive nodes only.
• EOF = End of Frame
• ACK = Acknowledge bit
106/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.3.3 Modes of Operation
The CAN Core unit assumes one of the seven
states described below:
– STANDBY. Standby mode is entered either on a
chip reset or on resetting the RUN bit in the Control/Status Register (CSR). Any on-going transmission or reception operation is not interrupted
and completes normally before the Bit Time Logic and the clock prescaler are turned off for minimum power consumption. This state is signalled
by the RUN bit being read-back as 0.
Once in standby, the only event monitored is the
reception of a dominant bit which causes a wakeup interrupt if the SCIE bit of the Interrupt Control
Register (ICR) is set.
The STANDBY mode is left by setting the RUN
bit. If the WKPS bit is set in the CSR register,
then the controller passes through WAKE-UP
otherwise it enters RESYNC directly.
It is important to note that the wake-up mechanism is software-driven and therefore carries a
significant time overhead. All messages received
after the wake-up bit and before the controller is
set to run and has completed synchronization
are ignored.
– WAKE-UP. The CAN bus line is forced to dominant for one bit time signalling the wake-up condition to all other bus members.
Figure 57. CAN Controller State Diagram
ARESET
RUN & WKP S
STAN DBY
RUN
RUN & WKPS
WAKE-UP
RESYNC
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF ) & 128 * 11 Recessive bits
RUN
IDLE
Write to DATA7 |
TX Error & NRTX
Start Of Frame
TX OK
RX OK
Arbitration lost
TRANSMIS SION
RECEPTI ON
RX Error
TX Error
BOFF
ERROR
BOFF
n
107/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
– RESYNC. The resynchronization mode is used
to find the correct entry point for starting transmission or reception after the node has gone
asynchronous either by going into the STANDBY
or bus-off states.
Resynchronization is achieved when 128 sequences of 11 recessive bits have been monitored unless the node is not bus-off and the
FSYN bit in the CSR register is set in which case
a single sequence of 11 recessive bits needs to
be monitored.
– IDLE. The CAN controller looks for one of the following events: the RUN bit is reset, a Start Of
Frame appears on the CAN bus or the DATA7
register of the currently active page is written to.
– TRANSMISSION. Once the LOCK bit of a Buffer
Control/Status Register (BCSRx) has been set
and read back as such, a transmit job can be
submitted by writing to the DATA7 register. The
message with the highest priority will be transmitted as soon as the CAN bus becomes idle.
Among those messages with a pending transmission request, the highest priority is given to
Buffer 3 then 2 and 1. If the transmission fails due
to a lost arbitration or to an error while the NRTX
bit of the CSR register is reset, then a new transmission attempt is performed . This goes on until
the transmission ends successfully or until the
job is cancelled by unlocking the buffer, by setting the NRTX bit or if the node ever enters busoff or if a higher priority message becomes pending. The RDY bit in the BCSRx register, which
was set since the job was submitted, gets reset.
When a transmission is in progress, the BUSY bit
in the BCSRx register is set. If it ends successfully then the TXIF bit in the Interrupt Status Register (ISR) is set, else the TEIF bit is set. An
interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
The ETX bit in the same register is used to get an
early transmit interrupt and to automatically unlock the transmitting buffer upon successful completion of its job. This enables the CPU to get a
new transmit job pending by the end of the current transmission while always leaving two buffers available for reception. An uninterrupted
stream of messages may be transmitted in this
way at no overrun risk.
108/164
Note 1: Setting the SRTE bit of the CSR register
allows transmitted messages to be simultaneously received when they pass the acceptance
filtering. This is particularly useful for checking
the integrity of the communication path.
Note 2: When the ETX bit is reset, the buffer with
the highest priority and with a pending transmission request is always transmitted. When the
ETX bit is set, once a buffer participates in the arbitration phase, it is sent until it wins the arbitration even if another transmission is requested
from a buffer with a higher priority.
– RECEPTION. Once the CAN controller has synchronized itself onto the bus activity, it is ready
for reception of new messages. Every incoming
message gets its identifier compared to the acceptance filters. If the bitwise comparison of the
selected bits ends up with a match for at least
one of the filters then that message is elected for
reception and a target buffer is searched for. This
buffer will be the first one - order is 1 to 3 - that
has the LOCK and RDY bits of its BCSRx register reset.
– When no such buffer exists then an overrun
interrupt is generated if the ORIE bit of the ICR
register has been set. In this case the identifier of the last message is made available in the
Last Identifier Register (LIDHR and LIDLR) at
least until it gets overwritten by a new identifier picked-up from the bus.
– When a buffer does exist, the accepted message gets written into it, the ACC bit in the
BCSRx register gets the number of the matching filter, the RDY and RXIF bits get set and an
interrupt is generated if the RXIE bit in the ISR
register is set.
Up to three messages can be automatically
received without intervention from the CPU
because each buffer has its own set of status
bits, greatly reducing the reactiveness requirements in the processing of the receive interrupts.
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
– ERROR. The error management as described in
the CAN protocol is completely handled by hardware using 2 error counters which get incremented or decremented according to the error
condition. Both of them may be read by the appli-
cation to determine the stability of the network.
Moreover, as one of the node status bits (EPSV
or BOFF of the CSR register) changes, an interrupt is generated if the SCIE bit is set in the ICR
Register. Refer to Figure 58.
Figure 58. CAN Error State Diagram
When TECR or RECR > 127, the EPSV bit gets set
ERROR ACTI VE
ERROR PASSI VE
When TECR and RECR < 128,
the EPSV bit gets cleared
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
When TECR > 255 the BOFF bit gets set
and the EPSV bit gets cleared
BUS OFF
109/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.3.4 Bit Timing Logic
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and resynchronizing on following edges.
Its operation may be explained simply when the
nominal bit time is divided into three segments as
follows:
– Synchronisation segment (SYNC_SEG): a bit
change is expected to lie within this time segment. It has a fixed length of one time quanta (1
x tCAN ).
– Bit segment 1 (BS1): defines the location of the
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compensate for positive phase drifts due to differences in
the frequency of the various nodes of the network.
– Bit segment 2 (BS2): defines the location of the
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programmable between 1 and 8 time quanta but may also be
automatically shortened to compensate for negative phase drifts.
The resynchronization jump width (RJW) defines
an upper bound to the amount of lengthening or
shortening of the bit segments. It is programmable
between 1 and 4 time quanta.
A valid edge is defined as the first transition in a bit
time from dominant to recessive bus level provided the controller itself does not send a recessive
bit.
If a valid edge is detected in BS1 instead of
SYNC_SEG, BS1 is extended by up to RJW so
that the sample point is delayed.
Conversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by up to
RJW so that the transmit point is moved earlier.
As a safeguard against programming errors, the
configuration of the Bit Timing Register (BTR) is
only possible while the device is in STANDBY
mode.
Figure 59. Bit Timing
NOMINAL BIT TIME
SYNC_SEG
1 x tCAN
BIT SEGMENT 1 (BS1)
BIT SEGMENT 2 (BS2)
tBS1
tBS2
SAMPLE POINT
110/164
TRANS MIT POINT
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.4 Register Description
The CAN registers are organized as 6 general purpose registers plus 5 pages of 16 registers spanning the same address space and primarily used
for message and filter storage. The page actually
selected is defined by the content of the Page Selection Register. Refer to Figure 60.
10.7.4.1 General Purpose Registers
INTERRUPT STATUS REGISTER (ISR)
Read/Write
Reset Value: 00h
7
RXIF3 RXIF2 RXIF1
0
TXIF
SCIF
ORIF
TEIF
EPND
Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3
− Read/Clear
Set by hardware to signal that a new error-free message is available in buffer 3.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2
− Read/Clear
Set by hardware to signal that a new error-free
message is available in buffer 2.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1
− Read/Clear
Set by hardware to signal that a new error-free message is available in buffer 1.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
Bit 4 = TXIF Transmit Interrupt Flag
− Read/Clear
Set by hardware to signal that the highest priority
message queued for transmission has been successfully transmitted (ETX = 0) or that it has passed
successfully the arbitration (ETX = 1).
Cleared by software.
Bit 3 = SCIF Status Change Interrupt Flag
− Read/Clear
Set by hardware to signal the reception of a dominant bit while in standby or a change from error active to error passive and bus-off while in run. Also
signals any receive error when ESCI = 1.
Cleared by software.
Bit 2 = ORIF Overrun Interrupt Flag
− Read/Clear
Set by hardware to signal that a message could not
be stored because no receive buffer was available.
Cleared by software.
Bit 1 = TEIF Transmit Error Interrupt Flag
− Read/Clear
Set by hardware to signal that an error occurred during the transmission of the highest priority message
queued for transmission.
Cleared by software.
Bit 0 = EPND Error Interrupt Pending
− Read Only
Set by hardware when at least one of the three error
interrupt flags SCIF, ORIF or TEIF is set.
Reset by hardware when all error interrupt flags
have been cleared.
Caution;
Interrupt flags are reset by writing a ”0” to the corresponding bit position. The appropriate way consists in writing an immediate mask or the one’s complement of the register content initially read by the
interrupt handler. Bit manipulation instruction
BRES should never be used due to its read-modifywrite nature.
111/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
INTERRUPT CONTROL REGISTER (ICR)
Read/Write
Reset Value: 00h
7
0
0
ESCI
RXIE
TXIE
SCIE
ORIE
TEIE
ETX
Bit 6 = ESCI Extended Status Change Interrupt
− Read/Set/Clear
Set by software to specify that SCIF is to be set on
receive errors also.
Cleared by software to set SCIF only on status
changes and wake-up but not on all receive errors.
Bit 5 = RXIE Receive Interrupt Enable
− Read/Set/Clear
Set by software to enable an interrupt request
whenever a message has been received free of errors.
Cleared by software to disable receive interrupt requests.
Bit 4 = TXIE Transmit Interrupt Enable
− Read/Set/Clear
Set by software to enable an interrupt request
whenever a message has been successfully transmitted.
Cleared by software to disable transmit interrupt
requests.
112/164
Bit 3 = SCIE Status Change Interrupt Enable
− Read/Set/Clear
Set by software to enable an interrupt request
whenever the node’s status changes in run mode or
whenever a dominant pulse is received in standby
mode.
Cleared by software to disable status change interrupt requests.
Bit 2 = ORIE Overrun Interrupt Enable
− Read/Set/Clear
Set by software to enable an interrupt request
whenever a message should be stored and no receive buffer is avalaible.
Cleared by software to disable overrun interrupt requests.
Bit 1 = TEIE Transmit Error Interrupt Enable
− Read/Set/Clear
Set by software to enable an interrupt whenever an
error has been detected during transmission of a
message.
Cleared by software to disable transmit error interrupts.
Bit 0 = ETX Early Transmit Interrupt
− Read/Set/Clear
Set by software to request the transmit interrupt to
occur as soon as the arbitration phase has been
passed successfully.
Cleared by software to request the transmit interrupt to occur at the completion of the transfer.
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 00h
7
0
0
BOFF
EPSV
SRTE NRTX
FSYN WKPS
RUN
Bit 6 = BOFF Bus-Off State
− Read Only
Set by hardware to indicate that the node is in busoff state, i.e. the Transmit Error Counter exceeds
255.
Reset by hardware to indicate that the node is involved in bus activities.
Bit 5 = EPSV Error Passive State
− Read Only
Set by hardware to indicate that the node is error
passive.
Reset by hardware to indicate that the node is either
error active (BOFF = 0) or bus-off.
Bit 4 = SRTE Simultaneous Receive/Transmit Enable − Read/Set/Clear
Set by software to enable simultaneous transmission and reception of a message passing the acceptance filtering. Allows to check the integrity of
the communication path.
Reset by software to discard all messages transmitted by the node. Allows remote and data frames
to share the same identifier.
Bit 3 = NRTX No Retransmission
− Read/Set/Clear
Set by software to disable the retransmission of unsuccessful messages.
Cleared by software to enable retransmission of
messages until success is met.
Bit 2 = FSYN Fast Synchronization
− Read/Set/Clear
Set by software to enable a fast resynchronization
when leaving standby mode, i.e. wait for only 11 recessive bits in a row.
Cleared by software to enable the standard resynchronization when leaving standby mode, i.e. wait
for 128 sequences of 11 recessive bits.
Bit 1 = WKPS Wake-up Pulse
− Read/Set/Clear
Set by software to generate a dominant pulse when
leaving standby mode.
Cleared by software for no dominant wake-up
pulse.
Bit 0 = RUN CAN Enable
− Read/Set/Clear
Set by software to leave standby mode after 128 sequences of 11 recessive bits or just 11 recessive
bits if FSYN is set.
Cleared by software to request a switch to the
standby or low-power mode as soon as any on-going transfer is complete. Read-back as 1 in the
meantime to enable proper signalling of the standby
state. The CPU clock may therefore be safely
switched OFF whenever RUN is read as 0.
113/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
BAUD RATE PRESCALER REGISTER (BRPR)
Read/Write in Standby mode
Reset Value: 00h
7
RJW1 RJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BIT TIMING REGISTER (BTR)
Read/Write in Standby mode
Reset Value: 23h
0
7
BRP0
0
RJW[1:0] determine the maximum number of time
quanta by which a bit period may be shortened or
lengthened to achieve resynchronization.
tRJW = tCAN * (RJW + 1)
BRP[5:0] determine the CAN system clock cycle
time or time quanta which is used to build up the individual bit timing.
tCAN = tCPU * (BRP + 1)
Where tCPU = time period of the CPU clock.
The resulting baud rate can be computed by the formula:
0
BS22
BS21
BS20
BS13
BS12
BS11
BS10
BS2[2:0] determine the length of Bit Segment 2.
tBS2 = tCAN * (BS2 + 1)
BS1[3:0] determine the length of Bit Segment 1.
tBS1 = tCAN * (BS1 + 1)
Note: Writing to this register is allowed only in
Standby mode to prevent any accidental CAN protocol violation through programming errors.
PAGE SELECTION REGISTER (PSR)
Read/Write
Reset Value: 00h
7
1 -------------------------------------- B R = ------------------------------------------------------t CP U × ( BRP + 1 ) × ( BS1 + BS2 + 3 )
0
0
0
0
0
PAGE PAGE PAGE
2
1
0
0
PAGE[2:0] determine which buffer or filter page is
mapped at addresses 0010h to 001Fh.
Note: Writing to this register is allowed only in
Standby mode to prevent any accidental CAN protocol violation through programming errors.
114/164
PAGE2
PAGE1
PAGE0
Page Title
0
0
0
Diagnosis
0
0
1
Buffer 1
0
1
0
Buffer 2
0
1
1
Buffer 3
1
0
0
Filters
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.4.2 Paged Registers
LAST IDENTIFIER HIGH REGISTER (LIDHR)
Read/Write
Reset Value: Undefined
7
LID10
0
LID9
LID8
LID7
LID6
LID5
LID4
LAST IDENTIFIER LOW REGISTER (LIDLR)
Read/Write
Reset Value: Undefined
LID2
0
LID1
LID0
LRTR
LDLC
3
LDLC
2
LDLC
1
7
TEC7
0
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
LID3
LID[10:3] are the most significant 8 bits of the last
Identifier read on the CAN bus.
7
TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
Reset Value: 00h
LDLC
0
LID[2:0] are the least significant 3 bits of the last
Identifier read on the CAN bus.
LRTR is the last Remote Transmission Request bit
read on the CAN bus.
LDLC[3:0] is the last Data Length Code read on the
CAN bus.
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
In case of an error during transmission, this counter
is incremented by 8. It is decremented by 1 after
every successful transmission. When the counter
value exceeds 127, the CAN controller enters the
error passive state. When a value of 256 is reached,
the CAN controller is disconnected from the bus.
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
Reset Value: 00h
7
REC7
0
REC6 REC5
REC4
REC3
REC2
REC1
REC0
REC[7:0] is the Receive Error Counter implementing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN standard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
IDENTIFIER HIGH REGISTERS (IDHRx)
Read/Write
Reset Value: Undefined
7
ID10
0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID[10:3] are the most significant 8 bits of the 11-bit
message identifier.The identifier acts as the message’s name, used for bus access arbitration and
acceptance filtering.
115/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
BUFFER CONTROL/STATUS REGs. (BCSRx)
Read/Write
Reset Value: 00h
IDENTIFIER LOW REGISTERS (IDLRx)
Read/Write
Reset Value: Undefined
7
ID2
ID1
ID0
RTR
DLC3
DLC2
DLC1
0
7
DLC0
0
ID[2:0] are the least significant 3 bits of the 11-bit
message identifier.
RTR is the Remote Transmission Request bit. It is
set to indicate a remote frame and reset to indicate
a data frame.
DLC[3:0] is the Data Length Code. It gives the
number of bytes in the data field of the message.The valid range is 0 to 8.
DATA REGISTERS (DATA0-7x)
Read/Write
Reset Value: Undefined
7
DATA
7
0
DATA
6
DATA
5
DATA
4
DATA
3
DATA
2
DATA
1
DATA
0
DATA[7:0] is amessage data byte. Upto eight such
bytes may be part of a message. Writing to byte
DATA7 initiates a transmit request and should always be done even when DATA7 is not part of the
message.
116/164
0
0
0
0
ACC
RDY
BUSY LOCK
Bit 3 = ACC Acceptance Code
− Read Only
Set by hardware with the id of the highest priority
filter which accepted the message stored in the
buffer.
ACC = 0: Match for Filter/Mask0. Possible match
for Filter/Mask1.
ACC = 1: No match for Filter/Mask0 and match for
Filter/Mask1.
Reset by hardware when either RDY or RXIF gets
reset.
Bit 2 = RDY Message Ready
− Read/Clear
Set by hardware to signal that a new error-free
message is available (LOCK = 0) or that a transmission request is pending (LOCK = 1).
Cleared by software when LOCK = 0 to release
the buffer and to clear the corresponding RXIF bit
in the Interrupt Status Register.
Cleared by hardware when LOCK = 1 to indicate
that the transmission request has been serviced or
cancelled.
Bit 1 = BUSY Busy Buffer
− Read Only
Set by hardware when the buffer is being filled
(LOCK = 0) or emptied (LOCK = 1).
Reset by hardware when the buffer is not accessed by the CAN core for transmission nor reception purposes.
Bit 0 = LOCK Lock Buffer
− Read/Set/Clear
Set by software to lock a buffer. No more message
can be received into the buffer thus preserving its
content and making it available for transmission.
Cleared by software to make the buffer available
for reception. Cancels any pending transmission
request.
Cleared by hardware once a message has been
successfully transmitted provided the early transmit interrupt mode is on. Left untouched otherwise.
Note that in order to prevent any message corruption or loss of context, LOCK cannot be set nor reset while BUSY is set. Trying to do so will result in
LOCK not changing state.
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
FILTER HIGH REGISTERS (FHRx)
Read/Write
Reset Value: Undefined
MASK HIGH REGISTERS (MHRx)
Read/Write
Reset Value: Undefined
7
FIL11
0
FIL10
FIL9
FIL8
FIL7
FIL6
FIL5
FlL4
FIL[11:3] are the most significant 8 bits of a 12-bit
message filter. The acceptance filter is compared
bit by bit with the identifier and the RTR bit of the
incoming message. If there is a match for the set
of bits specified by the acceptance mask then the
message is stored in a receive buffer.
FILTER LOW REGISTERS (FLRx)
Read/Write
Reset Value: Undefined
7
FIL3
0
FIL2
FIL1
FIL0
0
0
0
0
7
0
MSK1 MSK1
MSK9 MSK8 MSK7
1
0
MSK6 MSK5 MSK4
MSK[11:3] are the most significant 8 bits of a 12bit message mask. The acceptance mask defines
which bits of the acceptance filter should match
the identifier and the RTR bit of the incoming message.
MSKi = 0: don’t care.
MSKi = 1: match required.
MASK LOW REGISTERS (MLRx)
Read/Write
Reset Value: Undefined
7
MSK3 MSK2 MSK1 MSK0
0
0
0
0
0
FIL[3:0] are the least significant 4 bits of a 12-bit
message filter.
MSK[3:0] are the least significant 4 bits of a 12-bit
message mask.
117/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Figure 60. CAN Register Map
5Ah
Interrupt Status
5Bh
Interrupt Control
5Ch
Control/Status
5Dh
Baud Rate Prescaler
5Eh
Bit Timing
5Fh
Page Selection
60h
6Fh
118/164
Paged Reg1
Paged Reg1
Paged
Paged
Reg1Reg0
Paged
Reg2
Paged
Paged
Reg2Reg1
Paged
Paged
Reg2Reg1
Paged
Reg3
Paged
Paged
Reg3Reg2
Paged
Paged
Reg3Reg2
Paged
Reg4
Paged
Paged
Reg4Reg3
Paged
Paged
Reg4Reg3
Paged
Reg5
Paged
Paged
Reg5Reg4
Paged
Paged
Reg5Reg4
Paged
Reg6
Paged
Paged
Reg6Reg5
Paged
Paged
Reg6Reg5
Paged
Reg7
Paged
Paged
Reg7Reg6
Paged
Paged
Reg7Reg6
Paged
Reg8
Paged
Paged
Reg8Reg7
Paged
Paged
Paged
Reg9Reg8Reg7
Paged
Paged
Reg9Reg8
Paged
Paged
Reg9Reg8
Paged
Reg10
Paged
Reg9
Paged
Reg10
Paged
Reg9
Paged
Reg10
Paged
Reg11
Paged
Reg10
Paged
Reg11
Paged
Reg10
Paged
Reg11
Paged
Reg12
Paged
Reg11
Paged
Reg12
Paged
Reg11
Paged
Reg12
Paged
Reg13
Paged
Reg12
Paged
Reg13
Paged
Reg12
Paged
Reg13
Paged
Reg14
Paged
Reg13
Paged
Reg14
Paged
Reg13
Paged
Reg14
Paged
Reg15
Paged
Reg14
Paged
Reg15
Paged
Reg14
Paged
Reg15
Paged Reg15
Paged Reg15
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Figure 61. Page Maps
PAGE 0
PAGE 1
PAGE 2
PAGE 3
PAGE 4
60 h
LIDHR
IDHR1
IDHR2
IDHR3
FHR0
61 h
LIDLR
IDLR1
IDLR2
IDLR3
FLR0
62 h
DATA 01
DATA02
DATA03
MHR0
63 h
DATA 11
DATA12
DATA13
MLR0
64 h
DATA 21
DATA22
DATA23
FHR1
65 h
DATA 31
DATA32
DATA33
FLR1
66 h
DATA 41
DATA42
DATA43
MHR1
DATA 51
DATA52
DATA53
MLR1
68 h
DATA 61
DATA62
DATA63
69 h
DATA 71
DATA72
DATA73
Reserved
Reserved
Reserved
67 h
Reserved
6A h
6B h
Reserved
6Ch
6Dh
TSTR
6E h
TECR
6Fh
RECR
BCSR1
BCSR2
BCSR3
Diagnosis
Buffer 1
Buffer 2
Buffer 3
Acceptance Filters
119/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Table 23. CAN Register Map and Reset Values
Address
(Hex.)
Page
Register
Label
7
6
5
4
3
2
1
0
5A
CANISR
Reset Value
RXIF3
0
RXIF2
0
RXIF1
0
TXIF
0
SCIF
0
ORIF
0
TEIF
0
EPND
0
5B
CANICR
Reset Value
0
ESCI
0
RXIE
0
TXIE
0
SCIE
0
ORIE
0
TEIE
0
ETX
0
5C
CANCSR
Reset Value
0
BOFF
0
EPSV
0
SRTE
0
NRTX
0
FSYN
0
WKPS
0
RUN
0
5D
CANBRPR
Reset Value
RJW1
0
RJW0
0
BRP5
0
BRP4
0
BRP3
0
BRP2
0
BRP1
0
BRP0
0
5E
CANBTR
Reset Value
0
BS22
0
BS21
1
BS20
0
BS13
0
BS12
0
BS11
1
BS10
1
5F
CANPSR
Reset Value
0
0
0
0
0
PAGE2
0
PAGE1
0
PAGE0
0
0
CANLIDHR
Reset Value
LID10
x
LID9
x
LID8
x
LID7
x
LID6
x
LID5
x
LID4
x
LID3
x
1 to 3
CANIDHRx
Reset Value
ID10
x
ID9
x
ID8
x
ID7
x
ID6
x
ID5
x
ID4
x
ID3
x
4
CANFHRx
Reset Value
FIL11
x
FIL10
x
FIL9
x
FIL8
x
FIL7
x
FIL6
x
FIL5
x
FIL4
x
0
CANLIDLR
Reset Value
LID2
x
LID1
x
LID0
x
LRTR
x
LDLC3
x
LDLC2
x
LDLC1
x
LDLC0
x
1 to 3
CANIDLRx
Reset Value
ID2
x
ID1
x
ID0
x
RTR
x
DLC3
x
DLC2
x
DLC1
x
DLC0
x
61, 65
4
CANFLRx
Reset Value
FIL3
x
FIL2
x
FIL1
x
FIL0
x
0
0
0
0
62 to 69
1 to 3
CANDRx
Reset Value
MSB
x
x
x
x
x
x
x
LSB
x
62, 66
4
CANMHRx
Reset Value
MSK11
x
MSK10
x
MSK9
x
MSK8
x
MSK7
x
MSK6
x
MSK5
x
MSK4
x
63, 67
4
CANMLRx
Reset Value
MSK3
x
MSK2
x
MSK1
x
MSK0
x
0
0
0
0
0
CANTECR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
CANRECR
Reset Value
MSB
0
0
0
0
0
0
0
LSB
0
CANBCSRx
Reset Value
0
0
0
0
ACC
0
RDY
0
BUSY
0
LOCK
0
60
60, 64
61
6E
6F
1 to 3
120/164
ST72311R, ST72511R, ST72512R, ST72532R
10.8 8-BIT A/D CONVERTER (ADC)
10.8.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
10.8.3 Functional Description
10.8.3.1 Analog Power Supply
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the VDD and VSS pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
See electrical characteristics section for more details.
10.8.2 Main Features
■ 8-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 62.
Figure 62. ADC Block Diagram
fCPU
COCO
0
ADON
0
fADC
DIV 2
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
HOLD CONTROL
RADC
AIN1
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
CADC
AINx
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
121/164
ST72311R, ST72511R, ST72512R, ST72532R
8-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the result never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than or equal
to VDDA (high-level voltage reference) then the
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (VAIN ) is lower than or equal to
VSSA (low-level voltage reference) then the conversion result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.8.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 63:
■ Sample capacitor loading [duration: tLOAD]
During this phase, the VAIN input voltage to be
measured is loaded into the CADC sample
capacitor.
■ A/D conversion [duration: tCONV]
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the CADC sample capacitor is disconnected
from the analog input pin to get the optimum
analog to digital conversion accuracy.
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
10.8.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 10.8.6 for the bit definitions and to Figure 63 for the timings.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/fADC=2/fCPU).
122/164
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
– Select the CH[3:0] bits to assign the analog
channel to be converted.
ADC Conversion
In the CSR register:
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 63. ADC Conversion Timings
ADON
ADCCSR WRITE
OPERATION
tCONV
HOLD
CONTROL
tLOAD
COCO BIT SET
10.8.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
10.8.5 Interrupts
None
ST72311R, ST72511R, ST72512R, ST72532R
8-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
COCO
0
ADON
0
CH3
CH2
CH1
0
7
CH0
D7
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by software reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
0
D6
D5
D4
D3
D2
D1
D0
Bit 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Bit 6 = Reserved. must always be cleared.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
123/164
ST72311R, ST72511R, ST72512R, ST72532R
8-BIT A/D CONVERTOR (ADC) (Cont’d)
Table 24. ADC Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
0070h
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
ADCCSR
Standard
Reset Value
COCO
CH2
CH1
CH0
0071h
0
0
0
0
0
(Hex.)
124/164
ADON
0
0
0
ST72311R, ST72511R, ST72512R, ST72532R
11 INSTRUCTION SET
11.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two sub-modes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 25. ST7 Addressing Mode Overview
Mode
Syntax
Destination
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+0
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Relative
Direct
jrne loop
PC+/-127
Relative
Indirect
jrne [$10]
PC+/-127
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip
00..FF
+1
00..FF
byte
+2
+1
00..FF
byte
+2
+2
00..FF
byte
+3
125/164
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask (level 3)
RIM
Reset Interrupt Mask (level 0)
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte contains the operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
126/164
11.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
11.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 26. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
LD
11.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset is following the opcode.
Relative (Indirect)
The offset is defined in memory, which address
follows the opcode.
Function
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Additions/Substractions operations
BCP
Bit Compare
Short Instructions
Only
Functio n
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
127/164
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Code Condition Flag modification
SIM
RIM
SCF
RCF
Using a pre-byte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2
End of previous instruction
PC-1
Prebyte
PC
opcode
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the effective address
128/164
RSP
RET
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Function /Example
Dst
Src
I1
H
I0
N
Z
C
ADC
Add with Carry
A= A+M+C
A
M
H
N
Z
C
ADD
Addition
A= A+M
A
M
H
N
Z
C
AND
Logical And
A= A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
jrf *
JRIH
Jump if Port B INT pin = 1
(no Port B Interrupts)
JRIL
Jump if Port B INT pin = 0
(Port B interrupt)
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
JRM
Jump if I1:0 = 11
I1:0 = 11 ?
JRNM
Jump if I1:0 <> 11
I1:0 <> 11 ?
JRMI
Jump if N = 1 (minus)
N=1?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
reg, M
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
1
I1
reg, M
0
H
I0
C
129/164
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
Description
Function /Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
MUL
I1
H
I0
N
Z
N
Z
dst <= src
reg, M
M, reg
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2’s compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A= A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
PUSH
Push onto the Stack
push Y
M
reg, CC
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I1:0 = 10 (level 0)
RLC
Rotate left true C
C <= A <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => A => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Substract with Carry
A= A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I1:0 = 11 (level 3)
SLA
Shift left Arithmetic
C <= A <= 0
SLL
Shift left Logic
SRL
Shift right Logic
SRA
Shift right Arithmetic
SUB
0
I1
H
C
0
I0
N
Z
N
Z
N
Z
C
C
0
1
A
0
M
1
1
1
reg, M
N
C <= A <= 0
reg, M
N
Z
C
0 => A => C
reg, M
0
Z
C
A7 => A => C
reg, M
N
Z
C
Substraction
A= A-M
A
N
Z
C
SWAP
SWAP nibbles
A7-A4 <=> A3-A0
reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
WFI
Wait for Interrupt
XOR
Exclusive OR
N
Z
130/164
A = A XOR M
A
M
M
1
1
1
0
Z
C
ST72311R, ST72511R, ST72512R, ST72532R
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are referred to VSS.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the minimum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V
voltage range) and VDD=3.3V (for the 3V≤VDD≤4V
voltage range). They are given only as design
guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 64.
12.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 65.
Figure 65. Pin input voltage
ST7 PIN
VIN
Figure 64. Pin loading conditions
ST7 PIN
CL
131/164
ST72311R, ST72511R, ST72512R, ST72532R
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device under these condi12.2.1 Voltage Characteristics
Symbol
V DD - VSS
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
Ratings
Maximum value
Supply voltage
6.5
Analog reference voltage (VDD≥VDDA )
|∆VDDx| and |∆VSSx| Variations between different digital power pins
|VSSA - VSSx|
Variations between digital and analog ground pins
VDDA - VSSA
VIN
Input voltage on VPP pin
Input voltage on any other pin 1) & 2)
6.5
50
50
V SS-0.3 to 13
VSS-0.3 to VDD+0.3
V ESD(HBM)
Electro-static discharge voltage (Human Body Model)
VESD(MM)
Electro-static discharge voltage (Machine Model)
Unit
V
mV
V
see Section 12.7.2 ”Absolute Electrical Sensitivity” on page 141
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
IVDD
Total current into VDD power lines (source)
3)
150
IVSS
Total current out of VSS ground lines (sink) 3)
150
IIO
IINJ(PIN) 2) & 4)
ΣIINJ(PIN) 2)
Output current sunk by any standard I/O and control pin
25
Output current sunk by any high sink I/O pin
50
Output current source by any I/Os and control pin
- 25
Injected current on VPP pin
±5
Injected current on RESET pin
±5
Injected current on OSC1 and OSC2 pins
±5
Injected current on any other pin 5) & 6)
±5
Total injected current (sum of all I/O and control pins) 5)
± 20
Unit
mA
12.2.3 Thermal Characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section 13.2 ”THERMAL CHARACTERISTICS” on page 155 )
Notes:
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<V SS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effect on analog part, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive
and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
132/164
ST72311R, ST72511R, ST72512R, ST72532R
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
VDD
fOSC
TA
Parameter
Conditions
Min
Max
Unit
V
Supply voltage
see Figure 66 and Figure 67
3.0
5.5
External clock frequency
VDD≥3.5V (without EEPROM)
VDD≥4.5V (with EEPROM)
0 1)
16
VDD≥3.0V
Ambient temperature range
0
1)
MHz
8
1 Suffix Version
0
70
6 Suffix Version
-40
85
7 Suffix Version
-40
105
3 Suffix Version
-40
125
°C
Figure 66. fOSC Maximum Operating Frequency Versus VDD Supply for devices without EEPROM 2)
fOSC [MHz]
FUNCTIONALI TY
GUARANTEE D
IN THIS AREA
16
FUNCTIONALI TY
NOT GUARANTEED
IN THIS AREA
FUNCTI ONALITY
NOT GUARANTEED
IN THIS AREA
WITH RESONA TOR 1)
8
4
1
0
SUPPLY VOLTAGE [V]
2.5
3
3.5
4
4.5
5
5.5
Figure 67. fOSC Maximum Operating Frequency Versus VDD Supply for device with EEPROM 2)
FUNCTIONALI TY NOT GUARAN TEED IN THIS AREA
FOR TEMPERATURE HIGHER THAN 85°C
fOSC [MHz]
FUNCTIONALI TY
GUARANTEE D
IN THIS AREA
16
FUNCTIONALI TY
NOT GUARANTEED
IN THIS AREA
FUNCT IONALITY
NOT GUARANTEE D
IN THIS AREA
WITH RESONATO R 1)
8
4
1
0
SUPPLY VOLTAGE [V]
2.5
3
3.5
4
4.5
5
5.5
Notes:
1. Guaranteed by construction. A/D operation is not guaranteed below 1MHz.
2. Operating conditions with TA=-40 to +125°C.
133/164
ST72311R, ST72511R, ST72512R, ST72532R
OPERATING CONDITIONS (Cont’d)
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating condition for VDD, fOSC, and TA.
Min
Typ 1)
Max
VIT+
Reset release threshold
(VDD rise)
3.95
4.15
4.35
VIT-
Reset generation threshold
(VDD fall)
3.70
3.90
4.10
Vhyst
LVD voltage threshold hysteresis
VtPOR
VDD rise time rate 2)
tg(VDD)
Filtered glitch delay on VDD
Symbol
Parameter
Condition s
Unit
V
VIT+-VIT-
250
mV
0.02
V/ms
Not detected by the LVD
40
ns
Figure 68. LVD Threshold Versus VDD and fOSC for ROM devices 2)
fOSC [MHz]
DEVICE UNDER
RESET
IN THIS AREA
FUNCTI ONALITY
NOT GUARAN TEED
IN THIS AREA
16
FUNCTI ONAL AREA
8
0
2.5
3
3.5
VIT-≥3.70
SUPPLY VOLTAGE [V]
4
4.5
5
5.5
Notes:
1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
134/164
ST72311R, ST72511R, ST72512R, ST72532R
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over temperature range does not take into account the clock
source current consumption. To get the total deSymbol
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Parameter
∆IDD(∆Ta)
Conditions
Supply current variation vs. temperature
Max
Unit
10
%
Typ 1)
Max 2)
Unit
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
2.5
6.5
14.5
4
9
20
fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
0.3
0.8
1.8
0.5
2.0
3.0
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
1.6
3.6
8
2.4
5.4
12
fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
0.15
0.45
1
0.3
0.9
1.5
Constant VDD and fCPU
12.4.1 RUN and SLOW Modes
Conditions
Supply current in RUN mode 3)
(see Figure 69)
Supply current in SLOW mode 4)
(see Figure 70)
IDD
Supply current in RUN mode 3)
(see Figure 69)
Supply current in SLOW mode 4)
(see Figure 70)
4.5V≤VDD≤5.5V
Parameter
3V≤VDD≤3.6V
Symbol
Figure 69. Typical IDD in RUN vs. fCPU
mA
Figure 70. Typical IDD in SLOW vs. fCPU
IDD [mA]
IDD [mA]
20
2.5
500kHz
8MHz
2MHz
4MHz
500kHz
125kHz
2
15
31.25kHz
1.5
10
1
5
0.5
0
0
3
3.5
4
4.5
VDD [V]
5
5.5
3
3.5
4
4.5
5
5.5
VDD [V]
Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤V DD≤5.5V range) and VDD=3.3V (3V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
switched off; clock input (OSC1) driven by external square wave, LVD disabled.
4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
V SS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.
135/164
ST72311R, ST72511R, ST72512R, ST72532R
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 WAIT and SLOW WAIT Modes
Parameter
Supply current in WAIT mode 3)
(see Figure 71)
Supply current in SLOW WAIT mode 4)
(see Figure 72)
Supply current in WAIT mode 3)
(see Figure 71)
3V≤VDD≤3.6V
IDD
Typ 1)
Max 2)
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
1.25
3.2
5.2
2
5
9
fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
0.2
0.6
1.2
0.35
1
2
fOSC=1MHz, fCPU=500kHz
fOSC=4MHz, fCPU=2MHz
fOSC=16MHz, fCPU=8MHz
0.7
1.6
2.7
1
2.6
4.5
fOSC=1MHz, fCPU=31.25kHz
fOSC=4MHz, fCPU=125kHz
fOSC=16MHz, fCPU=500kHz
0.1
0.3
0.6
0.15
0.5
1
Conditions
4.5V≤VDD≤5.5V
Symbol
Supply current in SLOW WAIT mode 4)
(see Figure 72)
Figure 71. Typical IDD in WAIT vs. fCPU
IDD [mA]
7
1.5
8MHz
2MHz
mA
Figure 72. Typical IDD in SLOW-WAIT vs. fCPU
IDD [mA]
6
Unit
500kHz
500kHz
125kHz
31.25kHz
5
1
4
3
0.5
2
1
0
0
3
3.5
4
4.5
VDD [V]
5
5.5
3
3.5
4
4.5
5
5.5
VDD [V]
Notes:
1. Typical data are based on TA=25°C, VDD=5V (4.5V≤V DD≤5.5V range) and VDD=3.3V (3V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals switched off; clock input (OSC1)
driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
V DD or VSS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.
136/164
ST72311R, ST72511R, ST72512R, ST72532R
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.3 HALT and ACTIVE-HALT Modes
Symbol
IDD
Parameter
Typ 1)
Conditions
-40°C≤TA≤+105°C
3.0V≤V DD
VDD≤5.5V
Supply current in HALT mode 2)
40°C≤TA≤+125°C
Supply current in ACTIVE-HALT mode 3)
12.4.4 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over temperature range does not take into account the clock
Symbol
Parameter
IDD(CK)
Supply current of resonator oscillator
IDD(LVD)
LVD supply current
0
50
Max
Unit
10
50
µA
150
source current consumption. To get the total device consumption, the two current values must be
added (except for HALT mode).
Condit ions
6) & 7)
HALT mode
Typ 4)
Max 5)
600
850
100
150
Unit
µA
12.4.5 On-Chip Peripheral
Symbol
IDD(TIM)
Parameter
16-bit Timer supply current 8)
9)
IDD(SPI)
SPI supply current
I DD(ADC)
ADC supply current when converting 10)
Conditions
fCPU=8MHz
fCPU=8MHz
fADC=4MHz
Typ
VDD=3.3V
50
VDD=5.0V
150
VDD=3.3V
250
VDD=5.0V
350
VDD=3.3V
800
VDD=5.0V
1100
Unit
µA
Notes:
1. Typical data are based on TA=25°C.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), LVD disabled.
3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode
with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled.
4. Typical data are based on TA=25°C, VDD=5V.
5. Data based on characterization results, not tested in production.
6. Data based on characterization results done with the typical external components, not tested in production.
7. As the oscillator is based on a current source, the consumption does not depend on the voltage.
8. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer
counter stopped (selecting external clock capability). Data valid for one timer.
9. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communication (data sent equal to 55h).
10. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
137/164
ST72311R, ST72511R, ST72512R, ST72532R
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating condition for VDD, fOSC, and TA.
12.5.1 General Timings
Symbol
tc(INST)
tv(IT)
Min
Typ 1)
Max
Unit
2
4
12
tCPU
fCPU=8MHz
250
500
1500
ns
10
22
tCPU
fCPU=8MHz
1.25
2.75
µs
Max
Unit
Parameter
Conditi ons
Instruction cycle time
Interrupt reaction time
tv(IT) = ∆tc(INST) + 10
2)
12.5.2 External Clock Source
Symbol
Parameter
Condi tions
Min
Typ
VOSC1H
OSC1 input pin high level voltage
0.7xVDD
VDD
VOSC1L
OSC1 input pin low level voltage
VSS
0.3xVDD
tw(OSC1H)
tw(OSC1L)
OSC1 high or low time 3)
tr(OSC1)
tf(OSC1)
OSC1 rise or fall time 3)
R OBP
see Figure 73
V
15
ns
15
Oscillator bypass exteranl resistor
1
kΩ
Figure 73. Typical Application with an External Clock Source
90%
VOSC1H
10%
VOSC1L
tr(OSC1)
tf(OSC1)
tw(OSC1H)
tw(OSC1L)
12.5.3 Crystal and Ceramic Resonator Oscillators
Symbol
Parameter
Conditio ns
Min
Max
Unit
4
16
MHz
12
21
pF
fOSC
Oscillator Frequency
C L1, CL2
Load capacitance 4)
RS=100Ω 5)
tSTART
Oscillator start-up time
Depends on resonator quality. A typical value is 10ms
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
4. CL1 (resp.CL2) is load capacitance on OSC1 (resp. OSC2) pin.
5. RS is the equivalent serial resistance of the crystal or ceramic resonator.
138/164
ST72311R, ST72511R, ST72512R, ST72532R
12.6 MEMORY CHARACTERISTICS
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
12.6.1 RAM and Hardware Registers
Symbol
VRM
Parameter
Data retention mode 1)
Conditi ons
HALT mode (or RESET)
Min
Typ
Max
1.6
Unit
V
12.6.2 EEPROM Data Memory
Symbol
tprog
tret
NRW
Parameter
Programming time
(for 1 up to 16 bytes at a time)
Data retention 3)
Write erase
cycles 3)
Conditi ons
Min
Typ
Max
-40°C≤TA≤+85°C
10
-40°C≤TA≤+125°C
15
TA=+55°C 2)
TA=+25°C
Unit
ms
20
Years
300 000
Cycles
12.6.3 EPROM Program Memory
Symbol
WERASE
terase
tret
Parameter
UV lamp
Erase Time
Conditions
Min
Lamp wavelength 2537Å
4)
Data retention 3)
Typ
Max
15
UV lamp is placed 1 inch
from the device window
without any interposed
filters
15
TA =+55°C 2)
20
Unit
Watt.sec
/cm2
20
min
years
Notes:
1. Minimum VDD supply voltage without losing data stored into RAM (in in HALT mode or under RESET) or into hardware
registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. The data retention time increase when the TA decreases.
3. Data based on reliability test results and monitored in production.
4. Data given only as guidelines.
139/164
ST72311R, ST72511R, ST72512R, ST72532R
12.7 EMC CHARACTERISTICS
ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-44 standard.
A device reset allows normal operations to be resumed.
Susceptibility tests are performed on a sample basis during product characterization.
12.7.1 Functional EMS
(Electro Magnetic Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■
Symbol
Parameter
Condition s
Neg 1)
Pos 1)
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-2
-1
1
V FFTB
Fast transient voltage burst limits to be apVDD=5V, TA=+25°C, fOSC=8MHz
plied through 100pF on VDD and VDD pins
conforms to IEC 1000-4-4
to induce a functional disturbance
-4
4
Unit
kV
Figure 74. EMC Recommended star network power supply connection 2)
ST72XXX
10nF 0.1µF
ST7
DIGITAL NOISE
FILTERING
VDD
VSS
VDD
POWER
SUPPLY
SOURCE
VSSA
EXTERNAL
NOISE
FILTERING
VDDA
0.1µF
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10nF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
140/164
ST72311R, ST72511R, ST72512R, ST72532R
EMC CHARACTERISTICS (Cont’d)
12.7.2 Absolute Electrical Sensitivity
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note.
12.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 75 and the following test sequences.
Machine Model Test Sequence
– CL is loaded through S1 by the HV pulse generator.
– S1 switches position from generator to ST7.
– A discharge from CL to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
– R (machine resistance), in series with S2, ensures a slow discharge of the ST7.
Human Body Model Test Sequence
– CL is loaded through S1 by the HV pulse generator.
– S1 switches position from generator to R.
– A discharge from CL through R (body resistance)
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
Symbol
Ratings
Maximum value 1) Unit
Conditions
V ESD(HBM)
Electro-static discharge voltage
(Human Body Model)
TA=+25°C
2500
V ESD(MM)
Electro-static discharge voltage
(Machine Model)
TA=+25°C
TBD
V
Figure 75. Typical Equivalent ESD Circuits
S1
CL=100pF
S1
ST7
S2
HIGH VOLTAGE
PULSE
GENERAT OR
R=10k~10MΩ
HIGH VOLTAGE
PULSE
GENERATOR
R=1500Ω
ST7
CL=200pF
HUMAN BODY MODEL
S2
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
141/164
ST72311R, ST72511R, ST72512R, ST72532R
EMC CHARACTERISTICS (Cont’d)
12.7.2.2 Static and Dynamic Latch-Up
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
■
DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 76. For
more details, refer to the AN1181 ST7
application note.
Electrical Sensitivities
Symbol
LU
DLU
Parameter
Class 1)
Conditions
Static latch-up class
TA=+25°C
TA=+85°C
Dynamic latch-up class
VDD=5.5V, fOSC=4MHz, TA=+25°C
A
A
TBD
Figure 76. Simplified Diagram of the ESD Generator for DLU
RCH=50MΩ
RD=330Ω
DISCHAR GE TIP
VDD
VSS
CS =150pF
ESD
GENERATOR 2)
HV RELAY
ST7
DISCHARGE
RETURN CONNECTION
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
142/164
ST72311R, ST72511R, ST72512R, ST72532R
EMC CHARACTERISTICS (Cont’d)
12.7.3 ESD Pin Protection Strategy
To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to
prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be protected must not receive excessive current, voltage
or heating within their structure.
An ESD network combines the different input and
output ESD protections. This network works, by allowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 77 and Figure 78 for standard
pins and in Figure 79 and Figure 80 for true open
drain pins.
Standard Pin Protection
To protect the output structure the following elements are added:
– A diode to VDD (3a) and a diode from VSS (3b)
– A protection device between VDD and VSS (4)
To protect the input structure the following elements are added:
– A resistor in series with the pad (1)
– A diode to VDD (2a) and a diode from VSS (2b)
– A protection device between VDD and VSS (4)
Figure 77. Positive Stress on a Standard Pad vs. VSS
VDD
VDD
(3a)
(2a)
(1)
OUT
(4)
IN
Main path
(3b)
Path to avoid
(2b)
VSS
VSS
Figure 78. Negative Stress on a Standard Pad vs. VDD
VDD
VDD
(3a)
(2a)
(1)
OUT
(4)
IN
Main path
(3b)
VSS
(2b)
VSS
143/164
ST72311R, ST72511R, ST72512R, ST72532R
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
diode to VDD are not implemented. An additional
local protection between the pad and VSS (5a &
5b) is implemented to completly absorb the positive ESD discharge.
Multisupply Configuration
When several types of ground (VSS, VSSA, ...) and
power supply (VDD , VDDA, ...) are available for any
reason (better noise immunity...), the structure
shown in Figure 81 is implemented to protect the
device against ESD.
Figure 79. Positive Stress on a True Open Drain Pad vs. VSS
VDD
VDD
Main path
(1)
Path to avoid
OUT
(5a)
(4)
IN
(3b)
(5b)
(2b)
VSS
VSS
Figure 80. Negative Stress on a True Open Drain Pad vs. VDD
VDD
VDD
Main path
(1)
OUT
(3b)
(4)
IN
(3b)
(2b)
(3b)
VSS
VSS
Figure 81. Multisupply Configuration
VDD
VDDA
VDDA
VSS
BACK TO BACK DIODE
BETWEEN GROUNDS
VSSA
144/164
VSSA
ST72311R, ST72511R, ST72512R, ST72532R
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ 1)
2)
VIL
Input low level voltage
V IH
Input high level voltage 2)
Vhys
Schmitt trigger voltage hysteresis 3)
Max
0.3xVDD
0.7xVDD
400
Input leakage current
V SS≤V IN≤ VDD
±1
IS
Static current consumption 4)
Floating input mode
200
RPU
Weak pull-up equivalent resistor 5)
V IN=VSS
C IO
IO pin capacitance
5
Output high to low level fall time 2)
25
tf(IO)out
tr(IO)out
C L=50pF
Output low to high level rise time 2) Between 10% and 90%
tw(IT)in
External interrupt pulse time 6)
60
240
25
1
V
mV
IL
VDD=5V
Unit
µA
kΩ
pF
ns
tCPU
Figure 82. Two typical Applications with unused I/O Pin
VDD
10kΩ
ST72XXX
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 82). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The R PU pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
not tested in production.
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
145/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.8.2 Output Driving Current
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol
VOH 2)
Conditio ns
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 84)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(see Figure 85)
Figure 83. Typical VOL at VDD=5V (standard)
Vol [V]
Ta=-40°C
Ta=25°C
1.2
Min
Max
IIO=+5mA
1.3
IIO=+2mA
0.4
IIO=+20mA
1.3
IIO=+8mA
0.4
IIO=-5mA
VDD-2.0
IIO=-2mA
VDD-0.8
Unit
V
Figure 85. Typical VDD-VOH at VDD=5V
(Vdd=5V)
1.4
VDD=5V
VOL 1)
Parameter
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 83)
Vdd-Voh [V]
(Vdd=5V)
Ta=-40°C
1.5
Ta=25°C
Ta=85°C
Ta=85°C
1
1
0.8
Ta=125°C
Ta=125°C
0.6
0.5
0.4
0.2
0
0
0
2
4
6
8
-8
-6
-4
-2
0
Iio [mA]
Iio [mA]
Figure 84. Typical VOL at VDD=5V (high-sink)
Vol [V]
(Vdd=5V)
Ta=-40°C
2
Ta=25°C
1.5
Ta=85°C
1
Ta=125°C
0.5
0
0
10
20
30
40
Iio [mA]
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH .
146/164
ST72311R, ST72511R, ST72512R, ST72532R
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Condit ions
Min
Typ 1)
Max
2)
VIL
Input low level voltage
V IH
Input high level voltage 2)
Vhys
Schmitt trigger voltage hysteresis 3)
RON
Weak pull-up equivalent resistor 4)
Unit
0.3xV DD
0.7xVDD
tw(RSTL)out Generated reset pulse duration
400
V IN= VSS
VDD=5V
mV
20
Watchdog reset source
th(RSTL)in External reset pulse hold time
V
60
kΩ
µs
1
µs
20
Figure 86. Typical Application with RESET pin 5)
VDD
VDD
VDD
ST72XXX
INTERNAL RESET CONTROL
RON
0.1µF
4.7kΩ
EXTERNAL
RESET
CIRCUIT
RESET
0.1µF
WATCHDOG RESET
LVD RESET
12.9.2 VPP Pin
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol
Min
Max
VIL
Input low level voltage 6)
Parameter
Conditio ns
VSS
0.2
V IH
Input high level voltage 6)
VDD-0.1
12.6
Unit
V
Figure 87. Two typical Applications with VPP Pin 7)
VPP
PROGRAMMING
TOOL
VPP
4.7kΩ
ST72XXX
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R ON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
not tested in production.
5. The reset network protects the device against parasitic resets, especially in a noisy environment.
6. Data based on design simulation and/or technology characteristics, not tested in production.
7. When the in-circuit programming mode is not required by the application VPP pin must be tied to VSS.
147/164
ST72311R, ST72511R, ST72512R, ST72532R
12.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating condition for VDD , fOSC , and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(outpu compare, input capture, external clock,
PWM output...).
12.10.1 Watchdog Timer
Symbol
tw(WDG)
Parameter
Watchdog time-out duration
Conditions
fCPU =8MHz
Max
Unit
12,288
Min
Typ
786,432
tCPU
1.54
98.3
ms
Max
Unit
12.10.2 8-Bit PWM-ART Auto-Reload Timer
Symbol
Parameter
tres(PWM) PWM resolution time
Condit ions
fCPU=8MHz
Min
Typ
1
tCPU
125
ns
fEXT
ART external clock frequency
0
fCPU/2
fPWM
PWM repetition rate
0
fCPU/2
ResPWM PWM resolution
VOS
PWM/DAC output step voltage
8
VDD=5V, Res=8-bits
20
MHz
bit
mV
12.10.3 16-Bit Timer
Symbol
Parameter
Condit ions
tw(ICAP)in Input capture pulse time
tres(PWM) PWM resolution time
fCPU=8MHz
Min
Typ
Max
Unit
1
tCPU
2
tCPU
250
ns
fEXT
Timer external clock frequency
0
fCPU/4
MHz
fPWM
PWM repetition rate
0
fCPU/4
MHz
16
bit
ResPWM PWM resolution
148/164
ST72311R, ST72511R, ST72512R, ST72532R
12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating condition for VDD , fOSC , and TA unless otherwise specified.
Symbol
Parameter
Conditio ns
Master
fSCK
1/tc(SCK)
fCPU=8MHz
SPI clock frequency
Slave
fCPU=8MHz
Min
Max
fCPU/128
0.0625
fCPU/4
2
0
fCPU/2
4
tr(SCK)
tf(SCK)
SPI clock rise and fall time
tsu(SS)
SS setup time
th(SS)
SS hold time
Slave
120
SCK high and low time
Master
Slave
100
90
tsu(MI)
tsu(SI)
Data input setup time
Master
Slave
100
100
th(MI)
t h(SI)
Data input hold time
Master
Slave
100
100
0
tw(SCKH)
tw(SCKL)
Unit
MHz
see I/O port pin description
Slave
ta(SO)
Data output access time
Slave
tdis(SO)
Data output disable time
Slave
tv(SO)
Data output valid time
th(SO)
Data output hold time
tv(MO)
Data output valid time
th(MO)
Data output hold time
120
ns
120
240
120
Slave (after enable edge)
0
Master (before capture edge)
0.25
tCPU
0.25
Figure 88. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
SCK INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
MISO OUTPUT
see note 2
tw(SCKH)
tw(SCKL)
MSB OUT
tsu(SI)
MOSI INPUT
tv(SO)
th(SO)
BIT6 OUT
tdis(SO)
tr(SCK)
tf(SCK)
LSB OUT
see
note 2
th(SI)
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV DD and 0.7xVDD.
149/164
ST72311R, ST72511R, ST72512R, ST72532R
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
Figure 89. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
SCK INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO OUTPUT
see
note 2
HZ
tv(SO)
th(SO)
MSB OUT
tsu(SI)
BIT6 OUT
LSB OUT
see
note 2
th(SI)
MSB IN
MOSI INPUT
tdis(SO)
tr(SCK)
tf(SCK)
BIT1 IN
LSB IN
Figure 90. SPI Master Timing Diagram 1)
SS INPUT
tc(SCK)
SCK INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tsu(MI)
MISO INPUT
MOSI OUTPUT see note 2
th(MI)
MSB IN
tv(MO)
tr(SCK)
tf(SCK)
BIT6 IN
LSB IN
th(MO)
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes:
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
150/164
ST72311R, ST72511R, ST72512R, ST72532R
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(RDI and TDO).
12.11.2 SCI - Serial Communications Interface
Subject to general operating condition for VDD , fOSC , and TA unless otherwise specified.
Conditions
Symbol
Parameter
f CPU
fTx
fRx
Accuracy
vs. Standard
~0.16%
Communication frequency
8MHz
~0.79%
12.11.3 CAN - Controller Area Network Interface
Subject to general operating condition for VDD , fOSC , and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
Symbol
tp(RX:TX)
Parameter
CAN controller propagation time
Prescaler
Standard
Baud
Rate
Unit
Conventional Mode
TR (or RR)=64, PR=13
TR (or RR)=16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 2, PR=13
TR (or RR)= 8, PR= 3
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
Extended Mode
ETPR (or ERPR) = 13
38400 ~38461.54
Extended Mode
ETPR (or ERPR) = 35
14400 ~14285.71
Hz
the input/output alternate function characteristics
(CANTX and CANRX).
Condit ions
Min
Typ
Max
Unit
60
ns
151/164
ST72311R, ST72511R, ST72512R, ST72532R
12.12 8-BIT ADC CHARACTERISTICS
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol
fADC
VAIN
Parameter
Conditions
Min
Typ 1)
ADC clock frequency
Conversion range voltage
2)
VSSA
Max
Unit
4
MHz
VDDA
3)
V
RAIN
External input resistor
RADC
Internal input resistor
1.5
kΩ
CADC
Internal sample and hold capacitor
Stabilization time after ADC enable
6
0 4)
pF
tSTAB
tLOAD
Sample capacitor loading time
1
4
µs
1/fADC
tCONV
Hold conversion time
2.250
9
µs
1/fADC
15
fCPU=8MHz, fADC=4MHz
kΩ
µs
Figure 91. Typical Application with ADC
VDD
SAMPLING SWITCH
VT
0.6V
RAIN
AINx
VAIN
CIO
0.1µF
VDD
1kΩ
VT
0.6V
IL
±1µA
RADC
CADC
0.1µF
VDDA
0.1µF
VSSA
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guidelines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.
152/164
ST72311R, ST72511R, ST72512R, ST72532R
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with VDD=5.0V
Symbol
Parameter
|E T|
Total unadjusted error 2)
EO
Offset error 2)
Conditions
Min
Max
Unit
1.5
2)
1)
-1
1
-0.5
0.5
EG
Gain Error
|ED|
Differential linearity error 2)
1
|EL|
Integral linearity error 2)
1
fCPU=8MHz, fADC =4MHz
LSB
Figure 92. ADC Accuracy Characteristics
Digital Result ADCDR
EG
255
254
1LS B
253
I DE AL
V
–V
DDA
S SA
= ---------------------------------------256
(2)
ET
(3)
7
(1)
6
5
EO
4
EL
3
ED
2
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET =Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL =Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
1
0
VSSA
Vin (LSBIDEAL)
1
2
3
4
5
6
7
253 254 255 256
VDDA
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
2. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.
153/164
ST72311R, ST72511R, ST72512R, ST72532R
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 93. 64-Pin Thin Quad Flat Package
Dim
mm
Min
inches
Typ Max
A
Typ Max
1.60
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35 1.40 1.45 0.053 0.055 0.057
B
0.30 0.37 0.45 0.012 0.015 0.018
C
0.09
0.20 0.004
0.008
D
16.00
0.630
D1
14.00
0.551
D3
12.00
0.472
E
16.00
0.630
E1
14.00
0.551
E3
12.00
0.472
e
0.80
K
L
L1
Min
0°
0.031
3.5°
7°
0.45 0.60 0.75 0.018 0.024 0.030
L1
1.00
L
0.039
Number of Pins
N
64
ND
16
NE
16
K
Figure 94. 64-Pin Epoxy Thin Quad Flat Package
∅P
Dim
mm
Min
Typ
A
L1
e
A1
L
∅n
G
B
Min
Typ
Max
2.40
0.095
0.60
0.024
B
0.25 0.38 0.50 0.010 0.015 0.020
E
15.80 16.00 16.20 0.622 0.630 0.638
E1
12.20 12.35 12.50 0.480 0.486 0.492
e
0.80
G
13.10
L
0.50
L1
1.10
0.031
0.515
0.020
0.043
∅n
0.35
0.013
∅P
1.10
0.043
A1
Number of Pins
A
ETQFP 64
inches
Max
N
64 (4x16)
Note: “ QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES
(ESO/EDIL/EQFP) IS NOT AUTHORIZED It is expressly specified that qualification and/or volume production of devices
using the package E.... in any applications is not authorized. Usage in any application is strictly restricted to development
purpose. Similar devices are available in plastic package mechanically compatible to the epoxy package for qualification
and volume production.”
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ST72311R, ST72511R, ST72512R, ST72532R
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
RthJA
Package thermal resistance (junction to ambient)
TQFP64
60
°C/W
Power dissipation 1)
500
mW
150
°C
PD
TJmax
Maximum junction temperature
2)
Notes:
1. The power dissipation is obtained from the formula P D=PINT+PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = T A + PD x RthJA.
155/164
ST72311R, ST72511R, ST72512R, ST72532R
13.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines.
Figure 95. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
150
SOLDERING
PHASE
80°C
Temp. [°C]
100
50
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
PREHEATING
PHASE
Time [sec]
0
20
40
60
80
100
120
140
160
Figure 96. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
90 sec at 125°C
150 sec above 183°C
Temp. [°C]
100
50
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
Recommended glue for SMD plastic packages dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
156/164
ST72311R, ST72511R, ST72512R, ST72532R
13.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL
To solder the TQFP64 device directly on the application board, or to solder a socket for connecting
the emulator probe, the application board should
provide the footprint described in Figure 97. This
footprint allows both configurations:
■ Direct TQFP64 soldering
■
YAMAICHI IC149-064-008-S5 socket soldering
to plug either the emulator probe or an adaptor
board with an TQFP64 clamshell socket.
This socket is not compatible with TQFP64
package.
Figure 97. TQFP64 Device And Emulator Probe Compatible Footprint
SK
E
E1
E3
mm
inches
Dim
Min
e
Typ Max
Min Typ Max
B
0.35 0.45 0.50 0.014 0.018 0.020
E
20.80
E1
0.819
14.00
0.551
E1
E3
SK
E
E3 11.90 12.00 12.10 0.468 0.472 0.476
B
e
0.75 0.80 0.85 0.029 0.031 0.033
SOCKET
SK*
DETAIL
26
1.023
Number of Pins
N
64 (4x16)
* SK: Plastic socket overall dimensions.
Table 27. Suggested List of TQFP64 Socket Types
Package / Probe
TQFP64
EMU PROBE
Adaptor / Socket Reference
Socket type
ENPLAS
OTQ-64-0.8-02
YAMAICHI
IC51-0644-1240.KS-14584
Open Top
Clamshell
YAMAICHI
IC149-064-008-S5
SMC
157/164
ST72311R, ST72511R, ST72512R, ST72532R
14 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (OTP) as well as in factory
coded versions (ROM). OTP devices are shipped
to customers with a default content (FFh), while
ROM factory coded parts contain the code supplied by the customer. This implies that OTP devices have to be configured by the customer using
the Option Bytes while the ROM devices are factory-configured.
14.1 OPTION BYTES
The option byte allows the hardware configuration
of the microcontroller to be selected.
The option byte has no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 programming tool). The default content of the OTP is fixed
to FFh. This means that all the options have “1” as
their default value.
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).
USER OPTION BYTE
7
0
FMP
Default
Value
1
1
1
1
USER OPTION BYTE
Bit 7:6,4 = Reserved, must always be 1.
Bit 5 = Reserved, must always be 0.
Bit 3 = FMP Full memory protection
This option bit allows the protection of the software
contents against piracy (program or data). When
the protection is activated, read-out of the EPROM
or data EEPROM contents is prevented by hardware.
0: Read-out protection enabled
1: Read-out protection disabled
Bit 2 = Reserved, must always be 1
158/164
1
1
WDG HALT
WDG SW
1
1
Bit 1 = WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
ST72311R, ST72511R, ST72512R, ST72532R
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the S19 hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on contractual points.
Figure 98. ROM Factory Coded Device Types
TEMP.
DEVICE PACKAGE RANGE X
/ XXX
Code name (defined by STMicroelectronics)
= LVD disabled
S= LVD enabled
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105 °C
3 = automotive -40 to +125 °C
T= TQFP
ST72311R6, ST72311R7, ST72311R9
ST72511R6, ST72511R7, ST72511R9
ST72512R4
ST72532R4
Figure 99. OTP User Programmable Device Types
TEMP.
DEVICE PACKAGE RANGE X
= LVD disabled
S= LVD enabled
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105 °C
3 = automotive -40 to +125 °C
T= TQFP
ST72T311R6, ST72T311R7, ST72T311R9
ST72T511R6, ST72T511R7, ST72T511R9
ST72T512R4,
ST72T532R4
159/164
ST72311R, ST72511R, ST72512R, ST72532R
TRANSFER OF CUSTOMER CODE (Cont’d)
MICROCONTROLLER OPTION LIST
Customer
Address
. . ... ... . .. .. . .. .. .. . .. ... . ..
. . ... ... . .. .. . .. .. .. . .. ... . ..
. . ... ... . .. .. . .. .. .. . .. ... . ..
Contact
. . ... ... . .. .. . .. .. .. . .. ... . ..
Phone N° . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72311R9
[ ] ST72311R7
[ ] ST72311R6
[ ] ST72511R9
[ ] ST72511R7
[ ] ST72511R6
Package:
[ ] TQFP64
Temperature Range:
[]
0°C to + 70°C [ ] - 40°C to + 85°C
[ ] - 40°C to + 105°C [ ] - 40°C to + 125°C
Oscillator Source Selection: [ ] Quartz Crystal/Ceramic resonator
[ ] External Clock
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
Watchdog Reset on Halt
[ ] Disabled
[ ] Enabled
Readout Protection:
[ ] Disabled
[ ] Enabled
LVD Reset
[ ] Disabled
Comments :
Supply Operating Range in the application:
Notes
. . ... ... . .. .. . .. .. .. . .. ... . ..
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date
. . ... ... . .. .. . .. .. .. . .. ... . ..
160/164
[ ] Enabled:
[ ] ST72512R4
[ ] ST72532R4
ST72311R, ST72511R, ST72512R, ST72532R
14.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
the ST7 from third party manufacturers can be oband software development tools for the ST7 microtain from the STMicroelectronics Internet site ➟
controller family. Full details of tools available for
http//st7.st.com.
Third Party Tools
■ ACTUM
■ HIWARE
■ BP
■ ISYSTEM
■ COSMIC
■ KANDA
■ CMX
■ LEAP
■ DATA I/O
Tools from these manufacturers include C compliers, emulators and gang programmers.
■ HITEX
STMicroelectronics Tools
Four types of development tool are offered by ST, all of which connect to a PC via a parallel (LPT) port:
In-Circuit Emulation
Programming Capability1)
Software Included
ST7 CD ROM with:
ST7 Development Kit
Yes. (Same features as
HDS2 emulator but no trace/
logic analyzer)
ST7 HDS2 Emulator
Yes, powerful emulation features including trace/ logic an- No
alyzer
ST7 Programming
Board
No
Yes (DIP packages only)
Yes (All packages)
– ST7 Assembly toolchain
– WGDB7 powerful Source Level
Debugger for Win 3.1, Win 95
and NT)
– C compiler demo versions
– ST Realizer for Win 3.1 and Win
95.
– Windows Programming Tools
for Win 3.1, Win 95 and NT
Note:
1. In Situ Programming (ISP) interface for FLASH devices.
Table 28. STMicroelectronics Development Tools
Supported Products
Development Kit
HDS2 Emulator
ST7MDT2-DVP2
ST7MDT2-EMU2B
ST72311R6, ST72311R7, ST72311R9
ST72511R6, ST72511R7, ST72511R9
ST72512R4
ST72532R4
Programming Board
ST7MDT2-EPB2/EU
ST7MDT2-EPB2/US
ST7MDT2-EPB2/UK
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ST72311R, ST72511R, ST72512R, ST72532R
15 ST7 GENERIC APPLICATION NOTE
Identification
Description
PROGRAMMING AND TOOLS
AN912
A simple guide to development tools
AN985
Executing code in ST7 RAM
AN986
Using the ST7 indirect addressing mode
AN987
ST7 in-circuit programming
AN988
Starting with ST7 assembly tool chain
AN989
Starting with ST7 Hiware C
AN1039
ST7 math utility routines
AN1064
Writing optimized hiware C language for ST7
EXAMPLE DRIVERS
AN969
ST7 SCI communication between the ST7 and a PC
AN970
ST7 SPI communication between the ST7 and E PROM
AN971
ST7 I C communication between the ST7 and E PROM
AN972
ST7 software SPI master communication
AN973
SCI software communication with a PC using ST72251 16-bit timer
AN974
Real time clock with the ST7 timer output compare
AN976
Driving a buzzer using the ST7 PWM function
AN979
Driving an analog keyboard with the ST7 ADC
AN980
ST7 keypad decoding techniques, implementing wake-up on keystroke
AN1017
Using the ST7 USB microcontroller
AN1041
Using ST7 PWM signal to generate analog output (sinusoid)
AN1042
ST7 routine for I C slave mode management
AN1044
Multiple interrupt sources management for ST7 MCUs
AN1045
ST7 software implementation of I C bus master
AN1047
Managing reception errors with the ST7 SCI peripheral
AN1048
ST7 software LCD driver
AN1048
ST7 timer PWM duty cycle switch for true 0% or 100% duty cycle
PRODUCT OPTIMIZATION
AN982
Using ceramic resonators with the ST7
AN1014
How to minimize the ST7 power consumption
AN1070
ST7 checksum selfchecking capability
PRODUCT EVALUATION
AN910
ST7 and st9 performance benchmarking
AN990
ST7 benefits versus industry standard
APPLICATIONS EXAMPLES
AN1086
ST7 / ST10U435 CAN-Do solutions for car multiplexing
TO GET MORE INFORMATION
To get the updated information on that product please refer to STMicroelectronics web server.
➟ http://st7.st.com/
162/164
ST72311R, ST72511R, ST72512R, ST72532R
16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
2.1
Main changes
- Section 8.4 ”LOW POWER MODES” on page 42 and Section 8.5 ”INTERRUPTS” on page
42 added in Section 8 ”I/O PORTS” on page 38.
- Section 10.2.5 ”Low Power Modes” on page 53 and Section 10.2.6 ”Interrupts” on page 53
added in Section 10.2 ”MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)” on page 52.
- ESD absolute maximum rating modified in Section 12.2 on page 132.
- EMC characteristics corrected in Section 12.7 on page 140.
Date
Feb-00
163/164
ST72311R, ST72511R, ST72512R, ST72532R
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved.
Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http:// www.st.com
164/164