STMICROELECTRONICS STV0974E

STV0974
Mobile Imaging DSP
Features
Description
■ Supports VS6552 - 640 x 480 (VGA) color
CMOS image sensor
The STV0974 is a low power digital image
processor designed for the VS6552 color VGA
image sensor. The STV0974 uses advanced image
processing techniques to deliver high quality VGA
images at up to 30 frames per second
(frame/s). The sensor data received via the low EMI
sensor interface is processed in real time: this
includes pixel defect correction, color interpolation,
image sharpness enhancement, selective noise
filtering, cropping and scaling, allowing digital zoom
for ViewFinder or MMS applications. Finally the
image can be JPEG-compressed in real-time. The
STV0974 also performs sensor housekeeping
functions such as automatic exposure and white
balance controls.
■ Supports VisionLink low EMI link to image
sensor
■ Specialized video processor for noise/defect
filtering, color reconstruction, sharpness
enhancement and radial corrections
■ Programmable gamma correction for LCD
support
■ Programmable cropping, down-sizing by 1.5,
2, 2.5, 3, 4, 5 and 6, MMS (Multi Media
Messaging Service) digital zoom
■ JPEG compression, with programmable
target file size
■ M-JPEG operation at up to 30 frame/s at VGA
resolution
Applications
■ Mobile phone embedded camera system
■ Programmable pixel output format including
ITU-R 656 modes, RGB viewfinder modes and
JPEG baseline
■ PDA embedded camera or accessory camera
■ Flashgun control
Technical Specifications
■ Wireless security camera
■ Flexible host interface:
●
8-bit data /Hsync /Vsync video output interface
and I²C camera control interface
●
8-bit microprocessor interface with 2 Kbyte
video FIFO for JPEG data, 10 Kbyte for nonJPEG data, interrupt and DMA requests
Sensor
640 x 480 color CMOS
(VS6552)
Frame rate (frame/s)
up to 30
Power supply
1.8 +/- 0.1 V
Power requirements
■ Multi-mode exposure control and color
balance
110 mW active
< 30 µW standby
Package dimensions
6 mm x 6 mm x 1.2 mm
■ 30 µW ultra low-power standby
Temperature range
[ -25; +70 ] °C
■ 6 x 6 mm TFBGA low-footprint & lead-free
package
Ordering Information
Ordering code
Package
STV0974/TR
TFBGA SnPb balls
STV0974E/TR
TFBGA
AFOP lead-free balls
Rev. 3
November 2004
1/69
STV0974
Contents
Chapter 1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1
Viewfinder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Still features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3
Live features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chapter 3
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chapter 4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2
Sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3
Video processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4
Video compression (VC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6
Video output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.7
Power management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9
Camera control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.10
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.5
AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.1
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.2
Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 7
PCB layout guide lines for the STV0974 and VS6552 . . . . . . . . . . . . . . . . . . . .64
2/69
STV0974
Chapter 8
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Chapter 9
Evaluation kit and demonstration boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
References
3/69
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
STV0974
1
Overview
Overview
The STV0974 is a mobile imaging digital signal processor which, when used with VS6552 CMOS
color VGA image sensor from STMicroelectronics, performs all the required data processing to
deliver good quality Viewfinder, still and live color images. The STV0974 performs high quality color
processing on images, achieving JPEG compression if requested and transfers them to a
baseband through one of the available interfaces.
Data is transferred from sensor to STV0974 through Low Electromagnetic Interference (EMI)
interface, using the sensor data transfer protocol over LVDS.
Data is transferred from STV0974 to Baseband
1.1
●
through the video output interface. In video mode, the processor streams video data in a format
which closely follows the data format specified in the ITU-R656 standard.
●
through the microprocessor Interface. In microprocessor mode, the video data is stored in a
small FIFO before is it pulled out of the asynchronous microprocessor interface by the host
system (with DMA support).
Viewfinder mode
When connected to microprocessor interface or video output interface, the STV0974 can process
Viewfinder image up to 30 frame/s.
1.2
Still features
When requested by the baseband, the STV0974 captures bayer data from the sensor. Data is then
color processed, down-scaled and/or compressed and sent through video output or microprocessor
interface. In still mode, the first image produced has a guaranteed good exposure and color
balance for single shot capture.
1.3
Live features
When connected to microprocessor interface or video output interface, the STV0974 can process
live video up to 30 frame/s and eventually proceed to down-scaling and compression with on-chip
Motion JPEG. Live mode is intended for capture of video sequences.
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Functional block diagram
2
STV0974
Functional block diagram
Figure 1: Functional block diagram
POR RST CLK PDN
Clock &
Power
management
SCL
RAM - ROM
Microprocessor
I2C
slave
SDA
Internal bus
PCLKN
PDATAP
PDATAN
MSCL
Sensor interface
PCLKP
VisionLink
serial
receiver
I2C master
MSDA
STV0974
5/61
VC
VP
Parallel
interface
and
FIFO
Video
output
interface
Mux
DIO[0:13]
STV0974
3
Signal description
Signal description
Table 1: STV0974 signal description
Pin name
Type
Description
Power supplies
VDD
PWR
Positive power supply
VCORE
PWR
Decoupling for internal core power supply
VDDPOR
PWR
Power on reset VDD supply 1.8 V
VSS
PWR
Digital ground
Sensor interface
PDATAP, PDATAN
subLVDS In
Sensor data +, sensor data -, with internal 100 Ω termination resistor
PCLKP, PCLKN
subLVDS In
Sensor clock +, sensor clock -, with internal 100 Ω termination resistor
MSDA
I/O
Sensor I2C data
MSCL
I/O
Sensor I2C clock
POR
O
Power on reset output
RST
I
Reset input
CLK
I
System clock
PDN
I
Power down
Host interface
DIO[0:11]DIO[13]
I/O
Host interface configurable I/O, see Table 2
DIO[12]
I/O
Flash Strobe Output (FSO)
SDA
I/O
Host I2C data
SCL
I/O
Host I2C clock
Test interface (ST internal use)
TMS
I
Test mode
TCK
I
Test clock
TDI
I
Test data in
TDO
O
Test data out
Not connected
NC
Not connected
Table 2: Host interface pins - output modes
Pin name
Microprocessor interface
Video port
DATA[0:7]
DATA[0:7]
RS
HSYNC
DIO[9]
CSN
VSYNC
DIO[10]
WRN
HCLK
DIO[11]
RDN
NC
DIO[12]
DRQ
FSOa
DIO[13]
IRQ
NC
DIO[0:7]
DIO[8]
a. Flash Strobe Output
6/61
Functional description
4
Functional description
4.1
Overview
STV0974
The processor includes a chain of dedicated video data processing blocks controlled by a
microprocessor. The processing blocks perform the main video pipe processing while the
microprocessor manages the interactions between the sensor, the functional blocks and the host.
The host controls and monitors the STV0974 via a set of read/write registers accessible via the I2C
interface for the streaming video mode and via the asychronous microprocessor interface for the
microprocessor mode.
In video mode, the processor streams video data in a format which closely follows the data format
specified in the ITU-R656 standard.
In microprocessor mode, the video data is stored in a small FIFO before is it pulled out of the
asynchronous microprocessor interface by the host system (with DMA support).
4.1.1
Video pipe block description
Please refer to the block diagram (Figure 1).
Sensor interface This block decodes the incoming serial data stream from the sensor (raw bayer
data) and converts it into a parallel form for the processing chain.
Video processor The video processor converts the raw bayer data from the sensor to RGB or
YUV processed data by applying a number of filters to the data then scaling and converting the
data into either one of the RGB modes or into YUV mode.
Video JPEG compressor The video compressor converts the processed data from the video
processor and converts the data into JPEG format. The compression ratio applied to the image can
be controlled by the microprocessor.
Streaming video output port In streaming video mode the data from either the video processor
or the video compressor is enclosed in a format which closely follows the data format specified in
the ITU-R656 standard.
Microprocessor interface In microprocessor interface mode, the data from the video processor or
video compressor is stored in a FIFO. The interface informs the system via an IRQ or a DRQ that
the FIFO is filling up. The system then has to pull some of the data from the STV0974 via the
microprocessor interface.
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STV0974
4.1.2
Functional description
Control
Register map The STV0974 is controlled via a register map that is maintained by the STV0974
microprocessor. Each register in the map has an address and contains either read or read/write
data. The read only registers detail the current state of the STV0974. Read/write registers can be
written to in order to modify the default behavior of the STV0974. The map is accessed via I2C or
via the microprocessor interface.
Micro processor interface In microprocessor interface mode the STV0974 register map can be
accessed by writing the address of the register to the port and then reading or writing the register
value.
Video output interface In streaming video mode, the STV0974 register map can be accessed via
the I2C port on the STV0974. The STV0974 is addressed by supplying the device address, register
address and value to be written or read.
Microprocessor The microprocessor maintains the system interface via the register map. Any
changes in system state are reflected in this map by the microprocessor and any changes
commanded by the host system via this interface are then applied by the microprocessor.
When the system is commanded to change state, the microprocessor configures the functional
blocks from the STV0974 and the sensor into the requested mode. The register map is updated
accordingly to reflect the new state of the hardware.
The microprocessor monitors statistics gathered from the incoming image data and responds to
changes in images. It adapts the functional block settings to correct for shifts in environmental
conditions such as light level and illumination color temperature. The microcontroller will optimize
these settings to provide the best quality image on all occasions.
4.1.3
Other functional blocks
Power management The hardware state of the STV0974 can be controlled by the power down pin
(PDN). Upon the application of power to the STV0974 and PDN release, the STV0974 power-onreset cell issues a timed reset pulse and then releases the STV0974 into its boot state.
The power-on-reset cell which output is the POR signal, is externally connected to the RST pin.
Clocks In sleep mode, the STV0974 clock is derived from the clock signal applied to the CLK pin.
In all other modes, the STV0974 clock is derived from the high speed clock received from the
sensor.
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Functional description
4.2
Sensor interface
4.2.1
Features
4.2.2
●
Low electromagnetic interference (EMI) interface with CMOS image sensors
●
High speed serial receiver, with data and clock inputs
●
Up to 120 Mbit/s operation using very low voltage differential signaling (vLVDS)
●
VisionLink transfer protocol
●
I²C compliant master controller, 1.8 V interface, up to 400 kHz operation
STV0974
Description
The STV0974 sensor interface is dedicated to the VS6552 image sensor that uses the VisionLink
data transfer protocol over vLVDS. This includes:
9/61
●
An I²C master controller supporting 1.8 V interface and 400 kHz operation. The I²C master port
signals are MSDA and MSCL that require external pull-up resistors. Internally, the I²C master is
a peripheral of the microprocessor control unit.
●
Two vLVDS receivers for sensor data and clock signals, PDATA and PCLK differential pairs
respectively. Each receiver accepts 1.8 V LVDS signals
●
A VisionLink data synchronization and extraction unit, which extracts image timing references,
active video and sensor status information. The extracted video stream in raw Bayer format
along with active video strobes are connected to the video processing unit. The sensor status
information is presented to the microprocessor control unit.
STV0974
Functional description
4.3
Video processing unit
4.3.1
Features
4.3.2
●
Low-power dedicated hardware video processing unit, pipeline operation up to VGA resolution
30 Hz
●
Image sensor correction stage including pixel defect correction and fixed pattern noise (FPN)
cancellation
●
Color interpolation stage with anti-aliasing and color matrix compensation
●
Optical system compensation stage including anti vignetting and sharpness enhancement
●
Noise reduction filter
●
Programmable gamma and s-curve gamma for LCD support
●
Full frame statistics gathering for exposure and color balance controls
●
Programmable output image size (downscale by 1.5, 2, 2.5, 3, 4, 5 and 6)
Overview
Figure 2: Video processing unit
FPN
Anti-vignetting
Input
Color interpolation
Color matrix
Gamma
Defect
correction
To video processing unit
and
video compression unit
Scaler
Noise
reduction
Statistics
gathering
Sharpness
enhancement
Microprocessor
control unit
Fixed Pattern Noise (FPN) cancellation The FPN cancellation algorithm removes any column
variability over the video area.
Statistics gathering Image statistics are gathered on the full resolution input image and
forwarded to the camera control unit for exposure and color balance control loops.
Anti vignetting A radial gain is applied to the image luminance to compensate for possible
luminance loss in the corners of the image due to an imperfect lens system.
Defect correction The defect correction algorithm can detect and correct any defective pixels in a
sensor array.
Noise reduction filter The noise reduction filter is based on an adaptive algorithm. This algorithm
performs filtering but does not affect image areas including significant information.
Color interpolation Each pixel RGB components are calculated by interpolation of the incoming
Bayer pattern.
10/61
Functional description
STV0974
Color matrix Each pixel (RGB vector) is multiplied by a color matrix to adjust color balance.
Viewfinder and live settings are independent to allow for optimization of both LCD display and
capture for later viewing (i.e. on a PC).
Sharpness enhancement A sharpening two-dimensional mask is applied to Green only and from
interpolation. The resulting data is added (with a gain factor) to the matrix RGB data.
Downscaler The downscaler unit extracts a rectangular region of interest and resizes the image by
resampling video data. Standard image size such as CIF, QVGA and QCIF are available as well as
a fully programmable custom size:
Table 3: Standard image size, VGA input
Format
Image size
Cropping
Scaling
Comments
VGA
640 x 480
None
None
CIF
352 x 288
528 x 432
/ 1.5
QVGA
320 x 240
None
/2
QCIF
176 x 144
528 x 432
/3
QQVGA
160 x 120
None
/4
SubQCIF
128 x 96
None
/5
QQCIF
88 x 72
528 x 432
/6
82.5% of input image used, centered
Custom
max VGA
Any
Any
See below
82.5% of input image used, centered
82.5% of input image used, centered
When custom size is selected, the crop and scale parameters are subject to the following
constraints to ensure proper operation:
●
Output image size must be in 8 x 8 pixels increments
●
Scaling factor can be any value giving an input image size within input limits
Gamma correction A non-linear gain is applied to each pixel’s RGB components to compensate
for the display’s non-linearity. A standard curve is available for image capture for later viewing on a
PC and an S-curve is available for LCD display.
Coder The coder unit converts the internal RGB video stream to a user selectable output video
format. It is based on a YUV digital video encoder with embedded synchronization codes,
compliant with [1], extended with the support of RGB formats for viewfinder usage, as shown in
Table 4.
11/61
STV0974
Functional description
Table 4: Output video formats
Name
Format
Description
UYVY
Y7Y6Y5Y4Y3Y2Y1Y0 U7U6U5U4U3U2U1U0
Y7Y6Y5Y4Y3Y2Y1Y0 V7V6V5V4V3V2V1V0
YUV (or YCBCR) 4:2:2 format as per [1]
RGB565
R4R3R2R1R0G5G4G3 G2G1G0B4B3B2B1B0
16-bit RGB format for direct viewfinder on 64 K color
LCDs.
RGB444
03020100R3R2R1R0 G3G2G1G0B3B2B1B0
16-bit RGB format for direct viewfinder on 4096 color
LCDs. Uses 4 bit per RGB component, the four MSB’s are
zero padded.
RGB332
R2R1R0G2G1G0B1B0
8-bit RGB format for low bit rate viewfinder usage.
Byte ordering assumes a little endian memory system, i.e. in 16-bit formats, the least significant
byte is sent first. For example, the UYVY format produces the sequence U Y0 V Y1... as per [1].
Note:
Nevertheless various options are available to suit memory system requirements:
●
Byte ordering can be changed to big endian
●
In YUV formats, the U and V components can be swapped
●
In RGB formats, the R and B components can be swapped
YUV format processing The RGB pixel is converted to YUV coordinates according to ITU-R
BT601 specification. The YUV coordinates are then rounded and clipped for an 8-bit
representation. To produce a 4:2:2 digital component video, U and V components are filtered and
down sampled by a factor of 2, coincident with Y sampling time.
RGB format processing Dithering: In order to avoid contouring effects on low color depth
displays, the RGB components are dithered prior to truncation to the required number of bits.
Framing: The output frame is produced by performing the following steps:
1 Blanking code insertion: During video blanking intervals, blanking codes are inserted in the
output stream. The default blanking code is the 16-bit pattern 0x1080, corresponding to Y =
0x10 and U/V = 0x80 as per [1].
2 Synchronization pattern detection and correction: The coder performs detection of various
synchronization patterns and applies a correction according to the current output format.
3 Video Timing Reference Code Insertion: A 4-byte sequence is inserted at the beginning and
the end of each digital video line to delineate lines and frames in the video stream. The
sequence is defined in [1] as FF 00 00 XY, where the XY byte is defined by:
Table 5: XY bits definition
Bit
Symbol
Definition
7 (msb)
1
Always 1.
6
F
Even / Odd Field. To maintain compatibility with[1], F is alternatively 0 or 1.
5
V
V = 1 during field blanking, 0 otherwise.
4
H
H = 1 during line blanking, 0 otherwise.
3
P3
Protection bit: P3 = V xor H
2
P2
Protection bit: P2 = F xor H
1
P1
Protection bit: P1 = V xor V
0 (lsb)
P0
Protection bit: P0 = F xor V xor H
SAV (Start of Active Video) is defined as the 4-byte sequence where H = 0.
EAV (End of Active Video) is defined as the 4-byte sequence where H = 1.
12/61
Functional description
4.4
STV0974
Video compression (VC)
Real time video compression permits a frame rate of 30 frame/s in any mode at VGA.
The JPEG compression engine is a standard baseline sequential JPEG encoder [2].
The compression ratio can be modified by applying a multiplication factor on the quantization table.
The quantization table can be scaled from a factor of 1/8 to a factor of 8.
The STV0974 video compression block includes a baseline DCT JPEG encoder compliant with
ISO DIS 10918-1.
The JPEG encoder has the following characteristics:
●
baseline sequential DCT based encoder
●
YUV 422 encoding only
●
up to VGA image size
●
scalable quantization table
●
standard quantization table
●
standard Huffman coder
The encoder top level block diagram is presented in Figure 3.
Figure 3: Encoder top level block diagram
Raster
Discrete
to block
Cosine
converter
transform
ZigZag
transform
Entropy
Quantize
coder
The input data is a YUV 422 8-bit data stream in raster order. The output data is a baseline JPEG
data stream.
13/61
STV0974
4.4.1
Functional description
Raster to block converter
This block transforms the raster scan ordered data into block based ordered data. This data
ordering is compliant with ISO DIS 10918-1 Annex A - Section A.2.
Figure 4: Data sequence at Raster to block input
pixel 1
line 1
line m
pixel n
Y
Y
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
Y
Y
Y
Y
Y
Y
U
U
U
U
U
U
Y
Y
Y
Y
Y
Y
V
V
V
V
V
V
The sequence of the input data stream is the following: line 1 from left to right up to pixel n, then line
2 from left to right......up to line m, pixel n.
The output data stream sequence is block based. The image is segmented into MCU (minimum
coded units) as illustrated in Figure 5.
Figure 5: MCU data order
pixel 1
pixel n
line 1
16 pixels
8 pixels
MCU(1,1)
MCU(2,1)
MCU (n/16 -1,1) MCU (n/16,1)
MCU(1,n/8)
MCU(2,n/8)
MCU(n/16 -1,n/8) MCU (n/16,n/8)
line n
14/61
Functional description
STV0974
The MCU sequence order is top left to top right and top to bottom.
Figure 6 shows the MCU structure made of 4 blocks: 2 blocks of 8x8 Y component, 1 block of 8x8 U
component and one block of 8x8 V component. The series of blocks must be processed according
to this order.
Figure 6: Structure of each MCU
MCU
Y
BlockY1
Y
U
BlockY2
BlockU
V
BlockV
Each block is composed of 8x8 components. Figure 7 presents the structure of BlockY1, as an
example.
Figure 7: Structure of block Y1
BlockY1
Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y
8
Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y
8
The data sequence inside each block is left to right and top to bottom.
To summarize, at the output of Raster to Block converter, the data order is the following:
Y data of blockY1 of first MCU (64 data from left to right, then top to bottom)
Y data of blockY2 of first MCU (64 data from left to right, then top to bottom)
U data of blockU of first MCU (64 data from left to right, then top to bottom)
V data of blockV of first MCU (64 data from left to right, then top to bottom)
Y data of blockY1 of second MCU (64 data from left to right, then top to bottom)
Y data of blockY2 of second MCU (64 data from left to right, then top to bottom)
U data of blockU of second MCU (64 data from left to right, then top to bottom)
V data of blockV of second MCU (64 data from left to right, then top to bottom)
... up to last image MCU.
15/61
STV0974
4.4.2
Functional description
Discrete Cosine Transform
This block performs a Discrete Cosine Transform on the incoming data stream. It is compliant with
ISO DIS 10918-1 Annex A - Section A.3.
The block processes each 8x8 input block to transform them into 8x8 DCT coefficients. The
calculation of the DCT coefficients is done by the formula:
2
F ( u, v ) = ---- ×
N
7
7
∑
∑
(2x + 1)uπ
( 2 y + 1 )v π
C ( u ) C ( v ) f ( x, y ) cos ---------------------------- cos ---------------------------16
16
x = 0y = 0
with
1
C ( u ) ,C ( v ) = ------2
∀( u, v ) = 0
C ( u ) ,C ( v ) = 1
4.4.3
∀( u, v ) ¼ 0
Zigzag transform
This block is in charge of setting the DCT coefficients in a sequence that corresponds to an
increasing spacial frequency of the cosine function. It is compliant with ISO DIS 10918-1 Annex A Section A.3.6.
Figure 8: ZigZag block sequence re-ordering
1 2
3
4
5
6
7
8
1
2
6
9 10 11 12 13 14 15 16
3
5
8 14 17 27 30 43
7 15 16 28 29
17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32
4 9 13 18 26 31 42 44
10 12 19 25 32 41 45 54
33 34 35 36 37 38 39 40
11 20 24 33 40 46 53 55
41 42 43 44 45 46 47 48
21 23 34 39 47 52 56 61
49 50 51 52 53 54 55 56
57 58 59 60 61 62 63 64
22 35 38 48 51 57 60 62
36 37 49 50 58 59 63 64
Input data sequence
Output data sequence
16/61
Functional description
4.4.4
STV0974
Quantization block
This block applies a uniform quantizer on all DCT coefficients, in ZigZag sequence. It is compliant
with ISO DIS 10918-1 Annex A - Section A.3.4.
The quantizer step size for each DCT coefficient Suv is the value of the corresponding element Q’uv
from the quantization table Q’.
Suv
Squv = round ⎛⎝ ------------⎞⎠
Q' uv
Where uv is the index of the zigzag coefficient.
Table Q’ is a scaled quantization table calculated for table Q as follows:
Squeeze
Q' = ------------------------- × Q
32
where Squeeze is a parameter value.
Table Q is represented in Figure 9, as described in ISO DIS 10918-1 Annex K.
Figure 9: Luminance and chrominance quantization tables
16
12
14
Q = 14
18
24
49
72
11
12
13
17
22
35
64
92
10
14
16
22
37
55
78
95
16
19
24
29
56
64
87
98
24
26
40
51
68
81
103
112
40
58
57
87
109
104
121
100
51
60
69
80
103
113
120
103
17
18
24
Q = 47
99
99
99
99
61
55
56
62
77
92
101
99
Quantization table for Y blocks
18
21
26
66
99
99
99
99
24
26
56
99
99
99
99
99
47
66
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
Quantization table for U and V blocks
Table 6 shows an example of VGA image when different squeeze values are applied by the user.
Table 6: VGA image size - YUV 4: 2: 2 - Example of image size after JPEG compression
Squeeze
a
Squeeze
quantization table
factor (Squeeze/8)
File size (Kbyte)
Bit per pixel
a. No compression
17/61
614
2
4
8
10
20
30
50
67
0.12
0.25
0.5
0.62
1.25
1.87
3.12
4.19
~80
~51
~32
~27
~21
~12
~9
~9
2.13
1.39
0.85
0.72
0.56
0.32
0.24
0.24
STV0974
4.4.5
Functional description
Entropy coder
This block performs the following functions:
●
insertion of JPEG Markers
●
runlength encoding
●
Huffman encoding
4.4.5.1 JPEG markers
These markers are compliant with ISO DIS 10918-1 Annex B.
The output JPEG file includes markers defined in Table 7, in order of appearance.
Table 7: JPEG markers included in STV0974 output data stream
Marker Function
Name
Value
Start of image
SOI
FFD8
Define Quantization Table
DQT
FFDB
Start of frame for baseline DCT
SOF0
FFC0
Define Huffman Tables
DHT
FFC4
Start of Scan
SOS
FFDA
End of image
End of image
FFD9
4.4.5.2 Runlength and Huffman encoding
Encoding of DC coefficient
The so-called DC coefficient is the first coefficient of each DCT data block. This DC coefficient is
coded through its DPCM difference with its previous value, which is huffman encoded. This is
described in ISO DIS 10918-1 Annex A - Section F.1.2.1. The DC Huffman tables are described in
ISO DIS 10918-1 Annex A - Section K.3.
Figure 10: Encoding of DC coefficient
DCT coefficient numbers in zigzag order
1
2
3
4
63
64
1
2
3
4
63
64
12
4
16
77
1
0
4
5
22
10
0
0
DC
AC
Block Y1 data values
DC
AC
Block Y2 data values
In the example from Figure 10, the DC coefficient in Block Y2 is equal to 4, the previous Luminance
DC coefficient is 12 (DC coefficient of Block Y1). The DPCM value is 4-12 = -8 and the encoded
value will be Huffman (-8). The code that is generated is Code = DC Huffman (-8).
Encoding of AC coefficients
The 63 left coefficients of each DCT block are called AC coefficients. They are encoded using runlength and Huffman encoder. The run-length encoding consists in counting the number of zero
values between each non-zero coefficient. When a non zero coefficient is found, the Huffman code
of the pair (number of preceding zero, Number value) is Huffman encoded. If a run contains more
than 15 zeros, a specific number called ZRL is Huffman encoded.
If all the values up to the end of the block are equal to zero, a specific code called EOB is Huffman
encoded.
18/61
Functional description
STV0974
The Huffman table used are described in ISO DIS 10918-1 Annex A - Section K.3.
Figure 11: Encoding of AC coefficient
1
2
12
0
DC
3
0
DCT coefficient numbers in zigzag order
63
64
1
2
3
4
77
1
AC
0
4
DC
Block Y1 data values
5
22
4
10
63
64
0
0
AC
Block Y2 data values
In the above example, the first AC coefficient of Block Y1 is 0, as good as the second one. The
zeros are not Huffman encoded, but the runlength counts them. When the first non-zero value is
reached (Coefficient 4 with value 77), the Huffman code for the pair (number of preceding zeros,
value) = (2,77) if Huffman encoded.
The code that is generated is Code = Huffman (2,77).
19/61
STV0974
Functional description
4.5
Microprocessor interface
4.5.1
Features
4.5.2
●
8-bit microprocessor interface, asynchronous read/write, one address bit
●
Indirect access to image sensor and coprocessor control registers
●
Direct access to image data (JPEG compressed or uncompressed)
●
On-chip 2048 byte image FIFO
●
Interrupt request output
●
8/16/32-byte burst DMA support
●
2 Kbyte video FIFO for JPEG data and 10 Kbyte FIFO for non-JPEG data
Description
The STV0974 can be connected to any general purpose 8-bit microprocessor via the
microprocessor interface. This interface substitutes functionally to the YUV and I²C interfaces, i.e.
both data and control flows are handled through the interface which provides:
●
access to the image data FIFO for fast transfers of scaled-down viewfinder images or fullresolution captured and compressed image data. For host systems with DMA support, a DMA
request line is provided, as well as programmable FIFO threshold for burst operation. For other
systems, an interrupt request output line is provided.The 2048-byte FIFO allows for greater
host system latencies; to suit system requirements, the FIFO threshold is programmable.
●
access to the camera subsystem configuration and control registers, through an address/data
register pair and a status register for data polling. Access requests are posted to the internal
controller core that handles the request (as in I²C mode) and finally acknowledges through the
microprocessor interface status register.
20/61
Functional description
4.5.3
STV0974
Direct registers
Access to the microprocessor interface direct registers is controlled by the state of CSN, RDN,
WRN and RS (Table 8).
Table 8: Microprocessor Interface Direct Registers
CSN
RDN
WRN
RS
Register accessed
0
1
0
0
Address Register (AR)
0
0
1
0
Status Register (SR)
0
1
0
1
Data Write register (DW)
0
0
1
1
Data Read register (DR)
1
X
X
X
No access
The direct registers are used to access all STV0974 indirect registers and external image sensor
registers through I²C. To read from a camera register:
1 Write AR with the indirect register address.
2 Poll the status register RDY bit until high.
3 Read the register data from DR.
To write to a camera register:
1 Write AR with the indirect register address.
2 Write DW with the register data.
3 Poll the status register RDY bit until high.
Note: 1 16-bit values are in little-endian representation, i.e. LSB at lower address.
2 No data polling is required to access the microprocessor interface indirect registers.
Address Register (AR)
The Address Register holds the 16-bit address of the camera register to access. AR is written by
two consecutive byte writes, least significant byte first.
Note:
To avoid LSB/MSB sequence mismatch, any read access (to DR or SR) guarantees that the
following write to AR updates the LSB (ADDR bits 7:0).
Table 9: Address Register
Bits
15
Name
ME
Type
WO
Description
0 = Image sensor register (forward command to I²C master).
1 = STV0974 register.
14
RW
WO
0 = Write access
1 = Read access
[13:0]
21/61
ADDR
WO
Camera register address.
STV0974
Functional description
Status Register (SR)
The status register is an 8-bit read-only direct register holding all pending requests from the camera
subsystem.
Table 10: Status Register
Bits
Name
Type
Description
7
IRQ
RO
Interrupt Request: IRQ is set when at least one of the interrupt sources is set, and the
corresponding bit mask is set.
6
-
-
Reserved.
5
EOF
-
End Of Frame: EOF is set by the falling edge of VENV
(output image vertical envelope).
SOF is cleared by writing ICLR bit 5.
4
SOF
RO
3
MCI
RO
Start Of Frame: SOF is set by the rising edge of VENV (output image vertical
envelope).
SOF is cleared by writing ICLR bit 4.
Micro-Core Interrupt: MCI is set by the micro-core to alert the host of the occurrence
of an internal event (status update, error, etc.…).
MCI is cleared by writing ICLR bit 3.
2
FERR
RO
1
FRDY
RO
FIFO Error: FERR is set by the FIFO controller if a FIFO overflow occurs, or if the
FIFO is not empty when cleared at the start of frame.
FERR is cleared by writing ICLR bit 2.
FIFO Ready: This bit indicates that the number of valid bytes in the FIFO is greater
than or equal to the FIFO threshold value, i.e:
FRDY = (Nbytes ≥ threshold)
During the inter-frame period, ‘threshold’ is forced to ‘1’ to flush the FIFO; otherwise,
‘threshold’ is determined by FHTR.
FRDY is level sensitive, i.e. it can be cleared only by reading FIFO.
0
RDY
RO
Ready: This bit indicates the state of the access request between the host and the
STV0974:
0 = Register access in progress,
1 = AR, DR and DW can be accessed by the host.
For a read access, RDY is cleared upon host write to AR (MSB); it is set by the microcore when DR is updated with the register data.
For a write access, RDY is cleared upon host write to DW; it is set by the micro-core
when the internal register is updated.
Note: RDY is high when AR points to the interface indirect registers.
22/61
Functional description
STV0974
Data Write Register (DW)
The data write register contains the byte to transfer to a camera register. DW can be written only
when SR bit RDY is set.
Table 11: Data write register
Bits
[7:0]
Name
DW
Type
Description
WO
Data Byte to write to camera subsystem.
Data Read Register (DR)
The Data Read Register contains the byte transferred from a camera register. DR is valid only
when SR bit RDY is set.
Table 12: Data Read register
Bits
[7:0]
4.5.4
Name
DR
Type
RO
Description
Data Byte read from the camera subsystem.
Indirect registers
The microprocessor interface indirect registers are accessed by the host using an indirect address
base of 0x8FF0 / 0xCFF0 (write / read). Register offsets are listed in Table 13:
Table 13: Microprocessor interface indirect register map a b
Offset
Name
Description
0x00
FIFO
FIFO read register.
0x01
MICR
Microprocessor interface control register
0x02
IMASK
Interrupt mask register
0x03
ICLR
Interrupt clear register
0x04
0x05
FTHR
FIFO threshold register.
0x06
0x07
FCNT
FIFO count register.
a. 16-bit values are in little-endian representation, i.e. LSB at lower address.
b. No data polling is required to access the microprocessor interface indirect registers.
23/61
STV0974
Functional description
FIFO Register (FIFO)
FIFO is a read-only register. When read, FIFO returns the least recent byte from the image data
FIFO, decrements the byte count and releases the FIFO interrupt if the count is lower than the
threshold. Reading from an empty FIFO returns the last valid byte read.
The image data FIFO is cleared at the beginning of VENV, the image vertical envelope. If the FIFO
is not empty, its contents are discarded and the FERR flag is raised in the status register SR. New
image data start to fill in the FIFO. If an overflow occurs during VENV, the FERR flag is also raised
in SR; FERR can be cleared through ICLR.
Table 14: FIFO register
Bits
[7:0]
Name
FIFO
Type
RO
Description
Image data byte (uncompressed or compressed).
Microprocessor Interface Control Register (MICR)
MICR controls and configures the image data transfer.
Table 15: Microprocessor Interface Control Register
Bits
Name
Type
Description
[7:6]
-
-
Reserved.
5
IRQPOL
RW
IRQ pin polarity:
0 = active high
1 = active low
4
DRQPOL
RW
DRQ pin polarity:
0 = active high
1 = active low
[3:2]
BSIZE
RW
DMA burst size and enable:
00 = DMA operation disabled, DRQ pin is high impedance
01 = 8-byte burst
10 = 16-byte burst
11 = 32-byte burst
1
-
-
Reserved, read as zero, ignored upon write
0
CLR
WO
Clear FIFO (Write Only, read as 0):
0 = No action
1 = Reset FIFO to empty state
24/61
Functional description
STV0974
Interrupt Mask Register (IMASK)
Table 16: Interrupt Mask Register
Bits
Name
Type
Description
[7:6]
-
-
Reserved
[5:0]
IMASK
RW
Each IMASK bit set to ‘1’ enables the corresponding interrupt source bit in the status
register (SR)
Interrupt Clear Register (ICLR)
Table 17: Interrupt Clear Register
Bits
Name
Type
[7:6]
-
-
[5:2]
ICLR
WO
[1:0]
-
-
Description
Reserved
Each ICLR bit written with a ‘1’ clears the corresponding interrupt source bit in the
status register (SR). Writing a ‘0’ has no effect
Reserved
FIFO Threshold Register (FTHR)
Table 18: FIFO threshold register
Description
FTRH
Holds the FIFO threshold value
NE = 1
threshold = 1
(TH is ignored)
NE = 0
threshold = TH * 16
(TH valid range is [1, 2...127])
This register is used to program values such as 1 (flush), 16 or 32 (DMA burst) or any greater value
up to 2032 for interrupt driven data transfer. Note that for proper DMA operation, ‘threshold’ must be
greater than or equal to the DMA burst size (MICR[BSIZE]).
Table 19: FIFO Threshold Register
Bits
Name
Type
Description
[15:11]
-
-
Reserved
[10:4]
TH
RW
Threshold value in 16-byte increments.
[3:1]
-
-
Reserved
0
NE
RW
Not Empty:
1 = Force threshold to 1 (TH is ignored)
0 = Normal
25/61
STV0974
Functional description
FIFO Count Register (FCNT)
FCNT is a read-only 16-bit register, returning the current number of bytes available in the FIFO.
Table 20: FIFO Count Register
Bits
[15:0]
4.5.5
Name
FCNT
Type
RO
Description
Number of bytes available in the image data FIFO.
Image transfer operation
Interrupt controlled transfer
The STV0974 generates interrupts by asserting the IRQ signal. The host interrupt handler performs
the following operations:
1 Read the status register SR to determine if the STV0974 is the interrupting device (IRQ bit) and
detect the active interrupt sources.
2 Acknowledge pending interrupts by writing ICLR.
3 Service the interrupt source(s), i.e. for example:
MCI: read micro-core status and error registers (camera control channel).
SOF: trigger frame synchronous task.
FF: empty the FIFO by reading 16-byte blocks (camera image data channel).
RDY: read DR for a pending read, write next AR (low-level byte transfer).
4 Interrupts can be disabled through IMASK.
DMA controlled transfer
The STV0974 supports DMA operation for image data transfer: the DRQ output signal is used to
trigger a DMA burst read transfer from peripheral to memory. A full image transfer under DMA
executes as follows:
Figure 12: Full image transfer under DMA
Frame
FIFO level
threshold
DRQ
(POL = 0)
FIFO
Read
12
1
n
1
n
IRQ
1 The STV0974 is initialized: DMA burst size, FIFO is cleared.
2 DRQ is asserted when the image FIFO threshold is reached or exceeded.
3 The DMA controller starts performing the burst read transfer consisting of 8, 16 or 32 byte reads.
26/61
Functional description
STV0974
4 DRQ is released after the first byte is read.
5 After the last byte of the burst is read, the transfer terminates on step 6 if the FIFO is empty and
the frame end is reached. Otherwise, transfer continues on step 2.
6 IRQ is asserted to signal the end of image transfer; the DMA channel is closed and re-initialized
for the next transfer.
This behavior ensures that no request can be missed by the controller, assuming DRQ is an edgesensitive signal. DRQ polarity can be reversed through MICR[POL] bit.
Note: 1 During DMA transfer, it is assumed that reading DR returns a byte from the FIFO, which means that
AR shall be pointing to the FIFO when the DMA channel is active. To access other registers while
performing DMA, the DMA controller must be halted and pending transfers properly flushed; then
indirect accesses to the camera subsystem can occur. Finally, AR must be restored and the DMA
controller released.
2 At the end of the transfer, FIFO underrun can occur if the image size is not an integer multiple of the
burst size: dummy bytes are appended at the end of the image buffer. Nevertheless, the JPEG endof-frame marker (0xffd9) delineates the buffer.
27/61
STV0974
Functional description
4.6
Video output interface
4.6.1
Video synchronization
The STV0974 supports two modes of data stream synchronization. Either the data stream can be
synchronized by separate HSYNC and VSYNC signal (see Section 4.6.3) or by Synchronization
codes in the data stream (see Section 4.6.2).
4.6.2
Synchronization codes
Horizontal synchronization The horizontal synchronization signal can be embedded within the
data. Figure 13 represents the synchronization codes generated in a line.
Figure 13: Embedded code horizontal timing
START OF DIGITAL ACTIVE LINE
START OF DIGITAL LINE
EAV Code
LINE BLANKING
F 0 0 X 8 1
F 0 0 Y 0 0
8 1 8 1
0 0 0 0
EAV Code
SAV Code
8 1
0 0
F 0 0 X D D D D D D D D
F 0 0 Y 0 1 2 3 0 1 2 3
D D F 0 0 X
2 3 F 0 0 Y
4-data
packet
4
4
NEXT LINE
Vertical synchronization
Figure 14: Embedded codes in vertical timing
START OF DIGITAL FRAME
EAV Code
8 1 8 1
0 0 0 0
Note:
8 1 8 1
0 0 0 0
END OF DIGITAL FRAME
FRAME BLANKING
F 0 0 X 8 1 8
F 0 0 Y 0 0 0
1
0
8 1 8 1
0 0 0 0
SAV Code
F 0 0 X 8 1 8 1
F 0 0 Y 0 0 0 0
8 1 8 1
0 0 0 0
The horizontal synchronization is not sent during vertical blanking.
28/61
Functional description
4.6.3
STV0974
HSYNC and VSYNC video synchronization
HSYNC and VSYNC synchronization timing is shown in the Figure 15.
Figure 15: Horizontal and vertical synchronization
HSYNC
H=1
H=0
VSYNC
EAV BlankingSAV
Active
V=0
Active lines
Blanking
V=1
4.6.4
Data timing
The YUV timing and the 3 RGB timings are also represented on Figure 16, with the associated
qualifying HCLK clock.
Figure 16: Timings with associated qualifying clocks
Data[7:0]
Un,n+1
Yn
Vn,n+1
Yn+1
Pix0_lsb
Pix0_msb
Pix2_lsb
Pix2_msb
Un+2,n+3
YCbCr
HCLK
RGB565
RGB444
Data[7:0]
Pix3_lsb
HCLK
Data[7:0]
RGB332
HCLK
29/61
Pix0
Pix1
Pix2
STV0974
4.6.5
Functional description
JPEG data on 8-bit parallel with qualification clock
This interface outputs JPEG on parallel 8-bit IOs. Different synchronization can be provided, as
described in Figure 17.
There are no defined lines in a JPEG data stream. The whole stream is output as a single frame
line with VSYNC and HSYNC asserted together.
Polarities of HSYNC, VSYNC and HCLK are programmable.
Figure 17: JPEG data output
JPEG 8-bit data
Data0
Data1
no data
Data2
no data
no data
Data3
HSYNC
VSYNC
HCLKx2
HCLKx2
Extra bytes can be added at the end of the image to ease the host DMA task.
30/61
Functional description
4.7
STV0974
Power management unit
The STV0974 is reset via the internal PowerOnReset cell (POR) or via an external control reset
line. The device reset is controlled by the RST pin.
The POR cell generates an output signal on the POR pin every time that the device external supply
is switched off or the PDN pin is activated.
Figure 18: Reset of STV0974
Application with POR reset cell
Application with external reset line
POR
POR
STV0974
STV0974
(left unconnected)
RST
RST
Connection
on application
board
Host control line
The STV0974 enters into power-up phase in two circumstances:
●
when the supplies are turned on with PDN pin high.
●
when the STV0974 exits from power-down (PDN pin rises with supplies already on).
At power-up, the STV0974 performs its initialization phase and goes into sleep mode.
Figure 19: State machine at power-up
Supplies turned on & PDN low
Supplies Off
Vdd = 0
Supplies
turned-off
Supplies
turned-off
Supplies
PDN high
turned-on
& PDN high
Boot
1
Sleep mode
31/61
Power-down
PDN low
STV0974
Functional description
Figure 20: Boot-up phase machine
VDD
t1
PDN
RST
t2
t3
t4
t5
POR
Clk
Mode
Reset
Sleep
Boot
Timing constraints:
Table 21: Timing constraints
Min.
Note:
Max.
Unit
t1
0
ms
t2
20
µs
t3
20
clk cycles
t4
2
ms
t5
7
µs
To be compatible with external power-on/internal power-down modes (ex: external VDD on and
PDN low), all input pads from baseband side as well as SCL and SDA pads on both sensor and
baseband sides are “fail-safe”.
The “timing constraints” mentioned above correspond to the minimum delay needed between
signals, in order to follow a correct power up sequence and insure an adequate initialization phase.
Referring to the application schematics (Section 8), STMicroelectronics recommends to connect
POR pin (internal supply) to RST pin (Reset).
32/61
Functional description
4.8
STV0974
Clock input
This block generates all the necessary internal clocks from an input range defined in Table 22. The
input clock pad accepts up to 26 MHz signals.
Table 22: System input clock frequency range
System clock frequencya
Min. (MHz)
Max. (MHz)
6.5
26
a. Standard supported input frequencies (in MHz):
6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2, 19.44, 26
33/61
STV0974
Functional description
4.9
Camera control unit
4.9.1
Features
●
●
4.9.2
User mode transition
I2C register map including high-level registers and low-level registers dedicated to scaler
control
Description
Figure 21: State machine user mode transitions
PDN
VDD
Boot
Reset
Power down
1
Sleep
Idle
Sleep
Flash
1
Flash
Idle
Live
Capture
Sleep
Sleep
Sleep
Idle
Idle
Viewfinder
Capture
Idle
Live
Capture
Viewfinder
Viewfinder
Capture
Live
PDN: Power Down pin
Viewfinder
i. the “1” transition is automatic
ii. Flash mode requires a firmware patch. Contact ST support.
iii. Flash mode is not available with the microprocessor interface
Modes
Power down ●Supply is internally cut.
Reset. Transitional state
Boot ●
Sleep mode This mode ensures that the coprocessor consumes the lowest possible power and I2C
control is possible. Patching should occur in sleep mode followed by setting the system clock
parameters.
Idle Mode The clock coming from the sensor is active and I2C control is possible.
Viewfinder Mode The viewfinder mode can be used to display dithered images on low color depth
local LCD displays. The programmable gamma allows for a wide range of displays. Different image
sizes and data formats can be chosen.
34/61
Functional description
STV0974
Still Mode This mode is used to take still pictures. Still picture parameters can be set for both
image size and data format. the first image output has a guaranteed exposure and color balance.
the number of frames output can also be set.
Live Mode Live clips can be generated in all the data and image formats.
Flash Mode Flash mode is used to take a single still picture and synchronously activate a flash
gun signal and illuminate the scene during the exposure period of the pixels.
Torch Mode For systems without a flash gun, a torch mode can replace the flash mode. Torch
mode is a setting (rather than a mode) which supports illumination of devices by producing a longer
illumination pulse with a lower intensity. In torch mode, illumination is switched on before the
camera is operated in one of the standard operating modes: ViewFinder, still capture or live.
Mode transitions
Boot to sleep The microcore starts following PDN de-activation. The right configuration is
obtained according to the following procedure:
1 Determine the sensor I2C chip address.
2 Read all sensor registers, either through I2C reads or status line interpretation.
3 Initialize internal registers.
The device then automatically goes into sleep mode
Sleep to idle When exiting sleep mode, the external clock register of the sensor is set, and the
sensor goes into Idle mode.
Figure 22: Sleep to idle timing
t0
SCL/SDA
t2
Goto VF
or Goto Live
974 Mode
Idle
Sleep
MSCL/MSDA
Sensor Mode
t1
Go to clk
Set
external clock active
Sleep
Get sensor
Go to Idle
characteristics
Clock Active
Clock Active
CLK from sensor
t0: Time to interpret Mode change command (< 1ms)
t1: Time to set clk characteristics (< 1ms)
t2: Time to get sensor characteristics (< 3ms) to go to idle
35/61
Idle
STV0974
Functional description
Idle to viewfinder / live The sensor field and line lengths are set according to user-defined frame
rate and data output format. The STV0974 processes all sensor data on the fly. Exposure and white
balance controls are computed at the end of each frame.
Figure 23: Idle to viewfinder or live
SCL/SDA
Goto VF
or Goto Live
974 Mode
Idle
VF or Live
MSCL/MSDA
Goto Video
Active
Sensor
settings
Sensor Mode
Idle
Video Active
VisionLink data
t0
t1
t2
t3
t0: Time to interpret Mode change command (< 1ms)
t1: Time to set VF or Live parameters inside the STV0974 and to send VF or Live settings to the sensor (~2ms)
t2: Time to go from Idle to Video Active state (Sensor side)
t3: Exposure time (Sensor side). It depends on the frame rate.
Viewfinder / live to idle
The STV0974 processes all the frame data and switches to idle mode after the last byte.
See Figure 24 below.
Figure 24: Viewfinder or live to idle timing
SCL/SDA
Goto Idle
974 Mode
VF or Live
Idle
STV0974
output data
MSCL/MSDA
Sensor Mode
Goto Idle
Video Active
Idle
VisionLink data
t0
t1
t2
t0: Time to interpret Mode change command (< 1ms)
t1: Time to finish sending frame (< 33 ms)
t2: Time to flush all the STV0974 video pipe and the interface FIFO (interface dependant)
36/61
Functional description
STV0974
Viewfinder to live/ Live to viewfinder The sensor field and frame lengths are set according to the
user defined Live/Capture frame rate and data output format. The latency of this transition is
minimal. See Figure 25 below.
Figure 25: Viewfinder to live or live to viewfinder
SCL/SDA
Goto
other streaming
mode
974 Mode
VF or Live
Live/VF
MSCL/MSDA
Sensor Mode
Video Active
STV0974
output data
1 frame max.
2 frames max.
Idle to capture Data is grabbed as fast as possible for exposure and white balance convergence.
When the system is stable (or timed-out), the user settings are sent to the sensor. See Figure 26.
Figure 26: Idle to capture timing
SCL/SDA
capture
974 mode
Idle
Capture in progress
Capture
Output link
MSCL/MSDA
Sensor mode
Idle
Video active
Input link
3 ms max.
Max = 20 frames @ maximum frame rate max 2 frames
Mean ~8 frames
Min. = 1 frame
Viewfinder to capture Two cases can occur:
1 The system (exposure, white balance) is already stable in viewfinder mode. The user settings
are sent to the sensor. The processed frame is sent after a short latency.
2 The system has not stabilized. STV0974 enters transient mode and, when stable, automatically
goes into Capture mode.
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STV0974
Functional description
Once the image is sent, the STV0974 automatically returns to Idle. See Figure 27.
Figure 27: Viewfinder to capture timing
SCL/SDA
capture
974 mode
ViewFinder
Capture in progress
Capture
STV0974
output data
MSCL/MSDA
Video active
Sensor mode
VisionLink data
Max 1 frame
Note:
Max 20 frames(Note 1)
Min = 0 frame
Max 2 frames
1 If the system exposure and white balance is already stable, the maximum delay is 1 frame.
Idle to Flash In idle mode, white balance must be set to a fixed setting (automatic white balance
setting is not recommended as no convergence is applied) and the “delay transfer mode” must be
set to 0 (no frame delay). When changing to flash mode, the maximum frame rate is automatically
set with respect to data format. The first frame is captured, processed and transferred by the
STV0974. The system automatically goes back to idle mode. Figure 28 illustrates the timing in flash
mode.
When setting the torch mode, the flash mode should not be used. All the standard operating modes
like ViewFinder, still capture or live operate normally. As an example, the automatic white balance
and exposure control as well as “delay transfer mode” can be active if required.
Figure 28: Flash mode diagram
1
Exposure time
Sensor data
output
Strobe request
from host
Flash Strobe
pulse (DIO12 pin)
2
STV0974
data out
1 Exposure time of pixels is automatically set to maximum exposure time
2 Strobe pulse width is clipped to a maximum of 8 lines
38/61
Functional description
4.9.3
STV0974
I²C register map
Register interpreter
The STV0974 I²C address is 0x08.
The addressing space is defined in Table 23 and Table 24.
Table 23: Fields of address map
Index Bit
Description
15
bit15 = 0: reserved for the sensor
bit15 = 1: STV0974
14
Pre-fetch read value
13
0: low-level register
1: high-level register
[12-8]
Page group
[7-0]
Register index
The customer accessible register map is divided into groups as listed in Table 24.
Table 24: Register groups
Group
Register group [0]
Description
- System read only registers (e.g. sensor ID, firmware revision)
- System clock setup
- High level operating modes
- Output format control
Register group [1]
- Frame rate control
- Image sizes
- Stills capture setup
Register group [2]
- Image appearance setup
- Image manipulation
- JPEG control
Register group [3]
- Color saturation
- Gamma control
39/61
Register group [4]
- Exposure control setup
Register group [5]
- White balance control
Register group [6]
- Flash mode management
STV0974
Functional description
There are restrictions related to the states at which registers can be accessed. Table 25 lists the
state coding used in the register description.
Table 25: Register state coding
State code
Description
I
Registers can be accessed safely while the system is in idle state
V
Registers can be accessed safely while the system is in ViewFinder state
C
Registers can be accessed safely while the system is in capture mode state
L
Registers can be accessed safely while the system is in live mode state
S
Registers can be accessed safely while the system is in sleep mode state
A
Registers can be accessed in all stable states
Register contents represent different data types as described in Table 26.
Table 26: Type of data
State Code
Description
I
Integer parameter. May be anywhere between 1 bit and 8 bit wide
M
Multiple field registers
B
Bit field register
C
Coded register
Registers listed as reserved or read-only should NOT be written to, as this may cause
unpredictable results.
The data format for each register uses the following coding:
●
D = Data (1 or 0 as required)
●
0 = Data bit must be set to 0
●
1 = Data bit must be set to 1
●
X = Don’t care (either 0 or 1 can be written with no system consequences)
●
R = Reserved
40/61
Functional description
STV0974
4.9.3.1 High-level interface
Register group 0
Table 27: System and status [register group 0]
Name
Index
R/W
State
code
Data
type
Format
default
DDDD.DDDD
Sensor ID Code
MSB
0xA000
R
A
I
Sensor ID Code
LSB
0xA001
R
A
I
Firmware Rom
Version
0xA002
R
A
I
External Clock
0xA004
R/W
S
MI
0xA005
R/W
S
MI
0010.0010
Bit[15:4]: sensor type
DDDD.DDDD
Bit [3:0]: Sensor revision
1000.XXXX
DDDD.DDDD
Firmware version identifier
0001.0100
Frequency MSBa
External Clock
Frequency LSB
Description
RRDD.DDDD
1101.0000
RRDD.DDDD
0000.0000
External clock frequency in MHz
coded as fixed point (5:11):
Bit [15:11]: Integer part
Bit [10:0]: Decimal part (1 unit = 1/
2048 MHz)
i.e. default value is 26MHz.
Sensor Clock
Derating
0xA006
Mode Status
0xA007
R
R
S
A
I
I
RRRR.DDDD
Sensor clock deratingb
0000.0001
[15-0]: Reserved
RRRR.DDDD
[15]: Booting
[14-7]: Reserved
[6]: Flash
[5]: Capture in progress
[4]: Live
[3]: Capture
[2]: Viewfinder
[1]: Idle
[0]: Sleep
Mode Control
0xA008
R/W
A
I
RRRR.DDDD
[15-7]: Reserved
0000.0000
[6]: Flash
[5]: Reserved
[4]: Live
[3]: Capture
[2]: Viewfinder
[1]: Idle
[0]: Sleep
Status Register
0xA009
R
A
I
DDDD.DDDD
0000.0000
41/61
STV0974 status (Table 10)
STV0974
Functional description
Table 27: System and status [register group 0]
Name
Input / Output
Protocol Control
Index
R/W
State
code
Data
type
0xA00A
R/W
S
I
Format
default
Description
RDDD.RDDD
Bit [7]: Reserved
0001.0100
Bit [6:4]: Input
0: Reserved
1: VisionLink
2-3: Reserved
4: Color bars generator
Bit [3]: Reserved
Bit [2:0]: Output
0: Reserved
1: Reserved
2: I2C/ITU-R 656 embedded
synchro
3: I2C /ITU-R 656 external synchro
I2C / JPEG parallel output
4: Microprocessor interface
controller / microprocessor
interface
5: Reserved
a. See Clock input section, for standard external clock frequencies supported.
b. The product limitation in derating mode is :
2: Half Speed -> Max I2C clock is 200 kHz
4: Quarter Speed -> Max I2C clock is 100 kHz
42/61
Functional description
STV0974
Register group 1
Table 28: Image characteristics [Register group 1]
Name
Still and Live
Sensor Frame
Ratea
Index
R/W
State
code
Data
type
0xA100
R/W
SIV
I
Format
default
Description
DDDD.DDDD
Frame rate coded as fixpoint (6:2):
0011.1100
Bit [7:2]: Integer part
Bit [1:0]: Decimal part
(1 unit = 0.25 frame/s)
Default is 15 frame/s
Still and Live
Output Image Size
0xA101
R/W
A
I
RRRR.RDDD
[7]: Custom b
0000.0000
[6]: QQCIF
[5]: SubQCIF
[4]: QQVGA
[3]: QCIF
[2]: QVGA
[1]: CIF
[0]: VGA
Still and Live
Output Image
Format
0xA102
R/W
SIV
I
RRRR.RDDD
[4]: JPEG
0000.0100
[3]: YUV 4:2:2
[2]: RGB 5:6:5
[1]: RGB 4:4:4
[0]: RGB 3:3:2
Still Multi-frames
Transfer Mode
0xA103
Delay transfer
Mode
0xA104
R/W
R/W
SIVL
SI
B
B
DDDD.DDDD
0... 254: 0...254 frame(s)
0000.0001
255: continuous.
DDDD.DDDD
0... 254: Minimum number of
frames (at 30 frame/s) to wait for
before sending the requested still
one.
0000.0000
255: Reserved
Viewfinder Frame
Rate
(STV0974 input)a
0xA105
R/W
SILC
I
DDDD.DDDD
Frame rate coded as fix point
0011.1100
(6:2)a:
bit [7:2]: Integer part
bit [1:0]: Decimal part
(1 unit = 0.25 frame/s)
Default is 15 frame/s
Viewfinder Image
Size
0xA106
R/W
A
I
RRRR.RDDD
[7]: Customb
0000.0101
[6]: QQCIF
[5]: SubQCIF
[4]: QQVGA
[3]: QCIF
[2]: QVGA
[1]: CIF
[0]: VGA
43/61
STV0974
Functional description
Table 28: Image characteristics [Register group 1]
Name
Viewfinder Image
Format
Index
R/W
State
code
Data
type
0xC107
R/W
SILC
I
Format
default
Description
RRRR.RDDD
[4]: JPEG
0000.0011
[3]: YUV 4:2:2
[2]: RGB 5:6:5
[1]: RGB 4:4:4
[0]: RGB 3:3:2
a. The corresponding frame rates are considered as targets. If the target cannot be achieved due to
derated sensor clock or output format versus output protocol, the closest possible frame rate is
achieved, knowing that 30 frame/s is the highest frame rate supported by the device.
b. For custom output sizes, please refer to Section 4.6. When continuous mode is selected (255), the
grabbed image is output until the mode control register is modified.
44/61
Functional description
STV0974
Register group 2
Table 29: Image control [register group 2]
Name
Index
R/W
State
code
Data
type
Antivignetting
Correction
0xA200
R/W
A
I
Format
default
Description
RRRR.DDDD
Correction in tens of percentage
0000.0110
0: 0%
10: 100%,
>10: Frozen
DEFCOR control
NORA control
0xA201
0xA202
R/W
R/W
A
A
M
I
DXXX.XXXX
Bit[7]: Defect correction matrix
(default is square matrix)
XDXX.XXXX
Bit(6]: Defect correction enable
(correction of bad pixels)
XXDX.XXXX
Bit[5]: Defect scythe enable
(Smooth filtering of good pixels)
XXXD.DXXX
Bit[4:3]: Defect scythe rank
(default is 0, maximum value
means narrow filter)
XXXX.XDDD
1010.0111
Bit[2:0]: Defect scythe weight
(default is 7, maximum value
means minimum weight applied)
RRRR.RDDD
Nora control register.
0001.0010
[0]: Nora disabled
[7]: Nora max strength
Default is 2
Mirror
0xA203
R/W
SI
B
RRRR.RRXD
Horizontal mirror
RRRR.RRDX
Vertical mirror
0000.0000
Sharpness Gain
0xA204
R/W
A
I
Sharpness
Enable
0xA205
R/W
A
B
JPEG Control
0xA206
00DD.DDDD
Sharpness gain
0000.1100
R/W
A
I
1111.1101
Sharpness enable
Bit[7:2]: low peak
Bit[1:0]: reserved
RDDD.DDDD
Bit [7]: JPEG control
0011.1110
0: Automatic file size computation
RRRR.RRRD
1: Manual squeeze control
Bit [6:0]: Control settings
if bit[7] = 0: Requested size of final
JPEG file (in Kbyte)
if bit [7] = 1: Manual squeeze
control with quantization table
scaled by bit [6:0]/8.
Applicable range of values for bit
[6:0] is [2; 67]
45/61
STV0974
Functional description
Register group 3
Table 30: Color management [register group 3]
Index
R/W
State
code
Data
type
Still / live Gamma
Standard Gain
0xA300
R/W
A
I
Still / live Gamma
S-Curve gain
0xA301
Still / live Gamma
Misc.
0xA302
Name
R/W
A
M
Format
default
RRRR.DDDD
Description
0000.0011
Bit[3:0]: gain for standard Gamma
curve
XXXX.DDDD
Bit[3:0]: Gain for low S-curve part
DDDD.XXXX
Bit[7:4]: Gain for high S-curve part
0100.0100
R/W
A
M
XRRR.DDDD
DRRR.XXXX
1000.0000
Viewfinder
Gamma
Standard Gain
0xA303
Viewfinder
Gamma
S-Curve gain
0xA304
Viewfinder
Gamma Misc.
0xA305
R/W
R/W
A
A
M
M
0000.0100
Bit[3-0]: Gain for standard Gamma
curve
XXXX.DDDD
Bit[3-0]: Gain for low S-Curve part
DDDD.XXXX
Bit[7-4]: Gain for high S-Curve part
RRRR.DDDD
0100.0100
R/W
A
M
XRRR.DDDD
DRRR.XXXX
1000.0000
YCbCr Control
Y range
0xA306
R/W
A
I
DDDD.DDDD
YCbCr Control
Y ceiling
0xA307
R/W
A
M
DDDD.XXXX
YCbCr Control
Y floor
0xA308
R/W
A
M
DDDD.XXXX
YCbCr Control
0xA309
R/W
A
I
DDDD.DDDD
CbCr saturationa
Bit[3:0]: S-curve pedestal
bit [7] = 1 Standard Gamma
bit[7] = 0 S-curve Gamma
1000.0000
Bit[3:0]: S-curve pedestal
bit [7] = 1 Standard Gamma
bit [7] = 0 S-curve Gamma
Y range value
(contrast enhancement)
Bit[7:4]: Ceiling value
0001.0000
0000.0000
Bit[3:0]: Floor value (signed value
in 2’s complement)
CbCr saturation
1000.0000
a. The maximum register value allowed is 144. For higher saturation capabilities, contact ST support.
Note:
YCbCr control registers are common for still/live and ViewFinder modes. As a consequence, if
different settings are applied in these modes and if for example still capture is requested from
ViewFinder mode, it is recommended to set a “transfer mode delay” corresponding to 1 frame
minimum, and also to respect a minimum wait of half of a frame prior to changing the YCbCr
settings.
46/61
Functional description
STV0974
Register group 4
Table 31: Exposure management [Register group 4]
Name
AC Frequency
Index
R/W
State
code
Data
type
Format
default
0xA400
R/W
SI
B
DDDD.DDDD
Description
AC Frequency in Hz
0011.0010
Exposure
weighting
0xA401
Exposure
compensation
0xA402
R/W
A
I
RRRR.RRDD
0000.0000
R/W
A
I
DDDD.DDDD
0001.1001
Zone weight:
[3]: Reserved
[2]: Backlit
[1]: Centered
[0]: Flat
One unit of compensation is
equivalent to 1/3 EV.
Default value is equivalent to 0 EV.
[Default - 2] is equivalent to -2/3
EV.
Valid range is 0 to 36
Register Group 5
Table 32: White balance management [register group 5]
Name
47/61
Index
White Balance
Mode
0xA500
Manual White
Balance
Red channel
0xA501
Manual White
Balance
Green channel
0xA502
Manual White
Balance
Blue channel
0xA503
R/W
R/W
State
code
Data
type
A
I
Format
default
RRRR.DDDD
0000.0001
R/W
A
C
DDDD.DDDD
0000.0000
Description
[15-9]: Reserved
[8]: Reserved
[7]: Reserved
[6]: Reserved
[5]: Reserved
[4]: User manual (using registers
below)
[3]: Reserved
[2]: Reserved
[1]: Automatic
[0]: Off
White balance user setting for the
red channel gain.
Contact ST for support.
R/W
A
C
DDDD.DDDD
0000.0000
White balance user setting for the
green channel gain.
Contact ST for support.
R/W
A
C
DDDD.DDDD
0000.0000
White balance user setting for the
blue channel gain.
Contact ST for support.
STV0974
Functional description
Register Group 6
Table 33: Flash mode management [register group 6]
Name
Index
Torch polarity
0x8A43
R/W
R/W
State
code
Data
type
I
I
Format
default
RRRR.RDDD
RRR.R000
Description
Bit[2:0]=0: Torch output (pin
DIO12) signal is low
Bit[2:0]=7: Torch output (pin
DIO12) signal is high
Torch control
0x8A44
R/W
I
I
RDRR.RRRR
R1RR.RRRR
Bit[6]=0: Torch output (pin DIO12)
pad enable.
Bit[6]=1: Torch output (pin DIO12)
pad in high impedance
Note:
Flash pulse
polarity
0x8A45
Flash pulse length
0x88D4
R/W
R/W
I
I
I
I
RDRR.RRRR
Bit[6]=0: Flash pulse active high.
R0RR.RRRR
Bit[6]=1: Flash pulse active low.
RRRR.RDDD
Bit[2:0]: line length - 1
0000.0000
Default is 0, corresponding to 1
video line (maximum pulse allowed
is 8 video lines).
Access to the bits mentioned here above is done through a read-modify-write sequence. As an
example, when torch mode is set:
- when in idle mode:
set 0x8A44 bit[6] to 0 to enable the torch mode
set 0x8A43 bit[2:0] to 7 to light the torch (if the torch is active high)
- go into required Active mode (still/live or ViewFinder):
set 0x8A43 bit[2:0] to 0 to extinguish the torch
In the case of flash mode:
- when in idle mode:
set 0x8A45 bit[6] to 1 to set the flash pulse active low (default setting is flash pulse active high)
set 0x88D4 bit[2:0] to 7 to set the flash pulse length to 8 video lines
set 0xA104 bit [7:0] to 0 to set 0 transfer frame delay
set 0xA500 bit[3:0] to 5 to set white balance to “daylight” fixed setting
- go into flash mode:
the system automatically goes back to Idle.
48/61
Functional description
STV0974
4.9.3.2 Low-level interface
Scaler low-level control
These registers are active only if either “Still and Live Output Image Size” or “Viewfinder Image
Size” registers are set to “custom” size.
Table 34: Scaler low-level control
Index
R/W
State
code
Data
type
Format
default
Source centre Xposition MSB
0x8060
R/W
A
I
RRRR.RRDD
Source centre Xposition LSB
0x8061
Source centre Yposition MSB
0x8062
Source centre Yposition LSB
0x8063
Viewfinder Dest.
Image Width MSB
0x8064
Viewfinder Dest.
Image Width LSB
0x8065
Viewfinder Dest.
image height MSB
0x8066
Viewfinder Dest.
image height LSB
0x8067
R/W
A
I
DDDD.DRRR
Viewfinder Scaling
factor
0x8068
R/W
A
I
RRRR.RDDD
Name
0000.0001
R/W
A
I
DDDD.DDDD
Description
X-coordinates of the centre of the
source image window.
Default is 322
0100.0010
R
A
I
RRRR.RRDD
0000.0000
R
A
I
DDDD.DDDD
Y-coordinates of centre of the
source image window.
Default is 242
1111.0000
R/W
A
I
RRRR.RRDD
0000.0000
R/W
A
I
DDDD.DRRR
Width of the destination image
(after scaling) in viewfinder mode.
The value must be a multiple of 8
pixels.
1010.0000
R/W
A
I
RRRR.RRDD
0000.0000
Height of the destination image
(after scaling) in viewfinder mode.
This value must be a multiple of 8
pixels.
0111.1000
0000.0100
Scaling factor in viewfinder mode:
[0]: Reserved
[1]: x1
[2]: x2
[3]: x3
[4]: x4 (default)
[5]: x5
[6]: x6
[7]: x1.5
[8]: x2.5
Still/Live Dest.
Image Width MSB
0x8069
Still/Live Dest.
Image Width LSB
0x806A
R/W
A
I
RRRR.RRDD
0000.0010
R/W
A
I
DDDD.D000
1000.0000
Width of the destination image
(after scaling) in still / live mode.
This value must be a multiple of:
- 2 pixels in YUV output format
- 16 pixels in JPEG output format
Registers only used for Capture
when in idle mode
49/61
Still/Live Dest.
image height MSB
0x806B
Still/Live Dest.
image height LSB
0x806C
R/W
A
I
RRRR.RRDD
0000.0001
R/W
A
I
DDDD.D000
1110.0000
Height of the destination image
(after scaling) in still / live mode.
This value must be a multiple of 8
pixels.
Registers only used for Capture
when in idle mode
STV0974
Functional description
Table 34: Scaler low-level control
Name
Still / Live Scaling
factor
Index
R/W
State
code
Data
type
Format
default
0x806D
R/W
A
I
RRRR.RDDD
0000.0001
Description
Scaling factor in Still/Live:
0: Reserved
1: x1 (Default)
2: x2
3: x3
4: x4
5: x5
6: x6
7: x1.5
8: x2.5
Note:
If the scaling factor it too high and the cropped image size is bigger than the full source image, the
scaling factor is automatically set to the closest possible high value.
MMS Downscale zoom
This section contains an example of how the low level scalar registers can be used to implement a
down scale ‘zoom’ feature suitable for MMS applications. The example assumes that the desired
output image size is 160 x 120 pixels. The choice of output image size will limit the number of
scaling options available. In this example we are able to select scaling factors 1, 1.5, 2, 2.5, 3 and 4.
The source image from which the scaled output images are derived is always the full VGA array,
640 x 480 pixels.
If a smaller output image is chosen, 96 x 80 for example, then clearly the entire scaling factor range
would be available.
With reference to the example below (Figure 29), a scaling factor of 4 actually yields a ‘zoom’ of 1.
This implies that the full scene field of view is preserved within the output image but heavily scaled.
To ensure that the smaller scaling factors produce the same output image size it is necessary for
the video processor to crop the source VGA image prior to scaling. This has the effect of limiting the
scene field of view but yields the ‘zoom’ effect.
50/61
Functional description
STV0974
Figure 29: MMS crop zoom example
VGA (640 x 480) source image
scaled for use in this document
Set of images below are
crop/scales to 160x120 pixels
for final display
1. Scale by 1 from 160x120 crop
2. Scale by 1.5 from 240x180 crop
3. Scale by 2 from 320x240 crop
4. Scale by 2.5 from 400x300 crop
5. Scale by 3 from 480x360 crop
6. Scale by 4 from 640x480 crop
1.
4.
Zoom factor = 4
2.
Zoom factor = 2.67
Zoom factor = 1.6
Zoom factor = 2
3.
Zoom factor = 1.333
5.
Zoom factor = 1
6.
4.9.3.3 Status error codes
A read from the Status Register (0xA009) yields status error codes as described in the table below.
The Status Register contents are reset to 0x00 by a write to the Mode Control register.
Table 35: Status error codes
Error code value
51/61
Description
Troubleshooting
0x00
No error
0x21
Sensor communication problem
0x22
Sensor temporarily not accessible. Retry.
0x23
Incompatible sensor
Re-grab new image
0x41
JPEG File too big
One of the requested JPEG frames is
larger than the target. User to restart
capture command
0x51
Time out
Sensor not responding. Need to go back to
Idle.
STV0974
Functional description
4.9.3.4 Firmware patching
The STV0974 has some firmware patching capabilities addressable through I2C and
microprocessor interfaces through control registers firmware patch code downloads. Up to 15
different patches can be downloaded within a limit of 512 bytes of RAM.
Table 36 : Patch control registers
Name
Index
R/W
Format
default
Patch enable
0x84BF
W
RRRR.RRDD
bit [1:0] = 01 patch enabled
Patch address
0x8480
W
RRRR.RRRR
bit [15:0] = Reserved
RRRR.RRRR
Patch address delivered by ST
1DDD.DDDD
bit [15] = 1
DDDD.DDDD
bit [14:0] = Patch memory offset
Description
bit [7:2] = 10 patch disabled
Ox8481
Patch memory
offset
0x84A0
0x84A1
W
The patch space starts from address 0x8600.
Patch structure:
“disable all patches”
“set address to patch”
“set offset of patch in memory”
“write patch in memory (starting from address 0x8600 + patch memory offset)”
“enable all patches”
The state in which to download the patch depends on the nature of the patch, most likely either idle
or sleep mode. Please contact ST support for patch delivery and recommendations for ideal use.
4.10
Additional features
There are a number of additional features which are supported by the STV0974, however
implementation of these features is not supported by this datasheet. Please contact the ST support
team for support of these features if you have a specific requirement.
●
The polarity of the HSYNC and VSYNC signal can be programmed. However, these are nonstandard settings.
●
The transmitted byte order of the RGB and YUV is programmable.
●
The viewfinder color matrix can be programmed to match the characteristics of a local LCD
display.
52/61
Electrical characteristics
STV0974
5
Electrical characteristics
5.1
Absolute maximum ratings
Symbol
VDD
Parameter
Value
Unit
-0.5 to +2.2
V
-0.5 to (VDD + 0.5)
V
Supply current
100
mA
Current on any signal pin
±10
mA
-40 to 150
°C
Supply voltage
(including
VCORE &
VDDPOR)
Voltage on any signal pin
IDD
TSTO
Storage temperature
TLEAD, 974E
Lead temperature (soldering, 10 s) for lead-free package
+260
°C
TLEAD, 974
Lead temperature (soldering, 10 s) for leaded package
+225
°C
Caution: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
5.2
Operating conditions
Symbol
5.3
Parameter
VDD
Supply voltage
TA
Ambient temperature
Value
Unit
+1.7 to +1.9
V
-25 to +70
°C
Value
Unit
65
°C/W
Thermal data
Symbol
Rth(j-a)
Parameter
Junction-ambient thermal resistance - TFBGA56a
a. Typical, measured with the component mounted on an evaluation PC board in free air.
53/61
STV0974
5.4
Electrical characteristics
DC electrical characteristics
Over operating conditions unless otherwise specified.
Symbol
Parameter
Test conditions
Min.
Max
Unit
VIL
Input low voltage
-0.3
0.3 VDD
V
VIH
Input high voltage
0.7 VDD
VDD + 0.3
V
VOL
Output low voltage
IOL < 2 mA
0.2 VDD
V
VOH
Output high voltage
-IOH < 2 mA
IIL
Input leakage current
Input pins
I/O pins
VSS < VIN < VDD
CIN
Input capacitance
SCL, MSCL
TA = 25 °C, freq. = 1 MHz
CI/O
Input / Output capacitance
SDA, MSDA
TA = 25 °C, freq. = 1 MHz
0.8 VDD
V
± 10
±1
µA
µA
6
pF
8
pF
Typ.
Max
Unit
Table 37: Power supply specificationsa
Symbol
Parameter
Test Conditions
IDDPD
VDD supply current in
power-down mode
VDD = max ; PDN < VIL
5
20
µA
IDDIDLE
VDD supply current in idle mode
VDD = max ; mode = idle.
15
25
mA
IDDACTIVE_
JPEG
VDD supply current in active live
mode
VDD = max ; mode = live or
ViewFinder or capture
JPEG at VGA 30 frame/s.
65
75
mA
IDDACTIVE
NON_JPEG
VDD supply current in active live
mode
VDD = max ; mode = live or
ViewFinder or capture
YUV at VGA 30 frame/s.
55
75
mA
a. Same power consumption for Viewfinder, live and capture modes if same output image size and
output data format.
54/61
Electrical characteristics
STV0974
5.5
AC electrical characteristics
5.5.1
CLK
Table 38: CLK electrical characteristics (Figure 30)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCDC
DC coupled square wave voltage
1.7
1.8
1.9
Vp-p
fCLK
Clock frequency input
6.5
13
26
MHz
Min.
Typ.
Max.
Unit
400
kHz
Figure 30: CLK electrical characteristics
1/fCLK
VCDC
5.5.2
I2C slave timing
Table 39: I2C slave timing (Figure 31)
Symbol
Parameter
fSCL
SCL clock frequency
tLOW
Clock pulse width low
1.3
µs
tHIGH
Clock pulse width high
0.6
µs
tSP
Pulse width of spikes which are suppressed by the
input filter
tBUF
Bus free time between transmissions
1.3
µs
tHD.STA
Start hold time
0.6
µs
tSU.STA
Start set-up time
0.6
µs
tHD.DAT
Data in hold time
0.15
tSU.DAT
Data in set-up time
100
tR
SCL / SDA rise timea
300
ns
tF
SCL / SDA fall timea
300
ns
tSU.STO
Stop set-up time
tDH
Data out hold-time
50
0.9
µs
0.6
0.9
a. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum
capacitance on both SDA and SCL.
55/61
µs
ns
0.6
0
ns
µs
STV0974
Electrical characteristics
Figure 31: I2C slave timing
Stop
Start
Start
SDA
tBUF
tR
tLOW
Stop
tHD.STA
tF
SCL
tHD.STA
Note:
5.5.3
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
tDH is the same timing as tHD.DAT. tDH is a value driven by the STV0974. tHD.DAT is the value
when the host is driving.
I2C master timing
Table 40: I2C master timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
200
400
kHz
fSCL
MSCL clock frequency a
tLOW
Clock pulse width low
1.1
µs
tHIGH
Clock pulse width high
0.6
µs
tBUF
Bus free time between transmissions
1.3
µs
tHD.STA
Start hold time
0.6
µs
tSU.STA
Start set-up time
0.6
µs
tHD.DAT
Data in hold time
0.15
tSU.DAT
Data in set-up time
100
tR
MSCL / MSDA rise time b
300
ns
tF
MSCL / MSDA fall time b
300
ns
tSU.STO
Stop set-up time
tDH
Data out hold-time
0.9
µs
0.9
ns
0.6
0
µs
µs
0.6
a. 200 kHz recommended through system patch. Please contact ST for details.
b. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum
capacitance on both MSDA and MSCL.
56/61
Electrical characteristics
STV0974
Figure 32: I2C master timing
Stop
Start
SDA
tBUF
Start
tLOW
tR
Stop
tHD.STA
tF
SCL
tHD.STA
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
i. tDH is the same timing as tHD.DAT. tDH is a value driven by the STV0974. tHD.DAT is the value
when the host is driving.
57/61
STV0974
5.5.4
Electrical characteristics
Video output timing
Table 41: Video output timing (Figure 33)
Symbol
tDS
Parameter
Min.
Data and synchro setup timea
Typ.
Max.
Unit
10
ns
10
ns
16
ns
tDH
Data and synchro hold time
tCKH
Clock pulse width high a
tCKP
Clock period a
44
ns
tCKR
Clock rise timea
5
ns
Max.
Unit
a
a. with a 12 pF capacitance
Figure 33: Video output timing
tCKP
tCKH
hclk
tDS
tCKR
tDH
Data[7:0]
hsync/vsync
5.5.5
Microprocessor read/write timing
Table 42: Microprocessor read and write cycle timingv
Symbol
Parameter
Min.
Typ.
tAS
RS, CSN valid to RDN or WRN low
7
ns
tAH
RS, CSN hold after RDN or WRN high
7
ns
tRACC
Read access time
40
ns
tLZ
RDN high to data high impedance
15
ns
tRP
Read pulse width
40
ns
tWP
Write pulse width
45
ns
tWDS
Data setup to WRN high
35
ns
tRREC
Read recovery time
30
ns
tWREC
Write recovery time
22
ns
tZL
RDN low to data low impedance
0
ns
tRDH
RDN low to data invalid
0
ns
tWDH
Data hold after WRN high
5
ns
58/61
Electrical characteristics
STV0974
Figure 34: Read cycle timing
RS
CSN
tAS
tAH
tRP
tRREC
RDN
(WRN high)
tLZ
tRACC
tZL
tRDH
Data[7:0]
Figure 35: Write cycle timing
RS
CSN
tAS
tAH
tWP
WRN
(RDN high)
tWREC
tWDS
tWDH
Data[0:7]
5.5.6
VisionLink serial receiver timing
Table 43: VisionLink serial receiver input timing (Figure 36)
Symbol
59/61
Parameter
Min.
Typ.
Max.
Unit
tDS
Data setup time
1
ns
tDH
Data hold time
2.7
ns
tCKP
Clock period
8.3
ns
STV0974
Electrical characteristics
Figure 36: VisionLink basic input timing
tCKP
PCLK
tDS
tDH
PDATA
Table 44: Receiver VisionLink / SubLVDS electrical characteristics
Symbol
Parameter
VI
Input common mode voltage range
VIDTH
Input differential threshold
(Va -Vaz)
tPWRUP/
PWRDN
Power-up/-down time
Min
Typ
Max
Unit
VDD /2 0.4
VDD/2
VDD/2 +
0.4
V
+/-200
mV
10
µs
+/-50
2
60/61
Package mechanical data
STV0974
6
Package mechanical data
6.1
Pin assignment
Figure 37: STV0974 pin assignment
1
2
3
4
5
6
7
8
9
10
A
VSS DIO2 DIO1 DIO0 RST
POR VDD
B
VCORE
VSS
VDDPOR
VDD
C
VSS
NC
NC
NC
TCK PDN
SCL
NC
TDO
SDA
VCORE
VSS
CLK
VSS
PCLKP
PDATAP
MSCL
VDD
PCLKN
PDATAN
MSDA
DIO8
VSS
VDD
TMS
VSS
TDI
D
E
F
G
H
J
VSS VCORE VSS
DIO3
VDD VCORE
DIO9
DIO10
K
DIO4 DIO5 VDD DIO6
61/61
DIO7 DIO13 DIO12 VSS DIO11 VDD
STV0974
6.2
Package mechanical data
Package dimensions
Table 45: TFBGA 6x6x1.20 56 2R10 0.50 - Package dimensions a b c
Reference
Min.
A
1.010
A1
0.150
A2
Typ.
Max.
Unit
1.200
mm
mm
0.820
mm
b
0.250
0.300
0.350
mm
D
5.850
6.000
6.150
mm
D1
4.500
E
5.850
6.000
mm
6.150
mm
E1
4.500
mm
e
0.500
mm
F
0.600
ddd
.eee
.fff e
d
0.750
0.900
mm
0.080
mm
0.15
mm
0.05
mm
a. Max mounted height is 1.20mm. Based on a 0.27mm ball pad diameter.
Solder paste is 0.15mm thickness and 0.27mm diameter.
b. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array.
Thin profile:
-The total profile height (Dim A) is measured from the seating plane to the top component
- A = (1.01 to 1.20) mm
- Fine pitch: e>1.00mm pitch
c. The terminal A1 corner must be identified on the top surface of the package by using a corner
chamfer, ink or metallized markings, indentation or other feature of package body or integral
heatslug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal
A1 corner.
d. The tolerance of position that controls the location of the pattern of balls with respect to datums A
and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located
on true position with respect to datums A and B as defined by e. The axis perpendicular to datum
C of each ball must lie within this tolerance zone.
e. The tolerance of position that controls the location of the balls within the matrix with respect to
each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and
located on true position as defined by e. The axis perpendicular to datum C of each ball must lie
within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the
respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.
.
62/61
Package mechanical data
STV0974
Figure 38: TFBGA 56 6x6x1.2 2R10 0.5
C
seating
plane
A
A1
A2
ddd
C
A
D
B
D1
e
F
F
e
E1
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10
0b (56 balls)
A1 corner index area
(see note 3)
bottom view
63/61
STV0974
7
PCB layout guide lines for the STV0974 and VS6552
PCB layout guide lines for the STV0974 and VS6552
Normal good PCB design practice should be observed for the layout of the STV0974.
Power and ground planes should be used to supply power to STV0974.
The high speed subLVDS signal pairs (PCLKP,PCLKN) and (PDATAP,PDATAN) should be routed as
balanced transmissions lines with a characteristic balanced impedance of between 80 to 120 Ω.
The two traces in the signal pair should be routed together and should be matched in length to
within +/-3mm. The pairs of balanced line traces should be matched in length to within +/- 10mm.
To save components, 100 Ω termination resistors are embedded in the high speed subLVDS signal
pairs (PCLKP/PCLKN) and (PDATAP/PDATAN) of the STV0974.
All passive components for the STV0974 should be placed in close proximity to the device,
including the decoupling capacitors. The decoupling capacitors for the VS6552 should be placed
close to the sensor.
64/61
65/61
100 nF
AVDD
2.8V
100 nF
AGND
VS6552
4.7k
1.8V
MSCL
MSDA
100 nF
1.8V
2 DIO12 can be used for flash mode
TCK
VSS x 11
VDD x 6
VDDPOR
MSCL
MSDA
PCLKN
PCLKP
PCLKN
PDATAN
PCLKP
TDI TMS
VCORE
POR
RST
SCL
SDA
DIO13
Note 2 DIO12
DIO11
10nF
SCL
SDA
HCLK
VSYNC
+VI/O
+VI/O
CLK
DIO[0:7] DATA[0:7]
HSYNC
DIO8
Note 1
VSYNC
DIO9
HCLK
DIO10
STV0974
PDATAP PDN
PDATAN
Note: 1 Low level shifter reference: 74VCX1632245
For connection details, contact ST.
GND
CEXT
VDD
PDN PDATAP
EXTCLK
POWERDOWN
8
1.8V
100 nF
CLK
+VI/O
Application schematics
STV0974
Application schematics
Figure 39: Mobile camera application, 8-bit parallel video interface, VI/O = 2.8V with low level shifter
GND
CEXT
AVDD
2.8V
100 nF
100 nF
VDD
1.8V
100 nF
CLK
AGND
VS6552
4.7k
1.8V
MSCL
MSDA
100 nF
Cd
1.8V
TCK
VSS x 11
VDD x 6
VDDPOR
MSCL
MSDA
PCLKN
TDI TMS
STV0974
VCORE
POR
RST
SCL
SDA
DIO13
DIO12
DIO11
DIO10
DIO9
PCLKP
PCLKP
PCLKN
DIO8
CLK
DIO[0:7]
PDATAN
PDATAP PDN
PDATAN
PDN PDATAP
10nF
IRQ
DRQ
RDN
WRN
CSN
RS
DATA[0:7]
EXTCLK
POWERDOWN
STV0974
Application schematics
Figure 40: Mobile camera application, microprocessor interface, VI/O = 1.8V, no low level shifter
66/61
Evaluation kit and demonstration boards
9
STV0974
Evaluation kit and demonstration boards
A number of support kits are available. The evaluation kit is recommended for evaluation and
system integration as it is an open system and electrical connections can be made from the EVK to
the host system. The demonstration boards are small kits that do not allow hard connections to the
customers system.
Table 46: Ordering details
Part Number
67/61
Description
STV-974-/552S-E01
Evaluation kit including base board, STV0974 plug in, flex attached VS6552 plug-in and
socketed VS6552 plug-in
STV-974/552S-R01
Demonstration board with flex attached VS6552
STV-974/552S-R02
Demonstration board with socketed VS6552
STV0974
Revision history
Revision history
Revision
Date
Comments
0.1
December 2003
Product preview, draft 10 released in ADCS
0.2
January 2004
Update of application schematics to reflect the changes on some pin name for the
VS6552.
Update of some register default values.
1
April 2004
Description of video compression block in Functional description.
Addition of Register Group 6 for flash mode (I²C register map.)
Review of register default values in I²C register map.
Review and update of device characteristics in Electrical characteristics
1
June 2004
Minor revision. Updated cross reference to Table 35
2
28 Oct 2004
Document status changed to datasheet to reflect the product maturity level.
Changes applied:
Table 21: Timing constraints : t5 value changed to 7 µs minimum (instead of 20µs)
Table 41: Video output timing (Figure 33) - Note 1 change capacitance value to
12pF( instead of 30 pF)
Section 3: Signal description: Added precisions about internal resistor for
PDATAP/N and PCLKP/N
Electrical characteristics: Modified IDDP typical value 5 µA (instead of 10).
PCB layout guide lines for the STV0974 and VS6552: Added one sentence about
embedded termination resistors in the STV0974.
3
23 Nov 2004
Minor revision. Format update.
References
[1]
ITU-R Rec.BT.656-4. Interfaces for digital component video signals in 525-line and 625-line
television system operating at the 4:2:2 level of recommendation ITU-R BT.601 (Part A), 19861992-1994-1995-1998
[2]
ITU-T Rec. T.81 (1992E) - ISO/IEC 10918-1:1993(E), Information Technology- Digital
compression and Coding of Continuous-tone Still Images - Requirements and Guidelines
68/69
STV0974
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of
such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication
or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.
This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical
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