• Integrates the IEEE 802.11b Physical Layer (Baseband) and the Media Access
Controller (MAC) for Supporting Standard Rates up to 11 Mbps
• Supports Antenna Diversity Algorithm, Automatic Receive Gain Control, Transmit Gain
Control, Transmit Filter for Japanese Regulatory and Differential or Single-ended I- and
Q- Baseband Signals
Integrates 160 KBytes of SRAM Organized in Five Banks of 32 KBytes Each, Offering
the Flexibility for Individually Configuring Each of Them as Program or Data Memory
Zero Wait States for Program Execution
Fast Data Transfers through DMA Channels
Low-power ARM7TDMI® RISC Processor
The BootsTrap Code Supports External SPI EEPROM for the Custom Configuration
Parameters Used during the Device Enumeration Phase as Well as Default Parameters
for First Time EEPROM Programming
Glueless Parallel Flash Memory Interface, Supporting up to 128 KBytes of Nonvolatile
Glueless External SRAM Interface for All MAC Operations, Supporting up to
128 KBytes of External Memory
Wired Equivalency Privacy (WEP) in Hardware Supporting 64-bit and 128-bit Keys
Hardware Implementation of TKIP
Hardware Implementation of AES Encryption Supporting Various Modes
The WLAN Functions Can Be Easily Changed or Updated to New Requirements Since
They are Implemented in Microcode
Supports 11 Mbps Rates with Automatic Fallback to 5.5, 2 and 1 Mbps
SPI Interface and 13 GPIO Pins
176-ball LFBGA Package
Low-voltage 1.8V Core Operation
Media Access
(MAC) and
Baseband with
PCI Interface
Block Diagram
SPI Interface
MAC Support
Unit (MSU)
Common Memory
Interface Controller
Boot ROM
Rev. 2390BS–WLAN–07/03
Note: This is a summary datasheet. A complete document is available
under NDA. For more information, please contact your local Atmel Sales
The AT76C506A is a single-chip baseband controller that can handle IEEE 802.11b
standard compliant data rates of up to 11 Mbps and provides all processing and functionality needed for the MAC protocol of IEEE 802.11b. The AT76C506A is a slave PCI
device that allows Host access to any memory location of the device. Power management support conforming to PCI Power Management Specification v1.1 is also provided
so that the device can be used for mini PCI applications.
The AT76C506A incorporates an ARM7TDMI processor using a sophisticated architecture to control the on-chip peripherals, manage the internal memory and allocate data
queue buffers as well as to communicate with the host through the PCI parallel bus. The
processor peripheral logic consists of a PCI bus interface, a Serial Peripheral Interface
(SPI), a MAC unit, a 802.11b baseband controller, a WEP/TKIP engine block, an AES
engine block, two memory controllers and the ARM® subsystem consisting of an Interrupt Controller, two 32-bit timers and an address decoder unit.
The ARM7TDMI core supports two alternative instruction sets. Powerful 32-bit code can
be executed by the processor in ARM operating mode. However, a 16-bit instruction
subset is also available in Thumb® mode. Thumb mode can be selected to exploit full
processor power with limited external memory resources. Note that ARM7TDMI operating mode can be changed at run time with negligible overhead.
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