FREESCALE MC33902

Freescale Semiconductor
Advance Information
Document Number: MC33902
Rev. 3.0, 8/2009
High Speed CAN Interface with
Embedded 5.0 V Supply
33902
The MC33902 is a high speed CAN physical interface. The device
includes an internal 5.0 V supply for the CAN bus transceiver, and
requires only a connection to a battery line.
The MC33902 provides 4 operation modes, including low power
modes with remote and local wake-up.
The device has very low sleep and standby current consumption.
Features
• High speed CAN interface for baud rates of 40 kb/s to 1.0 Mb/s
• Compatible to ISO11898 standard
• Single supply from battery. No need for a 5.0 V supply for CAN
interface
• I/O compatible from 2.75 V to 5.5 V via a dedicated input terminal
(3.3 V or 5.0 V logic compatible)
• Low Power mode with remote CAN wake-up and local wake-up
recognition and reporting
• CAN bus failure diagnostics and TXD/RXD pin monitoring, cold
start detection, wake-up sources reported through the ERR pin
• Enhanced diagnostics for bus, TXD, RXD and supply pins
available through Pseudo SPI via existing terminals EN, STBY
and ERR.
• Split terminal for bus recessive level stabilization
• INH output to control external voltage regulator
• Pb-free packaging designated by suffix code EF
HIGH SPEED CAN PHYSICAL INTERFACE
EF SUFFIX (PB-FREE)
98ASB42565B
14-PIN SOICN
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MCZ33902EF/R2
-40°C to 125°C
14 SOIC
VBAT
33902
Voltage
INH
WAKE
Regulator
VSUP
GND
INH
5V Reg
VIO
VDD
VDD
I/O
EN
ERR
CAN
Controller
Tx
TXD
Rx
RXD
I/O & Control
MCU
STBY
Bus
Diag.
CANH
SPLIT
Bus Driver
& Receiver
30
CAN bus
30
CANL
Figure 1. MC33902 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
INH
Detector
VSUP
WAKE
INH
5.0 V Regulator
control
Monitoring
VSUP
Pattern
Wake-up
Receiver
Detection
VIO
Vio
TXD
RXD
EN
STBY
Logic Control / Interface / P_SPI
Driver
Rin
2.5 V
CANH
Differential
Receiver
Rin
CANL
Thermal
Driver
ERR
QL
VDD
Failure Detection
GND
QH
Buffer
SPLIT
& Management
Figure 2. 33902 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
PIN CONFIGURATION
TXD
1
14
STBY
GND
2
13
CANH
VDD
3
12
CANL
RXD
4
11
SPLIT
VIO
5
10
VSUP
EN
6
9
WAKE
INH
7
8
ERR
Figure 3. 33902 Pin Connections
Table 1. 33902 Pin Definitions
Pin Number
Pin Name
Pin Function
Formal Name
Definition
1
TXD
Input
Transmit data
2
GND
Output
Ground
3
VDD
Output
Voltage Digital Drain
4
RXD
Output
Receive data
5
VIO
Input
Voltage supply for I/O
Input supply for the digital input output pins
6
EN
Input
Enable
Enable input for device static mode control.
CAN bus transmit data input pin
Ground termination
CAN dedicated internal voltage regulator, (decoupling capacitor required
for voltage stabilization)
CAN bus receive data output pin, wake-up flag in Low Power mode
MOSI (Master Out, Slave In) during P_SPI operation.
7
INH
Output
Inhibit
8
ERR
Output
Active low Error
Inhibit output for control of an external power supply regulator
Pin for static error and wake-up flag reporting
MISO (Master In, Slave Out) during P_SPI operation.
9
WAKE
Input
Wake
Wake input
10
VSUP
Input
Voltage supply
11
SPLIT
Output
Split
12
CANL
Input/output
CAN LOW
CAN low pin
13
CANH
Input/output
CAN HIGH
CAN high pin
14
STBY
Input
Standby
Battery supply pin
Output for connection of the CAN bus termination middle point
Standby input for device static mode control.
CLK (Clock) during P_SPI operation.
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Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
DC voltage on VSUP
VSUP
-0.3 to +40
V
DC voltage on CANL, CANH, SPLIT
VBUS
ELECTRICAL RATINGS
V
Continuous (Steady State)
-27 to +27
Transient Voltage (Load Dump)
-27 to +40
DC voltage on VIO
VVIO
-0.3 to 5.5
V
DC voltage on EN, STBY, ERR, TXD, RXD
VDIG
-0.3 to VIO +0.3
V
VWAKE
-0.3 to 29
V
ILH
200
mA
IVDD
240
mA
ESD on CANH, CANL and Split (HBM)
VESDCH
+-2000
V
ESD on CANH, CANL and Split (IEC61000-4, CZAP = 150 pF, Rzap = 330 Ω)
VESDIEC
+-8000
V
VESCH
+-2000
V
Junction temperature
TJ
150
°C
Ambient temperature
TA
-40 to 125
°C
Storage temperature
TST
-55 to 165
°C
RθJA
140
°C/W
DC voltage on Wake
Continuous current on CANH and CANL
DC current on VDD
ESD on all pins except CANH, CANL, Split (HBM)
THERMAL RATINGS
THERMAL RESISTANCE
Thermal resistance junction to ambient (SO14)
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Nominal voltage range
VSUPN
5.5
-
27
V
Extended voltage range, fully functional, parametric value(s) not
guaranteed
VSUPEX
4.5
-
5.5
V
ISUPSLEEP
-
10
ISUPSTB
-
14
30
µA
ISUPNORMAL
1.0
4.0
6.0
mA
INPUT PIN (VSUP)
Supply current in Sleep mode, VSUP ≤ 13.5 V, VIO = 0 V
Supply current in Standby mode (VSUP ≤13.5 V, 5 V enabled at VDD
terminal, default operation)
Supply current in Normal mode, TXD high
Supply current in Listen Only mode, TXD high
µA
ISUPLISTEN
1.0
4.0
6.0
mA
BATFAIL Flag internal threshold
VBFTHS
1.5
3.3
5.5
V
BATFAIL Flag hysteresis
VBFHYS
-
0.5
-
V
VSUV
-
5.8
-
V
VSUVHYS
-
0.2
-
V
VDDOUT
4.5
5.0
5.5
V
Drop voltage at IOUT = 100 mA
VDROP
-
-
500
mV
VDD low detection threshold
VDDTH
4.0
4.25
4.5
V
IOUT
150
-
-
mA
IOUTLP
5.0
-
100
µA
Thermal prewarning junction temperature (Available via P_SPI. ERR low
if ERR-EXT flag is set)
TPR
130
150
170
°C
Thermal shutdown (junction)
TSD
155
170
190
°C
Temperature threshold difference
TDIFF
20
-
-
°C
External Capacitor
CEXT
1.0
-
100
µF
VIO
2.75
−
5.5
V
Input Current in Normal and Listen Only modes, RXD and ERR PIN
current =0, TXD = high
IVIOLIST
5.0
30
200
µA
Input Current in Normal mode, TXD = 0 V (Normal and Listen Only)
IVIONORM
50
350
1000
µA
IVIOSLP-STBY
−
2.0
5.0
µA
VSUP under-voltage threshold (In Normal and Listen only)
VSUP under-voltage threshold hysteresis (In Normal and Listen only)
OUTPUT PIN (VDD)
Output Voltage
Output Current Capability, for information only. Current for CAN
tranceiver supply only.
Current Source Capability, in standby and Go To Sleep mode.
INPUT SUPPLY PIN (VIO)
Voltage range
Input Current in Standby or Sleep mode, VIO < 5.0 V
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Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
High Level Input Voltage
VIH
0.7 VIO
-
-
V
Low Level Input Voltage
VIL
-
-
0.3 VIO
V
IPD EN-STBY
1.0
4.0
10
µA
IPD TXD
-
-250
-
µA
VOUTLOW
0.0
-
0.3 VIO
V
VOUTHIGH
0.7 VIO
-
VIO
V
IOUTHIGH
-12
-5.0
-2.0
mA
IOUTLOW
2.0
5.0
12
mA
Output Drop Voltage (IINH), IOUT = 100 uA)
INHDROP
0.05
0.2
0.8
V
leakage Current (Sleep mode)
INHLEAK
-
-
5.0
µA
Low level threshold voltage
WAKELTH
2.0
2.5
3.0
V
High level threshold voltage
WAKEHTH
2.0
2.7
3.5
V
Input Current
IWAKEIN
-10
0
10
µA
VCOM
-12
-
12
V
Differential input voltage, recessive state at RXD
VCANH-VCANL-R
-
-
500
mV
Differential input voltage, dominant state at RXD
VCANH-VCANL-D
900
-
VDIFF-HYST
-
100
-
mV
Input resistance
RIN
5.0
-
50
kΩ
Differential input resistance
RIND
10
-
100
kΩ
Common mode input resistance matching
RINM
-3.0
0.0
3.0
%
CANH output voltage(45 Ω < RBUS < 65 Ω)
VCANH
LOGIC INPUT PINS (EN, STBY, TXD)
Pull-down Current, EN, STBY, VIN = VIO
Pull-up Current, TXD, VIN = 0 V
DATA OUTPUT PINS (RXD) AND (ERR)
Low Level Output Voltage
I = 5.0 mA
High Level Output Voltage
I = -3.0 mA
High Level Output Current
V = VIO - 0.4 V
Low Level Output Current
V = 0.4 V
OUTPUT PIN (INH)
INPUT PIN (WAKE)
VWAKE = -0.2 to 18 V
LOGIC INPUT/OUTPUT PINS (CANH, CANL)
Bus pins common mode voltage for full functionality
Differential input hysteresis (RXD)
mV
V
TX dominant state
2.75
3.5
4.5
TX recessive state
2.0
2.5
3.0
TX dominant state
0.5
1.5
2.25
TX recessive state
2.0
2.5
3.0
TX dominant state
1.5
2.0
3.0
V
TX recessive state
-500
0.0
50
mV
CANL output voltage(45 Ω < RBUS < 65 Ω)
Differential output voltage(45 Ω < RBUS < 65 Ω)
VCANL
V
VOH-VOL
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CANH output current capability - Dominant state
ICANH
-
-
-25
mA
CANL output current capability - Dominant state
ICANL
25
-
-
mA
CANL over-current detection - Error reported in register
ICANL-OC
75
120
195
mA
CANH over-current detection - Error reported in register
ICANH-OC
-195
-120
-75
mA
CANH, CANL input resistance device supplied and in Sleep mode,
VCANH, VCANL from 0 V to 5.0 V
RINSLEEP
5.0
-
50
kΩ
VCANLP
-0.1
0.0
0.1
V
-
-
250
-
-
400
LOGIC INPUT/OUTPUT PINS (CANH, CANL) (CONTINUED)
CANL, CANH output voltage in Sleep and Standby modes
(45 Ω < RBUS < 65 Ω)
CANH, CANL input current, device un supplied, VSUP and VIO connected
to GND (ref. fig.)
ICAN
VCANH, VCANL = 5.0 V
VCANH, VCANL = -2.0 to + 7.0 V
µA
CANH AND CANL DIAGNOSTIC INFORMATION
CANL to GND detection threshold
VLG
-
1.75
-
V
CANH to GND detection threshold
VHG
-
1.75
-
V
CANL to VBAT detection threshold, valid if VSUP > 7.0 V
VLVB
-
VSUP-2.0
-
V
CANH to VBAT detection threshold, valid if VSUP > 7.0 V
VHVB
-
VSUP-2.0
-
V
CANL to VDD detection threshold
VL5
-
VDD-0.43
-
V
CANH to VDD detection threshold
VH5
-
VDD-0.43
-
V
Loaded condition Isplit =+- 500 µA
0.3 VDD
0.5 VDD
0.7 VDD
Unloaded condition Rmeasure > 1.0 MΩ
0.45 VDD
0.5 VDD
0.55 VDD
-12 V < VSPLIT< +12 V
-
0.0
5.0
-22 V < VSPLIT< +35 V
-
-
70
SPLIT
Output voltage
Leakage current
VSPLIT
V
ILSPLIT
µA
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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TXD Dominant State Timeout
tDOUT
300
Bus dominant clamping detection
tDOM
300
600
900
µs
700
1000
Propagation loop delay TXD to RXD, recessive to dominant
µs
tLRD
Propagation delay TXD to CAN, recessive to dominant
tTRD
60
140
210
ns
-
70
110
Propagation delay CAN to RXD, recessive to dominant
ns
tRRD
Propagation loop delay TXD to RXD, dominant to recessive
tLDR
-
45
140
ns
50
120
200
Propagation delay TXD to CAN, dominant to recessive
ns
tTDR
Propagation delay CAN to RXD, dominant to recessive
tRDR
-
75
150
ns
-
50
140
Loop time TXD to RXD, Slew rate 1 (Selected by P_SPI)
Rec to Dom
Dom to Rec
ns
tLOOPSL1
50
-
310
ns
Loop time TXD to RXD, Slew rate 2 (Selected by P_SPI)
Rec to Dom
Dom to Rec
tLOOPSL2
50
-
310
ns
tWAKE
-
10
-
µs
VDIFF = 1.15 V, Ta =-40°C
2.5
-
-
VDIFF = 2.0 V, Ta =-40°C
2.0
-
-
VDIFF = 1.15 V, 25°C ≤ Ta ≤ 125°C.
2.0
-
-
-
35
-
µs
-
25
-
µs
tDEV-TR
8.0
-
15
µs
tLP-NP
-
35
-
µs
tH
-
35
-
µs
TIMING (REF TO FIG 7)
STATE MACHINE TIMING
External Wake-up Filter Time
3-Pulse pattern wake-up - Pulse width
Time to report local wake-up event
tPWIDTH
tLOC WAKE-
µs
REP
Time to report CAN wake-up event
tCAN WAKEREP
Device state transition time (P_SPI versus static mode change distinction)
except from Standby and Go To Sleep modes
Transition time from Standby mode to any mode
Transition time from go to sleep to Sleep mode («Go To Sleep» command)
VIO low to Sleep mode timing
VDD low to CAN driver disable timing
VDD low to regulator disable timing
tVIO- SLP
-
10
-
ms
tVDD-CANOFF
-
10
-
ms
tVDDOFF
-
50
-
ms
PSEUDO SPI (P_SPI)TIMING
P_SPI Operation frequency
FREQ
0.0625
-
4.0
MHz
SCLK Clock High Time
tWSCLKH
0.125
-
8.0
µs
SCLK Clock Low Time
tWSCLKL
0.125
-
8.0
µs
EN to Falling Edge of STBY
tSISU
40
-
-
ns
Falling Edge of STBY to EN
tSIH
40
-
-
ns
ERR rise Time
tRSO
-
25
50
ns
tFSO
-
25
50
ns
CL = 15 pF
ERR fall Time
CL = 15 pF
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 27 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
tVALID
-
-
50
ns
tCANON-OFF
-
-
20
µs
Time from Rising Edge of STBY to ERR valid data
Delay Between P_SPI Command and CAN in Normal Mode or CAN in Sleep
mode. Device in Normal mode (measured after P_SPI 8th clock cycle rising
edge).
TIMING DIAGRAMS
tPCLK
tWSCLKH
STBY
tWSCLKL
Dn
D7
D0
tSIH
tSISU
Di7
EN
Din
Di0
tVALID
ERR
Do6
Do7
Do0
EN and ERR state changed at STBY rising edge
Figure 4. P_SPI Timing
TXD
tLRD
0.7 VIO
tLDR
0.3 VIO
RXD
0.3 VIO
0.7 VIO
Figure 5. Propagation Loop Delay TXD to RXD
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
tTRD
TXD
0.7 VIO
tTDR
0.3 VIO
VDIFF
0.9 V
tRRD
RXD
0.5V
tRDR
0.7 VIO
0.3 VIO
Figure 6. Propagation Delays TXD to CAN and CAN to RXD
12 V
10 µF
VSUP
VIO
5.0 V
33902
100 nF
5.0 V
VDD
RBUS
60 Ω
STBY
15 pF
2.2 µF
CANH
EN
Signal generator
100 nF
TXD
CANL
RXD
GND SPLIT
CBUS
100 pF
All pins are not shown
Figure 7. Test Circuit for Timing Characteristics
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
TRANSMIT DATA (TXD)
This input is the CAN transmit data pin. It is the interface
from the MCU to the output on the CAN bus. If TxD is low
(dominant), then the signal on the CAN bus will be dominant
(CANH is ~5.0 V and CANL is ~0 V). If TxD is high
(recessive), then the signal on the CAN bus will be recessive
(CANH and CANL will be ~2.5 V). The TxD thresholds are
3.3 V and 5.0 V compatible (depending on VIO voltage) to
accommodate the implementation of various MCUs. There
are three slew rates available, which are selected via the
Pseudo SPI.
is expected to shut down, which would then turn off the MCU
and any other device that is powered up by the external
regulator. This should considerably decrease the module’s
current consumption.
GROUND (GND)
WAKE (WAKE)
Ground termination pin.
VOLTAGE DIGITAL DRAIN (VDD)
This is the dedicated embedded supply voltage for the
CAN interface. A capacitor must be connected to this pin.
CAN interface current is sourced from this pin if device is in
transmit and receive mode. In low power modes, current for
the CAN interface is sourced directly from the VSUP pin.
RECEIVE DATA (RXD)
This output pin is the CAN receive data. It is the interface
to the MCU, which reports the state of the CAN bus. If the
CAN bus is recessive (CANH and CANL ~2.5 V), then the
signal on RxD will be high (recessive). If the CAN bus is
dominant (CANH is ~5.0 V and CANL is ~0 V), then the
signal on RxD will be low (dominant). This pin is also an
active-low wake-up flag in low power, which reports a wakeup event to the MCU. RxD thresholds are 3.3 V and 5.0 V
compatible (depending on the VIO voltage) to accommodate
the implementation of various MCUs.
VOLTAGE SUPPLY FOR I/O (VIO)
This is the dedicated input supply pin to determine voltage
thresholds for the digital input/output pins. The VIO
thresholds range from 2.75 V to 5.5 V to accommodate the
implementation of 3.3 V or 5.0 V MCUs.
ENABLE (EN)
This is the enable input pin for device static mode control.
This pin is connected to the MCU to place transceiver in the
desired mode. Functional voltage thresholds are determined
by VIO voltage to accommodate the implementation of 3.3 V
or 5.0 V MCUs. MOSI (Master Out, Slave In) during Pseudo
SPI communication.
ACTIVE LOW ERROR (ERR)
The dedicated active low flag reporting pin reports any
static errors, flags and wake-ups to the MCU depending on
devices operating state. MISO (Master In, Slave Out) during
Pseudo SPI communication.
The Wake input pin is used to wake-up the device from
sleep mode after a Battery to Gnd, or Gnd to Battery
transition. This pin is usually connected to an external switch
in the application module, and SHOULD NOT be left open. If
Wake pin functionality is not being used, it should be
connected to GND to avoid false wake-ups. This pin exhibits
a high-impedance for low input current when implemented
below 18 V. If voltage exceeds 18V at the pin, a series
resistor should be used to limit the amount of current that the
device will start sinking.
VOLTAGE SUPPLY (VSUP)
This is the power supply input pin. The DC operating
voltage for the device is 5.5 V to 27 V. A reverse battery
protection diode should be implemented. This pin is able to
sustain automotive transient conditions, such as 40 V load
dumps and 27 V jump start conditions. The device’s
quiescent sleep current is typically around 10 μA.
SPLIT (SPLIT)
This is the output pin for middle point connection of CANH
and CANL when implementing split termination. Pin voltage
is typically around half of VDD (2.5 V) with or without loads.
This pin must be left open if split CAN termination is not
implemented.
CAN HIGH (CANH)
This is the CAN High input/output pin. CANH circuitry is
design to work as a high side switch connected to VDD. In the
recessive state, this switch is turned off and CANH is then
biased to SPLIT voltage or GND, depending on device’s
operating state. In the dominant state, the switch is turned on
and CANH is biased to VDD voltage. The CANH pin is
protected and diagnostics reporting is available against short
to Battery, Gnd, and 5.0 V (VDD).
INHIBIT (INH)
The inhibit output pin controls an external power supply
regulator. When the INH output is low, the external regulator
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Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CAN LOW (CANL)
STANDBY (STBY)
This is the CAN Low input/output pin. CANL circuitry is
design to work as a low side switch connected to GND. In the
recessive state, this switch is turned off and CANL is then
biased to SPLIT voltage or Gnd, depending on device’s
operating state. In the dominant state, the switch is turned on
and CANL is biased to GND voltage. The CANL pin is
protected and diagnostics reporting is available against short
to Battery, Gnd, and 5.0 V (VDD).
This is the standby input pin for device static mode control.
This pin is connected to the MCU to place transceiver in the
desired mode. Functional voltage thresholds are determined
by VIO voltage to accommodate the implementation of 3.3 V
or 5.0 V MCUs. CLK (Clock) during Pseudo SPI
communication.
33902
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
STATE DIAGRAMS
STBY 1
EN 1
and VIO > VIO low threshold
if VIO ON (2)
Normal mode (STBY 1, EN 1)
STBYB 1
EN 1
VDD ON, INH ON
STBYB 0
EN 1
Driver ON; Receiver ON, SPLIT 2.5 V
(From any state if
VI/O low, after
VDD ON, INH ON
TVIO-SLP, if
VSUP > VSUV
Terminated to ground, SPLIT HZ
ERR report: wake-up source &
(VDD low and CAN bus failure) (7)
STBY 1
EN 1
Go to sleep (STBY 0, EN 1)
ERR report: Wake-up
STBY 0
EN 1
STBY 1
EN 1
t>tH
STBY 0
EN 1
Sleep (STBY 0, EN 0)
VDD OFF, INH HZ (6)
Automatic transition
(4)
Terminated to ground, SPLIT HZ
Controlled transition
(4
)
ERR report: Wake-up (2)
STBY 1
EN 0
STBY 0
EN 0
STBY 1
EN 0
Listen Only (STBY 1, EN 0)
VDD ON, INH ON
Driver OFF; Receiver ON, SPLIT 2.5 V
Standby (STBY 0, EN 0)
STBY 1
EN 0
ERR report: BATfail) (1)
VDD ON (5), INH ON
STBY 0
EN 0
(VDD low, local failure) (3)
Legend:
Mode (STBY, EN)
Local or CAN
wake-up
Terminated to ground, SPLIT HZ
Power up
ERR report: Wake-up
STBY 1
EN 0
and with VIO > VIO low threshold
Power
Down
(VDD ON, INH)
(CAN, SPLIT)
if VIO ON (2)
(ERR)
Notes
1. Coming from Standby mode
2. If VI/O is still switched on
3.
4.
5.
Coming from Normal mode
If batfail flag and wake-up flag are cleared. An attempt to enter Sleep mode without batfail and wake-up flag cleared has no effect
Limited current capability, to maintain the capacitor at VDD charged.
6.
7.
A high level on INH will report a wake-up in Sleep mode
After 4 TXD pulses rising edge
Figure 8. State Diagram
33902
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 5. Functional Table
STBY
EN
Mode
VDD
ON
INH
(8)
0
0
Standby
0
0
Sleep
OFF
High
HZ
0
1
Go to sleep
ON
High
1
0
Listen Only
ON
High
1
1
Normal
ON
High
RXD
CAN
ERR (active low)
Active LOW:
report wake-up event (9)
Terminated to GND
Active LOW:
report wake-up event (9)
Receiver: ON
Driver: OFF
•Report local failure, VDD
low, Bat fail
Driver and
Receiver: ON
•wake-up source (10)
•BUS failures, VDD low
High: recessive state
Low: dominant state
Notes
8. With limited current capability, in order to maintain the capacitor at VDD pin charged
9.
10.
Provided if VIO > 2.5 V.
Before 4th TX pulse rising edge
VSUP
Start
5.8 V
VSUP_low
5.8 V
VSUP_low
5.0 V
VDD
VDD
VDD re-enabled
5.0 V
VDD_low
~3.0 V
End
VDD overload condition
4.25 V
4.25 V
CAN driver enabled
5.0 V
VDD_low
4.25 V
4.25 V
50 ms
(3)
VDD disabled
10 ms
CAN driver disable
VDD re-enabled (2)
50 ms
VDD disabled (3)
10 ms
CAN driver disabled
ERR(1)
MODE
Normal or Listen Only
Normal or Listen Only
ERR(1)
2
EN, STBY, VIO high
VDD low illustration, VSUP > VSUP low (VSUP > 5.8 V)
VDD low illustration, cranking pulse VSUP < VSUP low (VSUP < 5.8 V) and CRANK bit low in P_SPI register.
1) See figure on ERR reporting
2) VDD is re enabled when VSUP recovers (VSUP low flag goes from H to L) or by a mode change via EN and STBY input.
3) Capacitor charged maintained by internal device current source
Figure 9. VDD Low Illustration
33902
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
DEVICE STATE DESCRIPTION
LISTEN ONLY MODE
STANDBY MODE
Standby mode is a reduced current consumption mode.
CANH and CANL lines are terminated to GND, the SPLIT pin
is high-impedance. In order to monitor bus activities, the CAN
wake-up receiver is ON, INH output remains ON. The voltage
on VIO should be maintained.
The VDD regulator is ON with limited current capability, in
order to maintain the capacitor at VDD charged and allow a
fast transition to Normal mode and fast CAN communication.
Wake-up events occurring on the CAN bus or on the
WAKE pin are reported by a low level of the ERR and RXD
pins. The Standby mode is also the first mode entered after a
device power up. In this case, the VDD regulator is activated
to charge the VDD capacitor, and then the regulator enters the
reduced current capability mode, in order to optimize and
reduce system current consumption. Depending upon the
VDD capacitor ‘s Equivalent Series Resistance (ESR), a
voltage drop can be observed. See Figure 10.
5V
VDD low (4.25 V)
VE
device start-up
VE
VE
VE = esr x VDD current limitation
0V
EN, STBY
Main VDD
ON
wake-up event detected
Main regulator OFF
Weak regulator ON
Main VDD
ON
This mode is used to disable the CAN driver, but leave the
CAN receiver active. In this mode, the device is only able to
report the CAN state on the RXD pin. The TXD pin has no
effect on CAN bus lines. This mode is entered by setting the
EN and STBY pins to [0, 1].
In this mode, coming from Normal mode, the ERR pin
reports local failures occurring on the TXD and RXD pins, and
VDD low. When this mode is entered from the Standby mode,
the ERR pin reports the BATFAIL flag.
The VDD regulator is ON. The SPLIT pin is active and a
2.5 V biasing is provided on the SPLIT output pin.
GO TO SLEEP MODE
Go to sleep is an intermediate mode to ultimately set the
device in Sleep mode. The go to sleep is entered by setting
the EN and STBY pins to [1, 0]. If the EN and STBY pins are
maintained to [1,0] for a time longer than tH, the Sleep mode
is automatically entered. In go to Sleep mode, the VDD
regulator remains in its previous state and the SPLIT pin is
deactivated. INH is active.
SLEEP MODE
The Sleep mode is a low power mode. It is entered from
the Go To Sleep mode by setting the EN and STBY pins to [1
0], and automatically from Go To Sleep mode after tH. In
Sleep mode, the VDD regulator is turned off and the SPLIT
pin is deactivated, INH is high-impedance.
In Sleep mode and Go To Sleep mode, the device is able
to wake-up on CAN bus activity or transitions on the WAKE
pin. A wake-up from Sleep mode will set the device in
Standby mode. Sleep mode is also automatically reached if
the voltage at VIO is below the VIOTH for more time than
TVIO-SLP.
DEVICE MAIN FLAGS DESCRIPTION:
Sleep
Standby
Normal
Figure 10. VDD Regulator Start-up
NORMAL MODE
In Normal mode, both the CAN driver and receiver are ON.
In this mode, the CAN bus is controlled by the TXD pin level,
and the CAN bus state is reported on the RXD pin.
The VDD regulator is ON. It supplies the CAN driver and
receiver.The SPLIT pin is active and a 2.5 V biasing is
provided on the SPLIT output pin.
In Normal mode, the ERR pin reports the wake-up source
and the bus failure, after 4 TXD pulses. Normal mode is
entered by setting the EN and STBY pins high. Entering
Normal mode will clear the BATFAIL flag.
This section describes the flags available when the device
is controlled via the EN and STBY pins in a static manner (no
P_SPI control). Additional information and control are
possible using the Pseudo SPI (refer to Extended device
operation).
BATFAIL
This flag is set to signal that the voltage on the VSUP pin
has dropped below VBFTHS, particularly after the device was
disconnected from the battery. In Listen Only mode, the
BATFAIL flag will be available on the ERR pin, coming from
standby, Go To Sleep and Sleep modes. When VSUP is
below VBF threshold, all internal flags and registers are reset
to their initial condition.
CAN Bus Wake-up (WU)
From Standby or Sleep mode, this flag is set if a correct
pattern has been received on the CAN bus. This wake-up is
reported on ERR and RXD pins by a low level in Standby
mode, as well as in Sleep mode if VIO is present.
33902
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The flag is cleared by leaving the Normal mode or by a
P_SPI reading.
Using the P_SPI, it is possible to get detailed failure
information.
WAKE Pin - Local Wake-up (WU)
VDD low
From the Standby, Go To Sleep or Sleep mode, this flag is
set if a transition on the WAKE pin is detected. This wake-up
is reported on the ERR pin by a low level in Standby mode,
as well as in Sleep mode if VIO is present.
The wake-up flag is cleared by leaving the Normal mode
or by P_SPI reading.
VDD low flag is set in Normal and Listen Only mode when
VDD is below the VDD low threshold. After a time longer than
tVDD-CANOFF, the CAN is disabled and after a time longer than
tVDDOFF, the VDD regulator is disabled to avoid a battery
discharge.
If the CRANK bit is set high, the VDD regulator and CAN
will not be disabled if VSUP is below VSUV. When VSUP is
above VSUV, the CRANK bit has no effect.
VDD low flag is reported in Normal and Listen Only mode,
so the user can differentiate between local and bus failures
by changing modes and observing ERR staying low.
In case of a double failure (local and bus failure) at the
same time, the results will be the same: ERR low in Normal
and in Listen Only mode. However, this is unlikely to occur.
This flag is cleared when entering low power, or when VDD
is above VDD low threshold, plus the P_SPI reading.
The VDD regulator is re enabled as soon as VSUP rises
above VSUP low, or by a mode change (refer to the crank
pulse illustration).
The CAN is re-enabled as soon as VDD is above VDD low
threshold. (refer to crank pulse illustration).
Wake-up Source
Wake-up source is reported on the ERR pin by entering
Normal mode, before 4 TX pulses. The ERR pin is low to
indicate a local wake-up, and high to indicate CAN wake-up.
Local Failure
This flag is a logic «OR» of the following failures: TXD
dominant clamping, RXD recessive clamping, TXD-to-RXD
short-circuit and VDD low condition. This flag is reported in
Listen Only on the ERR pin coming from Normal mode.
Using the P_SPI, it is possible to get detailed failure
information.
BUS Failure
The BUS failure flag is set if the CAN transceiver detects
a bus line short-circuit condition to VSUP, VDD, or GND,
during five consecutive dominant-recessive cycles on the
TXD pin. In addition, this flag reports a bus dominant
clamping condition. In Normal mode, the bus failure flag is
available on the ERR pin.
ERR Pin
The ERR pin reports various information depending upon
the device state, the device state transition, and event on the
TXD pin.
Table 6 shows the diagnostic flag availability when the
device is controlled in a static manner.
Table 6. “Static” Diagnostic Flags
Flag
Accessibility
BATFAIL
Listen-Only mode (coming from Standby, Go-to-Sleep, Sleep)
Clearing Diagnostic
Leaving Normal mode
CANWU or Local WU
Standby, Go-to-Sleep, Sleep (provided VIO is present)
Leaving Normal mode or by setting the BATFAIL
Wake-up source
Normal mode (Before the fourth dominant to recessive edge on the
TXD pin)
Leaving Normal mode, or by setting BATFAIL flag.
BUS Failure
Normal mode (After the fourth dominant to recessive edge on the
TXD pin)
Re-entering Normal mode
Local Failure
Listen Only mode (coming from Normal mode)
Entering Normal mode or TXD high while RXD low.
VDD low
Normal mode (After the fourth dominant to recessive edge on the
TXD pin) and Listen Only mode (coming from Normal mode)
VDD > VDD low threshold
Evaluation mode
By RXD low, when coming from Sleep or Standby into Normal or
Listen Only modes.
RXD goes from low to high, to signal the device is ready
and has exited low power modes (TLP-NP parameter).
33902
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 11 shows the meaning of the ERR pin versus the device state, the state transition and the events on TXD.
ERR MEANING
DEVICE MODE
WAKE-UP SOURCE
NORMAL
STBY = 1
EN = 1
4 dominant
pulses at TXD
Local Wake-up => ERR low; CAN Wake-up => ERR high
STBY = 1
EN = 1
STBY = 1
EN = 1
STBY = 1
EN = 1
STBY = 1
EN = 0
STBY = 1
EN = 0
LISTEN ONLY
STBY = 1
EN = 0
GO TO SLEEP
STANDBY
SLEEP
BUS FAILURE,
VDDlow, Bus dom,
CANH or CANL short to GND
5.0 V or VBAT => ERR low
BATFAIL
VSUP Low =>ERR high
LOCAL FAILURE
VDD low, TXD-PD, RXD-PR, TXD short to RXD => ERR low
STBY = 1
EN = 0
STBY = 0
EN = X
STBY = 0
EN = X
STBY = 0
EN = X
STBY = 0
EN = X
STBY = 0
EN = X
WAKE-UP EVENT
CAN Wake-up or Local Wake-up => ERR low
Figure 11. ERR versus device state
CAN INTERFACE DESCRIPTION:
CAN Interface Supply
The supply voltage for the CAN driver is the VDD pin. The
CAN interface also has a supply path from the battery line,
through the VSUP pin. This path is used in CAN Sleep mode
to allow wake-up detection.
During CAN communication (transmission and reception),
the CAN interface current is sourced from the VDD pin.
During CAN low power mode, the current is sourced from the
VSUP pin.
CAN Driver Operation in Normal Mode
The CAN driver will be enabled as soon as the device is in
Normal mode and the TXD pin is recessive.
When the CAN interface is in Normal mode, the driver has
two states: recessive or dominant. The driver state is
controlled by the TXD pin. The bus state is reported through
the RXD pin.
When TXD is high, the driver is set in the recessive state,
and CANH and CANL lines are biased to the voltage set at
VDD divided by 2, approx. 2.5 V.
When TXD is low, the bus is set into the dominant state,
and the CANL and CANH drivers are active. CANL is pulled
low and CANH is pulled high.
The RXD pin reports the bus state: CANH minus the CANL
voltage is compared versus an internal threshold (a few
hundred mV).
If “CANH minus CANL” is below the threshold, the bus is
recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is
dominant and RXD is set low.
The SPLIT pin is active and provide a 2.5 V biasing to the
SPLIT output.
Normal Mode and Slew Rate Selection
The CAN signal slew rate selection is done via the P_SPI.
By default, and if no P_SPI is used, the device is in the fastest
slew rate. Three slew rates are available. The slew rate
controls the recessive to dominant and dominant to recessive
transitions, which are also dependent on CANH and CANL
capacitance. This also affects the delay time from the TXD
pin to the bus, and from the bus to RXD. The loop time is thus
affected by the slew rate selection.
Minimum Baud rate
The minimum baud rate is determined by the shortest TXD
permanent dominant timing detection. The maximum number
of consecutive dominant bits in a frame is 12 (6 bits of active
error flag and its echo error flag).
The shortest TXD dominant detection time of 300 μs leads
to a single bit time of: 300 μs / 12 = 25 μs.
So the minimum Baud rate is 1 / 25 μs = 40 kBaud.
33902
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Termination
Low Power Mode
The device supports the two main types of bus
terminations:
• Differential termination resistors between CANH and
CANL lines
In low power mode, the CAN is internally supplied from the
VSUP pin.
In low power mode, the CANH and CANL drivers are
disabled, and the receiver is also disabled. CANH and CANL
have a typical 40 kΩ impedance to GND. The wake-up
receiver can be activated if wake-up is enabled by the P_SPI
command. The SPLIT pin is high-impedance.
When the device is set back into Normal mode, CANH and
CANL are set back into the recessive level. This is illustrated
in the following diagram.
• Split termination concept, with the mid point of the differential termination connected to GND through a capacitor,
and to the SPLIT pin
• Refer to Typical Application and Bus Termination Options
and WAKE Pin Configuration on page 27
.
TXD
Dominant state
Recessive state
CANH-DOM
CANH
CANL/CANH-REC
2.5 V
CANH-CANL
CANL
CANL-DOM
High ohmic t termination (50kohms) to GND
RXD
SPLIT
2.5 V
MC33902: bus driver
High-impedance
MC33902: receiver
(bus dominant set by other IC)
Go to Sleep,
Sleep or Standby mode
Normal or Listen Only mode
Normal or Listen Only mode
Figure 12. Bus Signal in Normal and Low Power Mode
Wake-up
Pattern Wake-up
When the CAN interface is in Sleep mode with wake-up
enabled, the CAN bus traffic is detected. The CAN bus wakeup signal is a pattern wake-up. CAN wake-up cannot be
disabled.
In order to wake-up the CAN interface, the wake-up
receiver must receive a series of 3 consecutive valid
dominant pulses. This is the default setting in which the CAN
WU-pattern bit is set low. CAN WU-pattern bit can be set high
by P_SPI, and the wake up will occur after a single pulse
duration of a minimum of 4.0 μs.
A valid dominant pulse should be longer than tPWIDTH. The
3 pulses should occur in a time frame of 120 μs to be
considered valid. When 3 pulses pass these criteria the wake
signal is detected. This is illustrated in Figure 13.
CAN Wake-up Report
The CAN wake reports depend upon the low power mode
selected, Sleep or Standby. In Sleep mode, the INH pin is
activated. In Standby mode, the VIO voltage is present and
the wake-up is reported by the ERR and RXD pin low level.
Ref to Table 5.
.
CANH
CAN bus
Dominant
Pulse # 2
Dominant
Pulse # 1
Dominant
Pulse # 3
Dominant
Pulse # 4
CANL
Incoming CAN Message
Internal differential wake-up
receiver signal
Internal wake-up signal
min tPWIDTH
max 120 μs
Figure 13. Pattern Wake-up
33902
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CAN BUS DIAGNOSTIC
The aim is to implement a diagnostic of bus short-circuit to
GND, VBAT, and the internal application circuit board 5.0 V.
Several comparators are implemented on the CANH and
H5
Hb
TX
Logic
Diag
Hg
Lg
VR5
VBAT (12-14 V)
VRVB
VDD
VRG
L5
VRVB (VSUP-2.0 V)
CANH
VDD (5.0 V)
VR5 (VDD-.43 V)
CANH dominant level (3.6 V)
CANL
VRG
Lb
CANL lines. These comparators monitor the bus level in the
recessive and dominant states. The information is then
managed by the logic circuitry to properly determine the
failure and report it.
Recessive level (2.5 V)
VRG (1.75 V)
VRVB
CANL dominant level (1.4 V)
VR5
GND (0.0 V)
Figure 14. CAN Bus Simplified Structure Truth Table for Failure Detection
Table 7 indicates the state of the comparators in case of a bus failure, and depending upon the driver state.
Table 7. Failure Detection Truth Table
Failure description
Driver recessive state
Driver dominant state
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
No failure
1
1
0
1
CANL to GND
0
0
0
1
CANH to GND
0
0
0
0
Lb (threshold VSUP-2.0 V)
Hb (threshold VSUP-2.0 V)
Lb (threshold VSUP-2.0 V)
Hb (threshold VSUP-2.0 V)
No failure
0
0
0
0
CANL to VBAT
1
1
1
1
CANH to VBAT
1
1
0
1
L5 (threshold VDD-0.43 V)
H5 (threshold VDD-0.43 V)
L5 (threshold VDD-0.43 V)
H5 (threshold VDD-0.43 V)
No failure
0
0
0
0
CANL to 5.0 V
1
1
1
1
CANH to 5.0 V
1
1
0
1
Detection Principle
In the recessive state, if one of the two bus lines are
shorted to GND, VDD, or VBAT, the voltage at the other line
follows the shorted line, due to the bus termination
resistance. For example: if CANL is shorted to GND, the
CANL voltage is zero, the CANH voltage measured by the Hg
comparator is also close to zero.
In the recessive state, the failure detection to GND or
VBAT is possible. However, it is not possible with the above
implementation to distinguish which of the CANL or CANH
lines are shorted to GND or VBAT. A complete diagnostic is
possible once the driver is turned on, and in the dominant
state.
Number of Samples for Proper Failure Detection
The failure detector requires at least one cycle of the
recessive and dominant states to properly recognize the bus
failure. The error will be fully detected after 5 cycles of the
recessive-dominant states. As long as the failure detection
circuitry has not detected the same error for 5 recessivedominant cycles, the error is not reported.
Bus clamping detection
If the bus is detected to be in dominant for a time longer
than (tDOM), the bus failure flag is set and the ERR is set low
in Normal mode.
Such conditions could occur if the CANH line is shorted to
a high voltage. In this case, current will flow from the high
voltage short-circuit through the bus termination resistors
(60 Ω) and then in the Split terminal (if used), and through the
device CANH and CANL input resistors, which are terminated
to an internal 2.5 V biasing or to GND (Sleep mode).
Depending upon the high voltage short-circuit, the number
of nodes, usage of split terminal, RIN actual resistor, and
node state (sleep or active), the voltage developed across the
bus termination can be sufficient to create a positive
dominant voltage between CANH and CANL. The RXD pin
will be low. This would prevent the start of any CAN
33902
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
communication, and thus a proper failure identification
(requires 5 pulses on TXD). The bus dominant clamp circuit
will help to determine such failure situation.
RX Permanent Recessive Failure
The aim of this detection is to diagnose an external
hardware failure at the RX output pin and ensure that a
TXD
permanent failure at RX does not disturb the network
communication. If RX is shorted to a logic high signal, the
CAN protocol module within the MCU will not recognize any
incoming message. In addition it will not be able to easily
distinguish the bus idle state and can start communication at
any time. In order to prevent this, an RX failure detection is
necessary.
CANL&H
Diag
TX driver
Logic
Diff output
VIO/2
VIO
Rxsense
RXD
Diff
60
CANL
RX short to VDD
RX flag latched
RXD output
CANH
RX driver
Sampling
Sampling
VDD
RX flag
Prop delay
The RX flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 15. RX Path Simplified Schematic, Rx Short to VDD Detection
Implementation for Detection
The proposed implementation is to sense the RXD output
voltage at each low to high transition of the differential
receiver. Excluding the internal propagation delay, the RXD
output should be low when the differential receiver is low. In
case of an external short to VDD at the RXD output, RXD will
be tied to a high level and can be detected at the next low to
high transition of the differential receiver.
As soon as the RXD permanent recessive is detected, the
RXD driver is deactivated.
Once the error is detected, the flag is latched and the
driver is disabled. The error is reported at ERR pin and via
P_SPI.
Recovery Condition
The internal recovery is done by sampling a correct low
level at the Bus as shown in Figure 16.
CANL&H
Diff output
Sampling
RXD output
Sampling
Rx short to VDD
Rx flag latched
Rx no longer shorted to VDD
RX flag (internal signal)
Figure 16. RX Path Simplified Schematic, Rx Short to VDD Detection
33902
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Important Information for Bus Driver Reactivation RXD
The driver stays disabled until the failure is cleared (RX is
no longer permanent recessive). One transition on the CAN
bus (internal differential receiver transition), and the bus
driver is activated by entering into Normal mode.
TXD PERMANENT DOMINANT
Principle
If the TXD is set to a permanent low level, the CAN bus is
set into dominant level, and no communication is possible.
The 33902 has a TXD permanent time out detector. After the
timeout, the bus driver is disabled and the bus is released into
a recessive state. The TXD permanent flag is set.
Recovery
The TXD permanent dominant is used and activated in
case of a TXD short to RXD. The recovery condition for a
TXD permanent dominant (recovery means the re-activation
of the CAN drivers) is done by entering into a Normal mode
controlled by the MCU, or when TXD is recessive, while RXD
changes from recessive to dominant.
TXD TO RXD SHORT CIRCUIT:
In read mode, the following flags are available:
- CAN bus detail diagnostic
- Local failure diagnostic
- Voltage monitoring
- Wake-up flags, wake pin level
- P_SPI errors
- Device identification
P_SPI Diagram
Figure 17 illustrates the P_SPI operation. A clock signal
should be generated on the STBY pin, EN input operates as
Data In (MOSI) and the ERR output pin operates as Data Out
(MISO).
In order to start a P_SPI operation, the level at STBY
should be low (1), as shown in Figure 17. Bit D7 starts at the
rising edge of STBY. Bit D7 level should be opposite to the
level before. D7 is then internally sampled at the STBY falling
edge.
The sampling of opposite level at (1) and (3) is the
confirmation of a P_SPI message start.
Then the P_SPI bit D6 starts, and the device will drive the
ERR pin to a level opposite to the one when P_SPI started
(5): this is the confirmation that the device has correctly
detected a P_SPI message start (acknowledgement).
Principle
If TXD is shorted to RXD during incoming dominant
information, RXD is set low. Consequently, the TXD pin is low
and drives CANH and CANL into a dominant state. Thus the
bus is stuck in dominant state. No further communication is
possible.
D7
(2)
STBY
(4)
(1)
(3)
Detection and Recovery
The TXD permanent dominant time out will be activated
and release the CANL and CANH drivers. However, at the
next incoming dominant bit, the bus will then be stuck in
dominant again. The recovery condition is same as the TXD
dominant failure.
EN
EN
Adr
Device in Normal mode
EN=1
EN
EN
Adr
Device in Listen Only
EN=0
EXTENDED DEVICE OPERATION
P_SPI msg start
The device has extended functionality which allows device
control and diagnostic readings via the P_SPI (Pseudo Serial
Peripheral Interface), and using the STBY, EN and ERR pins.
ERR
ERR
P_SPI Operation
The P_SPI operation is similar to a standard SPI interface
operation in slave mode. It uses the EN, STBY and ERR pins,
which have the functions of MOSI, SCLK and MISO. There is
no chip select (CS).
In write mode, the following functions and control are
accessible:
- CAN driver slew rate selection
- ERR pin operation mode
- CAN wake-up mode
- CRANK mode operation
D6
(5)
ERR
ERR
ERR pin high at
P_SPI start
ERR pin low at
P_SPI start
P_SPI msg detected (=acknowledge)
Figure 17. : P_SPI Message Start
Full P_SPI Message:
Figure 4 describes the complete P_SPI message and
timing.
33902
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Distinction Between P_SPI and Traditional Operation.
If the device is in Normal mode and should stay in Normal
mode after the P_SPI command, the EN and STBY pins
should be 1,1 at end of the P_SPI command.
If the device is in Listen Only mode, EN and STBY pins
should be 0,1, in order to set or maintain the device in Listen
Only mode.
The distinction between static device control and control
via P_SPI is performed by the duration of the EN and STBY
level. If the EN and STBY levels change before a time of
“tDEV-TR” then the device detects a P_SPI operation. If the EN
and / or STBY levels are stable for a time longer than 15 μs,
then the device state will be changed according to EN / STBY
level and device state diagram.
This means that the device mode change is done after a
delay of typ tDEV-TR and consequently the P_SPI frequency
operation should be faster than (1 / (2 * tDEV-TR).
With tDEV-TR = 8.0 μs, the SPI equivalent frequency should
be greater than 62.5 kHz.
A min delay of 15 μs should be observed between two
P_SPI messages.
The delay is measured between the last transition of the
EN/STBY of the 1st message, and the 1st EN/STBY
transition of the next message.
End of P_SPI Message:
P_SPI Availability:
At the P_SPI message, the state of EN and STBY pins
should be in line with the device mode expectation:
example:
The P_SPI is operating only in Normal and Listen Only
mode. It is not operating in Standby and Sleep modes.
Table 8 is the mapping of the P_SPI register.
Time between 2 P_SPI Message:
Table 8. P_SPI Bit Mapping
D7
D6
D5
D4
D3
D2
D1
D0
MOSI
STAR
T
ADRR
Rb/W
MOSI 4
MOSI 3
MOSI 2
MOSI 1
MOSI 0
MISO
ERR
ACK=ER
Rb
MISO 5
MISO 4
MISO 3
MISO 2
MISO 1
MISO 0
MOSI
STAR
T
0
0 (read)
0
1
MISO
ERR
ACK=ER
Rb
0
BATFA
IL
X
MOSI
STAR
T
0
1 (write)
ERR_EXT
CAN SR1
CAN SR0
CAN WU - pattern
CRANK
MISO
ERR
ACK=ER
Rb
0
0
PASS ID1
PASS ID0
MET ID1
MET ID0
MOSI
STAR
T
1
0
1
MISO
ERR
ACK=ER
Rb
Bus
dom
VDD
temp
0
1
0
1
0
LxWU WILS CANW
U
0
Rx-PR CAN cur Tx-PD
1
0
1
Test/
def
1
0
1
VMONF SPIerr
0
1
0
1
CANF
0
0
1
VSO CANF2 VSUV CANF1 VIO low CANF0 VDDlo
V
w
Low power mode definition: Standby, Go To Sleep and
Sleep modes.
Description
VSUP voltage < VSUP low threshold, also called Power On flag
Set
VSUP below VBFTH (3.3 V)
Reset
Entering Normal mode or P_SPI reading (Listen Only)
Action
Avoid entering Go To Sleep. Set ERR low in Listen Only mode coming from low power modes
BATFAIL
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22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Description
Wake-up event occurred on the WAKE pin
Set
In low power mode, by a local wake pin transition
Reset
Exit Normal mode or P_SPI reading (Listen Only and Normal mode)
Action
Avoid entering Go To Sleep mode. Set ERR low in low power modes
Description
Wake-up event occurred on CAN bus
Set
In low power mode, by CAN wake-up
Reset
Exit Normal mode or P_SPI reading (Listen Only and Normal mode)
Action
Avoid entering Go To Sleep mode. Set ERR and RXD low in low power modes
Description
Voltage monitoring flag: OR of VSOV, VSUV, VIO, VDDLOW, VDD prewarning Temp
Set
In normal and listen only modes: OR of VSOV, VSUV, VIO, VDDLOW, VDD prewarning Temp
Reset
Entering low power mode or (Failure removed + P_SPI reading (Listen Only and Normal mode))
Action
If ERR_EXT is set, ERR pin set low. ERR is low for the VDD low flag, despite the ERR-EXT bit.
Description
Failure on the CAN bus. OR of CANF2, CANF1, CANF0 bits
Set
In Normal and Listen Only modes: OR of TXDPD, RXDPR, CANcur, CAN bus failures
Reset
Entering low power mode or (Failure removed + P_SPI reading (Listen Only and Normal mode))
Action
Depending upon failure. ref to detail flag description
Description
Real time WAKE input level. Low is WAKE below threshold, high is WAKE above threshold.
Set
WAKE pin higher than threshold
Reset
WAKE pin lower than threshold
Action
No action
Description
Pseudo SPI error: Incomplete transmission error during start of P_SPI
Set
When P_SPI frame does not have 8 clock pulses
Reset
Entering low power mode or P_SPI reading (Listen Only and Normal mode)
Action
P_SPI wrong command is ignored
Description
ERR pin operation report all flags
Configure
By P_SPI
Reset
Entering low power mode
Action
When high, extend the ERR output pin to report all flags (when available) in any modes. When low
(default) ERR reports default flags.
LxWU
CANWU
VMONF
CANF
WILS
SPIerr
ERR_EXT
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Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Description
00: CAN slew rate 0
11: CAN slew rate 0
01: CAN slew rate 1
10: CAN slew rate 2
CANSR (1,0)
CAN WU pattern
CRANK
PASS ID(1,0),
METID(1,0)
Configure
By P_SPI in Listen Only and Normal mode
Reset
Entering low power mode
Action
Change CAN slew rate (ref to parametric). Default is 00.
Description
Select between 2 wake-up mechanisms
Configure
By P_SPI in Listen Only and Normal mode
Reset
Leaving low power mode
Action
When high wake-up occurs after 1 pulse of a minimum of 4.0 μs (parameter). When low, (default) wakeup occurs after 3 pulses of a minimum of 600ns (parameters).
Description
When this flag is set, the VDD low condition does not disable CAN and VDD regulator, if VSUV flag is set.
Configure
By P_SPI in Normal and Listen Only modes
Reset
Entering low power mode or P_SPI write (Listen Only and Normal mode)
Action
No disable of CAN and VDD regulator in case of a VDD low condition, and the VSUV flag is set. ERR reports
a VDD low condition. The P_SPI VDD low flag is set.
Set
Report device internal identification
Reset
Action
Description
Detect a bus voltage dominant for a time longer than tDOM.
Set
This flag is set if the bus is detected to be in dominant for more than tDOM
Reset
Entering low power mode, bus recessive P_SPI reading (Listen Only and Normal mode)
Action
No action, set ERR low in Normal mode
Description
Over-current occurred on the CANH or CANL driver
Set
In Normal mode, if the CANH or CANL current exceed the threshold (parameter)
Reset
Entering low power mode, the CAN current below threshold + P_SPI reading (Listen Only and Normal
mode)
Action
By default no action. If the ERR-EXT bit is set, the ERR is set low.
BUS dom
CAN cur
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RX-PR
TX-PD
Description
RXD short to high (recessive level)
Set
In Normal and Listen Only modes, if the RXD permanent recessive condition is detected
Reset
Entering low power mode, the RXD recovery condition reached + P_SPI reading (Listen Only and Normal
mode)
Action
Set the local failure flag, disable the CAN driver, set ERR low in Listen Only mode coming from Normal
mode
Description
TXD permanent dominant
Set
In NORMAL modes, if TXD permanent dominant condition detected
Reset
Entering low power mode, TXD recovery condition reached + P_SPI reading (Listen Only and Normal
mode)
Action
Set the local failure flag, disable the CAN driver, set ERR low in Listen Only mode coming from Normal
mode
Description
0 0 0: No CAN bus failure
0 0 1:CANL short to GND
0 1 0: CANL short to VDD
0 1 1: CANL short to VBAT
1 0 1: CANH short to GND
1 1 0: CANH short to VDD
CANF (2,1,0)
1 1 1: CANH short to VSUP
Set
In Normal modes, if CAN failure condition detected
Reset
Entering low power mode, CAN failure recovery condition reached + P_SPI reading (Listen Only and
Normal mode)
Action
Set the bus failure flag, set the ERR low in Normal mode after 4 Tx pulses
Description
VDD regulator reaches temperature prewarning
Set
In Normal mode or Listen Only mode, if the VDD temperature reaches the prewarning threshold
Reset
Real time report, reset if the temperature falls below the prewarning threshold
Action
By default no action. If the ERR-EXT bit is set, ERR is set low.
Description
VSUP over-voltage detected
Set
In Normal and Listen Only modes, if the VSUP over-voltage threshold condition detected
Reset
Entering low power mode, VSUP over-voltage threshold condition recovered + P_SPI reading (Listen Only
and Normal mode)
Action
By default no action. If the ERR-EXT bit is set, the ERR is set low.
VDD temp
VSOV
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Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VSUV
VIO low
VDD low
Description
VSUP under-voltage detected
Set
In Normal and Listen Only modes, if the VSUP under-voltage threshold condition detected
Reset
Entering low power mode, VSUP under-voltage threshold condition recovered + P_SPI reading (Listen
Only and Normal mode)
Action
When VSUP voltage rises above the VSUS threshold, the VDD regulator is re-enabled if disabled previously
by a VDD low condition
Description
VIO low detected
Set
In all modes, if VIO under-voltage threshold condition detected
Reset
Entering low power mode, VIO under-voltage threshold condition recovered + P_SPI reading (listen only
and normal mode)
Action
After 10ms, set the device in Sleep mode, if VSUV low (don’t enter Sleep mode during crank and power
up phase).
Description
VDD voltage < VDDLOW flag threshold
Set
In all modes, if VDD under-voltage threshold condition detected
Reset
Entering low power mode, VDD under-voltage threshold condition recovered + P_SPI reading (Listen Only
and Normal mode), mode change between Normal and Listen Only if VDD regulator was turned off
previously by a VDD low condition for more than 50ms.
Action
After 10 ms, disable the CAN, after 50 ms disable the regulator, if CRANK bit is set low (default).
33902
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Typical application
VBAT
D1
VBAT
VSUP
C7
WAKE
C1
C4
VIN
GND VREG
VOUT
EN
S
INH
VDD
2.75 V to 5.0 V
VIO
C2
VCC
Micro
controller
component list:
D1: 1N4004 type
C1: >=100 nF
C2: >=100 nF
C3: >=2.2 μF
C4: >=50 pF
C5:>=50 pF
C6: 1.0 to 10 nF
C7: 1.0 to 63 μF
R1: 22 kΩ
Rb: customer defined, ex 10 kΩ
Rb
R1
C3
MC33902
EN
GPIO
CANH
STBY
ERR
CAN
Tx
Protocol
Controller Rx
SPLIT
CAN bus
C6
30 Ω
TXD
RXD
C4
30 Ω
CANL
GND
C5
Supported CAN terminations
Split termination
CANH
30 Ω
Standard termination
CANH
C4
SPLIT
SPLIT
CAN bus
C6
30 Ω
No termination
CANL
CANH
C4
No
connect
60 Ω
CAN bus
CANL
SPLIT
C4
No
connect
CAN bus
CANL
C5
C5
C5
ECU connector
MC33902: WAKE Pin Configurations
Switch to GND
Switch to VBAT
VBAT
R1
S
Rb
R1
WAKE
WAKE
WAKE
C4
Unused WAKE
VBAT
S
C4
Rb
Figure 18. Typical Application and Bus Termination Options and WAKE Pin Configuration
33902
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
COMPARISON WITH COMPETITION 14 PIN HIGH SPEED CAN TRANSCEIVER
COMPARISON WITH COMPETITION 14 PIN HIGH SPEED CAN TRANSCEIVER
The table below is a comparison between the MC33902 and the competition 14 pin high speed CAN transceiver having no
embedded power supply.
Item
MC33902
Competition w/o Embedded Regulator
VDD pin
Output. Requires local decoupling capacitor(s). No extra
load should be connected.
Input. Requires connection to a 5.0 V supply.
Wake pin
Fixed threshold typ 3.0 V with hysteresis. No pull-up or
pull-down. High-impedance input. Connect to GND when
not used.
Threshold VBAT -3.0 V. Active pull-up when input is above
threshold. Active pull-down when input is below threshold.
ERR pin
Active low, reports flags, or used as MISO during P_SPI
communication. Strong driver (capability typ. 3.0 mA).
Active low, reports flags, weak driver, requiring 8.0 μs
stabilization time
EN and STBY pins Input used for static mode control. Used as CLOCK and
MOSI during P_SPI communication.
Input used for mode control.
Bus dom failure
flag
Failure reported on ERR pin in Normal mode
Failure reported on the ERR pin in Listen Only mode
(considered as a bus failure => reported in Normal mode) (considered as a local failure)
VDD low flag
No effect on device mode. Failure on CAN transceiver
supply should not affect the complete ECU. VDD is
disabled “locally” to reduce current consumption. The
ERR pin is set low in Normal and Listen Only mode. VDD
low threshold set at 4.25 V
Set the device into Sleep mode. INH is turned OFF. If the ECU
regulator is controlled by INH, ECU is turned OFF.
VIO low flag
Same
Same
Wake-up time
From Sleep or Standby mode, device needs 35 μs typ. to
be ready.
No need for a delay for device ready.
Transition time
At least 8.0 μs, to differentiate between a static transition
and P_SPI communication
Immediate transition. However, the ERR pin has weak driver
and an 8.0 μs stabilization time is required. When the device
is switched between Normal and Listen Only mode to check
the fail flag, a delay of 8.0 μs is needed.
33902
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ASB42565B listed below.
EF-PIN (PB-FREE)
98ASB42565B
ISSUE H
33902
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
REVISION HISTORY
REVISION HISTORY
REVISION
3.0
DATE
8/2009
DESCRIPTION OF CHANGES
• Initial Release
33902
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC33902
Rev. 3.0
8/2009