FOD8001 High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Features Description ■ High Noise Immunity characterized by Common Mode The FOD8001 is a 3.3V/5V high-speed logic gate Optocoupler, which supports isolated communications allowing digital signals to communicate between systems without conducting ground loops or hazardous voltages. It utilizes Fairchild’s proprietary coplanar packaging technology, Optoplanar ®, and optimized IC design to achieve high noise immunity, characterized by high common mode rejection and power supply rejection specifications. Rejection (CMR) and Power Supply Rejection (PSR) specifications – 20kV/µs Minimum Static CMR @ Vcm = 1000V – 25kV/µs Typical Dynamic CMR @ Vcm = 1500V, 20MBaud Rate – PSR in excess of 10% of the supply voltages across full operating bandwidth ■ High Speed: – 25Mbit/sec Date Rate (NRZ) – 40ns max. Propagation Delay – 6ns max. Pulse Width Distortion – 20ns max. Propagation Delay Skew ■ 3.3V and 5V CMOS Compatibility ■ Extended industrial temperate range, -40°C to 105°C temperature range ■ Safety and regulatory pending approvals: – UL1577, 3750 VACRMS for 1 min. – IEC60747-5-2 (pending) This high-speed logic gate optocoupler, packaged in a compact 8-pin small outline package, consists of a highspeed AlGaAs LED driven by a CMOS buffer IC coupled to a CMOS detector IC. The detector IC comprises an integrated photodiode, a high-speed transimpedance amplifier and a voltage comparator with an output driver. The CMOS technology coupled to the high efficiency of the LED achieves low power consumption as well as very high speed (40ns propagation delay, 6ns pulse width distortion). Related Resources ■ www.fairchildsemi.com/products/opto/ Applications ■ www.fairchildsemi.com/pf/FO/FOD0721.html ■ Industrial fieldbus communications ■ www.fairchildsemi.com/pf/FO/FOD0720.html – Profibus, DeviceNet, CAN, RS485 ■ Programmable Logic Control ■ Isolated Data Acquisition System ■ www.fairchildsemi.com/pf/FO/FOD0710.html Functional Schematic VDD1 1 8 VDD2 VI 2 7 NC 3 6 VO * GND1 4 Truth Table VI LED H OFF L ON VO H L 5 GND2 *: Pin 3 must be left unconnected ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler December 2010 Pin Number Pin Name 1 VDD1 2 VI Pin Function Description Input Supply Voltage Input Data 3 LED Anode – Must be left unconnected 4 GND1 Input Ground 5 GND2 Output Ground 6 VO Output Data 7 NC Not Connected 8 VDD2 Output Supply Voltage Absolute Maximum Ratings (TA = 25°C Unless otherwise specified.) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Value Units TSTG Storage Temperature -40 to +125 °C TOPR Operating Temperature -40 to +105 °C TSOL Lead Solder Temperature (Refer to Reflow Temperature Profile) 260 for 10 sec °C 0 to 6.0 V VDD1, VDD2 Supply Voltage VI Input Voltage II Input DC Current -0.5 to VDD1 + 0.5 V -10 to +10 µA VO Output Voltage -0.5 to VDD2 + 0.5 V IO Average Output Current 10 mA PDI Input Power Dissipation(1)(3) 90 mW PDO Dissipation(2)(3) 70 mW Total Power Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Max. Unit -40 +105 °C Operation)(4) 3.0 3.6 V Supply Voltages (5.0V Operation)(4) 4.5 5.5 VIH Logic High Input Voltage 2.0 VDD VIL Logic Low Input Voltage 0 0.8 V tr, tf Input Signal Rise and Fall Time 1.0 ms TA VDD1, VDD2 Ambient Operating Temperature Min. Supply Voltages (3.3V V Notes: 1. Derate linearly from 25°C at a rate of tbd W/°C 2. Derate linearly from 25°C at a rate of tbd mW/°C. 3. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings. 4. 0.1µF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 2 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Pin Definitions Symbol VISO RISO CISO Characteristics Input-Output Isolation Voltage Isolation Resistance Isolation Capacitance Test Conditions f = 60Hz, t = 1.0 min, II-O VI-O = ≤ 10µA(5)(6) 500V(5) VI-O = 0V, f = 1.0MHz(5) Min. Typ.* Max. Unit 3750 — — VacRMS 1011 — — Ω — 0.2 — pF Notes: 5. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 6. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration. Electrical Characteristics (Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C) Symbol Parameter Conditions Min. Typ. Max. Units INPUT CHARACTERISTICS IDD1L Logic Low Input Supply Current VI = 0V 6.2 10.0 mA IDD1H Logic High Input Supply Current VI = VDD1 0.8 3.0 mA IIA, IIB Input Current +10 µA -10 OUTPUT CHARACTERISTICS IDD2L Logic Low Output Supply Current VI = 0V 4.5 9.0 mA IDD2H Logic High Output Supply Current VI = VDD1 4.5 9.0 mA VOH Logic High Output Voltage IO = -20µA, VI = VIH, VDD2 = +3.3V 2.9 3.3 IO = -4mA, VI = VIH, VDD2 = +3.3V 1.9 2.9 VOL Logic Low Output Voltage ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 IO = -20µA, VI = VIH, VDD2 = +5.0V 4.4 5.0 IO = -4mA, VI = VIH, VDD2 = +5.0V 4.0 4.8 V IO = 20µA, VI = VIL 0 0.1 IO = 4mA, VI = VIL 0.3 1.0 V www.fairchildsemi.com 3 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Isolation Characteristics (Apply over all recommended conditions, typical value is measured at TA = 25°C) VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C) Symbol Parameter Test Conditions Min. Typ. Max. Unit tPHL Propagation Delay Time to Logic Low Output CL = 15pF 25 40 ns tPLH Propagation Delay Time to Logic High Output CL = 15pF 25 40 ns PWD Pulse Width Distortion, | tPHL – tPLH | PWD = 40ns, CL = 15pF 2 6 ns 25 Mb/s 20 ns Data Rate tPSK Propagation Delay Skew CL = 15pF(7) tR Output Rise Time (10%–90%) 6.5 ns tF Output Fall Time (90%–10%) 6.5 ns |CMH| Common Mode Transient Immunity at Output High VI = VDD1, VO > 0.8 VDD1, VCM = 1000V(8) 20 40 kV/µs |CML| Common Mode Transient Immunity at Output Low VI = 0V, VO < 0.8V, VCM = 1000V(8) 20 40 kV/µs CPDI Input Dynamic Power Dissipation Capacitance(9) 30 pF CPDO Output Dynamic Power Dissipation Capacitance(9) 3 pF Notes: 7. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low. 9. Unloaded dynamic power dissipation is calculated as follows: CPD x VDD x f + IDD + VPD where f is switched time in MHz. ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 4 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Switching Characteristics (Apply over all recommended conditions, typical value is measured at Figure 1. Typical Output Voltage vs. Input Voltage 4.0 Figure 2. Input Voltage Switching Threshold vs. Input Supply Voltage 2.0 VDD1 = VDD2 = 3.3V VITH - Typical Input Voltage Swicthing Threshold (V) 3.5 VO - Output Voltage (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VDD2 = 3.3V 1.8 1.6 1.4 1.2 1.0 0 1 2 3 4 5 3.0 3.5 VI - Input Voltage (V) Figure 3. Propogation Delay vs. Ambient Temperature 32 4.0 4.5 5.0 5.5 VDD1 - Input Supply Voltage (V) Figure 4. Pulse Width Distortion vs. Ambient Temperature 4.0 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V 3.5 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V PWD - Pulse Width Distortion (ns) t P - Propagation Delay (ns) 30 28 26 t 24 t PHL PLH 3.0 2.5 2.0 1.5 1.0 22 0.5 0.0 20 -40 -20 0 20 40 60 80 -40 100 -20 TA - Ambient Temperature (°C) Figure 5. Typical Rise Time vs. Ambient Temperature 7.5 0 20 40 60 TA - Ambient Temperature (°C) 80 100 Figure 6. Typical Fall Time vs. Ambient Temperature 7.5 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V 7.0 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V 7.0 tf - Fall Time (ns) t r - Rise Time (ns) 6.5 6.5 6.0 5.5 5.0 6.0 4.5 5.5 4.0 -40 -20 0 20 40 60 80 100 -40 TA - Ambient Temperature (°C) ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 -20 0 20 40 60 TA - Ambient Temperature (°C) 80 100 www.fairchildsemi.com 5 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Typical Performance Curves Figure 7. Typical Propogation Delay vs. Output Load Capacitance Figure 8. Typical Width Distortion vs. Output Load Capacitance 34 2.6 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V 2.4 PWD - Pulse Width Distortion (ns) 32 t P - Propagation Delay (ns) Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V 30 t PHL 28 26 t PLH 2.2 2.0 1.8 1.6 1.4 24 1.2 22 1.0 15 20 25 30 35 40 45 50 55 15 20 25 C L - Output Load Capacitance (pF) Figure 9. Typical Rise Time vs. Output Load Capacitance 12 11 35 40 45 50 55 Figure 10. Typical Fall Time vs. Output Load Capacitance 16 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V 14 10 12 9 tf - Fall Time (ns) tr - Rise Time (ns) 30 C L - Output Load Capacitance (pF) 8 7 10 8 6 6 4 5 2 4 15 20 25 30 35 40 45 C L - Output Load Capacitance (pF) 50 15 55 20 25 30 35 40 45 50 55 C L - Output Load Capacitance (pF) Figure 11. Input Supply Current vs. Frequency Figure 12. Output Supply Current vs. Frequency 6.0 6.5 VDD1 = 5.5V V DD1 = VDD2 = 5.5V * Pin 6 Floating 6.0 T = 105°C 5.0 T = 25°C IDD2 - Output Supply Current (mA) IDD1 - Input Supply Current (mA) 5.8 5.5 A A 4.5 T = -40°C A 4.0 T = 25°C A 5.6 TA = -40°C 5.4 T = 105°C A 5.2 3.5 5.0 3.0 0 2000 4000 6000 8000 f - Frequency (kHz) ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 10000 0 12000 2000 4000 6000 8000 f - Frequency (kHz) 10000 12000 www.fairchildsemi.com 6 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Typical Performance Curves (Continued) 1 8 2 7 0.1µF VDD1 = 3.3V 0.1µF 0V–3.3V 3 VDD2 = 3.3V VO 6 Pulse width = 40ns Duty Cycle = 50% CL 4 5 tPLH tPHL 3.3V Input 50% VIN VOH 90% Output 50% VOUT 10% VOL tR tF Figure 13. Test Circuit for Propogation Delay Time and Rise Time, Fall Time 1 8 2 7 0.1µF SW 0.1µF VDD2 = 3.3V B A 3 VDD1 = 3.3V VO 6 CL 4 5 + – VCM 1kV VCM GND VOH Switching Pos. (A) VIN = 3.3V CMH 0.8 x VDD 0.8V VOL Switching Pos. (B) VIN = 0V CML Figure 14. Test Circuit for Instantaneous Common Mode Rejection Voltage ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 7 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Test Circuits Noise is defined as any unwanted signal that degrades or interferes with the operation of a system or circuit. Input-output noise rejection is a key characteristic of an optocoupler, and the performance specification for this noise rejection is called, “Common Mode Transient Immunity or Common Mode Rejection, CMR”. The CMR test configuration is presented in high speed optocoupler datasheets, which tests the optocoupler to a specified rate of interfering signal (dv/dt), at a specified peak voltage (Vcm). Test circuit functions were built to interface a commercial pseudo-random bit sequence (PRBS) generator and error detector with a pair of high speed optocouplers, FOD8001, connected in a loop-back configuration. With a 10MBaud PRBS serial data stream, no error was detected until the common mode voltage rose above 2.5kV with a dv/dt of 45kV/us. And increasing the data rate beyond 10Mbaud, the test was conducted at 20MBaud, and no error was detected at dv/dt of 25kV/us at common mode voltage of 1.5kV. This defined noise signal is applied to the test device while the coupler is a stable logic high or logic low state. This test procedure evaluates the interface device in a constant or static logic state. This type of CMR can be referred to as “Static CMR”. Fairchild’s high speed optocouplers, which use an optically transparent, electrically conductive shield, and offer active totem pole logic output have static CMR in excess of 50KV/us at peak amplitudes of 1.5kV to 2.0kV. The test data for the dynamic CMR is comparable or better than the static CMR specifications found in the datasheet. These excellent noise rejection performances are results of the innovative circuit design and the proprietary coplanar assembly process. Power Supply Noise Rejection High levels of electrical noise can cause the optocoupler to register the incorrect logic state. The most commonly discussed noise signal is the common mode noise found between the input and output of the optocoupler. However, common mode noise is not the only path of noise into the input or output of the optocoupler. Due to the high gain and wide bandwidth of the transimpedance amplifier used for the photo detector circuits, power supply noise can cause the optocoupler to change state independent of the LED operation. Power supply noise is typically characterized as either random or periodic pulses with varying amplitudes and rates of rise and fall. The necessary tests have been conducted to understand the influence of the power supply noise and its effect of the proper operation of the FOD8001. The optocoupler under test offered power supply noise rejection in excess of 10% of the supply voltage for a frequency ranging from 100kHz to 35MHz, for logic high and logic low states. Dynamic Common Mode Rejection The noise susceptibility of an interface while it is actively transferring data is a common requirement in serial data communication. However, the static CMR specification is not adequate in quantifying the electrical noise susceptibility for optocouplers used in isolating high speed data transfer. A serial data communication network’s noise performance is usually quantified as the number of bit errors per second or as a ratio of the number of bits transmitted in a specified time frame. This describes Bit Error Rate, BER. Test equipment that evaluates BER is called a Bit Error Rate Tester, BERT. When a BERT system is combined with a CMR tester, the active or dynamic noise rejection of an isolated interface can then be quantified. This type of CMR is thus defined as “Dynamic CMR”. Therefore, evaluating the common mode rejection while the optocoupler is switching at high speed represents a realistic approach to understand noise interference. ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 8 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Application Information FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Small Outline Package Dimensions 0.164 (4.16) 0.144 (3.66) SEATING PLANE 0.202 (5.13) 0.182 (4.63) 0.010 (0.25) 0.006 (0.16) 0.143 (3.63) 0.123 (3.13) 0.008 (0.20) 0.003 (0.08) 0.021 (0.53) 0.011 (0.28) 0.244 (6.19) 0.224 (5.69) 0.050 (1.27) TYP Lead Coplanarity : 0.004 (0.10) MAX 0.024 (0.61) 0.060 (1.52) 0.275 (6.99) 0.155 (3.94) 0.050 (1.27) Note: All dimensions are in millimeters. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 9 8.0 ± 0.10 3.50 ± 0.20 2.0 ± 0.05 0.30 MAX Ø1.5 MIN 4.0 ± 0.10 1.75 ± 0.10 5.5 ± 0.05 12.0 ± 0.3 8.3 ± 0.10 5.20 ± 0.20 Ø1.5 ± 0.1/-0 6.40 ± 0.20 0.1 MAX User Direction of Feed Note: All dimensions are in millimeters. Ordering Information Option Order Entry Identifier Description No Suffix FOD8001 Small outline 8-pin, shipped in tubes (50 units per tube) R2 FOD8001R2 Small outline 8-pin, tape and reel (2,500 units per reel) All packages are lead free per JEDEC: J-STD-020B standard. Marking Information 1 8001 X YY S1 3 2 5 4 Definitions 1 Fairchild logo 2 Device number 3 One digit year code, e.g., ‘8’ 4 Two digit work week ranging from ‘01’ to ‘53’ 5 Assembly package code ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 10 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Carrier Tape Specification FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler Reflow Profile 300 260°C 280 260 >245°C = 42 Sec 240 220 200 180 Temperature (°C) 160 Time above 140 183°C = 90 Sec 120 1.822°C/Sec Ramp up rate 100 80 60 40 33 Sec 20 0 0 60 120 180 270 360 Time (s) ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 11 AccuPower™ Auto-SPM™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED® Dual Cool™ EcoSPARK® EfficientMax™ ESBC™ ® ® Fairchild ® Fairchild Semiconductor FACT Quiet Series™ FACT® FAST® FastvCore™ FETBench™ FlashWriter®* FPS™ F-PFS™ ® FRFET SM Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™ Motion-SPM™ OptoHiT™ OPTOLOGIC® ® OPTOPLANAR ® PowerTrench® PowerXS™ Programmable Active Droop™ QFET® QS™ Quiet Series™ RapidConfigure™ ™ Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ SPM® STEALTH™ SuperFET® SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS® SyncFET™ Sync-Lock™ ® PDP SPM™ * Power-SPM™ * Trademarks of System General Corporation, used under license by Fairchild Semiconductor. The Power Franchise® The Right Technology for Your Success™ TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™ TRUECURRENT™* µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILDíS WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILDíS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 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Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production Definition Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I51 ©2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.3 www.fairchildsemi.com 12 FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.