HD-15531/883 CMOS Manchester Encoder-Decoder March 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The Intersil HD-15531/883 is a high performance CMOS device intended to service the requirements of MIL-STD1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirements of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. • Support of MIL-STD-1553 • Data Rate (15531B) . . . . . . . . . . . . . . . 2.5 Megabit/Sec • Data Rate (15531) . . . . . . . . . . . . . . . . 1.25 Megabit/Sec • Variable Frame Length to 32-Bits • Sync Identification and Lock-In • Separate Manchester II Encode, Decode • Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V The HD-15531/883 also surpasses the requirements of MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531/883 can also be used in many party line digital data communications applications, such as a local area network or an environmental control system driven from a single twisted pair or fiber optic cable throughout a building. Ordering Information PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 1.25MBIT/SEC HD1-15531/883 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 5-170 2.5MBIT/SEC HD1-15531B/883 PKG. NO. F40.6 File Number 2962.1 HD-15531/883 Pinout HD-15531/883 (CERDIP) TOP VIEW VCC 1 40 COUNT C1 VALID WORD 2 39 COUNT C4 TAKE DATA’ 3 38 DATA SYNC TAKE DATA 4 37 ENCODER CLK SERIAL DATA OUT 5 36 COUNT C3 SYNCHR DATA 6 35 NC SYNCHR DATA SEL 7 34 ENCODER SHIFT CLK SYNCHR CLK 8 33 SEND CLK IN DECODER CLK 9 32 SEND DATA SYNCHR CLK SEL 10 31 ENCODER PARITY SEL BIPOLAR ZERO IN 11 30 SYNC SEL BIPOLAR ONE IN 12 29 ENCODER ENABLE UNIPOLAR DATA IN 13 28 SERIAL DATA IN DECODER SHIFT CLK 14 27 BIPOLAR ONE OUT TRANSITION SEL 15 26 OUTPUT INHIBIT NC 16 25 BIPOLAR ZERO OUT COMMAND SYNC 17 24 ÷ 6 OUT 23 COUNT 2 DECODER PARITY SEL 18 DECODER RESET 19 22 MASTER RESET 21 GND COUNT C0 20 Block Diagrams ENCODER GND 21 VCC 1 MASTER RESET 22 OUTPUT INHIBIT SEND CLK IN 33 26 6 OUT 24 ÷2 CHARACTER FORMER ÷6 27 BIPOLAR ONE OUT 25 BIPOLAR ZERO OUT ENCODER CLK 37 BIT COUNTER 32 20 C0 40 23 C1 C2 36 C3 39 C4 34 SEND DATA 28 29 SERIAL DATA IN ENCODER SHIFT CLK 5-171 30 31 SYNC SELECT ENCODER ENABLE ENCODER PARITY SELECT HD-15531/883 Block Diagrams (Continued) DECODER SYNCHRONOUS DATA SELECT UNIPOLAR DATA IN 13 BIPOLAR ONE IN BIPOLAR ZERO IN 12 7 8 SYNCHRONOUS DATA 4 TRANSITION FINDER 11 DATA SELECT GATE 17 CHARACTER IDENTIFIER 9 15 SYNCHRONIZER COMMAND 38 DATA SYNC 5 DECODER CLK DECODER CLK SELECT SYNCHRONOUS CLK SYNCHRONOUS CLK SELECT MASTER RESET TAKE DATA CLOCK SELECT DATA 2 PARITY 16 CHECK BIT RATE CLK SERIAL DATA OUT VALID WORD PARITY SELECT 8 14 10 DECODER SHIFT CLK 22 DECODER RESET 19 20 40 C0 5-172 3 BIT COUNTER 23 C1 36 C2 39 C3 C4 TAKE DATA HD-15531/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC CERDIP Package . . . . . . . . . . . . . . . . . . 35oC/W 9oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Encoder/Decoder Clock Rise Time (TECR, TDCR) . . . . . . .8ns Max Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . .8ns Max Sync. Transition Span (TD2) . . . . . . . . . . . 18 TDC Typical, (Note 1) Short Data Transition Span (TD4) . . . . . . . . 6 TDC Typical, (Note 1) Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1) TABLE 1. HD-15531/883, HD-15531B/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL TEST CONDITIONS LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS - 0.2 VCC V - V GND +0.5 V - V Input LOW Voltage VIL VCC = 4.5V and 5.5V 1, 2, 3 -55oC ≤ TA ≤ +125oC Input HIGH Voltage VIH VCC = 4.5V and 5.5V 1, 2, 3 -55oC ≤ TA ≤ +125oC 0.7 VCC Input LOW Clock Voltage VILC VCC = 4.5V and 5.5V 1, 2, 3 -55oC ≤ TA ≤ +125oC Input HIGH Clock Voltage VIHC VCC = 4.5V and 5.5V 1, 2, 3 -55oC ≤ TA ≤ +125oC VCC -0.5 Output LOW Voltage VOL IOL = +1.8mA, VCC = 4.5V (Note 2) 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V Output HIGH Voltage VOH IOH = -3.0mA, VCC = 4.5V (Note 2) 1, 2, 3 -55oC ≤ TA ≤ +125oC 2.4 - V Input Leakage Current II VI = VCC or GND, VCC = 5.5V 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA ICCSB VIN = VCC = 5.5V, Outputs Open 1, 2, 3 -55oC ≤ TA ≤ +125oC - 2 mA 7, 8 -55oC ≤ TA ≤ +125oC - - - Standby Supply Current Functional Test FT (Note 3) - NOTES: 1. TDC = Decoder clock period = 1/FDC. 2. Interchanging of force and sense conditions is permitted. 3. Tested as follows: f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH ≥ VCC/2 and VOL ≤ VCC/2. TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETER SYMBOL (NOTE 2) CONDI-TIONS GROUP A SUBGROUPS HD-15531/883 HD-15531B/883 TEMPERATURE MIN MAX MIN MAX UNITS ENCODER TIMING Encoder Clock Frequency FEC VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 15 - 30 MHz Send Clock Frequency FESC VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 2.5 - 5.0 MHz 5-173 HD-15531/883 TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) PARAMETER SYMBOL (NOTE 2) CONDI-TIONS GROUP A SUBGROUPS HD-15531/883 HD-15531B/883 TEMPERATURE MIN MAX MIN MAX UNITS - 1.25 - 2.5 MHz Encoder Data Rate FED VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC Master Reset Pulse Width TMR VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 150 - 150 - ns Shift Clock Delay TE1 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 125 - 80 ns Serial Data Setup TE2 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 75 - 50 - ns Serial Data Hold TE3 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 75 - 50 - ns Enable Setup TE4 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 90 - 90 - ns Enable Pulse Width TE5 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 100 - 100 - ns Sync Setup TE6 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 55 - 55 - ns 150 - 150 - ns Sync Pulse Width TE7 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC Send Data Delay TE8 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 50 0 50 ns Bipolar Output Delay TE9 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 130 - 130 ns Enable Hold TE10 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 10 - 10 - ns Sync Hold TE11 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 95 - 95 - ns DECODER TIMING Decoder Clock Frequency FDC VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 15 - 30 MHz Decoder Sync Clock FDS VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 2.5 - 5.0 MHz Decoder Data Rate FDD VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 1.25 - 2.5 MHz Decoder Reset Pulse Width TDR VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 150 - 150 - ns Decoder Reset Setup Time TDRS VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 75 - 75 - ns Decoder Reset Hold Time TDRH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 10 - 10 - ns Master Reset Pulse TMR VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 150 - 150 - ns Bipolar Data Pulse Width TD1 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC TDC +10 (Note 1) - TDC +10 (Note 1) - ns One Zero Overlap TD3 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - TDC-10 (Note 1) - TDC-10 (Note 1) ns Sync Delay (ON) TD6 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC -20 110 -20 110 ns 5-174 HD-15531/883 TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) PARAMETER (NOTE 2) CONDI-TIONS SYMBOL GROUP A SUBGROUPS HD-15531/883 HD-15531B/883 TEMPERATURE MIN MAX MIN MAX UNITS 0 110 0 110 ns Take Data Delay (ON) TD7 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC Serial Data Out Delay TD8 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 80 - 80 ns Sync Delay (OFF) TD9 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 110 0 110 ns Take Data Delay (OFF) TD10 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 110 0 110 ns Valid Word Delay TD11 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 110 0 110 ns Sync Clock to Shift Clock Delay TD12 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 75 - 75 ns Sync Data Setup TD13 VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 75 - 75 - ns NOTES: 1. TDC = Decoder Clock Period = 1/FDC. 2. AC Testing as follows: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing reference levels: VCC/2; Output load: CL = 50pF. TABLE 3. HD-15531/883, HD-15531B/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS CI VCC = OPEN, f = 1MHz, All measurements referenced to device GND 1 TA = +25oC - 25 pF CIO VCC = OPEN, f = 1MHz, All measurements referenced to device GND 1 TA = +25oC - 25 pF 1, 2 -55oC ≤ TA ≤ +125oC - 10 mA Input Capacitance Input/Output Capacitance Operating Power Supply Current ICCOP VCC = 5.5V, f = 1MHz NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes. 2. Guaranteed but not 100% tested. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100%/5004 1 Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C & D Samples/5005 1, 7, 9 5-175 HD-15531/883 Burn-In Circuit HD1-15531/883 CERDIP R VCC 1 40 A 2 39 A 3 38 A 4 37 R VCC VCC R A FO R 5 36 6 35 NC 7 34 A 8 33 9 32 10 31 11 30 12 29 GND 13 28 A 14 27 VCC 15 26 NC 16 25 17 24 18 23 A R VCC R GND R VCC R FO R GND R R A R GND R GND R VCC 19 22 20 21 R R VCC R A R GND NOTES: 1. VCC = 5.5V ±0.5V. 2. VIH = 4.5V ±10%. 3. VIL = -0.2V to +0.4V. 4. R = 47kΩ ±5%. 5. F0 = 100kHz ±10%. 5-176 R GND A VCC R R R GND VCC GND R VCC R A VCC R GND GND HD-15531/883 Die Characteristics DIE DIMENSIONS: 155 x 195 x 19 ±1mils GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ METALLIZATION: Type: Si-Al WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 Thickness: 11kÅ ±2kÅ Metallization Mask Layout HD-15531/883 DATA SYNC COUNT C1 VALID WORD TAKE DATA’ VCC COUNT C4 ENCODER CLK TAKE DATA COUNT C3 SERIAL DATA OUT ENCODER SHIFT CLK SYNCHR DATA SEND CLK IN SYNCHR DATA SEL SYNCHR CLK SEND DATA DECODER CLK ENCODER PARITY SEL SYNCHR CLK SEL SYNC SEL BIPOLAR ZERO IN ENCODER ENABLE BIPOLAR ONE IN SERIAL DATA IN UNIPOLAR DATA IN BIPOLAR ONE OUT DECODER SHIFT CLK OUTPUT INHIBIT TRANSITION SEL COMMAND SYNC BIPOLAR ZERO OUT DECODER PARITY SEL COUNT C0 DECODER RESET MASTER COUNT RESET 2 GND ÷ 6 OUT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 5-177