FOD8160 High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Features Description ■ Optoplanar® The FOD8160 is a 3.3 V / 5 V high-speed logic gate optocoupler with open collector output, which supports isolated communications to allow digital signals to communicate between systems without conducting ground loops or hazardous voltages. It utilizes Fairchild’s prioprietary Optoplanar® coplanar packaging technology and optimized IC design to achieve high noise immunity, characterized by high common-mode rejection specifications. ■ ■ ■ ■ packaging technology allows more than 10 mm creepage and clearance distance, and 0.5 mm insulation distance to achieve reliable and high voltage insulation High noise immunity characterized by common-mode transient immunity (CMTI) – 20 kV/µs Minimum CMTI Specifications guaranteed over 3 V to 5.5 V supply voltage and -40°C to 100°C extended industrial temperature range High speed, 10 Mbit/sec Data Rate (NRZ) Safety and regulatory approvals – UL1577, 5,000 VACRMS for 1 minute – DIN-EN/IEC60747-5-5, 1,414 V peak working insulation voltage (pending approval) Applications ■ Isolating intelligent power module The FOD8160, packaged in a wide-body SOP 5-Pin package, consists of an aluminium gallium arsenide (AlGaAs) LED and an integrated high-speed photodetector. The output of the detector IC is an open collector Schottky-clamped transistor. The electrical and switching characteristics are guaranteed over the extended industrial temperature range of -40°C to 100°C and a VCC range of 3 V to 5.5 V. Functional Schematic ■ Isolating industrial communication interface Related Resources ANODE 1 6 VCC ■ www.fairchildsemi.com/products/opto/ ■ www.fairchildsemi.com/pf/FO/FODM8061.html 5 VO ■ www.fairchildsemi.com/pf/FO/FODM611.html CATHODE 3 ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 4 GND www.fairchildsemi.com FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin January 2013 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Truth Table LED Output Off HIGH On LOW Pin Definitions Pin # Name Description 1 Anode 3 Cathode Anode 4 GND Output Ground 5 VO Output Voltage 6 VCC Output Supply Voltage Cathode Pin Configuration 1 6 ANODE CATHODE ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 5 3 4 VCC VO GND www.fairchildsemi.com 2 Symbol Parameter Min. Typ. Max. Unit Installation Classifications per DIN VDE 0110/1.89 Table 1 For Rated Mains Voltage < 150 Vrms I–IV For Rated Mains Voltage < 300 Vrms I–IV For Rated Mains Voltage < 450 Vrms I–IV For Rated Mains Voltage < 600 Vrms I–IV Climatic Classification 40/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 CTI Comparative Tracking Index 175 VPR Input to Output Test Voltage, Method b, VIORM x 1.875 = VPR, 100% Production Test with tm = 1 s, Partial Discharge < 5 pC 2,651 Vpeak Input to Output Test Voltage, Method a, VIORM x 1.5 = VPR, Type and Sample Test with tm = 60 s, Partial Discharge < 5 pC 2,121 Vpeak VIORM Maximum Working Insulation Voltage 1,414 Vpeak VIOTM Highest Allowable Over Voltage 8,000 Vpeak External Creepage 10.0 mm External Clearance 10.0 mm Insulation Thickness 0.5 mm Safety Limit Values – Maximum Values Allowed in the Event of a Failure Case Temperature 150 °C IS,INPUT Input Current 200 mA PS,OUTPUT Output Power 600 mW 109 Ω TS RIO Insulation Resistance at TS, VIO = 500 V ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 3 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Safety and Insulation Ratings As per DIN EN/IEC60747-5-5 (pending approval), this optocoupler is suitable for “safe electrical insulation” only within the safety limit data below. Compliance with the safety ratings shall be ensured by means of protective circuits. Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified. Symbol Parameter Value Units TSTG Storage Temperature -40 to +125 °C TOPR Operating Temperature -40 to +100 °C Junction Temperature -40 to +125 °C 260 for 10 sec °C Average Forward Input Current 25 mA VR Reverse Input Voltage 5.0 V PDI Input Power Dissipation(1) 45 mW V TJ TSOL Lead Solder Temperature (Refer to Reflow Temperature Profile on page 12) Input Characteristics IF Output Characteristics VCC Supply Voltage 0 to 7.0 VO Output Voltage -0.5 to VCC + 0.5 V IO Average Output Current 50 mA Output Power Dissipation(1) 85 mW PDO Note: 1. No derating required up to 100°C. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Min. Max. Unit Ambient Operating Temperature -40 +100 ºC VCC Supply Voltages(2) 3.0 5.5 V VFL Logic Low Input Voltage 0 0.8 V IFL Logic Low Input Current 250 µA IFH Logic High Input Current TA Parameter N Fan Out (at RL = 1 kΩ) RL Output Pull-up Resistor 6.0 330 15 mA 5 TTL loads 4,000 Ω Note: 2. 0.1 µF bypass capacitor must be connected between pins 4 and 6. ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 4 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Absolute Maximum Ratings Symbol Parameter Conditions Min. 5,000 VISO Input-Output Isolation Voltage TA = 25°C, R.H. < 50%, t = 1.0 min, II-O ≤ 20 µA(3)(4) RISO Isolation Resistance VI-O = 500 V(3) CISO Isolation Capacitance VI-O = 0 V, frequency = 1.0 MHz(3) Typ. Max. Units VACRMS 1011 Ω 1.0 pF Notes: 3. Device is considered a two-terminal device: pins 1 and 3 are shorted together and pins 4, 5, and 6 are shorted together. 4. 5,000 VACRMS for 1-minute duration is equivalent to 6,000 VACRMS for 1-second duration. Electrical Characteristics Apply over all recommended conditions; TA = -40°C to +100°C, 3.0 V ≤ VCC ≤ 5.5 V; unless otherwise specified. Typical value is measured at TA = 25°C and VCC = 3.3 V or VCC = 5 V. Symbol Parameter Conditions Min. Typ. Max. Units Figure 1.05 1.45 1.80 V 1 INPUT CHARACTERISTICS VF Δ(VF / TA) Forward Voltage IF = 10 mA Temperature Coefficient of Forward Voltage -1.8 BVR Input Reverse Breakdown Voltage IR = 10 µA IFHL Threshold Input Current VO = 0.6 V, IOL(sink) = 13 mA mV/°C 5.0 V 2.5 6.0 mA 2 OUTPUT CHARACTERISTICS VOL Logic Low Output Voltage IF = rated IFHL, IOL(sink) = 13 mA 0.4 0.6 V 3 IOH Logic High Output Current IF = 250 µA, VO = 3.3 V 8.0 50.0 µA 4 IF = 250 µA, VO = 5.0 V 3.0 40.0 µA 4 IF = 10 mA, VCC = 3.3 V 5.3 8.5 mA 5, 7 IF = 10 mA, VCC = 5.0 V 7.1 10.0 mA 5, 7 IF = 0 mA, VCC = 3.3 V 3.5 7.0 mA 6, 7 IF = 0 mA, VCC = 5.0 V 5.3 9.0 mA 6, 7 ICCL Logic Low Output Supply Current ICCH Logic High Output Supply Current ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 5 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Isolation Characteristics Apply over all recommended conditions; typical value is measured at TA = 25°C. Apply over all recommended conditions; TA = -40°C to +100°C, VCC = 3.3 V, IF = 6.0 mA; unless otherwise specified. Typical value is measured at TA = 25°C and VCC = 3.3 V. Symbol Parameter Conditions Min. Typ. RL = 350 Ω Data Rate Max. Units Figure 10 Mbit/sec tPHL Propagation Delay to Logic Low Output RL = 350 Ω, CL = 15 pF 40 80 ns 8, 9, 13 tPLH Propagation Delay to Logic High Output RL = 350 Ω, CL = 15 pF 50 90 ns 8, 9, 13 PWD Pulse Width Distortion, | tPHL – tPLH| RL = 350 Ω, CL = 15 pF 10 35 ns 10, 11, 13 tPSK Propagation Delay Skew RL = 350 Ω, CL = 15 pF 40 ns (5) tR Output Rise Time (10% to 90%) RL = 350 Ω, CL = 15 pF 20 ns 12, 13 tF Output Fall Time (90% to 10%) RL = 350 Ω, CL = 15 pF 10 ns 12, 13 | CMH | Common-Mode Transient Immunity at Output High IF = 0 mA, VO > 2 V, VCM = 1,000 V(6) 20 40 kV/µs 14 | CML | Common-Mode Transient Immunity at Output Low IF = 6.0 mA, VO < 0.8 V, VCM = 1,000 V(6) 20 40 kV/µs 14 Apply over all recommended conditions; TA = -40°C to +100°C, VCC = 5 V, IF = 6.0 mA; unless otherwise specified. Typical value is measured at TA = 25°C and VCC = 5 V. Symbol Parameter Conditions Min. Typ. RL = 350 Ω Data Rate Max. Units Figure 10 Mbit/sec tPHL Propagation Delay to Logic Low Output RL = 350 Ω, CL = 15 pF 37 80 ns 8, 9, 13 tPLH Propagation Delay to Logic High Output RL = 350 Ω, CL = 15 pF 41 90 ns 8, 9, 13 PWD Pulse Width Distortion, | tPHL – tPLH| RL = 350 Ω, CL = 15 pF 4 25 ns 10, 11, 13 tPSK Propagation Delay Skew RL = 350 Ω, CL = 15 pF(5) 40 ns tR Output Rise Time (10% to 90%) RL = 350 Ω, CL = 15 pF 22 ns 12, 13 tF Output Fall Time (90% to 10%) RL = 350 Ω, CL = 15 pF 9 ns 12, 13 | CMH | Common-Mode Transient Immunity at Output High IF = 0 mA, VO > 2 V, VCM = 1,000 V(6) 20 40 kV/µs 14 | CML | Common-Mode Transient Immunity at Output Low IF = 6.0 mA, VO < 0.8 V, VCM = 1,000 V(6) 20 40 kV/µs 14 ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 6 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Switching Characteristics ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 7 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Notes: 5. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH between any two units from the same manufacturing date code that are operated at same case temperature(±5°C), at same operating conditions, with equal loads (RL = 350 Ω, CL = 15 pF), and with an input rise time less than 5 ns. 6. Common-mode transient immunity at output HIGH is the maximum tolerable positive dVcm/dt on the leading edge of the common-mode impulse signal, VCM, to assure that the output remains HIGH. Common-mode transient immunity at output LOW is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, VCM, to assure that the output remains LOW. IFHL – THRESHOLD INPUT CURENT (mA) IF – INPUT LED CURENT (mA) 100 10 1 0.1 0.001 0.6 0.8 -40°C 25°C TA = 100°C 0.01 1.0 1.2 1.4 1.6 1.8 3.0 IOL = 13 mA 2.5 VCC = 3.3 V 1.5 1.0 -40 2.0 VCC = 5.0 V 2.0 -20 IOH – LOGIC HIGH OUTPUT SUPPLY CURRENT (μA) VOL – LOGIC LOW OUTPUT VOLTAGE (V) 0.50 IOL = 13 mA IF = 6 mA 0.45 0.40 VCC = 3.3 V 0.35 VCC = 5.0 V 0.30 0.25 -20 0 20 40 60 80 100 ICCH – LOGIC HIGH OUTPUT SUPPLY CURRENT (mA) ICCL – LOGIC LOW OUTPUT SUPPLY CURRENT (mA) 8 VCC = 5.0 V 6 VCC = 3.3 V 4 2 40 60 80 100 TA – AMBIENT TEMPERATURE (°C) 25 20 15 10 VCC = 3.3 V 5 VCC = 5.0 V 0 -40 -20 0 20 40 60 80 100 10 IF = 0 mA 8 6 VCC = 5.0 V 4 VCC = 3.3 V 2 0 -40 -20 0 20 40 60 80 100 TA – AMBIENT TEMPERATURE (°C) Figure 5. Logic Low Output Supply Current (ICCL) vs. Ambient Temperature ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 100 Figure 4. Logic High Output Current (IOH) vs. Ambient Temperature IF = 10 mA 20 80 TA – AMBIENT TEMPERATURE (°C) 10 0 60 IF = 250 μA VO = 3.3 V / 5.0 V Figure 3. Logic Low Output Voltage (VOL) vs. Ambient Temperature -20 40 30 TA – AMBIENT TEMPERATURE (°C) 0 -40 20 Figure 2. Threshold Input Current (IFHL) vs. Ambient Temperature Figure 1. Input LED Current (IF) vs. Forward Voltage (VF) 0.20 -40 0 TA – AMBIENT TEMPERATURE (°C) V F – FORWARD VOLTAGE (V) Figure 6. Logic High Output Supply Current (ICCH) vs. Ambient Temperature www.fairchildsemi.com 8 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Typical Performance Characteristics 80 IF = 0 mA (for ICCH), 10 mA (for ICCL) TA = 25°C tP – PROPAGATION DELAY (ns) ICC – OUTPUT SUPPLY CURRENT (mA) 10 8 ICCL 6 ICCH 4 2 0 3.0 3.5 4.0 4.5 5.0 Frequency = 5 MHz, 50% Duty Cycle IF = 6 mA, RL = 350 Ω 70 60 tPLH @ VCC = 3.3 V 50 tPLH @ VCC = 5.0 V 40 tPHL @ VCC = 5.0 V 20 -40 5.5 -20 VCC – OUTPUT SUPPLY VOLTAGE (V) (|tPHL – tPLH|) – PULSE WIDTH DISTORTION (ns) tP – PROPAGATION DELAY (ns) Frequency = 5 MHz, 50% Duty Cycle RL = 350 Ω, TA = 25°C 60 tPLH @ VCC = 3.3 V 50 tPLH @ VCC = 5.0 V tPHL @ VCC = 3.3 V tPHL @ VCC = 5.0 V 20 5 6 7 8 40 60 80 100 9 10 20 Frequency = 5 MHz, 50% Duty Cycle IF = 6 mA, RL = 350 Ω VCC = 3.3 V 16 12 8 VCC = 5.0 V 4 0 -40 -20 I F – INPUT LED CURRENT (mA) 0 20 40 60 80 100 TA – AMBIENT TEMPERATURE (°C) Figure 10. Pulse Width Distortion vs. Ambient Temperature Figure 9. Propagation Delay vs. Input LED Current (IF) 40 25 Frequency = 5 MHz, 50% Duty Cycle RL = 350 Ω, TA = 25°C Frequency = 5 MHz, 50% Duty Cycle IF = 6 mA, RL = 350 Ω tR, tF – RISE, FALL TIME (ns) (|tPHL – tPLH|) – PULSE WIDTH DISTORTION (ns) 20 Figure 8. Propagation Delay vs. Ambient Temperature 70 30 0 TA – AMBIENT TEMPERATURE (°C) Figure 7. Output Supply Current (ICC) vs. Output Supply Voltage (VCC) 40 tPHL @ VCC = 3.3 V 30 20 VCC = 3.3 V 15 10 VCC = 5.0 V 5 30 tR @ VCC = 5.0 V 20 tR @ VCC = 3.3 V tF @ VCC = 3.3 V 10 tF @ VCC = 5.0 V 0 -40 0 5 6 7 8 9 10 0 20 40 60 80 100 Figure 12. Rise Time (tR) and Fall Time (tF) vs. Ambient Temperature Figure 11. Pulse Width Distortion vs. Input LED Current (IF) ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 -20 TA – AMBIENT TEMPERATURE (°C) I F – INPUT LED CURRENT (mA) www.fairchildsemi.com 9 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Typical Performance Characteristics (Continued) FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Test Circuit Pulse Gen. 5 MHz tf = tr = 5 ns DC = 50% IF 0.1 μF Bypass 350 Ω CL Input Monitoring Mode VO Monitoring Node RM (IF = 6 mA) Input 50% tf tr 90% 1.5 V 10% VOL Output tPHL tPLH Figure 13. Test Circuit for Propagation Delay, Rise Time, and Fall Time IF VCC 0.1 μF Bypass SW 350 Ω CL VO Monitoring Node RM VCM Pulse Gen 1 kV VCM 90% 10% 0V tr tf VOH VO (IF = 0 mA) 2V 0.8 V VO (IF = 6 mA) VOL Figure 14. Test Circuit for Instantaneous Common-Mode Rejection Voltage ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 10 Part Number Package Packing Method FOD8160 Wide Body SOP 5-Pin Tube (100 units per tube) FOD8160R2 Wide Body SOP 5-Pin Tape and Reel (1,000 units per reel) FOD8160V (Preliminary) Wide Body SOP 5-Pin, DIN EN/IEC60747-5-5 Option Tube (100 units per tube) (Pending Approval) FOD8160R2V (Preliminary) Wide Body SOP 5-Pin, DIN EN/ IEC60747-5-5 Option Tape and Reel (1,000 units per reel) (Pending Approval) All packages are lead free per JEDEC: J-STD-020B standard. Marking Information 1 2 3 8160 V D X YY KK W 4 6 5 8 7 Definitions 1 Fairchild logo 2 Device number, e.g., ‘8160’ for FOD8160 3 DIN EN/IEC60747-5-5 option (only appears on component ordered with this option) 4 Plant code, e.g., ‘D’ 5 Last-digit year code, e.g., ‘D’ for 2013 6 Two-digit work week ranging from ‘01’ to ‘53’ 7 Lot-traceability code 8 Package assembly code, W ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 11 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Ordering Information FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Reflow Profile Temperature (°C) TP 260 240 TL 220 200 180 160 140 120 100 80 60 40 20 0 Max. Ramp-up Rate = 3°C/s Max. Ramp-down Rate = 6°C/s tP Tsmax tL Preheat Area Tsmin ts 120 240 360 Time 25°C to Peak Time (seconds) Profile Freature Pb-Free Assembly Profile Temperature Minimum (Tsmin) 150°C Temperature Maximum (Tsmax) 200°C Time (tS) from (Tsmin to Tsmax) 60–120 Seconds Ramp-Up Rate (tL to tP) 3°C/Second max. Liquidous Temperature (TL) 217°C Time (tL) Maintained Above (TL) 60–150 Seconds Peak Body Package Temperature 260°C +0°C / –5°C Time (tP) within 5°C of 260°C 30 Seconds Ramp-Down Rate (TP to TL) 6°C/Second max. Time 25°C to Peak Temperature ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 8 Minutes max. www.fairchildsemi.com 12 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Package Dimensions 0.20 C A-B 3.95 0.60 2X 1.27 4 6 D 1.38 A 6 4 1.27 4.60 11.38 11.80 11.60 9.20 0.10 C D 2X 1 3 1 0.33 C PIN ONE INDICATOR B 2.54 0.25 5X 0.51 0.31 3 2.54 C A-B D LAND PATTERN RECOMMENDATION 5 TIPS A 2.65 2.45 0.10 C SEATING PLANE 2.90 2.60 0.10 C 0.30 0.10 5X C NOTES: UNLESS OTHERWISE SPECIFIED 1.35 1.15 GAUGE PLANE 8° 0° 0.25 C (R1.29) A) THIS PACKAGE DOES NOT CONFORM TO ANY STANDARD. B) ALL DIMENSIONS ARE IN (R0.54) MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS D) DRAWING CONFORMS TO ASME 0.25 Y14.5M-1994 0.19 E) DRAWING FILE NAME: MKT-M05AREV2 0.74 0.44 SEATING PLANE SCALE: 3.2:1 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 www.fairchildsemi.com 13 Do t Po P2 E F d W1 W Bo K1 Ko P Ao User Direction of Feed Symbol W t Description Tape Width Dimmension in mm 24.00 +0.20 / -0.10 Tape Thickness 0.30 ±0.05 Po Sprocket Hole Pitch Do Sprocket Hole Diameter 1.50 +0.10 / -0.00 D1 Pocket Hole Diameter 1.50 +0.25 / -0.00 4.00 ±0.20 E Sprocket Hole Location 1.75 ±0.10 F Pocket Location 11.50 ±0.10 P2 2.00 ±0.10 P Pocket Pitch 8.00 ±0.10 Ao Pocket Dimension 4.50 ±0.10 Bo 12.00 ±0.10 Ko 3.35 ±0.10 K1 2.85 ±0.10 W1 d Cover Tape Width 21.30 ±0.10 Cover Tape Thickness 0.05 ±0.01 Max Component Rotation or Tilt ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1 D1 10° www.fairchildsemi.com 14 FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin Carrier Tape Specification (SOIC-5L OPTO R2 & R2V Option) FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin 15 www.fairchildsemi.com ©2012 Fairchild Semiconductor Corporation FOD8160 Rev. 1.0.1