FAIRCHILD AN-5058

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AN-5058
Family Frequently Asked Questions (FAQs)
Summary
The following questions are typical of Fairchild’s
µSerDes™ application support team answers the µSerDes
family. If you have a question not addressed here, please
contact your local Fairchild representative or email to
[email protected]
What is a µSerDes™?
The µSerDes is a low-cost, ultra-low EMI, very small
device that allows large amounts of data to flow between
points such as displays, cameras, and controllers. This is
achieved through a parallel-to-serial (serializer) conversion
at the source and serial-to-parallel (deserializer) conversion
at the destination.
Why is a Fairchild µSerDes™ serial interface better
than a parallel interface solution?
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© 2005 Fairchild Semiconductor Corporationwww.fairchildsemi.com
Rev. 1.0.1 • 3/22/07
Significantly reduced EMI over single-ended
technology solutions.
No power-up sequencing required. No change needed
for controller software.
Functions well where single-ended, current-mode
technology fails.
Can provide a greater than 25 to 4 wire reduction.
Can provide a greater than 50 to 7 wire reduction in bidirectional interfaces.
Can provide a lower-cost, more reliable interface
solution.
Can reduce overall component count over existing
LVCMOS technology.
Can use less board space over LVCMOS technologies.
AN-5058
APPLICATION NOTE
What are the differences among the µSerDes™ devices?
Each device in the Fairchild µSerDes family has been designed for specific architectures as shown in Table 1.
Table 1. µSerDes™ Family Comparisons
FIN12AC
Serializer /
Deserializer
12
40MHz
Function
Number of Bits
Max Frequency
Factory Options
(***Contact Factory)
Dynamic Current
(Serializer)
VDDA/S
VDDP
Read / Write
FIN224AC
Serializer /
Deserializer
22
26MHz
FIN324C
Serializer /
Deserializer
24
15MHz
Higher frequency
version
9.5mA @ 5MHz
11mA @ 10MHz
9.5mA @ 5MHz
9mA @ 5MHz
4mA @ 5.44MHz
2.5 to 3.3V
1.65 to 3.6V
Write
2.5 to 2.9V
1.65 to 3.6V
Write
2.5 to 2.9V
1.65 to 3.6V
Write
2.5 to 3.3V
1.65 to 3.6V
Write
2.5 to 3.0V
1.6 to VDDA/S
Read / Write
Camera
Small LCD
Small LCD
2.5 to 3.6V
1.65 to 3.6V
Write
Camera
Small LCD
Small LCD
Small LCD
RGB
µController
RGB
µController / RGB
µController
µController / RGB
/ SPI
No
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Tri-state
Yes
Tri-state
Yes
Tri-state
Yes
Tri-state
Yes
Known-state
No
Multiple frequency
range
Multiple frequency
range
Multiple frequency
range
RT180
15
BGA, MLP
0-Power Down; 1CKREF 20Mhz to
40MHz; 2-CKREF
5MHz to 14MHz;
3-CKREF 8MHz to
14MHz
8
BGA, MLP
0-Power Down; 1CKREF 2Mhz to
5MHz; 2-CKREF
5MHz to 15MHz;
3-CKREF 10MHz
to 20MHz
Tri-state
Yes
Multiple frequency
range; CTL
Standard or
High;PLL divide by
2 or 3
14
BGA, MLP
0-Power Down; 1CKREF 20Mhz to
40MHz; 2-CKREF
5MHz to 14MHz;
3-CKREF 8MHz to
28MHz
Selectable LVCMOS Edge
Rates
Selectable LVCMOS Pulse
Width
Output state
External timing required
Modes
FIN212AC
Serializer /
Deserializer
12
40MHz
48MHz & 2.5x2.5
package
8.5mA @ 5MHz
Recommended Interface
ESD in kV
Package
FIN24C
Serializer /
Deserializer
24
20MHz
26MHz
Ideal Application
Additional Features
FIN24AC
Serializer /
Deserializer
22
20MHz
8
BGA, MLP
0-Power Down; 14-bit control; 2-4bit control latch; 32-bit control
15
BGA, MLP
0-Power Down; 1CKREF 2Mhz to
5MHz; 2-CKREF
5MHz to 15MHz;
3-CKREF 10MHz
to 26MHz
15
BGA, MLP
Master/slave;
PAR/SPI; Strobe
selection;
Reset/standby;
Slew control
µSerDes™ Family Similarities and Features
Similarities across FIN24AC, FIN224AC, and FIN224C
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Same Package
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Same Pinout
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Same Voltage Range
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Same Voltage Translation Range
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Same CTL Drive
New Features
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Rolled LVCMOS Deserializer Edge Rates
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More ESD Protection
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More Wide CKP Pulse Width (FIN224AC)
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Less Power (FIN224AC)
© 2005 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 3/22/07
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AN-5058
APPLICATION NOTE
Implementation
Is there a special power-up sequence between
supplies for either a serializer or deserializer?
What distance can a µSerDes™ drive?
The distance that can be driven depends on the data rates
involved, acceptable bit error rate, and the transmission
medium. The maximum distance in ANSI/TIA/EIA-644-A,
the LVDS standard, is 10 meters. This distance is entirely
application dependent.
There is no required power-up sequence for either serializer
or deserializer.
Are there special settings or switches for the PLL
(S1, S2) on the FIN24 serializer?
Should special transmission mediums be used?
No. The PLL has a very wide range of operation.
The µSerDes can be used with any typical differential
transmission medium, including flex circuits, PC board,
and cables.
When is CTL™ technology better than singleended, current-mode technology?
In applications where a transmission line must be AC
coupled or when DC line balancing is necessary, singleended, current-mode technology is usually inadequate.
LVDS is superior because DC bias can be restored on the
deserializer side of the solution by using only resistors. In
addition, differential technologies offer better EMI than
single-ended technologies.
What impedance should the transmission
cable/flex be?
The transmission line should be 100Ω differential.
Is a termination resistor needed at the inputs to
the deserializer?
No. The 100Ω termination resistor is integrated into the
deserializer, so an external resistor is not necessary for
either clock or data lines.
How much is EMI reduced using a µSerDes™?
µSerDes provides ultra-low EMI as compared to legacy
single-ended technologies. The actual amount of EMI
reduction varies per application; however, Fairchild’s EMI
lab has documented cases of greater than -106.1dB
reduction over legacy single-ended technologies.
Do trace lengths need to be matched?
Yes. Trace lengths need to be matched like any bus
architecture. However, since the serializer and deserializer
have a flow-through design (traces do not need to cross to
connect devices), the effort to achieve this is minimal.
Is there special grounding scheme required for
µSerDes™?
Are there PCB layout guidelines available?
No special ground wire is required. The ground wire can be
subject to interference, as with single-ended, current-mode
technologies.
Yes. This can be downloaded from the Fairchild website or
may be obtained from [email protected]
How low is the power in power-down mode?
What is the typical common-mode voltage of the
µSerDes™?
The µSerDes device is specified to use less than 10µA in
power-down mode.
Typical common-mode voltage is approximately 700mV.
Are EMI filters necessary on the serial link?
Are there actual Gerber files available to download
to simplify or as an example of design?
Many applications no longer require EMI filters. If
additional filtering is required, Fairchild suggests
implementing a shielded flex of ribbon cable for the
following reasons:
Yes, please contact Fairchild Interface Group at
[email protected]
Is there a special power-down sequence between
serializer and deserializer?
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There is no required power-down sequence.
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© 2005 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 3/22/07
Saves space on the PCB.
Makes a solid ground between board assemblies
(no ground bounce).
Sideband signals in flex, not through µSerDes, can
radiate; shielding helps reduce this phenomenon.
ESD/EMI arrays are expensive.
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AN-5058
APPLICATION NOTE
Test and Diagnostics
Bits 21 and 22 on the FIN24A don’t seem to work
on the deserializer. Why?
Where is the ground for µSerDes™ devices?
All device grounds are connected to the ground slug,
underneath the µSerDes device. Care should be taken when
designing the board containing the µSerDes so that the
solder mask is pulled back from this slug.
Data input to pin 21 on the FIN24A serializer is output from
the deserializer on pin 23. Data input to pin 22 on the
FIN24A serializer is output at the deserializer on pin 24.
Why does the serial clock appear intermittent?
Do S1 and S2 control the frequency range for the
FIN24?
This is normal as a word boundary is embedded into the
serial stream. Please refer to the datasheet for a more indepth description.
The FIN24 has a set frequency range, where S1 and S2
control the directionality of data bits [21:24].
When I examine either the serial data path or the
serial clock path, the signal is distorted. Why?
What does a typical implementation look like for
an RGB interface?
Using a 50Ω high-speed terminated oscilloscope with the
probe ground to one side of an LVDS signal forces the 1.0V
bias to ground, resulting in a very incorrect signal. Use highimpedance probes or, alternatively, a board ground may be
offset to accommodate the ground of an oscilloscope. Contact
a Fairchild µSerDes representative for assistance.
Please see Figure 1 for a typical implementation.
Where can I get more information on how to use a
µSerDes™ with more complex architectures, such
as microcontroller interface or for a bi-directional
configuration?
Contact your local Fairchild representative or at
[email protected]
How should the serial clock or data stream look?
The clock or data stream is approximately a 225mV peakto-peak, roughly square, wave differential signal at
approximately 700mV bias with respect to ground.
Baseband
Processor
VDDP1
C2
VDDP2
VDDS/A
E2
C2
F2
A4
B4
GPIO
DP[17:0]
CNTL[0]
C3
CNTL[1]
D1
A3
CNTL[2] CKS+ E1
B3
CKSCNTL[3]
A2
CNTL[4]
G1
DS+
B2
F1
CNTL[5]
DSA1
R/W
D3 M/S
C4
VDDP1
F3
/STBY
/RES
CKSEL
G3
G2
B1
PAR/SPI
/STBY
/RES
CKSEL
Notes:
1.
2.
3.
4.
5.
E3
D2
C1
DP[17:0]
CNTL[0]
CNTL[1]
G1
CKS+ CNTL[2]
F1
CKS- CNTL[3]
CNTL[4]
D1 DS+
E1 DSCNTL[5]
R/W
M/S
PAR/SPI
SLEW
E3
D2
/RES
C1
H
Main Display
PCLK
R,G,B [5:0]
Hsync
Vsync
SD
D4:G6
C4
C3
A3
B3
OE
A2
B2
NC
A1 NC
D3
F3
G3
G2
B1
VDDP2
Edge Rate Control Option
SLEW must be connected
to VDDS or GND for low
power.
Write-only Interface.
Assumes BGA die on display.
/CS used to strobe sub-display data.
PCLK used for RGB mode.
Pin numbers for BGA package.
Figure 1.
© 2005 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 3/22/07
F2
WCLK0 A4
WCLK1 B4
STRB0
STRB1
D4:G6
R,G,B[5:0]
Hsync_D/C
Vsync
SD
OE
RESET
E2
VDDP VDDS/A
VDDP VDDS/A
/CS
PCLK
Sub-Display
Data [7:0]
D/C
/CS
RESET
P/S
R/W
VDDS/A
FIN324C RBG Application Example
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AN-5058
APPLICATION NOTE
Related Datasheets
FIN12AC
FIN12AC
FIN24AC
FIN24C
FIN224AC
FIN224C
FIN324C
µSerDes™ is a trademark of Fairchild Semiconductor Corporation.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2005 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 3/22/07
2.
A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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