RV4141A Low-Power, Ground-Fault Interrupter Features Description The RV4141A is a low-power controller for ACreceptacle, ground-fault circuit interrupters. These devices detect hazardous current paths to ground and ground to neutral faults. The circuit interrupter then disconnects the load from the line before a harmful or lethal shock occurs. Powered from the AC Line Built-In Rectifier Direct Interface to SCR 500μA Quiescent Current Precision Sense Amplifier Internally, the RV4141A contains a diode rectifier, shunt regulator, precision sense amplifier, current reference, time-delay circuit, and SCR driver. Adjustable Time Delay Minimum External Components Meets UL 943 Requirements Compatible with 110V or 220V Systems Available in an 8-Pin SOIC Package Two sense transformers, SCR, solenoid, three resistors, and four capacitors complete the design of the basic circuit interrupter. The simple layout and minimum component count ensure ease of application and longterm reliability. Features not found in other GFCI controllers include a low offset voltage sense amplifier, eliminating the need for a coupling capacitor between the sense transformer and sense amplifier, and an internal rectifier to eliminate high-voltage rectifying diodes. The RV4141A is powered only during the positive half period of the line voltage, but can sense current faults independent of its phase relative to the line voltage. The gate of the SCR is driven only during the positive half cycle of the line voltage. Ordering Information Part Number Operating Temperature Range Package RV4141AN -35 to +80°C 8-Lead, Plastic Dual-Inline Package (DIP) RV4141AMT -35 to +80°C 8-Lead, Plastic Small-Outline Integrated Circuit (SOIC) © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 Packing Method Rails Tape and Reel www.fairchildsemi.com RV4141A — Low-Power, Ground-Fault Interrupter December 2011 RV4141A — Low-Power, Ground-Fault Interrupter Block Diagram Figure 1. Block Diagram Pin Configuration Figure 2. Pin Assignment Pin Definitions Pin # Name Description 1 Amp Out 2 VFB Sense amplifier negative input 3 VREF Sense amplifier positive input – biased internally at +VS/2 4 GND Substrate ground for all circuitry 5 Line Anode of internal diode connected to supply voltage 6 +VS Supply input for RV4141A circuitry 7 SCR Trigger 8 Delay Cap Sense Amplifier Output – an external resistor to VFB sets the IFAULT threshold Output for triggering external SCR when a fault is detected An external capacitor to ground sets the delay time for a ground fault to be present before triggering the SCR © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Power Supply 10 mA PD Internal Power Dissipation 500 mW TSTG Storage Temperature Range -65 +150 °C TA Operating Temperature Range -35 +80 °C TJ Junction Temperature +125 °C TL Lead Soldering Temperature 10 Seconds, SOIC +260 60 Seconds, DIP +300 °C Thermal Characteristics Symbol JA Parameter Thermal Resistance © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 Typ. SOIC 240 DIP 160 Max. Unit RV4141A — Low-Power, Ground-Fault Interrupter Absolute Maximum Ratings °C/W www.fairchildsemi.com 3 ILINE = 1.5mA and TA = +25°C, RSET= 650k Symbol Parameter Conditions Min. Typ. Max. I2-3 = 11µA 25 27 29 ILINE = 750µA, I2-3 = 9µA 25 27 29 Units Shunt Regulator (Pins 5 to 4) VREG Regulated Voltage IQ Quiescent Current V5-4 = 24V 500 V µA Sense Amplifier (Pins 2 to 3) VOFF Offset Voltage GBW Gain Bandwidth tSK IBIAS -200 Design Value 0 200 3 µV MHz Slew Rate Design Value 1 Input Bias Current Design Value 30 100 V/µS 3.8 4.7 5.6 k I2-3 = 9µA 0 0.1 10.0 mV I2-3 = 11µA 3.0 3.8 4.5 V V7-4 = 0V, I2-3 = 11µA 400 600 ILINE = 750µA 12 13 14 V I2-3 = 0/11µA 1.8 2.5 3.0 µA/µA nA SCR Trigger (Pins 7 to 4) ROUT Output Resistance VOUT Output Voltage IOUT Output Current V7-4 = Open, I2-3 = µA µA RV4141A — Low-Power, Ground-Fault Interrupter Electrical Characteristics Reference Voltage (Pins 3 to 4) VREF Reference Voltage Delay Timer (Pins 8 to 4) Discharge / Charge Ratio (1) tDLY Delay Time C8-4 = 12nF IDLY Delay Current I2-3 = 11µA 2 30 40 ms 50 µA Notes: 1. Delay time is defined as starting when the instantaneous sense current (I2-3) exceeds 6.5V/RSET and ending when the SCR trigger voltage V7-6 goes HIGH. © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 www.fairchildsemi.com 4 (Refer to Figure 1 and Figure 3.) GFCI Application The precision op amp connected to pins 1 through 3 senses the fault current flowing in the secondary of the sense transformer, converting it to a voltage at pin 1. The ratio of secondary current to output voltage is directly proportional to feedback resistor, RSET. (Refer to Figure 3) The GFCI detects a ground fault by sensing a difference in current in the line and neutral wires. The difference in current is assumed to be a fault current creating a potentially hazardous path from line to ground. Since the line and neutral wires pass through the center of the sense transformer, only the differential primary current is transferred to the secondary. Assuming the turns ratio is 1:1000, the secondary current is 1/1000th the fault current. The RV4141A’s sense amplifier converts the secondary current to a voltage compared with either of the two window detector reference voltages. If the fault current exceeds the design value for the duration of the programmed time delay, the RV4141A sends a current pulse to the gate of the SCR. RSET converts the sense transformer secondary current to a voltage at pin 1. Due to the virtual ground created at the sense amplifier input by its negative feedback loop, the sense transformer's burden is equal to the value of RIN. From the transformer's point of view, the ideal value for RIN is 0Ω. This causes it to operate as a true current transformer with minimal error. However, making RIN equal to zero creates a large offset voltage at pin 1 due to the sense amplifier's very high DC gain. RIN should be selected as high as possible, consistent with preserving the transformer's operation as a true current mode transformer. A typical value for RIN is between 200 and 1000Ω. Detecting ground-to-neutral faults is more difficult. RB represents a normal ground fault resistance. RN is the wire resistance of the electrical circuit between load/ neutral and earth ground. RG represents the ground-toneutral fault condition. According to UL 943, the GFCI must trip when RN = 0.4Ω, RG = 1.6Ω, and the normal ground fault is 6mA. As seen in Equation (1), maximizing RIN minimizes the DC offset error at the sense amplifier output. The DC offset voltage at pin 1 contributes directly to the trip current error. The offset voltage at pin 1 is: VOS RSET /(RIN RSEC ) Assuming the ground fault to be 5mA, 1mA, and 4mA goes through RG and RN, respectively, causing an effective 1mA fault current. This current is detected by the sense transformer and amplified by the sense amplifier. The ground / neutral and sense transformers are mutually coupled by RG, RN, and the neutral wire ground loop, producing a positive feedback loop around the sense amplifier. The newly created feedback loop causes the sense amplifier to oscillate at a frequency determined by ground/neutral transformer secondary inductance and C4, which occurs at 8KHz. (1) where: VOS = Input offset voltage of sense amplifier; RSET = Feedback resistor; RIN = Input resistor; RSEC = Transformer secondary winding resistance. The sense amplifier has a specified maximum offset voltage of 200μV to minimize trip current errors. Two comparators connected to the sense amplifier output are configured as a window detector, whose references are -6.5V and +6.5V, referred to pin 3. When the sense transformer secondary RMS current exceeds 4.6/RSET, the output of the window detector starts the delay circuit. If the secondary current exceeds the predetermined trip current for longer than the delay time, a current pulse appears at pin 7, triggering the SCR. C2 is used to program the time required for the fault to be present before the SCR is triggered. Refer to Equation (2) for calculating the value of C2. Its typical value is 12nF for a 2ms delay. RSET is used to set the fault current at which the GFCI trips. When used with a 1:1000 sense transformer, its typical value is 1MΩ for a GFCI designed to trip at 5mA. The SCR anode is directly connected to a solenoid or relay coil. The SCR can be tripped only when its anode is more positive than its cathode. RIN should be the highest value possible that ensures a predictable secondary current from the sense transformer. If RIN is set too high, normal production variations in the transformer permeability causes unit-tounit variations in the secondary current. If it is too low, a large offset voltage error at pin 1 is present. This error voltage in turn creates a trip current error proportional to the input offset voltage of the sense amplifier. As an example, if RIN is 500Ω, RSET is 1M, RSEC is 45 and the VOS of the sense amplifier is its maximum of 200μV; the trip current error is ±5.6%. Supply Current Requirements The RV4141A is powered directly from the line through a series-limiting resistor called RLINE; its value is between 24k and 91k The controller IC has a built-in dioderectifier, eliminating the need for external power diodes.The recommended value for RLINEis 24kto 47k for110V systems and 47kto 91kfor 220V systems. WhenRLINEis 47kthe shunt regulator current is limited to3.6mA. The recommended maximum peak line currentthrough RLINE is 10mA. © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 RV4141A — Low-Power, Ground-Fault Interrupter Circuit Operation www.fairchildsemi.com 5 Calculating the Values of RSET and C2 Determine the nominal ground-fault trip-current requirement. This is typically 5mA in North America (117VAC) and 22mA in the UK and Europe (220VAC). Determine the minimum delay time required to prevent nuisance tripping, typically 1 to 2ms. The value of C2 required to provide the desired delay time is: C2 6 t (2) where: C2 is in Nf and t is the desired delay time in ms. Sense Transformers and Cores The sense and ground/neutral transformer cores are usually fabricated using high-permeability laminated steel rings. Their single-turn primary is created by passing the line and neutral wires through the center of its core. The secondary is usually from 200 to 1500 turns. Transformers may be obtained from Magnetic Metals, Inc. (www.magmet.com). The value of RSET to meet the nominal ground fault trip current specification is: RSET 4.6 N I FAULT COS 180(t/P) (3) where: RSET is in k t is the time delay in ms; P is the period of the line frequency in ms; IFAULT is the desired ground fault trip current in mA RMS; N is the number of sense transformer secondary turns. Note: 2. This formula assumes an ideal sense transformer is used. The calculated value of RSET may have to be changed up to 30% when using a non-ideal transformer. RV4141A — Low-Power, Ground-Fault Interrupter The SCR anode is directly connected to a solenoid or relay coil. It can be tripped only when its anode is more positive than its cathode. It must have a high dV/dt rating to ensure that line noise (generated by electrically noisy appliances) does not falsely trigger it. Also the SCR must have a gate drive requirement less than 200μA. C3 is a noise filter that prevents high-frequency line pulses from triggering the SCR. The relay solenoid should have a response time of 3ms or less to meet the UL 943 timing requirement. Figure 3. GFI Application Circuit © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 www.fairchildsemi.com 6 RV4141A — Low-Power, Ground-Fault Interrupter Physical Dimensions [ .400 10.15 .373 9.46 A ] .036 [0.9 TYP] (.092) [Ø2.337] (.032) [R0.813] PIN #1 .250±.005 [6.35±0.13] PIN #1 B TOP VIEW OPTION 1 TOP VIEW OPTION 2 [ ] .070 1.78 .045 1.14 .310±.010 [7.87±0.25] .130±.005 [3.3±0.13] .210 MAX [5.33] 7° TYP 7° TYP C [ ] .021 0.53 .015 0.37 .001[.025] C .015 MIN [0.38] .140 3.55 .125 3.17 .300 [7.62] [ ] .100 [2.54] .430 MAX [10.92] NOTES: .060 MAX [1.52] A. CONFORMS TO JEDEC REGISTRATION MS-001, VARIATIONS BA B. CONTROLING DIMENSIONS ARE IN INCHES REFERENCE DIMENSIONS ARE IN MILLIMETERS C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. D. DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. E. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. [ +0.127 .010+.005 -.000 0.254-0.000 ] N08EREVG Figure 4. 8-Lead, Plastic Dual-Inline Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 www.fairchildsemi.com 7 5.00 4.80 A 0.65 3.81 8 5 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 RV4141A — Low-Power, Ground-Fault Interrupter Physical Dimensions C OPTION A - BEVEL EDGE GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 5. 8-Lead, Plastic Small-Outline Integrated Circuit (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 www.fairchildsemi.com 8 RV4141A — Low-Power, Ground-Fault Interrupter © 2003 Fairchild Semiconductor Corporation RV4141A • Rev. 1.0.8 www.fairchildsemi.com 9