SANYO LE25CA322

Ordering number : ENA1678B
LE25CA322
Serial SPI EEPROM (SPI Bus)
(32Kbit)
Overview
The LE25CA322 is a 32Kbit EEPROM that supports serial peripheral interface (SPI). It realizes high speed operation and
high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. The interface is
compatible with SPI bus protocol, therefore, it is best suited for applications that require small-scale rewritable nonvolatile
parameter memory. Moreover, the LE25CA322 has a 32 bytes page rewrite function that provides rapid data rewriting.
Features
• Capacity
• Single supply voltage
• Serial interface
• Operating clock frequency
• Low current dissipation
• Page write function
• Rewrite time
• Number of rewrite times
• Data retention period
• High reliability
: 32Kbits (4K×8bits)
: 2.7V to 5.5V
: SPI Mode0, Mode3 supported
: 5MHz
: Standby
: 5μA (max.)
: Active (Read)
: 3mA (max.)
: Active (Rewrite) : 5mA (max.)
: 32bytes
: 5ms
: 105times/Address, 106 times/Page(Page=32Byte)
: 20years
: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Incorporates a feature to prohibit write operations under low voltage conditions.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
40611 SY/10511 SY/31710 SY 20100219-S00008 No.NA1678-1/14
LE25CA322
Package Dimensions
Package Dimensions
unit : mm (typ)
3032E
[LE25CA322M]
unit : mm (typ)
3245B
[LE25CA322TT]
3.0
5.0
2
1
0.15
0.35
(0.53)
1.7 MAX
1.27
2
0.65
0.125
SANYO : MFP8(225mil)
0.08
0.1
(0.85)
(1.5)
0.25
1.1MAX
1
(0.6)
0.5
0.63
3.0
4.4
6.4
4.9
8
8
SANYO : MSOP8(150mil)
Packages
MFP8 (225mil)
MSOP8(150mil)
: LE25CA322M
: LE25CA322TT
No.NA1678-2/14
LE25CA322
Pin Assignment
CS
1
Pin Descriptions
8
VDD
PIN.1
CS
Chip select
PIN.2
SO
Serial data output
PIN.3
WP
Write protect
PIN.4
VSS
Ground
PIN.5
SI
Serial data input
SO
2
7
HOLD
WP
3
6
SCK
PIN.6
SCK
Serial clock
VSS
4
5
SI
PIN.7
HOLD
Hold
PIN.8
VDD
Power supply
Block Diagram
XDECODER
ADDRESS
BUFFERS
&
LATCHES
EEPROM
Cell Array
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CONTROL
LOGIC
SERIAL INTERFACE
CS
SCK
SI
SO
WP
HOLD
No.NA1678-3/14
LE25CA322
Specifications
Absolute Maximum Rating/If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Parameter
Symbol
Conditions
Ratings
Unit
-65 to +150
°C
Supply voltage
-0.5 to 6.5
V
DC input voltage
-0.5 to 5.5
V
Overshoot voltage (below 20ns)
-1.0 to 6.5
V
Storage temperature
Operating Conditions
Parameter
Symbol
Conditions
Ratings
Operating temperature
Operating supply voltage
Unit
-40 to +85
°C
2.7 to 5.5
V
max
Unit
DC Electrical Characteristics
Parameter
Supply current when reading
Symbol
ICCR
Conditions
min
typ
CS = 0.1VDD, HOLD = WP = 0.9VDD
3
mA
5
mA
SI = 0.1VDD/0.9VDD, SO = Open
Operating frequency = 5MHz,
VDD = VDD Max
VDD = VDD max., VIN = 0.1VDD/0.9VDD
tWC = 5ms
Supply current when writing
ICCW
CMOS standby current
ISB
CS = VDD, VIN = VDD or VSS
VDD = VDD Max
5
μA
Input leakage current
ILI
VIN = VSS to VDD, VDD = VDD max.
2
μA
Output leakage current
ILO
VIN = VSS to VDD, VDD = VDD max.
2
μA
Input low voltage
VIL
VDD = VDD max.
-0.3
0.3VDD
V
Input high voltage
VIH
VDD = VDD min.
0.7VDD
VDD+0.3
V
Output low voltage
VOL
IOL = 3.0mA, VDD = 2.7V to 5.5V
Output high voltage
VOH
IOH = -0.4mA, VDD = 2.7V to 5.5V
0.4
0.8VDD
V
V
Capacitance at Ta = 25°C, f = 1.0MHz
Parameter
Symbol
Conditions
min
typ
max
Unit
Output pin capacitance
CDQ
VDQ = 0V
12
pF
Input pin capacitance
CIN
VIN = 0V
6
pF
Note : These parameters are sampled and not 100% tested.
AC Electrical Characteristics
Input pulse level
0.2×VDD to 0.8×VDD
Input pulse rise/fall time
10ns
Output detection voltage
0.5×VDD
Output load
30pF
No.NA1678-4/14
LE25CA322
AC Characteristics (at FCLK = 5MHz)/VDD = 2.7V to 5.5V
Parameter
Symbol
Clock frequency
Conditions
min
typ
max
FCLK
Unit
5
MHz
SCK logic high level pulse width
tCLHI
90
SCK logic low level pulse width
tCLLO
90
Input signal rise/fall time
tRF
CS setup time
tCSS
SCK setup time
tCLS
90
ns
Data setup time
tDS
20
ns
Data hold time
tDH
30
ns
CS hold time
tCSH
90
ns
SCK hold time
tCLH
90
ns
CS standby pulse width
tCPH
90
ns
CS output high impedance time
tCHZ
SCK output data time
tV
Output data hold time
tHO
WP setup time
WP hold time
HOLD setup time
ns
ns
1
90
us
ns
150
ns
80
ns
0
ns
tWPS
30
ns
tWPH
30
ns
tHS
30
ns
HOLD hold time
tHH
30
HOLD output low impedance time
tHLz
50
HOLD output high impedance time
tHHz
100
ns
Write cycle time
tWC
5
ms
SCK output low impedance time
tCLZ
ns
0
ns
ns
Table 1 Command Settings
Command
Write enable
(WREN)
Write disable
(WRDI)
Status register read
(RDSR)
Status register write
(WRSR)
Read
(READ)
Write
(WRITE)
1st bus
2nd bus
3rd bus
4th bus
5th bus
6th bus
nth bus
cycle
cycle
cycle
cycle
cycle
cycle
cycle
PD *1
PD *1
PD *1
PD *1
06h
04h
05h
01h
DATA
03h
A15-A8
A7-A0
02h
A15-A8
A7-A0
Explanatory notes for Table 1
The “h” following each code indicates that the number given is in hexadecimal notation.
Addresses A15 to A12 for all commands are “don’t care.”
*1: “PD” stands for page program data. Any amount of data from 1 to 32 bytes is input.
No.NA1678-5/14
LE25CA322
Figure 2 Serial Input Timing
(SPI Mode 0)
tCPH
CS
tCLS
tCSS
tCLHI tCLLO
tCSH
tCLH
SCK
tDS
SI
tDH
DATA VALID
High Impedance
SO
High Impedance
(SPI Mode 3)
tCPH
CS
tCLS
tCSS
tCLLO tCLHI
tCSH
tCLH
SCK
tDS
SI
SO
tDH
DATA VALID
High Impedance
High Impedance
No.NA1678-6/14
LE25CA322
Figure 3 Serial Output Timing
(SPI Mode 0)
CS
SCK
tCLZ
tHO
tCHZ
DATA VALID
SO
tV
SI
(SPI Mode 3)
CS
SCK
tCLZ
SO
tHO
tCHZ
DATA VALID
tV
SI
No.NA1678-7/14
LE25CA322
Description of Commands and Their Operations
“Table 1 Command Settings” provides a list and overview of the commands. A detailed description of the functions and
operations corresponding to each command is presented below.
1. Read (READ)
Consisting of the first through fourth bus cycles, the read command inputs the 16-bit addresses following (03h), and the
data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling edge of
fourth bus cycle bit0 as a reference. “Figure 4 READ” shows the timing waveforms.
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest
address, the internal address returns to the lowest address (0000h), and data output is continued. By setting the logic
level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO
is in a high-impedance state.
Figure 4 READ
CS
Mode3
SCK
0 1 2 3 4 5
6 7 8
15 16
23 24 25 26 27 28 29 30 31
Mode0
8CLK
SI
03h
Add.
Add.
(00000011)
(A15-A8)
(A7-A0)
High Impedance
SO
7 6 5 4 3 2 1 0 7
Data Out(N)
Data Out(N+1)
• Addresses A15 to A12 are “don’t care.”
• In synchronization with the rising edges of 0 to 23 clock signals, the command is identified and the addresses are
taken in through SI.
• In synchronization with the falling edges of 23 clock signal or later, the data is output to SO.
No.NA1678-8/14
LE25CA322
2. Status Registers
The status registers read the operating and setting statuses inside the device from outside (status register read) and set
the protect information (status register write). There are 8 bits in total, and “Table 2 Status Registers” gives the
significance of each bit.
Table 2 Status Registers
Bit
Name
Logic
Function
Bit0
RDY
0
Ready
1
Busy (in write operation)
Bit1
WEN
0
Write disabled
1
Write enabled
Bit2
BP0
0
Bit3
BP1
Power-on time
Information
0
0
Nonvolatile
1
Block protect information
0
See status register description on BP0 and BP1
information
Nonvolatile
information
1
Bit4
×
0
Reserved bit
0
Bit5
×
0
Reserved bit
0
Bit6
×
0
Reserved bit
0
Bit7
SRWP
0
Status register write enabled
Nonvolatile
1
Status register write disabled
information
2-1. Status Register Read (RDSR)
The contents of the status registers can be read using the status register read command. This command can be executed
even during write operation.
“Figure 5 Status Register READ” shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit7) is the first
to be output, and each time one clock is input, all the other bits up to RDY (bit0) are output in sequence, synchronized
to the falling clock edge. If the clock input is continued after RDY (bit0) has been output, the data is output by returning
to the bit (SRWP) that was first output, after which the output is repeated as long as the clock input is continued. The
data can be read by the status register read command at any time.
Figure 5 Status Register Read
CS
Mode3 0 1 2 3 4 5
SCK
6 7 8
9 10 11 12 13 14 15
Mode0
8CLK
SI
SO
05h
(00000101)
Hight Impedance
7 6 5 4 3 2 1 0 7
Status Register Out
No.NA1678-9/14
LE25CA322
2-2. Status Register Write (WRSR)
The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command.
RDY, WEN, bit4, bit5, and bit6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and
SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at
power-down.
“Figure 6 Status Register Write” shows the timing waveforms of status register write, and Figure 11 shows a status
register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates the
internal write operation at the rising CS edge after the data has been input following (01h). By the operation of this
command, the information in bits BP0, BP1, and SRWP can be rewritten. Since bits RDY (bit0), WEN (bit1), bit4, bit5,
and bit6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value
when rewriting the status register. Status register write ends can be detected by RDY of status register read. Information
in the status register can be rewritten 1,000 times (min.). To initiate status register write, the logic level of the WP pin
must be set high and the status register WEN must be set to “1”.
Figure 6 Status Register Write
Self-timed
Write Cycle
tSRW
CS
tWPS
tWPH
WP
Mode3
SCK
0 1 2 3 4 5 6 7 8
15
Mode0
8CLK
SI
SO
01h
(00000001)
DATA
Hight Impedance
2-3. Contents of Each Status Register
RDY (bit0)
Ready/Busy detection
The RDY register is for detecting the write end. When it is “1”, the device is in a busy state, and when it is “0”, it means
that the write operation is completed.
WEN (bit1)
Write enable
The WEN register is for detecting whether the device can perform write operations. If it is set to “0”, the device will not
perform the write operation even if the write command is input. If it is set to “1”, the device can perform write operation
in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to “1”, and by inputting the write disable command (04h), it can be set to “0”. In the following
states, WEN is automatically set to “0” in order to protect against unintentional writing.
• At power-on
• Upon completion of write
• Upon completion of status register write
∗ If a write operation has not been performed inside the device because, for instance, the command input for any of the
write operations has failed or a write operation has been performed for a protected address, WEN will retain the status
established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
No.NA1678-10/14
LE25CA322
BP0, BP1 (bits2, 3)
Block Protect Settings
Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be
set depending on these bits. For the setting conditions, refer to “Table 3 Protect Level Setting Conditions.”
Table 3 Protect Level Setting Conditions
Status Register Bits
Protection Block (Level)
Protected Area
BP1
BP0
0 (Whole area unprotected)
0
0
None
1 (Upper 1/4 area protected)
0
1
0C00h to 0FFFh
2 (Upper 1/2 area protected)
1
0
0800h to 0FFFh
3 (Whole area protected)
1
1
0000h to 0FFFh
SRWP (bit7)
Status Register Write Protect Settings
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is “1” and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP pin is high, the status registers are
not protected regardless of the SRWP state. The SRWP setting conditions are shown in “Table 4 SRWP Setting
Conditions.”
Table 4 SRWP Setting Conditions
WP Pin
SRWP
1
0
0
0
1
1
0
1
Mode
Software protected
(SPM)
Hardware protected
(HPM)
Status Register
Protected Area
Unprotected Area
Unprotected
Protected
Unprotected
Protected
Protected
Unprotected
Bit4, bit5, and bit6 are reserved bits, and have no significance.
3. Write Enable (WREN)
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is
the same as for setting status register WEN to “1”, and the state is enabled by inputting the write enable command.
“Figure 7 Write Enable” shows the timing waveforms when the write enable operation is performed. The write enable
command consists only of the first bus cycle, and it is initiated by inputting (06h).
• Write (WRITE)
• Status register write (WRSR)
4. Write Disable (WRDI)
The write disable command sets status register WEN to “0” to prohibit unintentional writing. “Figure 8 Write Disable”
shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by
inputting (04h).
The write disable state (WEN “0”) is exited by setting WEN to “1” using the write enable command (06h).
Figure 7 Write Enable
Figure 8 Write Disable
CS
CS
Mode3
SCK
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
8CLK
SI
SO
06h
(00000110)
High Impedance
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
SO
04h
(00000100)
High Impedance
No.NA1678-11/14
LE25CA322
5. Write (WRITE)
The LE25CA322 enables pages with up to 32bytes to be written. Any number of bytes from 1 to 32bytes can be written
within the same sector page (page addresses : A15 to A7). “Figure 9 Write” shows the write timing waveforms, and
Figure 12 shows a write flowchart. After the falling CS edge, the command (02H) is input followed by the 16-bit
addresses (Add). The write data is then loaded until the rising CS edge, and the internal addresses (A4 to A0) are
incremented (Add+1) every time the data is loaded in 1-byte increments. The data loading continues until the rising CS
edge. If the data loaded has exceeded 32bytes, the 64bytes loaded last are written. The write data must be loaded in
1-byte increments, and the write operation is not performed at the rising CS edge occurring at any other timing. The
write time is 5ms (max.) when 32bytes (1page) are written at one time.
Figure 9 Write
Self-timed
Write Cycle
tWC
CS
Mode3
SCK
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
279
Mode0
8CLK
SI
02h
Add.
Add.
PD
PD
PD
PD
(00000010)
(A15-A8)
(A7-A0)
(N)
(N+1)
(N+2)
(N+31)
High Impedance
SO
• Addresses A15 to A12 are “don’t care.”
6. Hold Function
Using HOLD pin, the hold function suspends serial communication (it places it in the hold status). “Figure 10 HOLD”
shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of
SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must
not rise or fall. The hold function takes effect when the logic of CS is low, and the hold status is exited and serial
communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI
and SCK are “don’t care.”
Figure 10 HOLD
CS
Active
HOLD
Active
tHS
tHS
SCK
tHH
tHH
HOLD
tHHZ
SO
tHLZ
High Impedance
7. Hardware Data Protection
In order to protect against unintentional writing at power-on, the LE25CA322 incorporates a power-on reset function.
No.NA1678-12/14
LE25CA322
8. Software Data Protection
This product eliminates the possibility of unintentional operations by not recognizing commands under the following
conditions.
• When a write command is input and the rising CS edge timing is not in a bus cycle (8CLK units of SCK).
• When the write data is not in 1-byte increments.
• When the status register write command is input for 2bus cycles or more.
9. Power-on
In order to protect against unintentional writing, CS must be kept at VDD at power-on. After power-on, the supply
voltage has stabilized at 2.7V or higher, wait for 10μs (tPU_READ) before inputting the command to start a read
operation. Similarly, wait for 10ms (tPU_WRITE) after the supply voltage has stabilized at 2.7V or higher before
inputting the command to start a write operation.
10. Decoupling Capacitor
A0.1μF ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure
that the device will operate stably.
Figure 11 Status Register Write Flowchart
Figure 12 Write Flowchart
Status register write
Write
Start
Start
06h
01h
Set write enable
command
06h
Set write enable
command
02h
Set status register
write command
Address 1
Data
Set write command
Address 2
Program start on
rising edge of CS
05h
Data 0
Data 1
Set status register
read command
Data n
NO
Bit 0= “0” ?
Write start on rising
edge of CS
YES
End of status
register write
*Automatically placed in write
disabled state at the end of the
status register write.
Set status register
read command
05h
NO
Bit 0= “0” ?
YES
*Automatically placed
in write disabled state
at the end of the write.
End of write
No.NA1678-13/14
LE25CA322
Application Note
1) Precautions at Power-on
In order to protect against unintentional writing, the LE25CA322 incorporates a power-on rest circuit. The following
conditions must be met in order to ensure that the power-on reset circuit will operate stably. No guarantees are given for
data in the event of an instantaneous power failure occurring during the write operation.
Symbol
VDD = 2.7 to 5.5V
Item
min
tRISE
Power rise time
tOFF
Power off time
Vbot
Power bottom voltage
typ
Unit
max
100
ms
10
ms
0.2
V
tRISE
VDD
tOFF
Vbot
0V
Note:
1). The CS pin must be set high.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
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product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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This catalog provides information as of April, 2011. Specifications and information herein are subject to change
without notice.
No.NA1678-14/14