SEMTECH SC4524C

SC4524C
28V 2A Step-Down Switching Regulator
POWER MANAGEMENT
Features
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Description
Wide input range: 3V to 28V
2A Output Current
200kHz to 2MHz Programmable Frequency
Precision 1V Feedback Voltage
Peak Current-Mode Control
Cycle-by-Cycle Current Limiting
Hiccup Overload Protection with Frequency Foldback
Soft-Start and Enable
Thermal Shutdown
Thermally Enhanced 8-pin SOIC Package
Fully RoHS and WEEE compliant
Applications


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
XDSL and Cable Modems
Set Top Boxes
Point of Load Applications
CPE Equipment
DSP Power Supplies
LCD and Plasma TVs
The SC4524C is a constant frequency peak current-mode
step-down switching regulator capable of producing 2A
output current from an input ranging from 3V to 28V. The
switching frequency of the SC4524C is programmable
up to 2MHz, allowing the use of small inductors and
ceramic capacitors for miniaturization, and high input/
output conversion ratio. The SC4524C is suitable for
next generation XDSL modems, high-definition TVs and
various point of load applications.
Peak current-mode PWM control employed in the
SC4524C achieves fast transient response with simple loop
compensation. Cycle-by-cycle current limiting and hiccup
overload protection reduces power dissipation during
output overload. Soft-start function reduces input startup current and prevents the output from overshooting
during power-up.
The SC4524C is available in SOIC-8 EDP package.
SS270 REV 4
Typical Application Circuit
Efficiency
BST
IN
SW
8.2PH
SC4524C
SS/EN
85
1N4148
C1
0.33PF
L1
80
OUT
R4
42.2k
5V/2A
FB
COMP
C7
10nF
C8
22pF
ROSC
R7
28.0k
GND
R5
15.8k
D2
20BQ030
R6
10.5k
C2
22PF
Efficiency (%)
C4
2.2PF
90
D1
10V – 28V
V IN
75
VIN = 12V
VIN = 24V
70
65
60
55
50
45
C5
2.2nF
40
L1: Coiltronics DR73-8R2
C2: Murata GRM31CR60J226K
C4: Murata GRM31CR71H225K
0
0.5
1
1.5
2
Load Current (A)
Figure 1. 1MHz 10V-28V to 5V/2A Step-down Converter
Dec. 2, 2010
Fig.1 Efficiency of the 1MHz 10V-28V to 5V/2A Step-Do
SC4524C
Pin Configuration
Ordering Information
SW
1
8
BST
IN
2
7
FB
ROSC
3
6
COMP
GND
4
5
SS/EN
9
Device
Package
SC4524CSETRT(1)(2)
SOIC-8 EDP
SC4524CEVB
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 2,500 devices.
(2) Available in lead-free package only. Device is fully WEEE and RoHS
compliant and halogen-free.
(8 - Pin SOIC - EDP)
Marking Information
yyww=Date code (Example: 0752)
xxxxx=Semtech Lot No. (Example: E9010)
SC4524C
Absolute Maximum Ratings
Thermal Information
VIN Supply Voltage ……………………………… -0.3 to 32V
Junction to Ambient (1) ……………………………… 36°C/W
BST Voltage ……………………………………………… 42V
Junction to Case (1) …………………………………
BST Voltage above SW …………………………………… 36V
Maximum Junction Temperature……………………… 150°C
5.5°C/W
Storage Temperature ………………………… -65 to +150°C
SS Voltage ……………………………………………-0.3 to 3V
FB Voltage …………………………………………… -0.3 to VIN
SW Voltage ………………………………………… -0.6 to VIN
Lead Temperature (Soldering) 10 sec ………………… 300°C
Recommended Operating Conditions
SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V
Input Voltage Range ……………………………… 3V to 28V
Peak IR Reflow Temperature ………………………….
Maximum Output Current ……………………………… 2A
260°C
ESD Protection Level ………………………………… 2000V
(2)
Operating Ambient Temperature …………… -40 to +105°C
Operating Junction Temperature …………… -40 to +125°C
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not recommended.
NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
(2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ.
Parameter
Conditions
Min
Typ
Max
Units
28
V
2.95
V
Input Supply
Input Voltage Range
VIN Start Voltage
3
VIN Rising
2.70
VIN Start Hysteresis
VIN Quiescent Current
VIN Quiescent Current in Shutdown
2.82
225
mV
VCOMP = 0 (Not Switching)
2
2.6
mA
VSS/EN = 0, VIN = 12V
40
52
µA
1.000
1.020
V
Error Amplifier
Feedback Voltage
Feedback Voltage Line Regulation
FB Pin Input Bias Current
0.980
VIN = 3V to 28V
0.005
VFB = 1V, VCOMP = 0.8V
-170
%/V
-340
nA
Error Amplifier Transconductance
300
µΩ-1
Error Amplifier Open-loop Gain
60
dB
COMP Pin to Switch Current Gain
10
A/V
VFB = 0.9V
2.4
V
COMP Source Current
VFB = 0.8V, VCOMP = 0.8V
17
COMP Sink Current
VFB = 1.2V, VCOMP = 0.8V
25
COMP Maximum Voltage
µA
Internal Power Switch
Switch Current Limit
Switch Saturation Voltage
(Note 1)
ISW = -2.6A
2.6
3.3
4.3
A
250
400
mV
SC4524C
Electrical Characteristics (Cont.)
Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ.
Parameter
Conditions
Min
Typ
Max
Units
Minimum Switch On-time
135
ns
Minimum Switch Off-time
100
ns
Switch Leakage Current
10
µA
Minimum Bootstrap Voltage
ISW = -2.6A
1.8
2.3
V
BST Pin Current
ISW = -2.6A
60
95
mA
Oscillator
Switching Frequency
Foldback Frequency
ROSC = 12.1kΩ
1.04
1.3
1.56
MHz
ROSC = 73.2kΩ
230
300
370
kHz
ROSC = 12.1kΩ, VFB = 0
100
ROSC = 73.2kΩ, VFB = 0
35
60
90
0.2
0.3
0.4
V
0.95
1.2
1.4
V
250
kHz
Soft Start and Overload Protection
SS/EN Shutdown Threshold
SS/EN Switching Threshold
Soft-start Charging Current
VFB = 0 V
VSS/EN = 0 V
VSS/EN = 1.5 V
1.9
1.6
Soft-start Discharging Current
2.4
3.2
µA
1.5
µA
Hiccup Arming SS/EN Voltage
VSS/EN Rising
2.15
V
Hiccup SS/EN Overload Threshold
VSS/EN Falling
1.9
V
Hiccup Retry SS/EN Voltage
VSS/EN Falling
0.6
1.0
1.2
V
Over Temperature Protection
Thermal Shutdown Temperature
165
°C
Thermal Shutdown Hysteresis
10
°C
Note 1: Switch current limit does not vary with duty cycle.
SC4524C
Pin Descriptions
SO-8
Pin Name
Pin Function
1
SW
Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the
bootstrap capacitor.
2
IN
Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane.
3
ROSC
An external resistor from this pin to ground sets the oscillator frequency.
4
GND
Ground pin
5
SS/EN
Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup
functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off
the regulator to low current state.
6
COMP
The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator.
7
FB
The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to
improve short-circuit robustness (see Applications Information for details).
8
BST
Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive
voltage higher than VIN in order to fully enhance the internal NPN power transistor.
9
Exposed Pad
The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the
PC board.
SC4524C
Block Diagram
IN
6
FB
7
2
SLOPE
COMP
COMP
+
+
ISEN
-
+
5.5m
+ EA
+
+
ILIM
-
OC
18mV
BST
V1
8
+
PWM
-
S
R
FREQUENCY
FOLDBACK
ROSC
Q
POWER
TRANSISTOR
CLK
OSCILLATOR
3
1.2V
1
+
R
R
SW
OVERLOAD
-
PWM
A1
SS/EN
5
1V
1.9V
REFERENCE
& THERMAL
SHUTDOWN
FAULT
SOFT- START
AND
OVERLOAD
HICCUP
CONTROL
GND
4
Figure 2. SC4524C Block Diagram
1.9V
SS/EN
IC
2.4 PA
B4
+
Q
B1
OVERLOAD
R
1V/2.15V
FAULT
S
ID
3.9 PA
B2
_
Q
S
OC
R
PWM
B3
Figure 3. Soft-start and Overload Hiccup Control Circuit
Curve 2
Curve 3
Typical Characteristics
SC4524A
Efficiency
80
V O=1.5V
65
60
55
V O=2.5V
70
65
60
55
1MHz, VIN =12V
D2 =20BQ030
1MHz, VIN =24V
D2 =20BQ030
Curve 6
45
Curve 5
45
50
1.01
V O=3.3V
75
Efficiency (%)
70
V O=5V
80
V O=2.5V
75
1.02
VIN =12V
85
V O=3.3V
Feedback Voltage vs Temperature
Efficiency
90
V O=5V
85
Efficiency (%)
SS270 REV 6-7
VFB (V)
SC4524A/B
90
SC4524C
50
40
0.5
1
1.5
0.97
2
0
0.5
Load Current (A)
1
1.5
Frequency Setting Resistor
vs Frequency
1000
-50
2
1
1.1
ROSC =73.2k
1.0
ROSC =12.1k
0.9
Curve 9
1.25 1.5 1.75 2
-50
-25
0
ROSC =73.2k
0.75
0.5
TA=25oC
0.25
ROSC =12.1k
25
50
75
SS270 REV 6-7
Switch Saturation Voltage
vs Switch Current
300
1
0
0.00
100 125
0.20
0.40
Temperature (OC)
Frequency (MHz)
SS270 REV 6-7
100 125
Foldback Frequency vs VFB
0.8
0.25 0.5 0.75 1
75
1.25
Normalized Frequency
Normalized Frequency
ROSC (k)
Curve 8
50
Temperature ( C)
Frequency vs Temperature
10
25
SS270 REV 6-7
1.2
100
0
o
VIN =12V
0
-25
Load Current (A)
SS270 REV 6-7
SS270 REV 6-7
0.99
0.98
40
0
1.00
0.60
0.80
1.00
VFB (V)
SS270 REV 6-7
Switch Current Limit vs Temperature
4.5
BST Pin Current vs Switch Current
100.0
VIN =12V
25oC
200
-40oC
150
100
50
0.0
0.5
1.0
1.5
Switch Current (A)
2.0
2.5
4.0
BST Pin Current (mA)
VCESAT (mV)
Current Limit (A)
125oC
250
3.5
3.0
VBST =15V
75.0
50.0
-40oC
125oC
25.0
0.0
2.5
-50
-25
0
25
50
75
Temperature (OC)
100 125
0
0.5
1
1.5
2
2.5
3
Switch Current (A)
SC4524C
Curve 12
Curve 11
Typical Characteristics (Cont.)
SS270 REV 6-7
SS270 REV 6-7
SS270 REV 6-7
VIN Supply Current
vs Soft-Start Voltage
VIN Thresholds vs Temperature
2.5
Start
2.8
2.7
2.6
80
-40oC
1.5
1.0
Curve 14
2.5
0.5
2.4
0.0
60
-40oC
-25
0
20
Curve 15
25
50
75
0
100 125
0.5
o
0
1
1.5
5
10
20
25
30
SS270 REV 6-7
Soft-Start Charging Current
vs Soft-Start Voltage
SS Shutdown Threshold
vs Temperature
VIN Quiescent Current vs VIN
0.40
125oC
15
VIN (V)
SS270 REV 6-7
2.5
0
2
VSS (V)
Temperature ( C)
SS270 REV 6-7
125oC
40
UVLO
-50
0.0
-0.5
SS Threshold (V)
-40oC
1.5
1.0
0.5
0.35
Current (uA)
2.0
Current (mA)
VSS = 0
125oC
2.0
Current (mA)
VIN Threshold (V)
2.9
VIN Shutdown Current vs VIN
100
Current (uA)
3.0
0.30
15
VIN (V)
20
25
-2.0
-3.0
0.20
10
-40oC
-1.5
-2.5
0.0
5
125oC
0.25
VCOMP = 0
0
-1.0
30
-50
-25
0
25
50
75
o
Temperature ( C)
100 125
0
0.5
1
1.5
2
VSS (V)
SC4524C
Applications Information
Operation
The SC4524C is a constant-frequency, peak current-mode,
step-down switching regulator with an integrated 28V,
2.6A power NPN transistor. Programmable switching
frequency makes the regulator design more flexible. With
the peak current-mode control, the double reactive poles
of the output LC filter are reduced to a single real pole by
the inner current loop. This simplifies loop compensation
and achieves fast transient response with a simple Type-2
compensation network.
As shown in Figure 2, the switch collector current is
sensed with an integrated 5.5mW sense resistor. The
sensed current is summed with a slope-compensating
ramp before it is compared with the transconductance
error amplifier (EA) output. The PWM comparator trip
point determines the switch turn-on pulse width. The
current-limit comparator ILIM turns off the power switch
when the sensed signal exceeds the 18mV current-limit
threshold.
Driving the base of the power transistor above the
input power supply rail minimizes the power transistor
saturation voltage and maximizes efficiency. An external
bootstrap circuit (formed by the capacitor C1 and the
diode D1 in Figure 1) generates such a voltage at the BST
pin for driving the power transistor.
When the SS/EN pin is released, the soft-start capacitor
is charged with an internal 1.9µA current source (not
shown in Figure 3). As the SS/EN voltage exceeds 0.4V,
the internal bias circuit of the SC4524C turns on and the
SC4524C draws 2mA from VIN. The 1.9µA charging current
turns off and the 2.4µA current source IC in Figure 3 slowly
charges the soft-start capacitor.
The error amplifier EA in Figure 2 has two non-inverting
inputs. The non-inverting input with the lower voltage
predominates. One of the non-inverting inputs is biased
to a precision 1V reference and the other non-inverting
input is tied to the output of the amplifier A1. Amplifier A1
produces an output V1 = 2(VSS/EN -1.2V). V1 is zero and COMP
is forced low when VSS/EN is below 1.2V. During start up,
the effective non-inverting input of EA stays at zero until
the soft-start capacitor is charged above 1.2V. Once VSS/
exceeds 1.2V, COMP is released. The regulator starts to
EN
switch when VCOMP rises above 0.4V. If the soft-start interval
is made sufficiently long, then the FB voltage (hence the
output voltage) will track V1 during start up. VSS/EN must be
at least 1.83V for the output to achieve regulation. Proper
soft-start prevents output overshoot. Current drawn from
the input supply is also well controlled.
Overload / Short-Circuit Protection
Table 2 lists various fault conditions and their
corresponding protection schemes in the SC4524C.
Shutdown and Soft-Start
Table 2: Fault conditions and protections
The SS/EN pin is a multiple-function pin. An external
capacitor (4.7nF to 22nF) connected from the SS pin to
ground sets the soft-start and overload shutoff times of
the regulator (Figure 3). The effect of VSS/EN on the SC4524C
is summarized in Table 1.
Table 1: SS/EN operation modes
SS/EN
Mode
Supply Current
<0.2V
Shutdown
18uA @ 5Vin
0.4V to 1.2V
Not switching
2mA
1.2V to 2.15V
Switching & hiccup disabled
>2.15V
Switching & hiccup armed
Load dependent
Pulling the SS/EN pin below 0.2V shuts off the regulator
and reduces the input supply current to 18µA (VIN = 5V).
Condition
Fault
Protective Action
Cycle-by-cycle limit at
IL>ILimit, V FB>0.8V
Over current
IL>ILimit, V FB<0.8V
Over current
VSS/EN Falling
Persistent over current
frequency foldback
Shutdown, then retry
SS/EN<1.9V
or short circuit
(Hiccup)
Tj>160C
Over temperature
Shutdown
programmed frequency
Cycle-by-cycle limit with
As summarized in Table 1, overload shutdown is disabled
during soft-start (VSS/EN<2.15V). In Figure 3, the reset input
of the overload latch B2 will remain high if the SS/EN
voltage is below 2.15V. Once the soft-start capacitor is
charged above 2.15V, the output of the Schmitt trigger
B1 goes high, the reset input of B2 goes low and hiccup
SC4524C
Applications Information (Cont.)
becomes armed. As the load draws more current from
the regulator, the current-limit comparator ILIM (Figure
2) will eventually limit the switch current on a cycle-bycycle basis. The over-current signal OC goes high, setting
the latch B3. The soft-start capacitor is discharged with
(ID - IC) (Figure 3). If the inductor current falls below the
current limit and the PWM comparator instead turns off
the switch, then latch B3 will be reset and IC will recharge
the soft-start capacitor. If over-current condition persists
or OC becomes asserted more often than PWM over
a period of time, then the soft-start capacitor will be
discharged below 1.9V. At this juncture, comparator B4
sets the overload latch B2. The soft-start capacitor will be
continuously discharged with (ID - IC). The COMP pin is
immediately pulled to ground. The switching regulator is
shut off until the soft-start capacitor is discharged below
1.0V. At this moment, the overload latch is reset. The
soft-start capacitor is recharged and the converter again
undergoes soft-start. The regulator will go through softstart, overload shutdown and restart until it is no longer
overloaded.
If the FB voltage falls below 0.8V because of output
overload, then the switching frequency will be reduced.
Frequency foldback helps to limit the inductor current
when the output is hard shorted to ground.
Fig.4
During normal operation, the soft-start capacitor is
charged to 2.4V.
Freq. (k)
ROSC (k)
Freq. (k)
110
700
25.5
1400
9.76
250
84.5
800
21.5
1500
8.87
300
69.8
900
18.2
1600
8.06
350
57.6
1000
15.8
1700
7.15
400
49.9
1100
14.0
1800
6.34
500
38.3
1200
12.4
1900
5.62
600
30.9
1300
11.0
2000
5.23
Minimum On Time Consideration
AC =
V
The operating
duty
cycle of a non-synchronous stepR = R 6  O − 1 
down 4switching
regulator
in continuous-conduction
1
.
0
V


mode (CCM) is given by
VO + VD
D=
VIN + VD − VCESAT
where VCESAT is the switch saturation voltage and VD is
voltage drop across the rectifying diode.
( V + VD ) ⋅ (1 − D)
DIL = O
FSW ⋅ L 1 control, the PWM modulating
In peak current-mode
ramp is the sensed current ramp of the power switch.
This current( Vramp
+ V is
) ⋅ (absent
1 − D) unless the switch is turned
L1 = O D
on. The intersection
this ramp with the output of the
20 % ⋅ IO of
⋅ FSW
voltage feedback error amplifier determines the switch
pulse width. The propagation delay time required to
immediately
the
IRMS _ CINturn
= I O off
⋅ D
⋅ (1switch
− D) after it is turned on is the
SS270 REV 6-7
minimum controllable switch on time (TON(MIN)).
O
R7 =
C5 =
C8 =
Vo
=
Vc
GPWM


1

DVO = DIL ⋅  ESR +
⋅ FSW ⋅ C O 
V =1.5V, I8=1A,
1MHz
180
AC =
(2)
O
 1
V 
1
R7 =
AC = − 20 ⋅ log
⋅
⋅ FB 
160  G CAR S 2 πFC C O
VO 
IO
C IN >140
=
1
1 .0 C

 =5 15
4 ⋅ DVIN ⋅ F1SW
AC = − 20 ⋅ log
⋅
⋅


 28 ⋅ 6 . 1 ⋅ 10 − 3 2 π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6 3 . 3 
120
C8 =
TON_MIN (ns)
(1)
VO + VD Frequency
SettingDthe
= Switching
VIN + VD − VCESAT
The switching frequency of the SC4524C is set with an
external resistor from the ROSC pin to ground. Table 3
lists standard( Vresistor
+ VD )values
⋅ (1 − Dfor
) typical frequency setting.
DIL = O
FSW ⋅ L 1
( VO + VD ) ⋅ (1 − D)
20 % ⋅ IO ⋅ FSW
ROSC (k)
200
200
The regulator output voltage is set with an external
resistive divider (Figure 1) with its center tap tied to the
FB pin. For a given R6 value, R4 can be found by
L1 =
ROSC (k)
Freq. (k)
Minumum On Time vs Temperature
Setting the Output Voltage
V
R 4 = R 6  O − 1 
1
 .0 V

Table 3: Resistor for Typical Switching Frequency
15 . 9
100
10 20 -50 -25 0 25 50 75 100 125
R7 =
= 22 . 3 k
0 . 28 ⋅ 10 −3
Temperature (OC)
1
C5 =
= 0 . 45 nF
3
3 Minimum On Time
2 π Figure
⋅ 16 ⋅ 104. Variation
⋅ 22 . 1 ⋅ 10of
with Ambient Temperature
1
C8 =
= 12pF
2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3
10


R4 = R6  O − 1 
 1 .0 V

 V

R4 = R6  O − 1 
 1VO. 0+VVD 
D=
VIN + VD − VCESAT
VO + VD
D=
VIN + VD − VCESAT
( V + VD ) ⋅ (1 − D)
DIL =TheOmaximum
least 2.6A.
deliverable load current for the
FSW ⋅ L 1
SC4524C is 2.6A minus
one half of the inductor ripple
( V + VD ) ⋅ (1 − D)
current.
DIL = O
( V + FVD ) ⋅⋅(L11− D)
L 1 = O SW
20 % ⋅ ICapacitor
O ⋅ FSW
Input Decoupling
( V + V ) ⋅ (1 − D)
L1 = O D
The input capacitor
20 % ⋅ IOshould
⋅ FSW be chosen to handle the RMS
IRMS _ CIN of
= IaO buck
⋅ D ⋅ converter.
(1 − D)
ripple current
This value is given by
SC4524C
Applications Information (Cont.)
Closed-loop measurement shows that the SC4524C
minimum on time is about 120ns at room temperature
(Figure 4). If the required switch on time is shorter than
the minimum on time, the regulator will either skip cycles
or it will jitter.
To allow for transient headroom, the minimum operating
switch on time should be at least 20% to 30% higher than
the worst-case minimum on time.
IRMS _ CIN = I O ⋅ D ⋅ (1 − D)
Minimum Off Time Limitation
The PWM latch in Figure 2 is reset every cycle by the
clock. The clock also turns off the power transistor to
refresh the bootstrap capacitor. This minimum off time
limits the attainable duty cycle of the regulator at a given
switching frequency. The measured minimum off time is
100ns typically. If the required duty cycle is higher than
the attainable maximum, then the output voltage will not
 VOits−set
be able
R 4 to
= Rreach
1  value in continuous-conduction
6
1
.
0
V


mode.
Inductor Selection
VO + VD
D=
VIN + VD − VCESAT
The inductor ripple current for a non-synchronous stepdown converter in continuous-conduction mode is
(V V
+ V ) ⋅ (1 − D)
RD4IL==R 6 O O D− 1 
V ⋅ L 1
 1 . 0FSW
(3)
where FSW is the switching frequency and L1 is the
( V V+ V+ )V⋅ (1 − D)
inductance.
LD1== O O D D
⋅ I ⋅ FSW
VIN 20
+ V%
D −OVCESAT
An inductor ripple current between 20% to 50% of the
maximum load current gives a good compromise among
IRMS _ cost
⋅ )D
⋅ (1 Re-arranging
− D)
CIN
OV
efficiency,
and
size.
Equation (3) and
( VO= I+
D ⋅ (1 − D)
D
I
=
L
assuming 35% inductor
FSW ⋅ L 1 ripple current, the inductor is
given by
 D ) ⋅ (1 − D) 1

(V + V

LD1VO= = DOIL ⋅  ESR
+
35 % ⋅ IO ⋅ FSW8 ⋅ FSW ⋅ C O 
(4)
If the input voltage varies over a wide range, then choose
L1 based on the nominal input voltage. Always verify
IRMS _ CIN = I O ⋅ D ⋅ (1 − D)
converter
operation at the input voltage extremes.
IO
C IN >
4 ⋅ DV ⋅ F
The peak current INlimitSWof SC4524C power transistor is at


1

DVO = DIL ⋅  ESR +
8 ⋅ FSW ⋅ C O 

(5)


1

DVOcapacitance
= DIL ⋅  ESR must
+
The input
also be high
enough to keep
8
⋅
F
⋅
C
SW
O 

input ripple voltage within specification. This is important


1 from
in reducing
EMI
 ESR +
 the regulator. The
DVO = the
DIL ⋅conductive
8
⋅
F
⋅
C
SW
O


input capacitance can be estimated from
AC =
AC =
AC =
R7 =
RC75 ==
CC5 ==
8
C8 =
Vo
=
Vc
Vo
=
Vc
GPWM
GPWM
R7 =
AC =
VIO
RC7 ==
(6)
RC4IN=>R 6  O − 1 
5
4⋅1D.V
0INV ⋅ FSW
AC =
 1IO
1 inputVripple
FB 
DV
is
the
allowable
voltage.


C
>
Awhere
=
−
20
⋅
log
⋅
⋅
IN
CC5 ==
IN
C
4⋅ V
DCA
VINRV⋅SFSW2 πFC C O VO 
G
8
O +
D
D=
Multi-layerVceramic
capacitors, which have very low ESR
IN + VD − VCESAT
1 handle high RMS1 ripple current,
1 . 0 C 8 =
(a few mW) and
can easily

AC = − 20 ⋅ log
⋅
⋅
=
R=7 15
−3
3
−6
are the ideal choice
3 .3 
28 ⋅ 6 . 1for
⋅ 10input2 πfiltering.
⋅ 80 ⋅ 10 A ⋅ single
22 ⋅ 10 4.7µF
X5R ceramic( Vcapacitor
is adequate for 500kHz or higher
O + VD ) ⋅ (1 − D)
D
I
=
switchingL frequency applications, and 10µF is adequate C 5 =
15 . 9
FSW ⋅ L 1
for 200kHz
500kHz
switching
For high
10 20 to


VFB frequency.
R7 =
=122 . 3 k 1
−
3


Avoltage
=
−
20
⋅
log
⋅
⋅
ceramic (1µF or 2.2µF) can be C =
C
0 . 28applications,
⋅ 10  G R a small
8
2 πDF)C C O VO 
( VO +CA
Vwith
D )S⋅ (1a−low
placedLin
parallel
ESR electrolytic capacitor to
1
1 =
203ESR
% ⋅ IOand
⋅ FSWbulk =capacitance
Csatisfy
0 . 45 nF requirements.
5 =
both the
2 π ⋅ 16 ⋅ 10
⋅ 22 .11 ⋅ 10 3
1
1 .0 

AC = − 20 ⋅ log
⋅
⋅
 = 15
−3
3
−6
3 . 3  Vo
2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10
 281 ⋅ 6 . 1 ⋅ 10
Output
Capacitor
=
C8 = I
= I O3 ⋅⋅ 22D.⋅1(1⋅ 10
− D3 ) = 12pF
Vc
_ CIN⋅ 10
2 πRMS
⋅ 600
The output15 .9ripple voltage DVO of a buck converter can be
10 20as
Rexpressed
= 22 . 3 k
7 =
− 3 (1 + s R
GPWM
Vo 0 . 28 ⋅ 10
ESR C O )
GPWM
=


1

V
(1 D
+VsO/ =ωD
s / ω+n Q + s 2 / ωn2 ) 
(7)
1⋅ + ESR
c
p )I(L1
8 ⋅ FSW
C5 =
= 0⋅.C
45O nF


2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3
where CO is the output capacitance.
R7 =
R
1
1
1
G
≈
, 3
ωp ≈ 3 = 12
, pF
ωZ =
,
CPWM
8 =
⋅ Rinductor
R ESR C O
⋅CA
600
. 1 ⋅ 10 R C O
S⋅ 10 ⋅ 22
Since2 πG
the
IO ripple current DIL increases as D
C IN >(Equation (3)), the output ripple voltage is C 5 =
decreases
AC
4 ⋅ DVIN ⋅ FSW
therefore
when V is at its maximum.
10 20 the highest
RV7o =
GPWM (1 + s R ESR C O )IN
= gm
2
VAc 10µF
(1 +to
s /47µF
ωp )(1X5R
+ s ceramic
/ ωn Q + scapacitor
/ ωn2 ) is found adequate C 8 =
1
output filtering in most applications. Ripple current
Cfor
5 =
2 πFoutput
Z1 R 7
in the
capacitor is not
R
1 a concern because1 the
GPWM ≈ 1
,
ωp ≈
,
ωZ =
,
RCO
R ESR C O
C 8 = GCA ⋅ R S
11
2 πFP1 R 7
AC
SC4524C
Applications Information (Cont.)
Freewheeling Diode
Use of Schottky barrier diodes as freewheeling rectifiers
reduces diode reverse recovery input current spikes,
easing high-side current sensing in the SC4524C. These
diodes should have an average forward current rating
at least 2A and a reverse blocking voltage of at least a
few volts higher than the input voltage. For switching
regulators operating at low duty cycles (i.e. low output
voltage to input voltage conversion ratios), it is beneficial
to use freewheeling diodes with somewhat higher
average current ratings (thus lower forward voltages). This
is because the diode conduction interval is much longer
than that of the transistor. Converter efficiency will be
improved if the voltage drop across the diode is lower.
Fig.5
The freewheeling diode should be placed close to the
SW pin of the SC4524C to minimize ringing due to trace
inductance. 20BQ030 (International Rectifier), B230A
(Diodes Inc.), SS13, SS23 (Vishay), CMSH1-40M, CMSH140ML and CMSH2-40M (Central-Semi.) are all suitable.
The freewheeling diode should be placed close to the SW
pin of the SC4524C on the PCB to minimize ringing due to
trace inductance.
For the bootstrap circuit, a fast switching PN diode
(such as 1N4148 or 1N914) and a small (0.33µF – 0.47µF)
ceramic capacitor is sufficient for most applications. When
bootstrapping from 2.5V to 3.0V output voltages, use a
low forward drop Schottky diode (BAT-54 or similar) for
D1. When bootstrapping from high input voltages (>20V),
reduce the maximum BST voltage by connecting a Zener
diode (D3) in series with D1 as shown in Figure 6 (b). If
VOUT > 8V, then a protection diode D4 between the SW
and the BST pins will be required as shown in Figure 6 (c).
D4 can be a small PN diode such as 1N4148 or 1N914 if
the operating temperature does not exceed 85 ºC. Use a
small Schottky diode (BAT54 or similar) if the converter is
to operate up to 125 ºC.
SS270 REV 6-7
Minimum Bootstrap Voltage
vs Temperature
2.2
2.1
Voltage (V)
inductor current of a buck converter directly feeds CO,
resulting in very low ripple current. Avoid using Z5U
and Y5V ceramic capacitors for output filtering because
these types of capacitors have high temperature and high
voltage coefficients.
2.0
1.9
1.8
ISW = -2.6A
1.7
1.6
-50
-25
0
25
50
75
Figure 5. Typical Minimum Bootstrap Voltage required
to Saturate Transistor (ISW= -2.6A).
Bootstrapping the Power Transistor
The typical minimum BST-SW voltage required to fully
saturate the power transistor is shown in Figure 5, which
is about 1.96V at room temperature.
The BST-SW voltage is supplied by a bootstrap circuit
powered from either the input or the output of the
converter (Figure 6(a), 6(b) and 6(c)). To maximize
efficiency, tie the bootstrap diode to the converter output
if VO>2.5V as shown in Figure (a). Since the bootstrap
supply current is proportional to the converter load
current, using a lower voltage to power the bootstrap
circuit reduces driving loss and improves efficiency.
100 125
Temperature (o C)
D1
BST
C1
VIN
VOUT
SW
IN
SC4524C
D2
GND
(a)
Figure 6(a). Bootstrapping the SC4524C from the
converter output
12
SC4524C
Applications Information (Cont.)
VFB 
 11 ⋅
11
FB 
AC =
=diagram
− 20
20 ⋅⋅ log
log
⋅V
The block
in
Figure
7
shows
the
control

 loops of a
A
−
⋅
⋅
C
 G
G CAR
R S 22 π
πFFC C
CO V
VO 
CA
S
C
O
O

buck converter with the SC4524C. The innerloop (current
VO
C1
 BSTV



O
R
=
R
−
1
loop) consists of a current sensing resistor (Rs=5.5mW) and
R 44 = R 66  1 . 0 V − 1 
VIN
VOUT
 1 .0 V



11 outer
11 ..00
 with11 gain (G⋅⋅ CA=18.5). The
SW
a current
IN
AC =
=amplifier
− 20
20 ⋅⋅ log
log(CA)
A
−
 28 ⋅ 6 . 1 ⋅ 10 −−33 2 π ⋅ 80 ⋅ 10 33 ⋅ 22 ⋅ 10 −−66 ⋅⋅ 3 .
C
3 .3
2 π amplifier
⋅ 80 ⋅ 10 (EA),
⋅ 22 ⋅ 10
 28 ⋅ 6 . 1of⋅ 10
an error
a
SC4524C
VFB  loop (voltage loop) consists
1
1
D2 
VGND
+
V


A
=
−
20
⋅
log
⋅
⋅
O
D
V
+
V
PWM modulator, and a LC filter.
OC
D
D=
=
 G R 2 πF C
D
VO 
C O
 CA S
VIN +
+V
VD −
−V
VCESAT
V
15 . 9
IN
D
CESAT
15
20. 9
10
20
10
Since the
current
loop is= internally
closed, the remaining
R
=
22 . 3 k
(b)
R 77 =
1
1for
1 . 0−−33 = 22 . 3 k is to design the voltage

0
.
28
⋅
10
task
the
loop
compensation
0
.
28
⋅
10
AC = − 20 ⋅ log D1
⋅  1
V ⋅   = 15 . 9 dB
1
−3
−6
D4
2 π⋅ 80compensator
⋅ 10⋅3 ⋅ 22 ⋅ 10(C
1 C ).
A.C1=⋅ 10
− 20 ⋅ log
⋅ FB
, R3,. 3and
(( V
VO +
+V
VD )) ⋅⋅ ((11 −
−D
D))  28 ⋅ 6
G CAR S 2C
D
Cπ5FC=
=C O V5 O 7 31 8
= 00 ..45
45nF
nF
DIIL =
= O

=
D
5
3 ⋅ 22 . 1 ⋅ 10 33
L
2
π
⋅
16
⋅
10
F
⋅
L
V
2
π
⋅
16
⋅
10
⋅
22
.
1
⋅
10
SW
1
FSW ⋅ L 1
BST
C1
= R 6  O − 1 
For a converter with switching frequency FSW, output
15 . 9
 1 .0 V
 VIN
1
1and
. 0 loading R, the
VOUT>8V
10 20
 inductance
111
L⋅ 1, output capacitance
C⋅ =
C
=
12pF
A
=
−
20
⋅
log
= 15 . 9 dB
=
=
22
.
3
k
SW

8
C
=
IN
C
33
(( V
VO +
+R V
V
)
⋅
(
1
−
D
)
−
3
− 6 33O = 12pF
7 D ) ⋅ (1 − D)
8
−3
3
2
π
⋅
600
⋅
10
⋅
22
.
1
⋅
10
3
.
3
⋅ 6 . 1 ⋅ 10(V ) 2to2ππ
⋅
80
⋅
10
⋅
22
⋅
10
 28 control

O
D 0 . 28 ⋅ 10
LL 1 =
= SC4524C
⋅
600
⋅
10
⋅
22
.
1
⋅
10
output (VO) transfer function in Figure 7 is
C
1
20 %
% ⋅⋅ IIO ⋅⋅ FFSW D2
VO + VD
20
O
SW
given
by:
1
GND
C5 =
= 0 . 45 nF
VIN + VD − VCESAT
2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 1520.9
GPWM ((11 +
+ ss R
R ESR C
C O ))
Vo
G
V
10
PWM
ESR O
o =
(8)
R
=
=
22
.
3
k
=
7
= II O ⋅⋅ D
D ⋅⋅ ((11 −
−D
D)) 1
−3
Vc ((11 +
+ ss // ω
ωp ))((11 +
+ ss // ω
ωn Q
Q+
+ ss 22 // ω
ωn22 ))
RMS __ CIN
CIN =
IIRMS
V
0
.
28
⋅
10
O
c
p
n
n
= diode or a Schottky3 diode
= 12pF
D4 is eitherC
a pn
8 juntion
depending on the
2operating
π⋅ 600temperature.
⋅ 10 ⋅ 22 . 1 ⋅ 10 3
1
This
transfer
function
has
a
finite
DC
gain
( VO + VD ) ⋅ (1 − D)
(C)
C5 =
= 0 . 45 nF
=
2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3
FSW ⋅ L 1
R
1
1
GPWM ≈
≈ R ,,
ωp ≈
≈ 1 ,,
ωZ =
= 1 ,,
G
ω
ω
Figures 6(b) and (c). Methods
of 11Bootstrapping
the


PWM
p
Z
GCA ⋅⋅ R
RS
RC
CO
R ESR C
CO
1
G
R
R
DV
VO =
=D
DIIL V⋅⋅oESR
ESR +
+ GPWM (1 +s R ESR C O )
CA
S
O
ESR O
D
SC4524C
O
L =
C
=
=
12
pF

8
⋅
F
⋅
C
8
2 3
SW)(1
⋅ C+OOs/ ωn2Qπ+⋅ 600
) ( V + V ) ⋅ (1 − D)
Vc (1 + s8 /⋅ FωSW
s2 / ω
⋅ 10
⋅ 22 . 1 ⋅ 10 3 AC
p
n)
= O D
AC
20
20 % ⋅ IO ⋅ FSW
10
20
10
Loop Compensation
an ESRRzero
F
at
=
Z
R 77 = g
gm
R
(1 + s R ESR
C=O ) m1 ,
Vo ω ≈ 1GPWM
G
≈
,
,
ω
=
PWM
p
Z
goal of compensation
to shape the frequency
1 = I The
2
IIOO isGCA
⋅RS
11Cn2O)
O ⋅ D ⋅ (1 − D) C
Vc (1 + sR/CωOp )(1 + s / ωnC
/ω
Cthe
>converter
_ CIN
CQ5 +=
=sR ESR
IN >
response
of
so
as
to
achieve
high
DC
IN
5
DV
VIN ⋅⋅ FFSW
πFFZ1 R
R
44 ⋅⋅ D
SW ⋅ C O 
22 π
IN
SW
Z1 77
accuracy and fast transient
response
while maintaining
a dominant low-frequency
pole FP at
AC
10 20
1
loop stability.
1
R7 =
R
1
C8 =
= 1
C
GPWM ≈
,
ω8p ≈ 2 πFP,1 R 7
ωZ =
,
gm


1
2
π
F
R
GCA ⋅ R S
R C O P1 7
R ESR C O

 SCHOTTKY DIODE
CONTROLLER AND
O = DIL ⋅  ESR +
8 ⋅ FSW ⋅ C O 
1

C5 =
Io
AC
and double poles at half the switching frequency.
CA
2Rs πFZ1 R 7
10 20
R7 =
gm
1
Including the voltage divider (R4 and R6), the control to
REF
C8 =
+
Vc
PWM 2 πF
R
feedback transfer function is found and plotted in Figure
EA
IO
P1 7
MODULATOR
1
FB
>
L1C
Vo
SW
5 =
8 as the converter gain.
4 ⋅ DVIN ⋅ FSW
2 πFZ1 R 7
D3
D1
12
Vramp
COMP
CCo8 =
C5
R7
C8
Resr
1R4
2 πFP1 R 7
Figure 7. Block diagram of control loops
R6
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at FZ1, and a high frequency pole
at FP1. The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
13
SC4524C
Applications Information (Cont.)
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
60
GAIN (dB)
30
Fz1
Fp1
Fp
0
CO
NV
-30
ER
T ER
Fc
LO
OP
G
EN
SA
TO
RG
Example: Determine the voltage compensator for an
800kHz, 12V to 3.3V/2A converter with 22uF ceramic
output capacitor.
Choose a loop gain crossover frequency of 80kHz, and
place voltage compensator zero and pole at FZ1=16kHz
(20% of FC), and FP1=600kHz. From Equation (9), the
required compensator gain at FC is
AIN
AIN
GA
IN
Fz
-60
1K
CO
MP
where gm=0.3mA/V is the EA gain of the SC4524C.
1
1
1.0 ·
§
A C 20 ˜ log¨¨
˜
˜
¸¸ 11.4dB
© 18.5 ˜ 5.5 ˜ 103 2ʌ ˜ 80 ˜ 103 ˜ 22 ˜ 106 3.3 ¹
Fsw/2
Then the compensator parameters are
10K
100K
FREQUENCY (Hz)
1M
 1
V 
1
AC = − 20 ⋅ log
⋅
⋅ FB 
 G CAR S 2 πFC C O VO 
Figure 8. Bode plots for voltage loop design
10M
R7
C5
10
11.4
20
12.4k
0.3 ˜ 10 3
1
2ʌ ˜ 16 ˜ 103 ˜ 12.4 ˜ 103
1
1
1 .0 
AC =the
− 20
⋅ log
⋅
Therefore,
procedure
of the voltage
loop design
for −6 ⋅
 = 15 . 9 dB
−3
3
3 .3  C
2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10
1
 28 ⋅ 6 . 1 ⋅ 10
the SC4524C can be summarized as:
8
2 ʌ ˜ 600 ˜ 103 ˜ 12.4 ˜ 103
0.8nF
21pF
15 . 9 gain, i.e. control to feedback transfer
(1) Plot the converter
Select R7=12.4k, C5=1nF, and C8=22pF for the design.
10 20
function.
R7 =
=
22
.
3
k
−3
28 ⋅ 10
(2) Select the0 .open
loop crossover frequency, FC, between
Compensator parameters for various typical applications
1
10% and
20%
of
the
switching
frequency.
At
F
,
find
the
are listed in Table 5. A MathCAD program is also available
C5 =
= 0 . 45 nF C
3
3
2
π
⋅
16
⋅
10
⋅
22
.
1
⋅
10
required compensator gain, AC. In typical applications with
upon request for detailed calculation of the compensator
ceramic output capacitors,
the
ESR
zero
is
neglected
and
parameters.
1
C
=
=
12
pF
the required
compensator gain at F can be estimated by
8
2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10C 3
 1
V 
1
(9)
Thermal Considerations
AC = − 20 ⋅ log
⋅
⋅ FB 
G CAR S 2 πFC C O VO 

GPWM (1 + s R ESR C O )
Vo
(3) Place =the compensator zero, FZ1,2 between
10% and
For the power transistor inside the SC4524C, the
Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn2 )
1 F.
1
1 .0 

20% ofAthe
crossover
frequency,
conduction
loss P , the switching loss PSW, and bootstrap
C
⋅
⋅
 = 15 . 9 dB C
C = − 20 ⋅ log
−3
3
−6
3
.
3
⋅ 6 . 1 ⋅F10
2 π ⋅ 80the
⋅ 10ESR⋅ 22
⋅ 10 circuitPloss
(4) Use the compensator
, to cancel
zero,
PBST,
be
 28 pole,
= Pcan
+ PBST + Pas
TOTAL
C +P
SWestimated
Q follows:
P1
FZ.
R
1
1
G
≈
,
ω ≈
,
ωZ =
,
(5) Then,PWM
the parameters
of the pcompensation
network
GCA15⋅.9R S
RCO
R ESR C O
PQ = VIN ⋅ 2mA
PC = D ⋅ VCESAT ⋅ IO
10 20by
can be calculated
R7 =
= 22 . 3 k
AC
0 . 28
⋅ 10 −3
1
10 20
PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW
R7 =
(10)
1
2
C 5 = gm
=
0
.
45
nF
2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3
I
1
PBST = D ⋅ VBST ⋅ O
C5 =
1
40
C 8 = 2 πFZ1 R 7 3
= 12pF
2 π⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3
1
where PVBST=is(1the
voltage and tS is the equivalent
C8 =
− DBST
) ⋅ Vsupply
D
D ⋅ IO
2 πFP1 R 7
GPWM (1 + s R ESR C O )
Vo
=
Vc (1 + s / ωp )(1 + s / ωn Q + s 2 / ωn2 )
14
P = (1 .1 ~ 1 .3 ) ⋅ I2 ⋅ R
IND
O
DC
SC4524C
switching time of the NPN transistor (see Table 4).
Table 4. Typical switching time
Input Voltage
12V
24V
28V
+ PBST +InPaddition,
the quiescent current loss is
Q
W
O
N
Load Current
1A
2A
12.5ns
15.3ns
22ns
25ns
25.3ns
28ns
PQ = VIN ⋅ 2mA
(11)
The total power loss of the SC4524C is therefore
⋅ I O ⋅ FSW
IO
40
⋅ IO
PTOTAL = PC + PSW + PBST + PQ
(12)
The temperature
rise⋅ of
= Fig.9
Vproduct
IN ⋅ 2 mA of the
PC = D ⋅ VCESAT
IO the SC4524C PisQthe
total power dissipation (Equation (12)) and qJA (36oC/W),
which is the thermal
impedance from junction to ambient
1
⋅ t S ⋅package.
VIN ⋅ I O ⋅ FSW
SW =
for thePSOIC-8
EDP
2
PCB Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation, the size of the loop formed by these components
should be minimized. Since the power switch is already
integrated within the SC4524C, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
I
) ⋅ I2O ⋅ R DCIt is not recommended
PBST = D ⋅ VBST ⋅ O to operate the SC4524C above
o
40
125 C junction temperature.
In the applications with high
input voltage and high output current, the switching
frequency
need
PD =may
(1 − D
) ⋅ VD to
⋅ IObe reduced to meet the thermal
requirement.
V IN
VOUT
PIND = (1 .1 ~ 1 .3 ) ⋅ I2O ⋅ R DC
ZL
Figure 9. Heavy lines indicate the critical pulse
current loop. The stray inductance of this
loop should be minimized.
C
Vin
15
SC4524C
Recommended Component Parameters in Typical Applications
Table 5 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output
voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator
parameters are calculated by assuming a 22mF low ESR ceramic output capacitor and a loop gain crossover frequency
of FSW/10.
Table 5. Recommended inductance (L1) and compensator (R7, C5, C8)
SC4524C
Compensator Parameters
Vin(V)
12
24
Typical Applications
Vo(V)
Io(A)
Fsw(kHz)
1
1.5
500
2
500
1
1000
2.5
500
2
1000
500
1
1000
3.3
500
2
1000
500
1
1000
5
500
2
1000
500
1
1000
7.5
500
2
1000
500
1
1000
10
500
2
1000
1
1.5
300
2
1
2.5
2
500
1
3.3
2
500
1
1000
5
500
2
1000
500
1
1000
7.5
500
2
1000
500
1
1000
10
500
2
1000
C2(uF)
22
Recommended Parameters
L1(uH)
R7(k)
C5(nF)
C8(pF)
8.2
4.32
3.3
10
4.7
15
6.81
1.5
22
6.8
12.1
0.82
10
6.8
6.81
1.5
22
3.3
12.1
0.68
10
15
9.09
1
22
8.2
18.7
0.68
10
8.2
9.09
1
22
4.7
18.7
0.68
15
14.3
0.82
10
24.9
0.68
8.2
14.3
0.82
4.7
27.4
0.68
15
21.5
0.82
10
8.2
38.3
0.68
8.2
21.5
0.82
4.7
38.3
0.68
10
25.5
0.82
4.7
51.1
0.68
4.7
25.5
0.82
2.2
51.1
0.68
10
5.49
3.3
47
8.2
15
7.5
1.5
8.2
10
22
9.09
1
10
22
12.1
0.82
22
15
26.1
0.68
10
10
12.1
0.82
22
6.8
26.1
0.68
10
33
21.5
0.82
15
38.3
0.68
10
21.5
0.82
22
8.2
38.3
0.68
10
22
26.1
0.82
22
10
51.1
0.68
10
10
26.1
0.82
22
8.2
51.1
0.68
10
16
SC4524C
Typical Application Schematics
V IN
D1
D3
24V
18V Zener 1N4148
C4
4.7PF
C1
0.33PF
BST
IN
SW
L1
OUT
8.2PH
1.5V/2A
R4
33.2k
SC4524C
SS/EN
FB
COMP
C7
10nF
C8
47pF
ROSC
GND
D2
R5
69.8k
R7
5.49k
R6
66.5k
20BQ030
C2
22PF
C5
3.3nF
L1: Coiltronics DR73-8R2
C2: Murata GRM31CR60J226K
C4: Murata GRM32ER71H475K
Figure 10. 300kHz 24V to 1.5V/2A Step-down Converter
V IN
D1
10V – 26V
C4
4.7PF
1N4148
C1
0.33PF
L1
BST
IN
SW
8.2PH
SC4524C
SS/EN
OUT
R4
33.2k
3.3V/2A
FB
COMP
C7
10nF
C8
33pF
R7
10.7k
ROSC
GND
R5
25.5k
C5
1nF
L1: Coiltronics DR73-8R2
R6
D2
20BQ030
14.3k
C2
22PF
C2: Murata GRM31CR60J226M
C4: Murata GRM32ER71H475K
Figure 11. 700kHz 10V-26V to 3.3V/2A Step-down Converter
17
TR
SC4524C
Fig.12(b) SS
Typical Performance Characteristics
(For A 24V to 5V/2A Step-down Converter with 1MHz Switching Frequency)
SS270 REV 6-7
Load Characteristic
6
Output Voltage (V)
5
24V Input (10V/DIV)
4
3
5V Output (2V/DIV)
2
1
SS Voltage (1V/DIV)
0
0
0.5
1
1.5
2
2.5
3
Load Current (A)
Fig.12(d) OCP
Figure 12(a). Load Characteristic
10ms/DIV
Figure 12(b). VIN Start up Transient (IO=2A)
5V Output Short (5V/DIV)
5V Output Response (500mV/DIV, AC Coupling)
Inductor Current (1A/DIV)
Retry Inductor Current (2A/DIV)
SS Voltage (2V/DIV)
40us/DIV
Figure 12(c). Load Transient Response
(IO= 0.3A to 2A)
20ms/DIV
Figure 12(d). Output Short Circuit (Hiccup)
18
SC4524C
Outline Drawing - SOIC-8 EDP
A
D
e
N
2X E/2
E1 E
1
2
ccc C
2X N/2 TIPS
e/2
B
D
aaa C
SEATING
PLANE
A2 A
C
bxN
bbb
A1
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
A
A1
A2
b
c
D
E1
E
e
F
H
h
L
L1
N
01
aaa
bbb
ccc
.069
.005
.065
.020
.010
.193 .197
.154 .157
.236 BSC
.050 BSC
.116 .120 .130
.085 .095 .099
.010
.020
.016 .028 .041
(.041)
8
0°
8°
.004
.010
.008
.053
.000
.049
.012
.007
.189
.150
C A-B D
1.75
0.13
1.65
0.51
0.25
4.90 5.00
3.90 4.00
6.00 BSC
1.27 BSC
2.95 3.05 3.30
2.15 2.41 2.51
0.25
0.50
0.40 0.72 1.04
(1.05)
8
0°
8°
0.10
0.25
0.20
1.35
0.00
1.25
0.31
0.17
4.80
3.80
h
F
EXPOSED PAD
h
H
H
c
GAGE
PLANE
0.25
L
(L1)
SEE DETAIL
SIDE VIEW
A
DETAIL
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
REFERENCE JEDEC STD MS -012, VARIATION BA.
4.
-H-
19
SC4524C
Land Pattern - SOIC-8 EDP
E
SOLDER MASK
D
DIMENSIONS
DIM
(C)
F
G
Z
Y
THERMAL VIA
Ø 0.36mm
P
X
C
D
E
F
G
P
X
Y
Z
INCHES
(.205)
.134
.201
.101
.118
.050
.024
.087
.291
MILLIMETERS
(5.20)
3.40
5.10
2.56
3.00
1.27
0.60
2.20
7.40
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2.
REFERENCE IPC-SM-782A, RLP NO. 300A.
3.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
20
SC4524C
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Phone: (805) 498-2111 Fax: (805) 498-3804
21