FAIRCHILD FIN224C

FIN224C
24-Bit Low-Power Serializer/Deserializer
Features
Data & Control Bits
Frequency
Capability
Interface
µController Usage
Dynamic Current
Standby Current
Core Voltage (VDDA/S)
I/O Voltage (VDDP)
ESD
Package
Ordering Information
Description
24
20MHz
HVGA
Microcontroller / RGB
I86 & m68
17mA at 10Mhz
10µA
2.5V to 3.3V
1.65V to 3.6V
15KV (IEC)
MLP-40 (6 x 6mm)
FIN224CMLX, MLP-40
Related Resources
ƒ For samples and questions, please contact:
The FIN224C μSerDes™ is a low-power serializer/
deserializer (μSerDes™) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred from
one point to another can be significantly reduced. Typical
reduction is 5:1 for unidirectional paths. Through the use of
differential signaling, shielding and EMI filters can also be
minimized, further reducing the cost of serialization.
The differential signaling is also important for providing a
noise-insensitive signal that can withstand radio and
electrical noise sources. Major reduction in power
consumption allows minimal impact on battery life in mobile
applications. It is possible to use a single Phase-Locked Loop
(PLL) for most applications, including bi-directional operation.
Applications
[email protected]
ƒ Slider, Folder, and Clamshell Mobile Handsets
ƒ GSM and CDMA Phones
Typical Application
Simple Interface
Serializer
+
-
70-130
Ohms
Deserializer
+
2
-
2
+
-
24-Bit Deserializer
24-Bit Serializer
Baseband
+
Built-in voltage
translation
Main
Display
Internal
Termination
Figure 1. Mobile Phone Example
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
October 2009
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Pin Configuration
Pin Name
STROBE
CKREF
CKP
DP[24:1]
/DIRO
Description
LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge)
LVCMOS Clock Input and PLL Reference
LVCMOS Word Clock Output
LVCMOS Data I/O
LVCMOS Control Output Inversion of DIRI
S1, S2
LVCMOS Select Pins, Controls the Mode of Operation, see Table 1
DIRI
LVCMOS Control, Selects Serializer or Deserializer Mode
DSO+ / DSIDSO- / DSI+
CKSI+, CKSICKSO+, CKSOVDDP
VDDS
VDDA
GND
0 Deserializer
1 Serializer
Serial Data I/O
Serial Clock Input
Serial Clock Output
Power Supply for Parallel I/O and Internal Circuitry
Power Supply for Serial I/O
Power Supply for Core
Ground Pins
32 STROBE
31 CKREF
33 DP[1]
34 DP[2]
35 DP[3]
36 DP[4]
37 DP[5]
38 DP[6]
39 DP[7]
40 DP[8]
Note:
1. 0 = VIL; 1 = VIH.
30 /DIRO
DP[9] 1
DP[10] 2
29 CKSO+
DP[11] 3
28 CKSO-
DP[12] 4
27 DSO+ / DSI-
VDDP 5
26 DSO- / DSI+
GND PAD
Must be Grounded
CKP 6
25 CKSI-
VDDA 20
S1 19
DP[24] 18
21 VDDS
DP[23] 17
DP[16] 10
DP[22] 16
22 S2
DP[21] 15
DP[15] 9
DP[20] 14
23 DIRI
DP[19] 13
DP[14] 8
DP[18] 12
24 CKSI+
DP[17] 11
DP[13] 7
Figure 2. MLP-40 Pinout (Through View)
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
2
Serializer / Deserializer, Operation, and Reset Modes
DIRI
S1
S2
Mode of Operation
Reset Mode
X
0
0
LVCMOS Outputs = High Impedance
LVCMOS Inputs = Known State
1
0
1
Serializer Mode
0
1
0
Deserializer Mode
Application Diagrams
Baseband
Processor
PCLK
DP[17:0]
HSYNC
VSYNC
/CS
Reset
Serializer
Deserializer
FIN224C
FIN224C
1.8V
2.8V
VDDP VDDS/A
2.8V
VDDP VDDS/A
CKREF
STROBE
CKP
CKSO+
DP[18:1]
CKSODP[19]
DP[20]
DSO+/DSIDP[21]
DSO-/DSI+
DP[24:22]
S1
S2
DIRI
/DIRO
CKP
2.8V
CKSI+
CKSI-
GND
DP[18:1]
DP[19]
DP[20]
DP[21]
DSO-/DSI+
DSO+/DSI- DP[24:22]
CKSI+
CKSI-
CKSO+
CKSO-
GND
Main Display
18-Bit RGB
PCLK
DATA[17:0]
HSYNC
VSYNC
/CS
RESET
S1
S2
DIRI
/DIRO
CKREF
STROBE
Figure 3. 18-Bit RGB Interface Block Diagram
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
3
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Table 1.
Baseband
Processor
/WE
DP[7:0]
DP[15:8]
A0
/CS0
/CS1
Reset
Serializer
Deserializer
FIN224C
FIN224C
1.8V
2.8V
VDDP VDDS/A
2.8V
VDDP VDDS/A
CKREF
STROBE
CKSO+
DP[8:1]
DP[
CKSODP[16:9]
DP
DP[17]
DP
DSO+/DSIDP[18]
DP[
DSO-/DSI+
DP
DP[19]
DP[24:
DP[24:20]
CKSI+
CKSIS1
S2
DIRI
GND
/DIRO
CKP
2.8V
CKP
DP[8:1]
DP
DP[:
DP[16:9]
DP
DP[17]
DP[18]
DP
DSO-/DSI+
DP[19]
DP
DSO+/DSIDP[24:20]
DP:
CKSI+
CKSI-
CKSO+
CKSO-
GND
S1
S2
DIRI
/DIRO
CKREF
STROBE
Main Display
16-Bit µController
/WE
DATA[7:0]
DATA[15:8]
A0
/CS0
Main Display
8-Bit µController
/WE
DATA[7:0]
A0
/CS1
Figure 4. Dual-Display µController Interface Block Diagram
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O
flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Keep all four differential serial wires the same length.
Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires.
Design goal of 70 to 130Ω differential characteristic impedance.
Do not place test points on differential serial wires.
Design differential serial wires a minimum of 2cm away from the antenna.
Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales
representative, or contact Fairchild directly at [email protected]fairchildsemi.com for applications notes or flex guidelines.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
4
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Clock
Source
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
Parameter
VDD
TSTG
Min.
Max.
Unit
Supply Voltage
-0.5
+4.6
V
All Input/Output Voltage
-0.5
+4.6
V
Storage Temperature Range
-65
+150
°C
TJ
Maximum Junction Temperature
+150
°C
TL
Lead Temperature (Soldering, 4 Seconds)
+260
°C
IEC 61000 Board Level
15.0
ESD
All Pins
2.5
Serial I/0, /RES, PAR/SPI to GND
8.0
kV
Human Body Model, JESD22-A114
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
VDDA, VDDS
VDDP
TA
(1)
Parameter
Min.
Max.
Unit
Supply Voltage
2.5
3.3
V
Supply Voltage
1.65
3.60
V
Operating Temperature
-30
+70
°C
Note:
1. VDDA and VDDS supplies must be hardwired together to the same power supply.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
5
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Absolute Maximum Ratings
Values valid for over supply voltage and operating temperature ranges unless otherwise specified. Typical values are tested
at TA = 25°C and VDD = 2.775V.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DC Parallel I/O Characteristics
VIH
Input High Voltage
0.65 x VDDP
VDDP
V
VIL
Input Low Voltage
GND
0.35 x VDDP
V
VOH
Output High Voltage
VDDP = 3.3±0.30V
IOH = -2.0mA
VDDP = 2.5±0.20V
0.75 x VDDP
V
VDDP = 1.8±0.18V
VDDP = 3.3±0.30V
VOL
Output Low Voltage
IOH = -2.0mA
VDDP = 2.5±0.20V
0.25 x VDDP
V
5
µA
VDDP = 1.8±0.18V
IIN
Input Current
-5
DC Serial Characteristics
IODH
Output High Source Current
IODL
Output Low Source Current
IOZ
Disabled Output Leakage Current
CKSO, DSO = 0V to VDDS,
S2 = S1 = 0V
IIZ
Disabled Input Leakage Current
CKSO, DSO = 0V to VDDS,
S2 = S1 = 0V
RTRM
Z
CKSI, DS Internal Receiver Termination Resistor
-1.75
mA
0.95
mA
±1
±5
±1
±5
Ω
100
Serial Transmission Line Impedance
70
100
µA
130
Ω
Power Characteristics
IDDA/SSER VDDA, VDDS Serializer Static Current
All DP and Control Inputs at 0V or No
CKREF, DIRI = 1
4.5
mA
IDDA/SDES VDDA, VDDS Derializer Static Current
All DP and Control Inputs at 0V or No
CKREF, DIRI = 0
5
mA
10MHz
11
mA
20MHz
15
mA
IDDSER
IDDDES
IDD_PD
Dynamic Serializer Current
IDDSER = IDDA + IDDS + IDDP
Dynamic Deserializer Current
IDDSER = IDDA + IDDS + IDDP
VDD Power-Down Current
IDD_PD = IDDA + IDDS + IDDP
CKREF = STROBE, DIRI = 1
CKREF = STROBE, DIRI = 0
10MHz
7
mA
20MHz
10
mA
0.1
µA
S1 = S2 = 0 All Inputs at GND or VDD
AC Serializer, DIRI = 1 Specifications
fMAX
Maximum CKREF Frequency
2
20
MHz
fREF
CKREF Frequency Relative to
STROBE
1.1 x fSTROBE
20
MHz
tCPWH
CKREF Clock HIGH Time
0.2
0.5
T
tCPWL
CKREF Clock LOW Time
0.2
0.5
T
tCLKT
LVCMOS Input Transition Time
tSPWH
STROBE Pulse Width HIGH/LOW
tSTC
DP[n] Setup to STROBE
tHTC
DP[n] Hold to STROBE
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
(Tx4) / 26
STROBE
tHTC
tSTC
DP[24:1]
90
ns
(Tx22) / 26
ns
2.5
ns
2.0
ns
www.fairchildsemi.com
6
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Electrical Specifications
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tTPLLS0
Phase Lock Loop Stabilization Time
200
µs
tTPLLD0
PLL Disable Time Loss of Clock
30
µs
AC Deserializer, DIRI = 0 Specifications
tSKEW_DS-
Allowed DS-CKS Input Signal Skew
-150
150
ps
tRCOH
CKP Out Low Time
13a-3
13a+3
ns
tRCOH
CKP Out High Time
13a-3
13a+13
ns
tPDV
Data Valid to CKP Low
8a-6
8a+1
ns
CKS
CKREF = STROBE, a = (1/f)/13
tROLH
Output Rise Time (20% to 80%)
18
ns
tROLH
Output Fall Time (20% to 80%)
18
ns
AC Enable and Disable Timing
tPLZ(HZ)
Deserializer Disable Time
25
ns
tPZL(ZH)
Deserializer Enable Time
2
µs
tPLZ(HZ)
Serializer Disable Time
25
ns
tPZL(ZH)
Serializer Enable Time
65
ns
Notes:
2. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of DSO. Signals are
edge aligned. Both outputs should have identical load condtions for this test to be valid.
3. If CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of
CKP remains 13 bit times.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
7
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Symbol
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
Physical Dimensions
0.15 C
6.00
B
A
(0.80)
6.00
PIN #1 IDENT
6.38MIN
4.37MAX
0.15 C
4.77MIN
0.80 MAX
0.10 C
0.08 C
(0.20)
0.05
0.00
0.20MIN
X4
C
0.28 MAX
SEATING
PLANE
X40
4.20
4.00
0.50TYP
E
0.50
0.30
0.50
4.20
4.00
(DATUM B)
(DATUM A)
PIN #1 ID
0.18-0.30
0.10
0.05
0.50
C A B
C
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION
WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION..
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994.
D. LAND PATTERN PER IPC SM-782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKT-MLP40Arev3.
Figure 6. 40-Lead, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which
covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/MLP40A.html
Ordering Information
Part Number
FIN224CMLX
Operating
Temperature Range
-30 to +70°C
Package
Eco Status
Green
40-Lead, Molded Leadless Package (MLP),
Quad, JEDEC MO-220, 6mm Square
Packing Method
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
8
µSerDes™ FIN224C — 24-Bit Low-Power Serializer/Deserializer
© 2009 Fairchild Semiconductor Corporation
FIN224C • Rev. 1.0.9
www.fairchildsemi.com
9