FREESCALE 68HC05BD7

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
68HC05BD7
68HC705BD7
68HC05BD2
SPECIFICATION
REV 2.0
(General Release)
 January 20, 1998
Technical Operation Taiwan
Taipei, Taiwan
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HC05BD7GRS/H
REV 2.0
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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Semiconductor,
Inc.
MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
TABLE OF CONTENTS
Freescale Semiconductor, Inc...
SECTION 1
GENERAL DESCRIPTION .............................................. 1
1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.2.3
1.2.3.1
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.2.10
1.2.11
1.2.12
1.2.13
1.3
SECTION 2
MEMORY ....................................................................... 11
2.1
2.2
2.3
2.4
SECTION 3
COP ..........................................................................................15
ROM .........................................................................................15
EPROM.....................................................................................15
RAM..........................................................................................15
CPU CORE..................................................................... 17
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.5.1
3.1.5.2
3.1.5.3
3.1.5.4
3.1.5.5
SECTION 4
4.1
4.2
4.3
Features......................................................................................1
Hardware Features................................................................1
Software Features .................................................................3
Signal Description.......................................................................7
VDD and VSS........................................................................7
IRQ/VPP................................................................................7
EXTAL, XTAL ........................................................................7
Crystal Oscillator..............................................................7
RESET ..................................................................................8
PA0-PA7................................................................................8
PB0-PB5................................................................................8
PC0*/PWM8*-PC1*/PWM9* ..................................................8
PC2/PWM10/ADC0- PC5/PWM13/ADC3 .............................8
PC6/PWM14/VSYNO, PC7/PWM15/HSYNO .......................8
PD0*/SDA*, PD1*/SCL* ........................................................8
PD2***/CLAMP, PD3*/SOG ..................................................8
PWM0**-PWM7** ..................................................................9
HSYNC, VSYNC ...................................................................9
Options .......................................................................................9
Registers...................................................................................17
Accumulator (A)...................................................................17
Index Register (X) ...............................................................18
Stack Pointer (SP)...............................................................18
Program Counter (PC) ........................................................18
Condition Code Register (CCR) ..........................................18
Half Carry Bit (H-Bit) ......................................................19
Interrupt Mask (I-Bit) ......................................................19
Negative Bit (N-Bit) ........................................................19
Zero Bit (Z-Bit) ...............................................................19
Carry/Borrow Bit (C-Bit) .................................................19
INTERRUPTS................................................................. 21
CPU Interrupt Processing .........................................................21
Reset Interrupt Sequence.........................................................23
Software Interrupt (SWI) ...........................................................23
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Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
4.4
4.4.1
4.4.2
4.4.3
4.4.4
SECTION 5
Freescale Semiconductor, Inc...
5.1
5.2
5.2.1
5.2.2
5.2.3
SECTION 6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
SECTION 7
7.1
7.2
7.3
7.4
7.5
7.6
SECTION 8
8.1
8.2
SECTION 9
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
Page ii
Hardware Interrupts.................................................................. 23
External Interrupt (IRQ)....................................................... 23
VSYNC Interrupt ................................................................. 24
DDC12AB Interrupt ............................................................. 24
Multi-Function Timer Interrupt (MFT) .................................. 25
RESETS..........................................................................27
External Reset (RESET) .......................................................... 27
Internal Resets ......................................................................... 27
Power-On Reset (POR) ...................................................... 27
Computer Operating Properly Reset (COPR)..................... 27
Illegal Address (ILADR) Reset ............................................ 28
OPERATING MODES ....................................................29
User Mode................................................................................ 29
SELF-CHECK MODE............................................................... 29
Bootstrap Mode ........................................................................ 29
Mode Entry ............................................................................... 29
EPROM Programming.............................................................. 30
Programming Sequence ..................................................... 30
Programming Control Register (PCR) ................................ 31
Low Power Modes.................................................................... 31
STOP Instruction................................................................. 31
WAIT Instruction ................................................................. 31
COP Watchdog Timer Considerations ..................................... 32
INPUT/OUTPUT PORTS ................................................33
Port A ....................................................................................... 33
Port B ....................................................................................... 33
Port C ....................................................................................... 33
Port D ....................................................................................... 33
Input/Output Programming ....................................................... 34
Port C and D Configuration Register........................................ 35
PULSE WIDTH MODULATION......................................37
Operation of 8-Bit PWM ........................................................... 37
Open-Drain Option Register..................................................... 38
DDC12AB INTERFACE .................................................39
Introduction............................................................................... 39
DDC12AB Features.................................................................. 39
Registers .................................................................................. 40
DDC Address Register (DADR) .......................................... 40
DDC Control Register (DCR) .............................................. 40
DDC Master Control Register (DMCR) ............................... 41
DDC Status Register (DSR)................................................ 43
DDC Data Transmit Register (DDTR)................................. 44
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
9.3.6
9.4
9.5
Freescale Semiconductor, Inc...
SECTION 10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.4
SECTION 11
11.1
11.2
11.2.1
11.2.2
SECTION 12
12.1
12.2
12.2.1
12.3
12.3.1
12.3.2
12.4
SECTION 13
13.1
13.2
13.3
13.4
13.5
13.5.1
13.5.2
13.6
SECTION 14
14.1
14.2
14.3
DDC Data Receive Register (DDRR)..................................44
Data Sequence .........................................................................45
Program Algorithm....................................................................45
SYNC PROCESSOR...................................................... 49
Introduction ...............................................................................49
Functional Blocks......................................................................49
Polarity Detection ................................................................49
Sync Signal Counters..........................................................49
Polarity Controlled HSYNO/VSYNO Outputs ......................49
CLAMP Pulse Output ..........................................................50
Registers...................................................................................51
Sync Processor Control and Status Register (SPCSR) ......51
Sync Processor Input/Output Control Register (SPIOCR) ..52
Vertical Frequency Registers (VFRs)..................................53
Hsync Frequency Registers (HFRs)....................................54
System Operation .....................................................................54
MULTI-FUNCTION TIMER............................................. 57
Introduction ...............................................................................57
Register ....................................................................................57
Multi-function Timer Control/status Register .......................57
MFT Timer Counter Register...............................................59
A/D CONVERTER.......................................................... 61
Introduction ...............................................................................61
Input..........................................................................................61
ADC0-ADC3 ........................................................................61
Registers...................................................................................62
ADC Control/status Register ...............................................62
ADC Channel Register ........................................................62
Program Example .....................................................................63
ELECTRICAL SPECIFICATIONS.................................. 65
Maximum Ratings .....................................................................65
Thermal Characteristics............................................................65
DC Electrical Characteristics ....................................................66
Control Timing ..........................................................................67
DDC12AB TIMING....................................................................68
DDC12AB Interface Input Signal Timing .............................68
DDC12AB Interface Output Signal Timing ..........................68
HSYNC/VSYNC Input Timing ...................................................69
MECHANICAL SPECIFICATIONS ................................ 71
Introduction ...............................................................................71
40-Pin DIP Package (Case 711-03) .........................................71
42-Pin SDIP Package (Case 858-01) .......................................71
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GENERAL RELEASE SPECIFICATION
Rev. 2.0
APPLICATION DIAGRAM .............................................73
Freescale Semiconductor, Inc...
SECTION 15
Page iv
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
Freescale Semiconductor, Inc...
LIST OF FIGURES
Figure 1-1: MC68HC05BD7 Block Diagram .....................................................................4
Figure 1-2: MC68HC05BD7/BD2 40-Pin DIP Pin Assignment .........................................5
Figure 1-3: MC68HC05BD7/BD2 42-Pin SDIP Pin Assignment.......................................6
Figure 1-4: Oscillator Connections ...................................................................................7
Figure 2-1: The 16K Memory Map of the MC68HC05BD7.............................................11
Figure 2-2: MC68HC05BD7 I/O Register $00-$0F.........................................................12
Figure 2-3: MC68HC05BD7 I/O Register $10-$1F.........................................................13
Figure 2-4: MC68HC05BD7 I/O Register $20-$2F.........................................................14
Figure 3-1: MC68HC05 Programming Model .................................................................17
Figure 4-1: Interrupt Processing Flowchart ....................................................................22
Figure 4-2: External Interrupt..........................................................................................24
Figure 6-1: Mode Entry Diagram ....................................................................................30
Figure 6-2: WAIT Flowcharts..........................................................................................32
Figure 7-1: Port I/O Circuitry...........................................................................................34
Figure 8-1: PWM Data Register .....................................................................................37
Figure 8-2: Relationship Between 5-Bit PWM and 3-Bit BRM........................................38
Figure 8-3: PWM Open-Drain Option Register...............................................................38
Figure 9-1: Software Flowchart of Slave Mode Interrupt Routine...................................47
Figure 9-2: Software Flowchart in Master mode: (a) Mode setup. (b) Interrupt routine..48
Figure 10-1: CLAMP output waveform ...........................................................................50
Figure 12-1: Structure of A/D Converter.........................................................................61
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Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
Page vi
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Semiconductor,
Inc.
MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
LIST OF TABLES
Freescale Semiconductor, Inc...
Table 4-1: Vector Address for Interrupts and Reset .......................................................21
Table 6-1: Mode Select Summary ..................................................................................30
Table 7-1: I/O Pin Functions...........................................................................................35
Table 9-1: Pre-scaler of Master Clock Baudrate ............................................................42
Table 11-1: COP Reset Rates and RTI Rates................................................................59
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Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
GENERAL DESCRIPTION
SECTION 1
The MC68HC05BD7 HCMOS microcontroller is a member of the M68HC05 Family of lowcost single-chip microcontrollers. It is particularly suitable as multi-sync computer monitor
controller. This 8-bit microcontroller unit (MCU) contains an on-chip oscillator, CPU, RAM,
ROM, DDC12AB module, parallel I/O, Pulse Width Modulator, Multi-Function Timer, 6-bit
ADC, and SYNC Processor.
1.1
Features
HC05 Core
•
Low cost, HCMOS technology
•
40-pin DIP and 42-pin SDIP packages
•
256 Bytes of RAM for HC05BD2
•
384 Bytes of RAM for HC05BD7HC705BD7
•
5.75K-Bytes of User ROM for HC05BD2
•
11.75K-Bytes of User ROM for HC05BD7
•
11.5K-Bytes of User EPROM for HC705BD7
•
26 Bidirectional I/O lines: 14 dedicated and 12 multiplexed I/O lines. 4 of
the 14 dedicated I/O lines and 6 of the 12 multiplexed I/O lines have max.
+12V or +5V open-drain output buffers
•
16 x 8-bit PWM channels: Two 8-bit PWM channels have +12V opendrain outputs: 8 dedicated 8-bit PWM channels have +5V open-drain
output options
•
EL
IM
IN
A
R
•
•
† DDC
Y
Hardware Features
PR
Freescale Semiconductor, Inc...
1.1.1
6-bit ADC with 4 selectable input channels
Multi-Function Timer (MFT) with Periodic Interrupt
•
Sync Signal Processor module for processing horizontal, vertical,
composite, and SOG SYNC signals; frequency counting; polarity
detection; polarity controlled HSYNO and VSYNO or extracted VSYNC
outputs, and CLAMP pulse output
•
DDC12AB† module contains DDC1 hardware and multi-master I2C††
hardware for DDC2AB protocol
•
Software maskable Edge-Sensitive or Edge and Level-Sensitive External
Interrupt
is a standard defined by VESA.
is a proprietary Philips interface bus.
†† I2C-bus
SECTION 1: GENERAL DESCRIPTION
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Page 1
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
COP watchdog Reset
•
Power-On Reset
•
Power Saving WAIT Mode; STOP Mode not implemented
PR
EL
IM
IN
A
R
Y
Freescale Semiconductor, Inc...
•
SECTION 1: GENERAL DESCRIPTION
Page 2
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Semiconductor,
Inc.
MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
Software Features
Similar to MC6800
•
8 X 8 unsigned multiply instruction
•
Efficient use of program space
•
Versatile interrupt handling
•
Software programmable external interrupt options
•
True bit manipulation
•
Addressing modes with indexed addressing for tables
•
Efficient instruction set
•
Memory mapped I/O
•
Upward software compatible with the MC146805 CMOS family
EL
IM
IN
A
R
Y
•
PR
Freescale Semiconductor, Inc...
1.1.2
SECTION 1: GENERAL DESCRIPTION
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Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
PA0
PWM0**
VDD
PA1
PWM1**
VSS
PA2
PA3
PA4
EXTAL XTAL
PORT
A
REG
DATA
DIR
REG
CORE
TIMER
(COP)
OSCILLATOR
AND DIVIDE
BY 2
PA5
PWM2**
PWM3**
PWM4**
PWM5**
PA6
Y
PWM6**
CPU CONTROL
ALU
PWM7**
6-bit ADC
A
PB0
R
PA7
68HC05 CPU
PB3*
PORT
B
REG
ACCUM
DATA
DIR
REG
DDC12AB
CPU REGISTERS
INDEX REG
IM
PB4*
0 0 0 0 0 0 0 0 1 1 STK PTR
PB5*
EL
PROGRAM COUNTER
COND CODE REG 1 1 1 H I N Z C
PC0*/PWM8*
PC1*/PWM9*
PR
PC2/PWM10/ADC0
PC3/PWM11/ADC1
PC4/PWM12/ADC2
PC5/PWM13/ADC3
PC6/PWM14/VSYNO
PC7/PWM15/HSYNO
PORT DATA
C
DIR
REG REG
5.75K-bytes ROM for
HC05BD2
11.75K-bytes ROM
for HC05BD7
11.5K-bytes EPROM
for HC705BD7
RAM
DATA PORT
DIR
D
REG REG
SP DDC12AB
PB2*
IN
PB1
PWM/ADC/HVPROCESSOR
Freescale Semiconductor, Inc...
RESET IRQ/VPP
Pulse
Width
Modulation
(PWM)
SYNC
PROCESSOR
PD0*/SDA*
PD1*/SCL*
PD2***/CLAMP
PD3*/SOG
HSYNC
VSYNC
256 bytes for HC05BD2
384 bytes for HC05BD7
384 bytes for HC705BD7
***: +5V open-drain
**: +5V open-drain option
*: +12V open-drain
IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version
Figure 1-1: MC68HC05BD7 Block Diagram
SECTION 1: GENERAL DESCRIPTION
Page 4
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1
40
VSYNC
PWM1**
2
39
HSYNC
PWM0**
3
38
PWM3**
RESET
4
37
PWM4**
VDD
5
36
PWM5**
VSS
6
35
PWM6**
XTAL
7
34
PWM7**
EXTAL
8
33
PC7/PWM15/HSYNO
PB5*
9
32
PC6/PWM14/VSYNO
PB4*
10
PB3*
11
31
PC5/PWM13/ADC3
30
PC4/PWM12/ADC2
29
PC3/PWM11/ADC1
28
PC2/PWM10/ADC0
27
PC1*/PWM9*
A
MC68HC05BD7
R
Y
PWM2**
40-PIN DIP
12
PB1
13
PB0
14
IRQ/VPP
15
26
PC0*/PWM8*
PA7
16
25
PD1*/SCL*
PA6
17
24
PD0*/SDA*
18
23
PA0
19
22
PA1
20
21
PA2
PA4
IM
EL
PA5
PA3
IN
PB2*
PR
Freescale Semiconductor, Inc...
Semiconductor,
Inc.
MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
**: +5V open-drain option
*: +12V open-drain
IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version
Figure 1-2: MC68HC05BD7/BD2 40-Pin DIP Pin Assignment
SECTION 1: GENERAL DESCRIPTION
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1
42
VSYNC
PWM1**
2
41
HSYNC
PWM0**
3
40
PWM3**
RESET
4
39
PWM4**
VDD
5
38
PWM5**
PD3*/SOG
6
37
PD2***/CLAMP
VSS
7
36
PWM6**
XTAL
8
35
PWM7**
EXTAL
9
34
PC7/PWM15/HSYNO
11
PB3*
12
PB2*
13
PB1
14
PB0
15
IRQ/VPP
16
PA7
17
PA6
18
PA5
PA4
PC6/PWM14/VSYNO
32
PC5/PWM13/ADC3
31
PC4/PWM12/ADC2
30
PC3/PWM11/ADC1
PC2/PWM10/ADC0
28
PC1*/PWM9*
27
PC0*/PWM8*
26
PD1*/SCL*
25
PD0*/SDA*
19
24
PA0
20
23
PA1
21
22
PA2
IM
29
PR
PA3
42-PIN SDIP
33
R
PB4*
MC68HC05BD7
A
10
IN
PB5*
Y
PWM2**
EL
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
***: +5V open-drain option
**: +5V open-drain option
*: +12V open-drain
IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version
Figure 1-3: MC68HC05BD7/BD2 42-Pin SDIP Pin Assignment
SECTION 1: GENERAL DESCRIPTION
Page 6
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
1.2
Signal Description
1.2.1
VDD and VSS
VDD is the positive supply pin and VSS is the ground pin.
1.2.2
IRQ/VPP
Y
1.2.3
EXTAL, XTAL
A
1. A crystal as shown in Figure 1-4(a)
R
The EXTAL and XTAL pins are the connections for the on-chip oscillator. The EXTAL, and
XTAL pins can accept the following sets of components:
IN
2. An external clock signal as shown in Figure 1-4(b)
IM
The frequency, fOSC, of the oscillator or external clock source is divided by two to produce
the internal operating frequency, fOP.
1.2.3.1
Crystal Oscillator
EL
The circuit in shows Figure 1-4(a) a typical oscillator circuit for an AT-cut, parallel resonant
crystal. The crystal manufacturer’s recommendations should be followed, as the crystal
parameters determine the external component values required to provide maximum
stability and reliable start-up. The load capacitance values used in the oscillator circuit
design should include all stray capacitances. The crystal and components should be
mounted as close as possible to the pins for start-up stabilization and to minimize output
distortion. An internal start-up resistor of approximately 2 MΩ is provided between
EXTAL and XTAL for the crystal type oscillator.
PR
Freescale Semiconductor, Inc...
This pin has two functions. While in user mode, this pin serves as IRQ, a general purpose
interrupt input which is software programmable for two choices of interrupt triggering
sensitivity. These options are: 1) negative edge-sensitive triggering only, or 2) both
negative edge-sensitive and level-sensitive triggering. In the latter case, either type of input
to the IRQ pin will produce the interrupt. This interrupt can be inhibited by setting the
INHIRQ bit in the MFT register. While in bootstrap mode, this pin is used as VPP pin for
HC705 version. It is used to supply high voltage needed for programming the user EPROM.
MCU
EXTAL
MCU
XTAL
EXTAL
(a) Crystal or
Ceramic Resonator
Connections
36 pF
36 pF
XTAL
unconnected
External Clock
(b) External
Clock Source
Connection
Figure 1-4: Oscillator Connections
SECTION 1: GENERAL DESCRIPTION
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GENERAL RELEASE SPECIFICATION
Rev. 2.0
1.2.4
RESET
This active low input-only pin is used to reset the MCU to a known start-up state. The
RESET pin contains an internal Schmitt trigger as part of its input to improve noise
immunity. See SECTION 5 for more details.
1.2.5
PA0-PA7
These eight I/O lines comprise Port A. The state of any pin is software programmable and
all Port A lines are configured as inputs during Reset. See SECTION 7 for a detailed
description of I/O programming.
PB0-PB5
PC0*/PWM8*-PC1*/PWM9*
R
1.2.7
Y
These six I/O lines comprise Port B. The state of any pin is software programmable and all
Port B lines are configured as inputs during Reset. PB2 to PB5 are +12V open-drain pins.
See SECTION 7 for a detailed description of I/O programming.
PC2/PWM10/ADC0- PC5/PWM13/ADC3
IM
1.2.8
IN
A
These two +12V open-drain pins are either 8-bit PWM channels 8 to 9 outputs or general
purpose I/O port C. The state of any pin is software programmable and all Port C lines are
configured as inputs during Reset. See SECTION 7 for a detailed description of I/O
programming.
1.2.9
EL
These four pins can be selected as general purpose I/O of port C, PWM or ADC input
channel 0-2. See SECTION 7 for how to configure the pins. Also see SECTION 8 and
SECTION 12 for a detailed description of these modules.
PC6/PWM14/VSYNO, PC7/PWM15/HSYNO
These two pins can be selected as general purpose I/O of port C, PWM or sync signal
outputs. See SECTION 7 for how to configure the pins. Also see SECTION 8 and SECTION
10 for a detailed description of these modules.
1.2.10
PR
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1.2.6
PD0*/SDA*, PD1*/SCL*
These pins are either general purpose I/O pins of port D or the data line (SDA) and clock
line (SCL) of DDC12AB. These two pins are open-drain pins. See SECTION 7 for how to
configure the pins. See SECTION 9 for a detailed description.
1.2.11
PD2***/CLAMP, PD3*/SOG
The PD2*** is +5V open-drain general purpose I/O pin and the PD3* is +12V open-drain
general purpose I/O pin. The PD2 pin could become the CLAMP pulse push-pull output to
Pre-AMP IC and the PD3 pin could become the SOG digital input of the Sync Processor
when the corresponding enable bit in SPIOCR register is set. These two pins will not be
bonded out in 40-pin DIP package.
SECTION 1: GENERAL DESCRIPTION
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GENERAL
RELEASE SPECIFICATION
1.2.12
PWM0**-PWM7**
These pins are dedicated for 8-bit PWM channels 0 to 7, which have +5V open-drain
software options. See SECTION 8 for a detailed description.
1.2.13
HSYNC, VSYNC
These two input pins are for video sync signals input from the host computer. The signals
will be used for video mode detection and output to HSYNO and VSYNO. The host
computer can also send a composite sync signal to the HSYNC input. This composite
signal will be separated internally. The polarity of the input signals can be either positive or
negative. These two pins contain internal Schmitt triggers as part of their inputs to improve
noise immunity. See SECTION 10 for a detail description.
Y
Options
EL
IM
IN
A
R
MC68HC05BD7 provides an option for IRQ interrupt edge only sensitivity or edge and level
sensitivity and one option register for individual PWM channels 0 to 7 to be programmed
as open-drain type output. The IRQ option is selected by setting the appropriate bit in the
MFTCSR register at address $0008 and the PWM open-drain option register is located at
address $0012.
PR
Freescale Semiconductor, Inc...
1.3
SECTION 1: GENERAL DESCRIPTION
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PR
EL
IM
IN
A
R
Y
Freescale Semiconductor, Inc...
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Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
SECTION 1: GENERAL DESCRIPTION
Page 10
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2.0
GENERAL
RELEASE SPECIFICATION
SECTION 2
MEMORY
The MC68HC05BD7 has a 16K byte memory map, consisting of user ROM/EPROM, RAM,
Self-Check/Bootstrap ROM, and I/O as shown in Figure 2-1.
$0000
I/O
48 Bytes
Y
$00C0
R
Stack
RAM
64 Bytes
256 Bytes for HC05BD2
384 Bytes for HC05BD7/HC705BD7
A
$0100
IN
$01B0
IM
Unused
$0E00
480 Bytes Bootstrap ROM for HC705BD7
Unused in HC05BD2/HC05BD7
EL
$0FE0
$1000
PR
Freescale Semiconductor, Inc...
$0030
$2800
User ROM
5.57K-bytes for HC05BD2
11.75K-bytes for HC05BD7
User EPROM
11.5K-bytes for HC705BD7
$3E00
$3F00 224 Bytes Self-Check ROM for HC05BD2/HC05BD7
Unused in HC705BD7
$3FE0
Self-Check/Bootstrap Vectors 16 Bytes
$3FF0
$3FFF
User Vectors 16 Bytes
Figure 2-1: The 16K Memory Map of the MC68HC05BD7
SECTION 2: MEMORY
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Page 11
$0001
$0002
$0003
$0005
$0006
W
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB5
PB4
PB3
PB2
PB1
PB0
PC5
PC4
PC3
PC2
PC1
PC0
PD3
PD2
PD1
PD0
DDRA2
DDRA1
DDRA0
DDRB2
DDRB1
DDRB0
DDRC3
DDRC2
DDRC1
DDRC0
DDRD3
DDRD2
DDRD1
DDRD0
IRQN
INHIRQ
RT1
RT0
R
PORT B DATA
PORTB
W
R
PORT C DATA
PORTC
PC7
W
PC6
R
PORT D DATA
PORTD
W
R
PORT A DATA DIRECTION
DDRA
W
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRB5
DDRB4
DDRB3
DDRC5
DDRC4
R
PORT B DATA DIRECTION
DDRB
W
R
PORT C DATA DIRECTION
DDRC
W
DDRC7
DDRC6
R
$0007
PORT D DATA DIRECTION
DDRD
W
$0008
MFT CTRL/STATUS REG
MFTCSR
W
$0009
5
R
R
TOF
MFT TIMER COUNTER REG
MFTCR
RTIF
TOFIE
RTIE
R MFTCR7 MFTCR6 MFTCR5 MFTCR4 MFTCR3 MFTCR2 MFTCR1 MFTCR0
W
R
$000A
CONFIGURATION REG 1
CR1
$000B
CONFIGURATION REG 2
CR2
$000C
SP CONTROL & STATUS
SPCSR
W
$000D
VERT FREQUENCY HIGH REG
VFHR
W
$000E
VERT FREQUENCY LOW REG
VFLR
$000F
HOR FREQUENCY HIGH REG
HFHR
W
R
PWM15
PWM14 PWM13 PWM12 PWM11 PWM10
PWM9
PWM8
ADC2
ADC1
ADC0
SCL
SDA
COMP
VINVO
HINVO
VPOL
HPOL
EL
HSYNO VSYNO
W
R
PR
Freescale Semiconductor, Inc...
$0004
6
R
PORT A DATA
PORTA
7
A
$0000
READ
WRITE
IN
REGISTER
IM
ADDR
Y
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
R
R
ADC3
VSIF
VSIE
VEDGE
VOF
0
0
VF12
VF11
VF7
VF6
VF5
VF4
HOVER
HFH6
HFH5
HFH4
VF10
VF9
VF8
VF3
VF2
VF1
VF0
HFH3
HFH2
HFH1
HFH0
W
R
W
UNIMPLEMENTED
RESERVED
Figure 2-2: MC68HC05BD7 I/O Register $00-$0F
SECTION 2: MEMORY
Page 12
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GENERAL
RELEASE SPECIFICATION
ADDR
$0010
$0011
$0012
$0013
REGISTER
READ
WRITE
7
6
5
4
3
2
1
0
R
0
0
0
HFL4
HFL3
HFL2
HFL1
HFL0
SOGIN
CLAMP
BPOR
SOUT
HOR FREQUENCY LOW REG
HFLR
SP IO CONTROL REG
SPIOCR
PWM OPEN-DRAIN OPTION
REGISTER
W
R VSYNCS HSYNCS
R
7PWMO 6PWMO 5PWMO 4PWMO 3PWMO 2PWMO 1PWMO 0PWMO
W
R
UNIMPLEMENTED
COINV
W
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
AD5
AD4
AD3
AD2
AD1
AD0
CHSL1
CHSL0
W
$0014
ADC CONTROL/STATUS REG
R RESULT
ADC CHANNEL REGISTER
R
Y
$0015
$0019
$001A
$001B
$001C
DDC STATUS REGISTER
DSR
DDC DATA TRANSMIT REG
DDTR
DDC DATA RECEIVE REG
DDRR
NAKIF
BB
DAD7
DAD6
DEN
DIEN
RXIF
TXIF
MATCH
RW
RXAK
SCLIF
TXBE
RXBF
DTD7
DTD6
DTD5
DTD4
DTD3
DTD2
DTD1
DTD0
DRD7
DRD6
DRD5
DRD4
DRD3
DRD2
DRD1
DRD0
ELAT
PGM
R
W
R
W
R
W
R
MAST
A
DDC CONTROL REGISTER
DCR
ALIF
W
DAD5
IN
$0018
DDC ADDRESS REGISTER
DADR
R
IM
$0017
DDC MASTER CONTROL REG
DMCR
DAD4
MRW
BR2
BR1
BR0
DAD3
DAD2
DAD1
EXTAD
TXAK
SCLIEN DDC1EN
W
R
EL
$0016
R
W
W
R
UNIMPLEMENTED
W
$001D
$001E
$001F
R
RESERVED FOR EPROM
CONTROL PCR
W
UNIMPLEMENTED
R
PR
Freescale Semiconductor, Inc...
W
RESERVED
W
R
W
UNIMPLEMENTED
RESERVED
Figure 2-3: MC68HC05BD7 I/O Register $10-$1F
SECTION 2: MEMORY
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GENERAL RELEASE SPECIFICATION
Rev. 2.0
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
0
0PWM4 0PWM3 0PWM2 0PWM1 0PWM0
0BRM2
0BRM1
0BRM0
1PWM4 1PWM3 1PWM2 1PWM1 1PWM0
1BRM2
1BRM1
1BRM0
2PWM4 2PWM3 2PWM2 2PWM1 2PWM0
2BRM2
2BRM1
2BRM0
3PWM4 3PWM3 3PWM2 3PWM1 3PWM0
3BRM2
3BRM1
3BRM0
4PWM4 4PWM3 4PWM2 4PWM1 4PWM0
4BRM2
4BRM1
4BRM0
5BRM2
5BRM1
5BRM0
6BRM2
6BRM1
6BRM0
7BRM2
7BRM1
7BRM0
8PWM4 8PWM3 8PWM2 8PWM1 8PWM0
8BRM2
8BRM1
8BRM0
9PWM4 9PWM3 9PWM2 9PWM1 9PWM0
9BRM2
9BRM1
9BRM0
R
W
R
W
R
W
W
Y
R
5PWM4 5PWM3 5PWM2 5PWM1 5PWM0
R
PULSE WIDTH MODULATOR
6PWM
W
6PWM4 6PWM3 6PWM2 6PWM1 6PWM0
R
PULSE WIDTH MODULATOR
7PWM
W
7PWM4 7PWM3 7PWM2 7PWM1 7PWM0
R
PULSE WIDTH MODULATOR
8PWM
W
R
PULSE WIDTH MODULATOR
9PWM
W
R
PULSE WIDTH MODULATOR
10PWM
W
R
PULSE WIDTH MODULATOR
11PWM
10PWM4 10PWM3 10PWM2 10PWM1 10PWM0 10BRM2 10BRM1 10BRM0
11PWM4 11PWM3 11PWM2 11PWM1 11PWM0 11BRM2 11BRM1 11BRM0
EL
$0027
1
R
PULSE WIDTH MODULATOR
5PWM
$0026
W
PULSE WIDTH MODULATOR
3PWM
$0025
2
R
PULSE WIDTH MODULATOR
2PWM
PULSE WIDTH MODULATOR
4PWM
3
W
PULSE WIDTH MODULATOR
1PWM
$0024
4
R
PULSE WIDTH MODULATOR
0PWM
W
R
PULSE WIDTH MODULATOR
12PWM
PULSE WIDTH MODULATOR
13PWM
W
PR
Freescale Semiconductor, Inc...
$0023
5
A
$0022
6
IN
$0021
7
IM
$0020
READ
WRITE
REGISTER
ADDR
PULSE WIDTH MODULATOR
14PWM
PULSE WIDTH MODULATOR
15PWM
12PWM4 12PWM3 12PWM2 12PWM1 12PWM0 12BRM2 12BRM1 12BRM0
R
W
R
13PWM4 13PWM3 13PWM2 13PWM1 13PWM0 13BRM2 13BRM1 13BRM0
14PWM4 14PWM3 14PWM2 14PWM1 14PWM0 14BRM2 14BRM1 14BRM0
W
R
15PWM4 15PWM3 15PWM2 15PWM1 15PWM0 15BRM2 15BRM1 15BRM0
W
UNIMPLEMENTED
RESERVED
Figure 2-4: MC68HC05BD7 I/O Register $20-$2F
SECTION 2: MEMORY
Page 14
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2.0
GENERAL
RELEASE SPECIFICATION
2.1
COP
The COP time-out is prevented by writing a ‘0’ to bit 0 of address $3FF0. See SECTION 11
for detail.
2.2
ROM
For MC68HC05BD7, the user ROM consists of 11.75K bytes of ROM from $1000 through
$3EFF and 16 bytes of user vectors from $3FF0 through $3FFF. For MC68HC05BD2, the
user ROM consists of 5.75K bytes of ROM from $2800 through $3EFF and 16 bytes of user
vectors from $3FF0 through $3FFF. The Self-Check ROM is located from $3F00 through
$3FE0 and Self-Check vectors are located from $3FE0 through $3FEF.
EPROM
RAM
IN
2.4
A
R
Y
For MC68HC705BD7, the user EPROM consists of 11.5K bytes of EPROM from $1000
through $3DFF and 16 bytes of user vectors from $3FF0 through $3FFF. The Bootstrap
ROM is located from $0E00 through $0FDF and Bootstrap vectors are located from $3FE0
through $3FEF, at the same location as Self-Check vectors.
Using the stack area for data storage or temporary work locations requires
care to prevent it from being overwritten due to stacking from an interrupt
or subroutine call.
EL
NOTE:
IM
The user RAM consists of 384 bytes from $0030 to $01AF for HC05BD7/HC705BD7. User
RAM consists of 256 bytes from $30 to $12F for HC05BD2. The stack pointer can access
64 bytes of RAM from $00FF to $00C0. See Section 3.1.3, Stack Pointer (SP).
PR
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2.3
SECTION 2: MEMORY
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IN
A
R
Y
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Freescale Semiconductor, MC68HC05BD7
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PR
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IM
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SECTION 2: MEMORY
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2.0
GENERAL
RELEASE SPECIFICATION
SECTION 3
CPU CORE
The MC68HC05BD7 has a 16K memory map. Therefore it uses only the lower 14 bits of
the address bus. In the following discussion the upper 2 bits of the address bus can be
ignored. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only
6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other
instructions and registers behave as described in this chapter.
Registers
13
12
11
0
0
0
0
0
10
9
0
0
8
IM
14
EL
15
6
IN
7
A
R
Y
The MCU contains five registers which are hard-wired within the CPU and are not part of
the memory map. These five registers are shown in Figure 3-1 and are described in the
following paragraphs.
0
1
5
4
3
2
1
0
ACCUMULATOR
A
INDEX REGISTER
X
1
STACK POINTER
SP
PROGRAM COUNTER
CONDITION CODE REGISTER
PR
Freescale Semiconductor, Inc...
3.1
1
1
PC
1
H
I
N
Z
C
CC
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 3-1: MC68HC05 Programming Model
3.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses
the accumulator to hold operands and results of arithmetic calculations or non-arithmetic
operations. The accumulator is not affected by a reset of the device.
SECTION 3: CPU CORE
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3.1.2
Index Register (X)
The index register shown in Figure 3-1 is an 8-bit register that can perform two functions:
•
Indexed addressing
•
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of the operand
address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset,
the CPU finds the operand address by adding the index register content to an 8-bit
immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand
address by adding the index register content to a 16-bit immediate value.
Y
3.1.3
Stack Pointer (SP)
IN
A
R
The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with memory
space less than 64K bytes the unimplemented upper address lines are ignored. The stack
pointer contains the address of the next free location on the stack. During a reset or the
reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is
then decremented as data is pushed onto the stack and incremented as data is pulled off
the stack.
3.1.4
EL
IM
When accessing memory, the ten most significant bits are permanently set to 0000000011.
The six least significant register bits are appended to these ten fixed bits to produce an
address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64
($40) locations. If 64 locations are exceeded, the stack pointer wraps around and
overwrites the previously stored information. A subroutine call occupies two locations on
the stack and an interrupt uses five locations.
Program Counter (PC)
The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices with memory
space less than 64K bytes the unimplemented upper address lines are ignored. The
program counter contains the address of the next instruction or operand to be fetched.
PR
Freescale Semiconductor, Inc...
The index register can also serve as an auxiliary accumulator for temporary storage. The
index register is not affected by a reset of the device.
Normally, the address in the program counter increments to the next sequential memory
location every time an instruction or operand is fetched. Jump, branch, and interrupt
operations load the program counter with an address other than that of the next sequential
location.
3.1.5
Condition Code Register (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the
results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be
individually tested by a program, and specific actions can be taken as a result of their
states. The condition code register should be thought of as having three additional upper
bits that are always ones. Only the interrupt mask is affected by a reset of the device. The
following paragraphs explain the functions of the lower five bits of the condition code
register.
SECTION 3: CPU CORE
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3.1.5.1
Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the
accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is
required for binary-coded decimal (BCD) arithmetic operations.
3.1.5.2
Interrupt Mask (I-Bit)
Negative Bit (N-Bit)
A
3.1.5.3
R
Y
A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the
interrupt mask to its state before the interrupt was encountered. After any reset, the
interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), or WAIT instructions.
IN
The negative bit is set when the result of the last arithmetic operation, logical operation, or
data manipulation was negative. (Bit 7 of the result was a logical one.)
3.1.5.4
IM
The negative bit can also be used to check an often tested flag by assigning the flag to bit
7 of a register or memory location. Loading the accumulator with the contents of that
register or location then sets or clears the negative bit according to the state of the flag.
Zero Bit (Z-Bit)
3.1.5.5
EL
The zero bit is set when the result of the last arithmetic operation, logical operation, data
manipulation, or data load operation was zero.
Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the
last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is
also set or cleared during bit test and branch instructions and during shifts and rotates. This
bit is neither set by an INC nor by a DEC instruction.
PR
Freescale Semiconductor, Inc...
When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts
are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt
mask is automatically set after the CPU registers are saved on the stack, but before the
interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the
interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt
mask is cleared.
SECTION 3: CPU CORE
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IN
A
R
Y
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SECTION 3: CPU CORE
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GENERAL
RELEASE SPECIFICATION
SECTION 4
4.1
INTERRUPTS
CPU Interrupt Processing
A
R
Y
If interrupts are not masked (I-bit in the CCR is cleared) and the corresponding interrupt
enable bit is set the processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs the processor completes the
current instruction, then stacks the current CPU register states, sets the I-bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If more than one
interrupt is pending following the stacking operation, the interrupt with the highest vector
location shown in Table 4-1 will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
IM
IN
When an interrupt is to be processed the CPU fetches the address of the appropriate
interrupt software service routine from the vector table at locations $3FF0 thru $3FFF as
defined in Table 4-1.
Table 4-1: Vector Address for Interrupts and Reset
N/A
N/A
N/A
SPCSR
DMCR
DSR
Flag
MFTCSR
N/A
N/A
Interrupts
EL
Register
N/A
N/A
N/A
VSIF
TXIF
RXIF
ALIF
NAKIF
SCLIF
TOF
RTIF
N/A
N/A
PR
Freescale Semiconductor, Inc...
Interrupts cause the processor to save register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not
cause the current instruction execution to be halted, but are considered pending until the
current instruction is complete.
CPU Int
Vector Adds.
Reset
Software
External Interrupt
VSINT
DDC12AB interrupt
RESET
SWI
IRQ
SP
DDC12AB
$3FFE-$3FFF
$3FFC-$3FFD
$3FFA-$3FFB
$3FF8-$3FF9
$3FF6-$3FF7
Timer Overflow
Real Time Interrupt
N/A
N/A
MFT
$3FF4-$3FF5
N/A
N/A
$3FF2-$3FF3
$3FF0-$3FF1
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from the stack
and normal processing to resume at the next instruction that was to be executed when the
interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt
processing.
SECTION 4: INTERRUPTS
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From
RESET
Y
Is
I-Bit
Set?
N
IRQ
External
Interrupt?
Y
Clear IRQ
Latch
N
Y
Y
Freescale Semiconductor, Inc...
V Sync
Interrupt?
Y
A
DDC12AB
Interrupt?
R
N
MFT
Interrupt?
IN
N
Y
EL
IM
N
PR
Fetch Next
Instruction
SWI
Instruction?
PC -> (SP,SP-1)
X -> (SP-2)
A -> (SP-3)
CC -> (SP-4)
Set I-Bit in CCR
Y
Load Interrupt
Vectors to PC
N
RTI
Instruction?
Y
Restore Registers
from Stack
CC, A, X, PC
N
Execute
Instruction
Figure 4-1: Interrupt Processing Flowchart
SECTION 4: INTERRUPTS
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GENERAL
RELEASE SPECIFICATION
4.2
Reset Interrupt Sequence
The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a
similar manner. A low level input on the RESET pin or an internally generated reset signal
causes the program to vector to its starting address which is specified by the contents of
$3FFE and $3FFF. The I-bit in the condition code register is also set. The MCU is
configured to a known state during this type of reset as described in SECTION 5.
Software Interrupt (SWI)
Hardware Interrupts
R
4.4
Y
The SWI is an executable instruction and a non-maskable interrupt since it is executed
regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), the
SWI instruction executes after interrupts which were pending before the SWI was fetched,
or before interrupts generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of $3FFC and $3FFD.
4.4.1
External Interrupt (IRQ)
IN
A
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is
set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables
the hardware interrupts. There are four types of hardware interrupts which are explained in
the following sections.
EL
IM
If the IRQ option is edge and level sensitive triggering (IRQN=0), a low level at the IRQ pin
and a cleared interrupt mask bit of the condition code register will cause an EXTERNAL
INTERRUPT to occur. If the MCU has finished with the interrupt service routine, but the IRQ
pin is still low, the EXTERNAL INTERRUPT will start again. In fact, the MCU will keep on
servicing the EXTERNAL INTERRUPT as long as the IRQ pin is low. If the IRQ pin goes
low for a while and resumes to high (a negative pulse) before the interrupt mask bit is
cleared, the MCU will not recognize there was an interrupt request, and no interrupt will
occur after the interrupt mask bit is cleared.
PR
Freescale Semiconductor, Inc...
4.3
If the IRQ option is negative edge sensitive triggering (IRQN=1), a negative edge occurs at
the IRQ pin and a cleared interrupt mask bit of the condition code register will cause an
EXTERNAL INTERRUPT to occur. If the MCU has finished with the interrupt service
routine, but the IRQ pin has not returned back to high, no further interrupt will be generated.
The interrupt logic recognizes negative edge transitions and pulses (special case of
negative edges) only. If the negative edge occurs while the interrupt mask bit is set, the
interrupt signal will be latched, and interrupt will occur as soon as the interrupt mask bit is
cleared. The latch will be cleared by RESET or cleared automatically during fetch of the
EXTERNAL INTERRUPT vectors. Therefore, one (and only one) external interrupt edge
could be latched while the interrupt mask bit is set. If the INHIRQ bit in the MFT register is
set, no IRQ interrupt can be generated.
The service routine address is specified by the contents of $3FFA and $3FFB. Figure 4-2
shows the two methods for the interrupt line (IRQ) to be recognized by the processor. The
first method is single pulses on the interrupt line spaced far apart enough to be serviced.
The minimum time between pulses is a function of the number of cycles required to execute
SECTION 4: INTERRUPTS
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GENERAL RELEASE SPECIFICATION
Rev. 2.0
the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not
occur until the MCU software has exited the routine (an RTI occurs). The second
configuration shows several interrupt line “wire-ANDed” to perform the interrupts at the
processor. Thus, if after servicing one interrupt and the interrupt line remains low, then the
next interrupt is recognized.
NOTE:
IRQN is located at bit 3 of the Multi-function Timer Register at $0008, and
is cleared by reset.
Edge-sensitive Trigger Condition
t ILIH
Y
The minimum pulse width tILIH is one
internal bus period.
The period tILIL should not be less than the
number of cycles it takes to execute the
interrupt service routine plus 21 cycles
IRQ1
R
t ILIL
t ILIH
Level-sensitive Trigger Condition
IN
A
If after servicing an interrupt, the IRQ
remains low, then the next interrupt is
recognized.
IM
IRQn
Normally used with pull-up resistor for
Wire-Ored connection
EL
IRQ
(MCU)
Figure 4-2: External Interrupt
4.4.2
VSYNC Interrupt
PR
Freescale Semiconductor, Inc...
IRQ
The VSYNC interrupt is generated when a specific edge of VSYNC input is detected as
described in SECTION 10. The interrupt enable bit, VSIE, for the VSYNC interrupt is
located at bit 7 of SYNC Processor Control and Status Register (SPCSR) at $000C. The Ibit in the CCR must be cleared in order for the VSYNC interrupt to be enabled. This
interrupt will vector to the interrupt service routine located at the address specified by the
contents of $3FF8 and $3FF9. The VSYNC Interrupt Flag (VSIF) must be cleared by writing
’0’ to it in the interrupt routine.
4.4.3
DDC12AB Interrupt
The DDC12AB interrupt is generated by the DDC12AB circuit as described in SECTION 9.
The interrupt enable bit for the DDC12AB interrupt is located at bit 6 of DDC12AB Control
Register (DCR) at $0018. The I-bit in the CCR must be cleared in order for the DDC12AB
interrupt to be enabled. This interrupt will vector to the interrupt service routine located at
the address specified by the contents of $3FF6 and $3FF7.
SECTION 4: INTERRUPTS
Page 24
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4.4.4
Multi-Function Timer Interrupt (MFT)
Y
R
A
IN
IM
EL
PR
Freescale Semiconductor, Inc...
There are two different Multi-Function Timer (MFT) interrupt flags that will cause an
interrupt whenever they are set and enabled. The interrupt flags and enable bits are located
in the MFT Control and Status Register. Either of these interrupts will vector to the same
interrupt service routine, located at the address specified by the contents of $3FF4 and
$3FF5. See Section SECTION 11, MULTI-FUNCTION TIMER for more informations on
MFT interrupts.
SECTION 4: INTERRUPTS
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IN
A
R
Y
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
PR
EL
IM
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SECTION 4: INTERRUPTS
Page 26
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2.0
GENERAL
RELEASE SPECIFICATION
SECTION 5
RESETS
The MCU can be reset from four sources—1 external and 3 internal:
•
External RESET pin
•
Power-On-Reset (POR)
•
Computer Operating Properly Watchdog Reset (COPR)
•
Illegal Address Reset (ILADR)
Y
External Reset (RESET)
5.2
IM
Activation of the RST signal is generally referred to as reset of the device,
unless otherwise specified.
EL
NOTE:
IN
A
R
The RESET pin is the only external reset source. This pin is connected to a Schmitt trigger
input gate to provide an upper and lower threshold voltage separated by a minimum
amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below
the lower threshold and remains in reset until the RESET pin rises above the upper
threshold. This active low input will generate the RST signal and reset the CPU and
peripherals. Termination of the external RESET input can alter the operating mode of the
MCU.
Internal Resets
The three internally generated resets are the initial power-on reset, the COP Watchdog
Timer reset, and the illegal address reset
5.2.1
PR
Freescale Semiconductor, Inc...
5.1
Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The
POR is strictly for power-on condition and is not able to detect a drop in the power supply
voltage (brown-out). There is an oscillator stabilization delay of 4065 internal processor bus
clock cycles (PH2) after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset function
is active at the end of this 4065 cycles delay, the RST signal will remain in the reset
condition until the other reset condition(s) end.
5.2.2
Computer Operating Properly Reset (COPR)
The internal COPR reset is generated automatically (if enabled) by a time-out of the COP
Watchdog Timer. This time-out occurs if the counter in the COP Watchdog Timer is not
reset (cleared) within a specific time by a program reset sequence. Refer to SECTION 11
for more information on this time-out feature.
SECTION 5: RESETS
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5.2.3
Illegal Address (ILADR) Reset
PR
EL
IM
IN
A
R
Y
Freescale Semiconductor, Inc...
The MCU monitors all opcode fetches. If an illegal address is accessed during an opcode
fetch, an internal reset is generated. Illegal address space consists of all unused locations
within the memory space and the I/O registers. (See Figure 2-1 : The 16K Memory Map
of the MC68HC05BD7.) Because the internal reset signal is used, the MCU comes out of
an ILADR Reset in the same operating mode it was in when the opcode was fetched. The
ILADR Reset is disabled in Test (Non User) Mode.
SECTION 5: RESETS
Page 28
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2.0
GENERAL
RELEASE SPECIFICATION
SECTION 6
OPERATING MODES
The HC05BD7/HC05BD2 has the following operating modes: single-chip mode (SCM) and
self-check mode.
The HC705BD7 has the following operating modes: User mode and bootstrap mode.
6.1
User Mode
Y
6.2
SELF-CHECK MODE
Bootstrap Mode
IN
6.3
A
R
In this mode, the reset vector is fetched from the 240-byte internal self-check ROM at
$3F00:$3FEF. The self-check ROM contains a self-check program to test the functions of
internal modules.
Mode Entry
EL
6.4
IM
In this mode, the reset vector is fetched from the 480-byte internal bootstrap ROM at
$0E00:$0FDF. The bootstrap ROM contains a small program which reads a program into
internal RAM and then passes control to execute EPROM programming.
The mode entry is done at the rising edge of the RESET pin. Once the device enters one
of the operating modes, the mode can only be changed by an external reset.
At the rising edge of the RESET pin, the device latches the states of IRQ and PB5 pins and
places itself in the specified mode. While the RESET pin is low, all pins are configured as
Single Chip Mode. The following table shows the states of IRQ and PB5 pins for each mode
entry.
PR
Freescale Semiconductor, Inc...
In this mode, all address and data bus activity occurs within the MCU so no external pins
are required for these functions.
SECTION 6: OPERATING MODES
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Rev. 2.0
Table 6-1: Mode Select Summary
MODE
RESET
USER MODE
SELF CHECK/BOOTSTRAP
IRQ
PB5
L or H
VTST
X
H
VTST = 1.8 x VDD
Single
Chip Mode
H
L
Y
VTST
R
IRQ
VTST = 1.8 x VDD
H = VDD
L = VSS
A
PB5
H
L
H
L
EPROM Programming
IM
6.5
IN
Figure 6-1: Mode Entry Diagram
EL
The 11.5K bytes of USER EPROM is positioned at $1000 through $3DFF with the vector
space from $3FF0 to $3FFF. The erased state of EPROM is read as $FF and EPROM
power is supplied from VPP and VDD pins.
The Programming Control Register (PCR) is provided for the EPROM programming. The
function of EPROM depends on the device operating mode.
In the User Mode, ELAT and PGM bits in the PCR are available for the user read/write and
the remaining test bits become read only bits.
PR
Freescale Semiconductor, Inc...
RESET
Please contact Motorola for Programming boards availability.
6.5.1
Programming Sequence
The EPROM programming is as follows:
- Set the ELAT bit
- Write the data to the address to be programmed
- Set the PGM bit
- Delay for the appropriate amount of time
- Clear the PGM and the ELAT bit
The last item may be done on a single CPU write. It is important to remember that an
external programming voltage must be applied to the VPP pin while programming, but it
should remain between VDD and VSS during normal operation.
SECTION 6: OPERATING MODES
Page 30
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6.5.2
Programming Control Register (PCR)
Program control register is provided for EPROM programming the device.
7
6
5
4
3
2
1
0
ELAT
PGM
0
0
R
PCR
$001D
W
0
0
0
0
0
0
A
R
Y
ELAT—EPROM Latch Control
0 - EPROM address and data bus configured for normal read.
1 - EPROM address and data bus configured for programming (writes to
EPROM cause address and data to be latched). EPROM is in programming
mode and can not be read. This bit is not writable to 1 when no VPP voltage
is applied to the VPP pin.
Low Power Modes
IM
6.6
IN
PGM—EPROM Program Command
0 - Programming power to EPROM array is switched off.
1 - Programming power to EPROM array is switched on.
EL
The MC68HC05BD7 has ONLY ONE low-power operational mode. The WAIT instruction
provides the only mode that reduces the power required for the MCU by stopping CPU
internal clock. The WAIT instruction is not normally used if the COP Watchdog Timer is
enabled. The STOP instruction is not implemented in its normal sense. The STOP
instruction will be interpreted as the NOP instruction by the CPU if it is ever encountered.
The flow of the WAIT mode is shown in Figure 6-2.
6.6.1
PR
Freescale Semiconductor, Inc...
reset ⇒
STOP Instruction
Since the execution of a normal STOP instruction results in the stoppage of clocks to all
modules, including the COP Watchdog Timer, this instruction is hence not implemented in
its usual way to make COP Watchdog Timer meaningful in monitor applications. Execution
of the STOP instruction will be the same as that of the NOP instruction. Hence, I bit in the
Condition Code Register will not be cleared.
6.6.2
WAIT Instruction
In the WAIT Mode the internal processor clock is halted, suspending all processor and
internal bus activity. Other Internal clocks remain active, permitting interrupts to be
generated from the Multi-Function Timer, or a reset to be generated from the COP
Watchdog Timer. The Timer may be used to generate a periodic exit from the WAIT Mode.
Execution of the WAIT instruction automatically clears the I-bit in the Condition Code
Register, so that any hardware interrupt can wake up the MCU. All other registers, memory,
and input/output lines remain in their previous states.
SECTION 6: OPERATING MODES
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6.7
COP Watchdog Timer Considerations
The COP Watchdog Timer is always enable in MC68HC05BD7. It will reset the MCU when
it times out. For a system that must have intentional uses of the WAIT Mode, care must be
taken to prevent such situations from happening during normal operations by arranging
timely interrupts to reset the COP Watchdog timer.
WAIT
Y
Freescale Semiconductor, Inc...
External Oscillator Active,
and Internal
Timer Clock Active
External
RESET?
IN
Y
A
R
Stop Internal Processor Clock,
Clear I-Bit in CCR
N
PR
EL
IM
Y
Y
Internal
COP
RESET?
N
External
H/W
Interrupt?
N
Y
Internal
Interrupt?
N
Restart
Internal Processor Clock
1.Fetch Reset Vector
or
2.Service Interrupt
a.Stack
b.Set I-Bit
c.Vector to Interrupt Routine
Figure 6-2: WAIT Flowcharts
SECTION 6: OPERATING MODES
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2.0
GENERAL
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SECTION 7
INPUT/OUTPUT PORTS
In the User Mode there are 26 bidirectional I/O lines arranged as 4 I/O ports (Port A, B, C,
and D). The individual bits in these ports are programmable as either inputs or outputs
under software control by the data direction registers (DDRs). Also, if enabled by software,
Port C and D will have additional functions as PWM outputs, DDC I/O and Sync Signal
Processor outputs.
Port A
7.2
A
R
Y
Port A is an 8-bit bidirectional port which does not share any of its pins with other
subsystems. The Port A data register is at $00 and the data direction register (DDR) is at
$04. Reset does not affect the data register, yet clears the data direction register, thereby
returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to
output mode.
Port B
Port C
EL
7.3
IM
IN
Port B is a 6-bit bidirectional port which does not share any of its pins with other
subsystems. PB2 to PB5 are +12V open-drain port pins. The Port B data register is at $01
and the data direction register (DDR) is at $05. Reset does not affect the data register, yet
clears the data direction register, thereby returning the ports to inputs. Writing a one to a
DDR bit sets the corresponding port bit to output mode.
Port C is an 8-bit bidirectional port which shares pins with PWM, Sync Processor, and ADC
subsystem. See SECTION 8 for a detailed description of PWM, SECTION 10 for a detailed
description of SYNC Processor, and SECTION 12 for a detailed description of ADC. These
pins are configured as PWM outputs when the corresponding bits in the CONFIGURATION
REGISTER 1 are set. PC6 and PC7 are configured to VSYNO and HSYNO outputs when
the corresponding bits in the CONFIGURATION REGISTER 2 are set. And PC2 to PC5 are
configured as ADC input channels as the corresponding bit in the CONFIGURATION
REGISTER 2 are set. If there is any confliction between the two configuration registers, the
CONFIGURATION REGISTER 2 has higher priority. The Port C data register is at $02 and
the data direction register (DDR) is at $06. Reset does not affect the data register, but
clears the data direction register, thereby returning the ports to inputs. Writing a one to a
DDR bit sets the corresponding port to output mode.
PR
Freescale Semiconductor, Inc...
7.1
7.4
Port D
Port D is a 4-bit bidirectional port. PD0 and PD1 shares their pins with DDC12AB
subsystem. See SECTION 9 for a detailed description of DDC12AB. These two pins are
configured to the corresponding functions when the corresponding bits in the
CONFIGURATION REGISTER 2 are set. They have open-drain output and hysteresis
input level to improve noise immunity. PD2 is a +5V open-drain general I/O pin which
SECTION 7: INPUT/OUTPUT PORTS
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GENERAL RELEASE SPECIFICATION
Rev. 2.0
shares its pin with the CLAMP output. See SECTION 10 for the description of CLAMP
signal. It becomes the CLAMP output when the CLAMP bit in SPIOCR register is set. PD3
is a +12V open-drain I/O pin which shares its pin with the SOG input. Also see SECTION
10 for the description of SOG input. It is configured as SOG input when the SOG bit in
SPIOCR register is set. The Port D data register is at $03 and the data direction register
(DDR) is at $07. Reset does not affect the data register, yet clears the data direction
register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode.
Input/Output Programming
R
Y
Bidirectional port lines may be programmed as an input or an output under software control.
The direction of the pins is determined by the state of the corresponding bit in the port data
direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured
as an output if its corresponding DDR bit is set. A pin is configured as an input if its
corresponding DDR bit is cleared.
IM
IN
A
During Reset, all DDRs are cleared, which configure all port pins as inputs. The data
direction registers are capable of being written to or read by the processor. During the
programmed output state, a read of the data register actually reads the value of the output
data latch and not the I/O pin. See Figure 7-1 and .
Read/Write DDR
Read Data
Internal HC05
Data Bus
EL
Write Data
Data Direction
Register Bit
Data
Register Bit
OUTPUT
I/O
PIN
PR
Freescale Semiconductor, Inc...
7.5
Reset
(RST)
Figure 7-1: Port I/O Circuitry
SECTION 7: INPUT/OUTPUT PORTS
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Table 7-1: I/O Pin Functions
DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in output mode. The output data latch is read.
Port C and D Configuration Register
R
7.6
Y
A “glitch” can be generated on an I/O pin when changing it from an input
to an output unless the data register is first pre-conditioned to the desired
state before changing the corresponding DDR bit from a zero to a one.
7
6
5
4
3
2
1
0
PWM15
PWM14
PWM13
PWM12
PWM11
PWM10
PWM9
PWM8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
HSYNO
VSYNO
ADC3
ADC2
ADC1
ADC0
SCL
SDA
0
0
0
0
0
0
0
0
W
reset ⇒
EL
R
CR1
$000A
IM
IN
A
Port C and Port D are shared with PWM, ADC, DDC12AB, and SYNC Processor. The
configuration registers at $0A and $0B are used to configure those I/O pins. They are
default to zero after poWer-on reset. Setting these bits will set the corresponding pins to
the corresponding functions. For example, setting SCL and SDA bits of register $0B will
configure Port D pins 1 and 0 as DDC12AB pins, regardless of DDR1 and DDR0 settings.
PR
Freescale Semiconductor, Inc...
NOTE:
R/W
R
CR2
$000B
W
reset ⇒
When any PWM8-PWM15 bits of CR1 register are set, the corresponding pins of port C
become the PWM output if the corresponding bits in CR2 register are clear. When the pin
is defined as PWM channel, it become an output only pin. When any ADC3-ADC0 bits of
the CR2 register are set, the corresponding pins of port C become the ADC input channels.
When HSYNO or VSYNO is set, the PC2 or PC3 becomes the output of HSYNC or VSYNC
accordingly, see SECTION 10 for the detail description of HSYNO and VSYNO outputs.
When SCL and SDA bits of the CR2 register are set, the DDC12AB use these two pins as
clock and data pins. In summary, the configuration in the CR2 register has higher priority
than in the CR1 register.
SECTION 7: INPUT/OUTPUT PORTS
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IN
A
R
Y
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
PR
EL
IM
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SECTION 7: INPUT/OUTPUT PORTS
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GENERAL
RELEASE SPECIFICATION
SECTION 8
PULSE WIDTH MODULATION
There are 16 PWM channels. Channel 0 to channel 7 are dedicated PWM channels with
5V open-drain option. Channel 8 to channel 15 are shared with ports C under the control
of the corresponding configuration register. The channel 8 and channel 9 are 12V opendrain outputs.
Operation of 8-Bit PWM
A
R
Y
Each 8-Bit PWM channel is composed of an 8-bit register which contains a 5-bit PWM in
MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. There are 16 data
registers as shown in Figure 8-1 located from $20 to $2F. The value programmed in the 5bit PWM portion will determine the pulse length of the output. The clock to the 5-bit PWM
portion is the MCU clock and the repetition rate of the output is hence 62.5 KHz at 2 MHz
MCU clock.
IN
The 3-bit BRM will generate a number of narrow pulses which are equally distributed
among an 8-PWM-cycle frame. The number of pulses generated is equal to the number
programmed in the 3-bit BRM portion. An example of the waveform is shown in Figure 8-2.
7
EL
IM
Combining the 5-bit PWM together with the 3-bit BRM, the average duty cycle at the output
will be (M+N/8)/32, where M is the content of the 5-bit PWM portion, and N is the content
of the 3-bit BRM portion. Using this mechanism, a true 8-bit resolution PWM type DAC with
reasonably high repetition rate can be obtained.
6
5
4
3
2
1
0
0PWM4
0PWM3
0PWM2
0PWM1
0PWM0
0BRM2
0BRM1
0BRM0
0
0
0
0
0
0
0
0
PR
Freescale Semiconductor, Inc...
8.1
R
PWMR
$20-$2F
W
reset ⇒
Figure 8-1: PWM Data Register
The value of each PWM Data Register is continuously compared with the content of an
internal counter to determine the state of each PWM channel output pin. Double buffering
is not used in this PWM design.
SECTION 8: PULSE WIDTH MODULATION
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Rev. 2.0
32 T
M = $00
M = $01
M = $0F
M = $1F
Y
R
T = 1 MCU Clock Period (0.5 µs if MCU clock = 2 MHz)
A
PWM cycles in which narrow pulses are
inserted in an 8-cycle frame
N
4
X1X
2, 6
1XX
1, 3, 5, 7
IM
IN
XX1
EL
Figure 8-2: Relationship Between 5-Bit PWM and 3-Bit BRM
8.2
Open-Drain Option Register
This PWM Open-Drain option Register contains 8 bits which are programmed to change
the output drive of individual PWM channel from channel 0 to channel 7 to be open-drain
type. This register is located at $0012
R
PWMOR
$12
PR
Freescale Semiconductor, Inc...
Narrow pulse possibly inserted
by the BRM
7
6
5
4
3
2
1
0
7PWMO
6PWMO
5PWMO
4PWMO
3PWMO
2PWMO
1PWMO
0PWMO
0
0
0
0
0
0
0
0
W
reset ⇒
Figure 8-3: PWM Open-Drain Option Register
When any bit in this register is one, the corresponding PWM channel output becomes +5V
open-drain type. When the bit is zero, the corresponding PWM channel has push-pull
output. All eight bits are clear upon reset.
SECTION 8: PULSE WIDTH MODULATION
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GENERAL
RELEASE SPECIFICATION
SECTION 9
Introduction
R
Y
This DDC12AB Interface Module is mainly used for monitor to show its identification
information to video controller. It contains DDC1 hardware and a two-wire, bidirectional
serial bus which is fully compatible with multi-master IIC bus protocol to support DDC2AB
interface. In DDC1 type of communication, the module is in transmit mode. For DDC2AB
protocol, the module can be either in transmit mode or in receive mode upon host’s
commands. When DDC1 hardware is enabled, the loaded data is serially clocked out to
SDA line by the rising edge of VSYNC input signal continuously. If DDC2 protocol is
selected, the module will act as a standard IIC module, and will response only when it is
addressed or in master mode. During DDC1 communication, the falling transition in the
SCL line can be detected to interrupt cpu for mode switching.
IN
A
This module not only can be applied in DDC12AB communication, but also can be used as
one typical command reception serial bus for factory setup and alignment purpose. It also
provides the flexibility of hooking additional devices to an existing system in future
expansion without adding extra hardware.
9.2
EL
IM
This DDC12AB module uses the SCL clock line and the SDA data line to communicate with
external DDC host or IIC interface. These two pins are shared with PD0 and PD1 port pins.
The outputs of SDA and SCL pins are all open-drain type. It means no clamping diode
connected between the pin and internal VDD. The maximum data rate typically is 100K bps.
The maximum communication length and the number of devices that can be connected are
limited by a maximum bus capacitance of 400 pF.
DDC12AB Features
•
•
•
•
DDC1 hardware
PR
Freescale Semiconductor, Inc...
9.1
DDC12AB INTERFACE
Fully compatible with multi-master IIC Bus standard
Software controllable acknowledge bit generation
Interrupt driven byte by byte data transfer
•
Calling address identification interrupt
•
Auto detection of RW bit and switching of transmit or receive mode
accordingly
•
Detection of START, repeated START, and STOP signals
•
Auto generation of START and STOP condition in master mode
•
Arbitration loss detection and No-ACK awareness in master mode
•
Master clock generator with 8 selectable baud rates
•
Automatic recognition of the received acknowledge bit
SECTION 9: DDC12AB INTERFACE
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Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
9.3
Registers
There are six different registers used in the DDC12AB module and the internal
configuration of these registers is discussed in the following paragraphs.
9.3.1
DDC Address Register (DADR)
7
6
5
4
3
2
1
0
DAD7
DAD6
DAD5
DAD4
DAD3
DAD2
DAD1
EXTAD
1
0
1
0
0
0
0
0
R
DADR
$0017
W
reset
A
Bit 0
9.3.2
EL
IM
IN
EXTAD
R
Y
These 7 bits can be the DDC2 interface’s own specific slave
address in slave mode or the calling address when in master
mode. So the program must update it as the calling address
while entering the master mode and restore its own slave
address after the master mode is quitted. This register is
cleared as $A0 upon reset.
The EXTAD bit is set to expand the calling address of this
module. When it is one, the module will acknowledge the
general call address $00 and the address comparison circuit
will only compare the 4 MSB bits in the DADR register. For
example, the DADR contains $A1, that means EXTAD is
enabled and the calling address is $A0, therefore, the module
can acknowledge the calling address of $00 and $A0 to $AF.
When it is clear, the module will only acknowledge to the
specific address which is stored in the DADR register. It is
clear upon reset.
DDC Control Register (DCR)
7
R
DCR
$0018
W
reset ⇒
6
PR
Freescale Semiconductor, Inc...
DAD7-DAD1 Bit 7-Bit 1
DEN
DIEN
0
0
5
X
4
X
3
2
1
TXAK
SCLIEN
DDC1EN
0
0
0
0
X
The DCR provides five control bits. DCR is cleared upon reset.
DEN
Bit 7
If the DDC module ENable bit (DEN) is set, the DDC module
is enabled. If the DEN is clear, the interface is disabled and all
flags will restore its power-on default states. Reset clears this
bit.
DIEN
Bit 6
If the DDC Interrupt ENable bit (DIEN) is set, the interrupt
occurs provided the TXIF or RXIF in the status register is set
or the ALIF or NAKIF in the DMCR register is set and the I-bit
in the Condition Code Register is cleared. If DIEN is cleared,
the interrupt of TXIF, RXIF, ALIF, and NAKIF are all disabled.
Reset clears this bit.
SECTION 9: DDC12AB INTERFACE
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Bit 3
SCLIEN
Bit 2
DDC1EN
Bit 1
If the transmit acknowledge enable bit (TXAK) is cleared, an
acknowledge signal will be sent out to the bus at the 9th clock
bit after receiving 8 data bits. When TXAK is set, no
acknowledge signal will be generated at the 9th clock (i.e.,
acknowledge bit = 1). Reset clears this bit.
If the SCL Interrupt ENable bit (SCLIEN) is set, the interrupt
occurs provided the SCLIF in the status register is set and the
I-bit in the Condition Code Register is cleared. If SCLIEN is
cleared, the interrupt of SCLIF is disabled. Reset clears this
bit.
When DDC1 protocol ENable (DDC1EN) is set, the VSYNC
input will be selected as clock input of DDC module. Its rising
edge will continuously clock out the data in the shift register.
No calling address comparison is performed. The RW bit in
the status register will be fixed to be one. If this bit is clear, the
SCLIF bit in the status register is also cleared. Reset clears
this bit.
7
6
5
ALIF
NAKIF
BB
0
0
R
W
reset ⇒
IM
DMCR
$0016
4
0
A
DDC Master Control Register (DMCR)
3
2
1
0
MAST
MRW
BR2
BR1
BR0
0
0
0
0
0
IN
9.3.3
R
Y
TXAK
EL
The DMCR contains two interrupt flags, one bus status flag, two master mode control bits,
and three baudrate select bits.
ALIF
Bit 7
The Arbitration Loss Interrupt Flag is set when software
attempt to set MAST but the BB has been set by detecting the
start condition on the lines or when the DDC12AB module is
transmitting a ’one’ to SDA line but detected a ’zero’ from SDA
line in master mode, which is so called arbitration loss. This
bit can generate an interrupt request to cpu when the DIEN bit
in DCR register is set and I-bit in the Condition Code Register
is clear. This bit is cleared by writing ’0’ to it or by reset.
NAKIF
Bit 6
The No AcKnowledge Interrupt Flag is only set in master
mode when there is no acknowledge bit detected after one
data byte or calling address is transferred. This bit can
generate an interrupt request to cpu when the DIEN bit in
DCR register is set and I-bit in the Condition Code Register is
clear. This bit is cleared by writing ’0’ to it or by reset.
BB
Bit 5
The Bus Busy Flag is set after a start condition is detected,
and is reset when a stop condition is detected. This bit can
supplement the software in initiating the master mode
protocol. Reset clears this bit.
PR
Freescale Semiconductor, Inc...
Semiconductor,
Inc.
MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
SECTION 9: DDC12AB INTERFACE
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Bit 4
MRW
Bit 3
BR2-BR0
Bit 2-Bit 0
If the software set the MASTer control bit, the module will
generate a start condition to the SDA and SCL lines and send
out the calling address which is stored in the DADR register.
But if the ALIF flag is set when arbitration loss occurs on the
lines, the module will discard the master mode by clearing the
MAST bit and release both SDA and SCL lines immediately.
This bit can also be cleared by writing zero to it or when the
NAKIF is set. When the MAST bit is cleared either by NAKIF
set or by software, not by ALIF set, the module will generate
the stop condition to the lines after the current byte
transmission is done. Reset clears this bit.
This MRW bit will be transmitted out as the bit 0 of the calling
address when the module sets the MAST bit to enter the
master mode. It will also determine the transfer direction of
the following data bytes. When it is one, the module is in
master receive mode. When it is zero, the module is in master
transmit mode. Reset clears this bit.
The three Baud Rate select bits will select one of eight clock
rates as the master clock when the module is in master mode.
The serial clock frequency is equal to the CPU clock divided
by the divider shown in following table. For the CPU clock will
be halted while program executes the WAIT instruction,
program must not enter WAIT mode when the DDC12AB
module is in Master mode in order not to hang up the
communication on the lines. These bits are cleared upon
reset.
EL
IM
IN
A
R
Y
MAST
BR2:BR1:BR0
PR
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
DIVIDER
0:0:0
20
0:0:1
40
0:1:0
80
0:1:1
160
1:0:0
320
1:0:1
640
1:1:0
1280
1:1:1
2560
Table 9-1: Pre-scaler of Master Clock Baudrate
SECTION 9: DDC12AB INTERFACE
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2.0
GENERAL
RELEASE SPECIFICATION
9.3.4
DDC Status Register (DSR)
This status register is readable only. All bits are cleared upon reset except bit 3 (RXAK) and
bit 1 (TXBE).
R
DSR
$0019
6
5
4
3
2
1
0
RXIF
TXIF
MATCH
SRW
RXAK
SCLIF
TXBE
RXBF
0
0
0
0
1
0
1
0
W
reset ⇒
Bit 7
TXIF
Bit 6
MATCH
Bit 5
SRW
Bit 4
The data Receive Interrupt Flag (RXIF) is set after the DDRR
is loaded with a newly received data. Once the DDRR is
loaded with received data, no more received data can be
loaded to the DDRR register. The only way to release the
DDRR register for loading next received data is that software
reads the data from the DDRR register to clear RXBF flag.
This bit is cleared by writing ’0’ to it or when the DEN is
disabled.
The data Transmit Interrupt Flag is set before the data of the
DDTR register is downloaded to the shift register. It is
software’s responsibility to fill the DDTR register with new
data when this bit is set. This bit is cleared by writing ’0’ to it
or when the DEN is disabled.
The MATCH flag is set when the received data in the DDRR
register is an calling address which matches with the address
or its extended addresses (EXTAD=1) specified in the DADR
register.
The Slave RW bit will indicate the data direction of DDC
protocol. It is updated after the calling address is received in
the DDC2 protocol. When it is one, the master will read the
data from DDC module, so the module is in transmit mode.
When it is zero, the master will send data to the DDC module,
the module is in receive mode. When DDC1EN is set, the
SRW bit will be one. The reset state of it is zero.
If the received acknowledge bit (RXAK) is low, it indicates an
acknowledge signal has been received after the completion of
8 data bits transmission on the bus. If RXAK is high, it
indicates no acknowledge signal has been detected at the 9th
clock. Then the module will release the SDA line for the
master to generate ’stop’ or ’repeated start’ condition. It is set
upon reset.
This SCLIF flag is set by the falling edge of SCL line only
when DDC1EN is enabled. This bit is cleared by writing zero
to it, clearing DDC1EN bit or when the DEN is disable.
EL
IM
IN
A
R
Y
RXIF
PR
Freescale Semiconductor, Inc...
7
RXAK
Bit 3
SCLIF
Bit 2
SECTION 9: DDC12AB INTERFACE
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TXBE
Bit 1
RXBF
Bit 0
7
6
5
4
3
DTD7
DTD6
DTD5
DTD4
DTD3
1
1
1
1
reset ⇒
1
IN
W
2
A
R
DDTR
$001A
Y
DDC Data Transmit Register (DDTR)
1
0
DTD2
DTD1
DTD0
1
1
1
R
9.3.5
The Transmit Buffer Empty (TXBE) flag indicates the status of
the DDTR register. When the cpu writes the data into the
DDTR register, the TXBE flag will be cleared. And it will be set
again after the data of the DDTR register has been loaded to
the shift register. It is default to be set when the DEN is
disable and will be cleared by writing data to the DDTR
register when the DEN is enabled.
The Receive Buffer Full (RXBF) flag indicates the status of the
DDRR register. When the cpu reads the data from the DDRR
register, the RXBF flag will be cleared. And it will be set after
the data or matched address is transferred from the shift
register to the DDRR register. It is cleared when DEN is
disabled or DDRR register is read when DEN is enabled.
EL
IM
The data written into this register after DEN is enabled will be automatically downloaded to
the shift register when the module detects the calling address is matched and the bit 0 of
the received data is one or when the data in the shift register has been transmitted with
received acknowledge bit, RXAK=0. So if the program doesn’t write the data into the DDTR
register (TXBE is cleared) before the matched calling address is detected, the module will
pull down the SCL line. If the cpu write a data to the DDTR register, then the written data
will be downloaded to the shift register immediately and the module will release the SCL
line, then the TXBE is set again and the TXIF flag is set to generate another interrupt
request for data. So the cpu may need to write the next data to the DDTR register to clear
TXBE flag and for the auto downloading of data to the shift register after the data in the shift
register is transmitted over again with RXAK=0. If the master receiver doesn’t acknowledge
the transmitted data, RXAK=1, the module will release the SDA line for master to generate
’stop’ or ’repeated start’ conditions. The data stored in the DDTR register will not be
downloaded to the shift register until next calling from master (TXBE remains unchanged).
PR
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
9.3.6
DDC Data Receive Register (DDRR)
R
DDRR
$001B
7
6
5
4
3
2
1
0
DRD7
DRD6
DRD5
DRD4
DRD3
DRD2
DRD1
DRD0
0
0
0
0
0
0
0
0
W
reset ⇒
The DDC Data Receive Register (DDRR) contains the last received data when the MATCH
flag is zero or the calling address from master when the MATCH flag is one. The DDRR
register will be updated after a data byte is received and the RXBF is zero. It is a read-only
register. The read operation of this register will clear the RXBF flag. After the RXBF flag is
SECTION 9: DDC12AB INTERFACE
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2.0
GENERAL
RELEASE SPECIFICATION
cleared, the register can load the received data again and set the RXIF flag to generate
interrupt request for reading the newly received data.
9.4
Data Sequence
a) Master Transmit mode
START Address 0
ACK
TXIF=1
TXBE=1
TX DataN
ACK
TXIF=1
TXBE=1
RX Data1
c) Slave Transmit mode
START Address 1
TX Data1
IM
ACK
RXIF=1
RXBF=1
TXiF=1
TXBE=1
MATCH=1
SRW=1
EL
TXBE=0
RXBF=0
d) Slave Receive mode
START Address 0
9.5
RX DataN
RXIF=1
RXBF=1
IN
RXBF=0
MAST=1
TXBE=0
RXBF=0
ACK
A
ACK
R
START Address 1
ACK
RX Data1
RXIF=1
RXBF=1
MATCH=1
SRW=0
ACK
NAK
STOP
NAKIF=1
MAST=0
TXBE=0
Y
b) Master Receive mode
PR
Freescale Semiconductor, Inc...
TXBE=0
MAST=1
MRW=0
TX Data1
NAK
STOP
RXIF=1
RXBF=1
NAKIF=1
MAST=0
TX DataN
NAK
STOP
RX DataN
NAK
STOP
TXIF=1
TXBE=1
ACK
RXIF=1
RXBF=1
RXIF=1
RXBF=1
Program Algorithm
The Figure 9-1 shows the algorithm of slave mode interrupt routine of DDC12B protocol.
The Figure 9-2 shows the algorithm of master mode setup and interrupt service routine.
When the DDC module detects an arbitration loss in master mode, it will release both SDA
and SCL lines immediately. But if there is no further "stop condition" detected, the module
will be hanged up. So it is recommended to have time-out software to recover from such ill
condition. The software can start the time-out counter by looking at the BB (Bus Busy) in
the bit 5 of DMCR and reset the counter when the completion of one byte transmission. If
the time-out occurred, program can clear DEN bit to release the bus, and then set DEN bit
SECTION 9: DDC12AB INTERFACE
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Rev. 2.0
PR
EL
IM
IN
A
R
Y
Freescale Semiconductor, Inc...
and DDC1EN bit to clear BB flag (This is the only way to clear BB flag by software while
the module is hanged up due to no "stop condition" received). The program can resume IIC
master mode after clearing the BB flag and DDC1EN bit.
SECTION 9: DDC12AB INTERFACE
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GENERAL
RELEASE SPECIFICATION
Interrupt
Y
SCLIF
=1?
N
Y
Clear TXIF
Write Data
to DDTR
Y
N
A
Y
Address
received
N
EL
N
IN
MATCH
=1?
Y RXIF =1?
IM
Clr DDC1EN
Clr SCLIEN
Clr SCLIF
R
Clear RXIF
Read Data
from DDRR
PR
Freescale Semiconductor, Inc...
TXIF =1?
N
SRW =1?
Y
Write
TXAK for
Next Byte
Receive
TXBE
=1?
Y
N
Write Data
to DDTR
RTI
Figure 9-1: Software Flowchart of Slave Mode Interrupt Routine
SECTION 9: DDC12AB INTERFACE
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Interrupt
RESET
Y
ALIF =1?
BB =1?
Y
N
Clear ALIF Set
"Failure" flag
for retry
*restore DADR
Y
A
N
MRW =1?
N
RXIF =1?
Y
Write
Y
End of
Data?
MRW<=0
DDTR <= 1st
Data
Clear RXIF
Read DDRR
EL
End of
Data?
Y
N
DDTR <=
Next Data
N
Set
"Incomplete"
flag for retry
Clr TXIF
N
IN
Read or
Write ?
MAST<=1
Y
R
TXIF =1?
IM
MRW<=1
N
Clr NAKIF
Y
Read
NAKIF
=1?
Y
SEI
DEN <= 1
DIEN <= 1
DADR <= TXAD**
TXAK <= 0 or 1***
CLI
PR
Freescale Semiconductor, Inc...
N
Next data is N
the last?
Y
*restore DADR
WAIT
TXAK <= 1
*restore DADR
DDTR <= $FF
MAST <= 0
*restore DADR
RTI
** TXAD means transmit address
*** TXAK is 1 when master
want receive only one byte
(a) Master mode setup
* Restore its own specific slave address
(b) Master mode interrupt routine
Figure 9-2: Software Flowchart in Master mode: (a) Mode setup. (b) Interrupt routine
SECTION 9: DDC12AB INTERFACE
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SECTION 10
10.1
SYNC PROCESSOR
Introduction
10.2.1
Polarity Detection
Y
Functional Blocks
R
10.2
10.2.2
EL
IM
IN
A
The HSYNC polarity detection circuit will measure the length of high period of HSYNC
inputs. If the length of high is longer than 7us and the length of low is shorter than 6us, the
HPOL bit will be zero, indicates negative polarity. If the length of low is longer than 7us and
the length of high is shorter than 6us, the HPOL bit is one, positive polarity. The VSYNC
polarity detection circuit perform the similar structure with HSYNC polarity detection circuit.
If the length of high is longer than 4ms and the length of low is shorter than 2ms, the VPOL
bit will be zero, indicates negative polarity. If the length of low is longer than 4ms and the
length of high is shorter than 2ms, the VPOL bit is one, positive polarity. Both HSYNC and
VSYNC polarity flags are read-only, and will not affect any internal circuitry. When the
COMP bit in SPCSR register is set, the HPOL bit will be the same as VPOL bit which is
detected under the criteria stated in previous statements.
Sync Signal Counters
PR
Freescale Semiconductor, Inc...
The functions of the module include polarity detection, horizontal frequency counter,
vertical frequency counter, and polarity controllable HSYNO and VSYNO outputs of various
input sources, such as separate H & V, Composite Sync from HSYNC, Sync-On-Green, or
internal free running H & V pulses. Besides, it also provides the CLAMP pulse output to the
external Pre-Amp chip. The SOGIN bit in SPIOCR register will determine the Composite
Sync input pin. All HSYNC, VSYNC, and SOG inputs have internal schmitt trigger to
improve noise immunity.
There are two counters (horizontal frequency counter and vertical frequency counter) to
count the number of horizontal sync pulses within 32ms period and the number of system
clock cycles between two vertical sync pulses. These two data can be read by the CPU to
check the signal frequencies and can be used to determine the video mode. The 13-bit
vertical frequency register encompasses vertical frequency range from about 15 Hz to 127
Hz. Due to the asynchronous timing between incoming VSYNC and internal processor
clock, there will be ±1 count error on the reading from the register for the same vertical
frequency. The horizontal counter counts the pulses on HSYNC pin, and is uploaded to the
$0F and $10 registers every 32.768ms. The step unit in the lower 5-bit register is
0.3125KHz. And the least 7 bits in the HFHR register shows the number of KHz of incoming
HSYNC signal. The MSB of the HFHR is the overflow flag of H-counter, which will be
cleared when the register is read by CPU.
10.2.3
Polarity Controlled HSYNO/VSYNO Outputs
The input HSYNC and VSYNC signal can be output to PC6 and PC7 when the
configuration bit of PC6 and PC7 in register $0B are set for SYNC output. Two
SECTION 10: SYNC PROCESSOR
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corresponding polarity control bits, bit 3 and bit 2 of register $0C, can change the polarity
of HSYNO/VSYNO outputs. The result HSYNO and VSYNO outputs can vary while the
setting in SPCSR and SPIOCR register is different. If the COMP bit in SPCSR register is
set, the incoming composite Sync signal will be the HSYNO output and the extracted
VSYNC with 6~7us delay will be the VSYNC output. When the SOUT bit in SPIOCR
register is set, the internal free-running 55.556KHz with 2us pulse will be the HSYNO
output and the other free-running 72.34Hz with 108us pulse will be the VSYNO output.
10.2.4
CLAMP Pulse Output
Y
CLAMP
(BPOR=0)
0.5-0.75us
IM
CLAMP
(BPOR=1)
IN
A
R
HSYNC
(HPOL=1)
HSYNC
(HPOL=0)
0.5-0.75us
0.5-0.75us
EL
0.5-0.75us
PR
Freescale Semiconductor, Inc...
The logic will generate a 0.5us - 0.75us pulse at either the leading edge or the trailing edge
which is specified by the BPOR bit in the SPIOCR register. See Figure 10-1 for its detail
timing relation. One control bit to invert the output polarity of CLAMP pulse is located at bit
5 of SPIOCR.
CLAMP
(BPOR=0)
0.5-0.75us
0.5-0.75us
CLAMP
(BPOR=1)
0.5-0.75us
Figure 10-1: CLAMP output waveform
SECTION 10: SYNC PROCESSOR
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RELEASE SPECIFICATION
10.3
Registers
10.3.1
Sync Processor Control and Status Register (SPCSR)
NOTE:
Please don’t use BSET or BCLR to manipulate this register when VSIE is
set and I-bit is clear, or it will cuase abnormal reset.
6
5
VSIE
VEDGE
0
0
4
3
COMP
VINVO
VSIF
bit 6
VSIF
bit 5
0
0
0
A
VEDGE
0
HPOL
When VSync Interrupt Enable (VSIE) bit is set, the VSIF flag
is enabled to generate an interrupt request to the CPU. When
VSIE is cleared, the VSIF flag is prevented from generating an
interrupt request. Reset clears this bit.
The VEDGE bit specifies the triggering edge of VSYNC
interrupt. When it is zero, the rising edge of internal VSYNC
signal which is either from the VSYNC pin or extracted from
the composite input signal will set VSIF flag. When it is one,
the falling edge of internal VSYNC signal will set VSIF flag.
Reset clears this bit.
This flag is a read-only bit and is set by the specified edge of
internal VSYNC signal which is either from the VSYNC pin or
extracted from the composite input signal. The triggering
edge is specified by the VEDGE bit, see the above description
of VEDGE for details. It is cleared by writing a zero to it or
reset.
This COMPosite video input enable bit is set to enable the
separator circuit which extracts the VSYNC pulse from
composite input in HSYNC pin. The extracted VSYNC pulse
will be fed into the vertical counter, vertical polarity detection
circuit, and VSYNO output circuit as well. Its measurable
timing is the same as the separate VSYNC pin input. Reset
clears this bit.
This bit controls the output polarity of the VSYNO signal.
When it is zero, the VSYNO output is identical to the VSYNC
input. When it is one, the inverted VSYNC signal is output to
VSYNO pin.
IN
bit 7
0
VPOL
EL
VSIE
0
0
IM
reset ⇒
1
HINVO
R
W
2
Y
R
SPCSR
$000C
7
PR
Freescale Semiconductor, Inc...
There are five registers associated with the SYNC PROCESSOR module as described
below.
COMP
bit 4
VINVO
bit 3
SECTION 10: SYNC PROCESSOR
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Rev. 2.0
HINVO
bit 2
VPOL
bit 1
HPOL
bit 0
Sync Processor Input/Output Control Register (SPIOCR)
VSYNCS
HSYNCS
5
4
3
2
COINV
HVTST
SOGIN
CLAMPOE
0
0
0
W
HSYNCS
bit 6
COINV
bit 5
HVTST
bit 4
SOGIN
0
0
A
bit 7
0
The VSYNCS bit reflects the logical state of VSYNC input. It
is a read only bit.
The HSYNCS bit reflects the logical state of HSYNC input. It
is a read only bit.
This Clamp Output INVert bit will invert the CLAMP output.
When it is zero, the CLAMP output has default positive going
pulse as illustrated in Figure 10-1. When it is one, the CLAMP
output is inverted as negative pulse generated. Reset clears
this bit.
This HV TeST bit is reserved for testing purpose. It can be
accessed only in test mode. So user must be careful while
developing the program in EVS platform. Reset clears this bit.
If the SOGIN bit is one, the SOG pin which is shared with PD3
will be selected as the composite sync input when the COMP
bit in SPCSR register is one. If it is zero, the HSYNC pin is the
default composite input pin when the COMP bit is one. Reset
clears this bit.
The CLAMP Output Enable bit is set to configure the PD2 pin
as the CLAMP pulse output pin. Reset clear this bit.
The Back PORch bit defines the triggering edge of clamp
output. When it is one, the clamp pulse is generated at the
trailing edge of HSYNC input. When it is zero, the clamp pulse
is generated at the leading edge of HSYNC input. Reset
clears this bit.
The SOUT will select the output signals of VSYNO and
HSYNO from the internal free-running counter. When it is
zero, the incoming HSYNC and VSYNC or extracted VSYNC
IN
VSYNCS
0
SOUT
IM
0
BPOR
0
EL
reset ⇒
1
Y
6
R
R
SPIOCR
$0011
7
PR
Freescale Semiconductor, Inc...
10.3.2
This bit controls the output polarity of the HSYNO signal.
When it is zero, the HSYNO output is identical to the HSYNC
input. When it is one, the inverted HSYNC signal is output to
HSYNO pin.
This bit shows the polarity of VSYNC input. If it is one, the
VSYNC input has positive polarity. If it is zero, the VSYNC
input has negative polarity. Reset clears this bit.
This bit shows the polarity of HSYNC input. If it is one, the
HSYNC input has positive polarity. If it is zero, the HSYNC
input has negative polarity. Reset clears this bit.
bit 3
CLAMPOE
bit 2
BPOR
bit 1
SOUT
bit 0
SECTION 10: SYNC PROCESSOR
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GENERAL
RELEASE SPECIFICATION
will be output to the HSYNO and VSYNO pins. When it is one,
the free-running 55.556KHz HSYNC with 2us negative pulse
and 72.34Hz VSYNC with 108us negative pulse will be
generated to the HSYNO and VSYNO output stages. Reset
clears this bit.
Vertical Frequency Registers (VFRs)
R
5
4
3
2
1
0
VOF
0
0
VF12
VF11
VF10
VF9
VF8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
VF7
VF6
VF5
VF4
VF2
VF1
VF0
0
0
0
0
0
0
0
R
0
IM
reset ⇒
IN
W
VF3
A
R
Y
W
reset ⇒
VFLR
$000E
6
$0823
130.21 Hz
129.94 Hz
$0824
60.01 Hz
59.95 Hz
130.07 Hz
129.80 Hz
$0825
59.98 Hz
59.92 Hz
100.08 Hz
99.92 Hz
$09C4
50.02 Hz
49.98 Hz
$04E3
100.00 Hz
99.84 Hz
$09C5
50.00 Hz
49.96 Hz
$04E4
99.92 Hz
99.76 Hz
$09C6
49.98 Hz
49.94 Hz
$06F9
70.07 Hz
69.99 Hz
$1FFD
15.266 Hz
15.262 Hz
$06FA
70.03 Hz
69.95 Hz
$1FFE
15.264 Hz
15.260 Hz
$06FB
69.99 Hz
69.91 Hz
$1FFF
15.262 Hz
15.258 Hz
VFR
Max Freq
$03C0
130.34 Hz
$03C1
$03C2
$04E2
PR
Freescale Semiconductor, Inc...
VFHR
$000D
7
Min Freq
VFR
Max Freq
Min Freq
130.07 Hz
60.04 Hz
59.98 Hz
EL
10.3.3
This 13-bit read only register pair contains information of the vertical frame frequency. An
internal counter counts the number of internal clocks between two VSYNC pulses. The
most significant 5 bits of counted value will then be transferred to high byte register, $0D,
and the least significant 8 bits of counted value is transferred to one intermediate buffer.
When the high byte register is read, the 8-bit counted value stored in the intermediate buffer
will be uploaded to the low byte register, $0E. So the program must read the high byte
register first then low byte register in order to get the complete counted value of one vertical
frame. If the counter overflow, the VOF flag will be set while the counter values stored in
SECTION 10: SYNC PROCESSOR
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GENERAL RELEASE SPECIFICATION
Rev. 2.0
the VFRs registers are meaningless. The data corresponds to the period of one vertical
frame. This register can be read to determine if the frame frequency is valid, and to
determine the video mode. The MSB in the VFHR register will indicate the overflow
condition when the period of VSYNC frame exceeds 64.768ms (lower than 15.258Hz). This
VOF flag is default to be zero and will be update every vertical frame or set when the
counter overflows.
The frame frequency is calculated by 1/(VFR±1 x 8µS) or 1/(VFR±1 x 16 x tcyc).
The table above shows examples for the Vertical Frequency Register, all VFR numbers are
in hexadecimal:
Hsync Frequency Registers (HFRs)
4
3
HOVER
HFH6
HFH5
HFH4
HFH3
0
0
0
0
7
6
5
0
0
0
0
0
W
0
HFH2
HFH1
HFH0
0
A
IN
0
0
0
0
3
2
1
0
HFL4
HFL3
HFL2
HFL1
HFL0
0
0
0
0
0
EL
reset ⇒
1
4
IM
R
2
Y
5
W
reset ⇒
HFLR
$0010
6
R
R
HFHR
$000F
7
This 13-bit read-only register pair contains the number of horizontal lines within 32ms and
one overflow bit, HOVER. An internal line counter counts the horizontal sync pulses within
32ms window of every 32.768ms period. The most significant 7 bits of counted value will
then be transferred to high byte register, $0F, and the least significant 5 bits of counted
value is transferred to one intermediate buffer. When the high byte register is read, the 5bit counted value stored in the intermediate buffer will be uploaded to the low byte register,
$10. So the program must read the high byte register first then low byte register in order to
get the complete counted value of horizontal pulses. The HOVER bit will be set immediately
if the number of incoming horizontal sync pulses in 32ms are more than 4095, that means
HSYNC frequency is over 128KHz. The HFHR data can be read to determine the number
of KHz of HSYNC frequency and the HFLR shows the sub-KHz value of HSYNC frequency.
This makes user easy to read the frequency of HSYNC and determine the video mode.
PR
Freescale Semiconductor, Inc...
10.3.4
10.4
System Operation
This module is used mainly for user to determine the video mode of incoming HSYNC and
VSYNC of various frequency and polarity. It is designed to assist in determining the video
mode including DPMS modes. The definition of ’No pulses’ of DPMS standard can be
detected when the value of H counter register is less than one or the VOF in the VFHR
register is set. For the HSYNC counter value will be updated repeatedly every 32.768ms
SECTION 10: SYNC PROCESSOR
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Y
R
A
IN
IM
EL
PR
Freescale Semiconductor, Inc...
and also we know the valid VSYNC pulse, more than 40Hz, could arrive in shorter time. So
it is recommended that user reads the counter value every 32.768ms period.
SECTION 10: SYNC PROCESSOR
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A
R
Y
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SECTION 11
11.1
MULTI-FUNCTION TIMER
Introduction
A
R
Y
The clock base for this module is derived from bus clock divided by four. For a 2 MHz E
(CPU) clock, the clock base is 0.5 MHz. This clock base is then divided by an 8-stage ripple
counter to generate the timer overflow. Timer overflow rate is thus E/1024. The output of
this 8-stage ripple counter then drives one stage divider to generate real time interrupt.
Hence, the clock base for real time interrupt is E/2,048. Real time interrupt rate is selected
by RT0 and RT1 bits of Multi-Function Timer Control/Status Register (MFTCSR). The
interrupt rates are E/2,048, E/(2,048X2), E/(2,048X4), and E/(2,048X8). The selected real
time interrupt rate is then divided by 64 to generate COP reset.
11.2
EL
IM
IN
The COP watchdog timer function is implemented by using a COP counter. The minimum
COP reset rates are controlled by RT0 and RT1 of MFTCSR. If the COP circuit times out,
an internal reset is generated and the normal reset vector is fetched. Preventing a COP
time-out is done by writing a ‘0’ to bit 0 of address $3FF0. This write operation resets the
divide-by-64 counter stage described in the previous paragraph. The COP counter has to
be cleared periodically by software with a period less than COP reset rate. It continues to
count even though the CPU is in WAIT mode. In MC68HC05BD7, the COP is always
enabled.
Register
There are two registers in the Multi-Function Timer as discussed below.
11.2.1
PR
Freescale Semiconductor, Inc...
This module provides miscellaneous function to the MC68HC05BD7. It includes a timer
overflow, real-time interrupt, and watchdog functions. Also included in the module is the
capability of selecting the mode of the maskable external interrupt pin, either edgetriggered mode only or both edge-triggered mode and level-triggered mode.
Multi-function Timer Control/status Register
NOTE:
Please don’t use BSET or BCLR to manipulate this register when I-bit is
clear, or it will generate abnormal reset.
7
6
5
4
3
2
1
0
TOF
RTIF
TOFIE
RTIE
IRQN
INHIRQ
RT1
RT0
0
0
0
0
0
0
1
1
R
MFTCSR
$0008
W
reset ⇒
TOF
bit 7
Timer Overflow Flag indicates if the 8-bit ripple counter
overflows. TOF is set when the 8-bit counter rolls over from
SECTION 11: MULTI-FUNCTION TIMER
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bit 4
IRQN
bit 3
INHIRQ
bit 2
RT1-0
bit 1,0
Y
RTIE
R
bit 5
A
TOFIE
IN
bit 6
EL
IM
RTIF
$FF to $00. A CPU interrupt request will be generated if
TOFIE is set. TOF is a clearable, read-only status bit. Clearing
the TOF is done by writing a ’0’ to TOF.
Real Time Interrupt Flag indicates if the output of the RTI
circuit goes active. The clock frequency that drives the RTI
circuit is E/2,048, giving a maximum interrupt period of 1.024
milliseconds at a bus rate of 2 MHz. A CPU interrupt request
will be generated if RTIE is set. RTIF is a clearable, read-only
status bit. Clearing the RTIF is done by writing a ’0’ to RTIF.
When Timer Over Flow Interrupt Enable (TOFIE) bit is set, the
TOF flag is enabled to generate an interrupt request to the
CPU. When TOFIE is cleared, the TOF flag is prevented from
generating an interrupt request.
When Real Time Interrupt Enable (RTIE) is set, the RTIF flag
is enabled to generate an interrupt request to the CPU. When
RTIE is cleared, the RTIF flag is prevented from generating an
interrupt request.
0 = Both level and edge triggering are detected for external
interrupt (IRQ).
1 = Only edge triggering is detected for external interrupt.
The INHibit IRQ bit will inhibit the external interrupt input.
When it is set, no active falling edge or low period will be
recognized as interrupt request. It is possible for a low state
input on the IRQ pin to be seen as a falling edge event when
the INHIRQ bit changes from one to zero, see Figure 4-2 for
reference. Reset clears this bit.
These two bits are used to define real time interrupt rate as
well as COP reset rate as tabulated in Table 11-1. Reset sets
these two bits for the slowest watchdog reset rate. Note that
the minimal COP reset period is determined by dividing the
COP master clock, which is the real time interrupt clock, by
63(63=64-1). The reason is that COP reset operation is
asynchronous to COP master clock edge. Therefore it is
possible that right after COP reset operation, a COP master
clock edge arrives to start counting COP period. The effective
count of the divide-by-64 counter is hence 63 rather than 64.
RT1, RT0 should only be changed right after COP timer has
been reset; otherwise, unpredictable result will occur.
PR
Freescale Semiconductor, Inc...
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GENERAL RELEASE SPECIFICATION
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SECTION 11: MULTI-FUNCTION TIMER
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GENERAL
RELEASE SPECIFICATION
RT1 RT0
RTI Period @ 2 MHz
Min. COP Reset Period @ 2 MHz E Clock
0
0
64.512 ms
1.024 ms
0
1
129.024 ms
2.048 ms
1
0
258.048 ms
4.096 ms
1
1
516.096 ms
8.192 ms
Table 11-1: COP Reset Rates and RTI Rates
MFT Timer Counter Register
5
4
3
MFTCR7
MFTCR6
MFTCR5
MFTCR4
MFTCR3
0
0
0
0
reset ⇒
0
A
W
2
Y
6
MFTCR2
R
R
MFTCR
$0009
7
0
1
0
MFTCR1
MFTCR0
0
0
EL
IM
IN
This 8-bit free-running counter register, MFTCR, can be read at location $0009. It is cleared
by reset.
PR
Freescale Semiconductor, Inc...
11.2.2
SECTION 11: MULTI-FUNCTION TIMER
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R
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Inc.
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SECTION 12
12.1
A/D CONVERTER
Introduction
R
Y
ADC0 or ADC1 or ADC2 or ADC3
+
2R
R
EL
IM
IN
R
A
RESULT
PR
Freescale Semiconductor, Inc...
The Analog-to-Digital Converter (ADC) system consists of four analog input channels and
a single 6-bit D/A Converter and Comparator, with continuous conversion. A result flag
indicates if the comparator output is above or below the analog Input. ADC is disabled by
setting AD5 to AD0 bits of ADC Control/Status Register to all 1’s. This disable function is
mainly for low power application.
R
R
2R
2R
2R
2R
R
2R
AD5
AD4
AD3
AD2
AD1
AD0
2R
Vdd
Figure 12-1: Structure of A/D Converter
12.2
Input
The ADC has four multiplexed input channels. Only one of the four channels will be
selected by CHSL1 and CHSL0 bits as analog input.
12.2.1
ADC0-ADC3
The ADC0 to ADC3 inputs are multiplexed with the PC2 to PC5 port pins. They are selected
as ADC input then the corresponding AD0-AD3 bit in the CR2 register is one. The user can
use the CHSL1 and CHSL0 bits to select one of the four channels to do the A/D Conversion
and get the approximate digital value of each input channel.
SECTION 12: A/D CONVERTER
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12.3
Registers
12.3.1
ADC Control/status Register
This read/write register, located at address $14, contains six control bits and one status bit.
7
R
ADCSR
$0014
6
5
4
3
2
1
0
AD5
AD4
AD3
AD2
AD1
AD0
0
0
0
0
0
0
RESULT
W
reset ⇒
0
0
Y
When set, D/A output ≥ ANALOG IN.
When clear, D/A output ≥ ANALOG IN.
R
AD5:0 - A/D Digital Result
12.3.2
ADC Channel Register
IM
IN
A
These bits are written by the user to perform successive
approximations in software. When a value causes the
RESULT bit to change state from the value immediately
before or after it, AD5:0 are considered to be the digital
equivalent of the analog input. Note that when AD5:0 are all
1’s, ADC is virtually turned off to minimize power
consumption.
7
R
ADCCR
$0015
W
reset ⇒
EL
The ADC Channel Register, located at address $15 contains only two bits.
6
5
PR
Freescale Semiconductor, Inc...
RESULT - Comparator Status Bit (Read Only)
0
0
0
4
0
3
0
2
0
1
0
CHSL1
CHSL0
0
0
CHSL1:CHSL0 - Channel select bits
These two bit will select one of the four ADC input channels
as analog input source. Following table shows its
configuration.
CHSL1:CHSL0 = 0 : 0 ==> ADC0
CHSL1:CHSL0 = 0 : 1 ==> ADC1
CHSL1:CHSL0 = 1 : 0 ==> ADC2
CHSL1:CHSL0 = 1 : 1 ==> ADC3
SECTION 12: A/D CONVERTER
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RELEASE SPECIFICATION
12.4
Program Example
;
;
;
;
;
;
Configuration Register
ADC Channel Register
ADC Control & Status Register
RAM byte to store the conversion result
RAM byte to store the high end of conversion
RAM byte to store the low end of conversion
Y
$0B
$15
$14
$50
$51
$52
$1000
#$3C
CR2
#$00
ADCCR
#$00
REFL
#$3F
REFH
REFH
REFL
; Configure PC2-PC5 as ADC inputs
R
; Select the input channel
A
; initial low end = #$00
;
;
;
;
;
;
A= (REFH + REFL)/2
Store the comparison data to D/A
Compare the stored value with REFL
If equal, the A is the result digital value
Check the RESULT flag
If lower, set A as the low end of conversion
IM
ADCSR
REFL
DONE
7,ADCSR,SETHI
REFL
DALP
REFH
DALP
ADCDATA
IN
; initial high end =#$3F
EL
CR2
EQU
ADCCR EQU
ADCSR EQU
ADCDATA EQU
REFH
EQU
REFL
EQU
ORG
LDA
STA
LDA
STA
LDA
STA
LDA
STA
DALP
LDA
ADD
LSRA
STA
CMP
BEQ
BRSET
STA
BRA
SETHI STA
BRA
DONE
STA
; If higher, set A as the high end of conversion
PR
Freescale Semiconductor, Inc...
The following example shows how to convert analog input channel 0 by using binary search
method. This approach method will guarantee any conversion can be done within 6
iterations, 98us at 2MHz bus clock. For ADCIN1 conversion, change #$00 to #$01. ADCCR
is the ADC Channel Register.
* Input voltage calculation at VDD=5V:
ADCDATA x 0.078125V ≤ INPUT ≤ (ADCDATA+1) x 0.078125V
SECTION 12: A/D CONVERTER
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A
R
Y
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Inc.
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SECTION 13
13.1
ELECTRICAL SPECIFICATIONS
Maximum Ratings
(Voltages referenced to VSS)
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Input Voltage
VIN
VSS –0.3 to VDD +0.3
V
IRQ Pin
VIN
VSS –0.3 to 2VDD +0.3
V
Current Drain Per Pin Excluding VDD and VSS
VIN
25
mA
0 to +70
°C
–65 to +150
°C
A
TA
R
Operating Temperature Range
MC68HC05BD7 (Standard)
Y
Symbol
TSTG
IN
Storage Temperature Range
13.2
EL
IM
This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (e.g., either VSS or VDD).
Thermal Characteristics
PR
Freescale Semiconductor, Inc...
Rating
Characteristic
Thermal Resistance
Plastic
Symbol
Value
Unit
θ JA
60
°C/W
SECTION 13: ELECTRICAL SPECIFICATIONS
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13.3
DC Electrical Characteristics
Typ
Max
Unit
Output High Voltage (ILoad = -5.0 mA)
PA0-PA7, PB0-PB1, PC2-PC7, PWM0-PWM7
VOH
VDD–0.8
—
—
V
Output Low Voltage (ILoad = 5.0 mA for +5V pins and
ILoad = 10.0 mA for +12V open-drain pins)
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD3, PWM0PWM7
VOL
—
—
0.5
V
Input High Voltage
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, RESET,
IRQ, EXTAL
(TTL Level) VSYNC, HSYNC, SOG
SDA,SCL
VIH
VIH
VIH
0.8 x VDD
2.0
0.8 x VDD
—
—
—
VDD
VDD
VDD
V
V
V
VSS
VSS
VSS
—
—
—
0.2 x VDD
0.8
0.2 x VDD
V
V
V
IDD
IDD
—
—
8
4
20
8
mA
mA
IOZ
—
—
10
µA
IIN
—
—
1
µA
COUT
CIN
—
—
—
—
12
8
pF
pF
I/O Ports Hi-Z Leakage Current
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD3
EL
Input Current
RESET, IRQ, EXTAL, VSYNC, HSYNC
IM
Supply Current (see Notes)
Run
Wait
VIL
PR
Capacitance
Ports (as Input or Output), RESET, IRQ, EXTAL, XTAL
HSYNC, VSYNC
R
Input Low Voltage
PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD3, RESET,
IRQ, EXTAL
(TTL Level) VSYNC, HSYNC, SOG
SDA,SCL
Y
Min
A
Characteristic
Freescale Semiconductor, Inc...
Symbol
IN
(VDD = 5.0 Vdc ±10%, VSS = 0Vdc, TA = 0˚C to +70˚C, unless otherwise noted)
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Wait IDD: Only timer system and SSP active.
4. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to EXTAL (fOSC = 4.2 MHz),
all inputs 0.2 VDC from rail; no DC loads, less than 50pF on all outputs, CL = 20 pF on EXTAL.
5. Wait IDD: All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD-0.2 VDC.
6. Wait IDD is affected linearly by the EXTAL capacitance.
SECTION 13: ELECTRICAL SPECIFICATIONS
Page 66
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
13.4
Control Timing
(VDD = 5.0 Vdc ±10%, VSS = 0Vdc, TA = 0˚C to +70˚C, unless otherwise noted)
Symbol
Min
Max
Units
fOSC
fOSC
—
dc
4.2
4.2
MHz
MHz
Internal Operating Frequency
Crystal Oscillator (fOSC/2)
External Clock (fOSC/2)
fOP
fOP
—
dc
2.1
2.1
MHz
MHz
Cycle Time (1/fop)
tCYC
480
—
ns
tOXON
—
100
ms
1.5
—
tCYC
125
—
ns
note 1
—
tCYC
100
—
ns
Frequency of Operation
Crystal Oscillator Option
External Clock Source
tRL
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILIH
R
RESET Pulse Width Low
tILIL
A
IRQ Interrupt Pulse Period
tOH, tOL
IN
EXTAL Pulse Width
NOTE:
1. The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21
EL
IM
tCYC.
PR
Freescale Semiconductor, Inc...
Crystal Oscillator Start-up Time (Crystal Oscillator option)
Y
Characteristic
SECTION 13: ELECTRICAL SPECIFICATIONS
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Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
13.5
DDC12AB TIMING
(VDD = 5.0 Vdc ±10%, VSS = 0Vdc, TA = 0˚C to +70˚C, unless otherwise noted
13.5.1
DDC12AB Interface Input Signal Timing
Symbol
Min
Max
Units
tHD.STA
2
—
tCYC
Clock low period
tLOW
4
—
tCYC
Clock high period
tHIGH
4
—
tCYC
Data set up time
tSU.DAT
250
—
ns
Data hold time
tHD.DAT
0
—
ns
START condition set up time (for repeated START condition only)
tSU.STA
2
—
tCYC
STOP condition set up time
tSU.STO
2
—
tCYC
R
A
DDC12AB Interface Output Signal Timing
IN
13.5.2
Parameter
IM
SDA / SCL rise time (see NOTE 1)
SDA / SCL fall time (see NOTE 1)
Data set up time
EL
Data hold time
NOTE:
Symbol
Min
Max
Units
tR
—
1.0
µs
tF
—
300
ns
tSU.DAT
tLOW
—
ns
tHD.DAT
0
—
ns
1. With 200 pF loading on the SDA/SCL pins
SDA
PR
Freescale Semiconductor, Inc...
START condition hold time
Y
Parameter
SCL
tHD.STA
tLOW
tHIGH
tSU.DAT
tHD.DAT
tSU.STA
tSU.STO
SECTION 13: ELECTRICAL SPECIFICATIONS
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
13.6
HSYNC/VSYNC Input Timing
(VDD = 5.0 Vdc ±10%, VSS = 0 VDC, TA = 0˚C to +70˚C, unless otherwise noted)
Min
Max
Units
VSYNC input sync pulse
tVI.SP
1/2
4096
tCYC
HSYNC input sync pulse
tHI.SP
1/2
12
tCYC
VSYNC to VSYNO delay (8pF loading)
tVVd
30
40
ns
HSYNC to HSYNO delay (8pF loading)
tHHd
30
40
ns
EL
IM
IN
A
R
Y
Symbol
PR
Freescale Semiconductor, Inc...
Parameter
SECTION 13: ELECTRICAL SPECIFICATIONS
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IN
A
R
Y
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
PR
EL
IM
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SECTION 13: ELECTRICAL SPECIFICATIONS
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Semiconductor,
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
SECTION 14
14.1
MECHANICAL SPECIFICATIONS
Introduction
The MC68HC05BD7 is available in 40-pin DIP and 42-pin SDIP packages.
40-Pin DIP Package (Case 711-03)
21
R
B
20
A
C
H
G
F
L
IN
N
A
1
K
D
J
M
IM
°
°
°
°
42-Pin SDIP Package (Case 858-01)
EL
14.3
! ! ! #! %% ! $"
! ! ! ! !
!
! ! #
! " Y
40
-A-
PR
Freescale Semiconductor, Inc...
14.2
42
! ! %
! ! ! #
! " $" 22
-B-
1
21
L
H
C
-T
G
F
D 42 PL
N
K
! M
J 42 PL
°
°
°
°
! SECTION 14: MECHANICAL SPECIFICATIONS
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IN
A
R
Y
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
PR
EL
IM
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SECTION 14: MECHANICAL SPECIFICATIONS
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MC68HC05BD7 Rev.Freescale
2.0
GENERAL
RELEASE SPECIFICATION
SECTION 15
1u
330
330
330
330
PA2
1u
1u
1u
1u
100
PC
100K
A
10K
10K
100K
R
100
10K
1K7
3K3
5K
3K3
CS0
CS1
10K
10K
10K
1K7
10K
10K
5K
10K
10K
PR
EL
OSD
1u
4K7
4K7
4K7
EEPROM
4K7
WP
34
HSYNO
33
VSYNO
32
PWM13
31
PWM12
30
ADC1
29
ADC0
28
PWM9*
27
PWM8*
26
SCL*
25
SDA*
24
PA0
23
PA1
22
1u
4K7
33p
10K
IN
4MHz
XTAL
EXTAL
PB5*
PB4*
PB3*
PB2*
PB1
PB0
IRQ
PA7
PA6
PA5
PA4
PA3
1u
42
VSYNC
41
HSYNC
40
PWM3**
39
PWM4**
38
PWM5**
37
CLAMP
36
PWM6**
35
PWM7**
IM
33p
4U7
0.1u
RESET IC
10K
10K
10K
PWM2**
PWM1**
PWM0**
RESET
VDD
SOG
VSS
4K7
MC68HC05BD7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
1u
Y
1u
4K7
1u
10K
330
Freescale Semiconductor, Inc...
1u
APPLICATION DIAGRAM
CS2
100
100
DDC
*Note: RESET IC is MC34064
SECTION 15: APPLICATION DIAGRAM
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IN
A
R
Y
Freescale Semiconductor, Inc...
Freescale Semiconductor, MC68HC05BD7
Inc.
GENERAL RELEASE SPECIFICATION
Rev. 2.0
PR
EL
IM
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SECTION 15: APPLICATION DIAGRAM
Page 74
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Home Page:
www.freescale.com
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Europe, Middle East, and Africa:
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HC05BD7GRS/H