application INFO available UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 Phase Shift Resonant Controller FEATURES DESCRIPTION • Zero to 100% Duty Cycle Control The UC1875 family of integrated circuits implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-voltage switching for high efficiency performance at high frequencies. This family of circuits may be configured to provide control in either voltage or current mode operation, with a separate over-current shutdown for fast fault protection. • Programmable Output Turn-On Delay • Compatible with Voltage or Current Mode Topologies • Practical Operation at Switching Frequencies to 1MHz • Four 2A Totem Pole Outputs • 10MHz Error Amplifier • Undervoltage Lockout • Low Startup Current –150µA • Outputs Active Low During UVLO • Soft-Start Control • Latched Over-Current Comparator With Full Cycle Restart • Trimmed Reference A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair (A-B, C-D). With the oscillator capable of operation at frequencies in excess of 2MHz, overall switching frequencies to 1MHz are practical. In addition to the standard free running mode, with the CLOCKSYNC pin, the user may configure these devices to accept an external clock synchronization signal, or may lock together up to 5 units with the operational frequency determined by the fastest device. Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a 10.75V threshold. 1.5V hysteresis is built in for reliable, boot-strapped chip supply. Over-current protection is provided, and will latch the outputs in the OFF state within 70nsec of a fault. The current-fault circuitry implements full-cycle restart operation. (continued) BLOCK DIAGRAM UDG-95073 SLUS229B - JULY 1999 - REVISED JUNE 2004 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 DESCRIPTION (cont.) Additional features include an error amplifier with bandwidth in excess of 7MHz, a 5V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry. Device UVLO Turn-On 10.75 15.25V 10.75V 15.25V UC1875 UC1876 UC1877 UC1878 These devices are available in 20-pin DIP, 28-pin “bat-wing” SOIC and 28 lead power PLCC plastic packages for operation over both 0°C to 70°C and –25°C to +85°C temperature ranges; and in hermetically sealed cerdip, surface mount, and ceramic leadless chip carrier packages for –55°C to +125°C operation. UVLO Turn-Off 9.25V 9.25V 9.25V 9.25V Delay Set Yes Yes No No CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Dil-20 (Top View) J or N Package Supply Voltage (VC, VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Output Current, Source or Sink DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A Analog I/0s (Pins 1, 2, 3, 4, 5, 6, 7, 15, 16, 17, 18, 19) . . . . –0.3 to 5.3V Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C Note: Pin references are to 20 pin packages. All voltages are with respect to ground. Currents are positive into, negative out of, device terminals. Consult Unitrode databook for information regarding thermal specifications and limitations of packages. CLCC-28 (Top View) L Package SOIC-28, (Top View) DWP Package VIN VC PWRGND OUTC OUTD OUTB OUTA 4 3 2 1 28 27 26 N/C 5 25 N/C N/C 6 24 DELAYSET C-D DELAYSET A-B 7 23 SS FREQSET 8 22 CS+ CLOCKSYNC 9 21 EA+ 10 20 E/A- 11 19 12 13 14 15 16 17 18 N/C SLOPE RAMP N/C N/C GND N/C E/A OUT VREF N/C 2 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 PLCC-28 (Top View) QP Package ELECTRICAL CHARACTERISTICS: Unless otherwise stated, –55°C < TA < 125°C for the UC1875/6/7/8, –25°C < TA < 85°C for the UC2875/6/7/8 and 0°C < TA < 70°C for the UC3875/6/7/8, VC = VIN = 12V, RFREQSET = 12kΩ, CFREQSET = 330pF, RSLOPE = 12kΩ, CRAMP = 200pF, CDELAYSET A-B = CDELAYSET C-D = 0.01µF, IDELAYSET A-B = IDELAYSET C-D = –500µA, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 10.75 11.75 V Undervoltage Lockout Start Threshold UC1875/UC1877 UC1876/UC1878 UVLO Hysteresis UC1875/UC1877 15.25 0.5 1.25 V 2.0 UC1876/UC1878 6.0 IIN Startup VIN = 8V, VC = 20V, RSLOPE open, IDELAY = 0 150 600 IC Startup VIN = 8V, VC = 20V, RSLOPE open, IDELAY = 0 V V Supply Current µA 10 100 µA IIN 30 44 mA IC 15 30 mA 5 5.08 V Voltage Reference Output Voltage TJ = +25°C Line Regulation 11 < VIN < 20V 1 10 mV Load Regulation IVREF = –10mA 5 20 mV Total Variation Line, Load, Temperature Noise Voltage 10Hz to 10kHz 50 µVrms Long Term Stability TJ = 125°C, 1000 hours 2.5 mV Short Circuit Current VREF = 0V, TJ = 25°C 60 mA 4.92 3 4.9 5.1 V UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, –55°C < TA < 125°C for the UC1875/6/7/8, –25°C < TA < 85°C for the UC2875/6/7/8 and 0°C < TA < 70°C for the UC3875/6/7/8, VC = VIN = 12V, RFREQSET = 12kΩ, CFREQSET = 330pF, RSLOPE = 12kΩ, CRAMP = 200pF, CDELAYSET A-B = CDELAYSET C-D = 0.01µF, IDELAYSET A-B = IDELAYSET C-D = –500µA, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 5 15 mV 0.6 3 µA Error Amplifier Offset Voltage Input Bias Current AVOL 1V < VE/AOUT < 4V 60 90 dB dB CMRR 1.5V < VCM < 5.5V 75 95 PSRR 11V < VIN < 20V 85 100 dB Output Sink Current VE/AOUT = 1V 1 2.5 mA Output Source Current VE/AOUT = 4V –1.3 –0.5 mA Output Voltage High IE/AOUT = –0.5mA 4 4.7 5 V Output Voltage Low IE/AOUT = 1mA 0 0.5 1 Unity Gain BW (Note 8) 7 11 MHz Slew Rate (Note 8) 6 11 V/µsec 1.3 V V PWM Comparator Ramp Offset Voltage TJ = 25°C (Note 3) Zero Phase Shift Voltage (Note 4) 0.55 0.9 PWM Phase Shift (Note1) and (Note 7) VE/AOUT > (Ramp Peak + Ramp Offset) 98 99.5 102 % VE/AOUT < Zero Phase Shift Voltage 0 0.5 2 % V Output Skew (Note 1) and (Note 7) VE/AOUT < 1V 5 ±20 nsec Ramp to Output Delay, (Note 8) UC3875/6/7/8 (Note 6) 65 100 nsec UC1875/6/7/8, UC2875/6/7/8 (Note 6) 65 125 nsec 1 1.15 MHz 0.2 2 % 1.20 MHz Oscillator Initial Accuracy TJ = 25°C Voltage Stability 11V < VIN < 20V 0.85 Total Variation Line, Temperature 0.80 Sync Pin Threshold TJ = 25°C 3.8 V Clock Out Peak TJ = 25°C 4.3 V Clock Out Low TJ = 25°C 3.3 Clock Out Pulse Width RCLOCKSYNC = 3.9kΩ 30 Maximum Frequency, (Note 7) RFREQSET = 5kΩ V 100 2 nsec MHz Ramp Generator/Slope Compensation Ramp Current, Minimum ISLOPE = 10µA, VFREQSET = VREF Ramp Current, Maximum ISLOPE = 1mA, VFREQSET = VREF –11 –0.8 Ramp Valley Ramp Peak - Clamping Level –14 –0.95 mA 0 RFREQSET = 100kΩ µA V 3.8 4.1 V 2 5 µA Current Limit Input Bias VCS+ = 3V Threshold Voltage Delay to Output, (Note 8) 2.5 2.6 V UC3875/6/7/8 2.4 85 125 nsec UC1875/6/7/8, UC2875/6/7/8 85 150 nsec 4 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, –55°C < TA < 125°C for the UC1875/6/7/8, –25°C < TA < 85°C for the UC2875/6/7/8 and 0°C < TA < 70°C for the UC3875/6/7/8, VC = VIN = 12V, RFREQSET = 12kΩ, CFREQSET = 330pF, RSLOPE = 12kΩ, CRAMP = 200pF, CDELAYSET A-B = CDELAYSET C-D = 0.01µF, IDELAYSET A-B = IDELAYSET C-D = –500µA, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS –3 µA Soft-Start/Reset Delay Charge Current VSOFTSTART = 0.5V –20 –9 Discharge Current VSOFTSTART = 1V 120 230 µA 4.3 4.7 V 300 mV Restart Threshold Discharge Level Output Drivers Output Low Level Output High Level IOUT = 50mA 0.2 0.4 V IOUT = 500mA 1.2 2.6 V IOUT = –50mA 1.5 2.5 V IOUT = –500mA 1.7 2.6 V Delay Set (UC1875 and UC1876 only) Delay Set Voltage IDELAY = –500µA 2.3 2.4 2.6 V Delay Time, (Note 8) IDELAY = –250µA (Note 5) (UC3875/6/7/8, UC2875/6/7/8) 150 250 400 nsec IDELAY = –250µA (Note 5) (UC1875/6/7/8) 150 250 600 nsec Note 1: Phase shift percentage (0% = 0°, 100% = 180°) is defined as θ = 200 Φ%, where q is the phase shift, and F and T are deT fined in Figure 1. At 0% phase shift, F is the output skew. Note 2: Delay time is defined as delay = T (1/2–(duty cycle)), where T is defined in Fig. 1. Note 3: Ramp offset voltage has a temperature coefficient of about –4mV/°C. Note 4: Zero phase shift voltage has a temperature coefficient of about –2mV/°C. Note 5: Delay time can be programmed via resistors from the delay set pins to ground. Delay time ≅ IDELAY = 62 .5 • 10 – 12 sec. Where IDELAY De lay s e t voltage The recommended range for IDELAY is 25mA £ IDELAY £ 1mA R DELAY Note 6: Ramp delay to output time is defined in Fig. 2. Note 7: Not production tested at -55°C. Duty Cycle = t/T Period = T TDHL (A to C) = TDHL (B to D) = Φ Phase Shift, Output Skew & Delay Time Definitions UDG-95074 UDG-95075 Figure 1 Figure 2 5 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 PIN DESCRIPTIONS CLOCKSYNC (bi-directional clock and synchronizationpin, any bypass capacitor on the VREF pin, bypass capin): Used as an output, this pin provides a clock signal. pacitors on VIN and the ramp capacitor, on the RAMP As an input, this pin provides a synchronization point. In pin, should be connected directly to the ground plane its simplest usage, multiple devices, each with their own near the signal ground pin. local oscillator frequency, may be connected together by OUTA-OUTD (outputs A-D): The outputs are 2A tothe CLOCKSYNC pin and will synchronize on the fastest tem-pole drivers optimized for both MOSFET gates and oscillator. This pin may also be used to synchronize the level-shifting transformers. The outputs operate as pairs device to an external clock, provided the external signal with a nominal 50% duty-cycle. The A-B pair is intended is of higher frequency than the local oscillator. A resistor to drive one half-bridge in the external power stage and load may be needed on this pin to minimize the clock is syncronized with the clock waveform. The C-D pair pulse width. will drive the other half-bridge with switching phase E/AOUT (error amplifier output): This is is the gain stage for overall feedback control. Error amplifier output voltage levels below 1 volt will force 0° phase shift. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source. CS+ (current sense):The non-inverting input to the current-fault comparator whose reference is set internally to a fixed 2.5V (separate from VREF). When the voltage at this pin exceeds 2.5V the current-fault latch is set, the outputs are forced OFF and a SOFT-START cycle is initiated. If a constant voltage above 2.5V is applied to this pin the outputs are disabled from switching and held in a low state until the CS+ pin is brought below 2.5V. The outputs may begin switching at 0 degrees phase shift before the SOFTSTART pin begins to rise -- this condition will not prematurely deliver power to the load. FREQSET (oscillator frequency set pin): A resistor and a capacitor from FREQSET to GND will set the oscillator frequency. shifted with respect to the A-B outputs. PWRGND (power ground):VC should be bypassed with a ceramic capacitor from the VC pin to the section of the ground plane that is connected to PWRGND. Any required bulk reservoir capacitor should parallel this one. Power ground and signal ground may be joined at a single point to optimize noise rejection and minimize DC drops. RAMP (voltage ramp):This pin is the input to the PWM comparator. Connect a capacitor from here to GND. A voltage ramp is developed at this pin with a slope: S e ns e Voltage dV = dT R S LOPE • C R AMP Current mode control may be achieved with a minimum amount of external circuitry, in which case this pin provides slope compensation. Because of the 1.3V offset between the ramp input and the PWM comparator, the error amplifier output voltage can not exceed the effective ramp peak voltage and duty DELAYSET A-B, DELAYSET C-D (output delay control): cycle clamping is easily achievable with appropriate valThe user programmed current flowing from these pins to ues of RSLOPE and CRAMP. GND set the turn-on delay for the corresponding output SLOPE (set ramp slope/slope compensation): A resistor pair. This delay is introduced between turn-off of one from this pin to VCC will set the current used to generate switch and turn-on of another in the same leg of the the ramp. Connecting this resistor to the DC input line bridge to provide a dead time in which the resonant voltage will provide voltage feed-forward. switching of the external power switches takes place. Separate delays are provided for the two half-bridges to SOFTSTART (soft start):SOFTSTART will remain at accommodate differences in the resonant capacitor GND as long as VIN is below the UVLO threshold. SOFTSTART will be pulled up to about 4.8V by an intercharging currents. nal 9µA current source when VIN becomes valid (assumEA– (error amplifier inverting input): This is normally coning a non-fault condition). In the event of a current-fault nected to the voltage divider resistors which sense the (CS+ voltage exceeding 2.5V), SOFTSTART will be power supply output voltage level. pulled to GND and them ramp to 4.8V. If a fault occurs EA+ (error amplifier non-inverting input): This is normally during the SOFTSTART cycle, the outputs will be immeconnected to a reference voltage used for comparison diately disabled and SOFTSTART must charge fully prior with the sensed power supply output voltage level at the to resetting the fault latch. EA+ pin. For paralleled controllers, the SOFTSTART pins may be GND (signal ground):All voltages are measured with re- paralled to a single capacitor, but the charge currents will spect to GND. The timing capacitor, on the FREQSET be additive. 6 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 PIN DESCRIPTIONS (cont.) VC (output switch supply voltage):This pin supplies power to the output drivers and their associated bias circuitry. Connect VC to a stable source above 3V for normal operation, above 12V for best performance. This supply should be bypassed directly to the PWRGND pin with low ESR, low ESL capacitors. NOTE: When VIN exceeds the UVLO threshold the supply current (IIN) will jump from about 100µA to a current in excess of 20µA. If the UC1875 is not connected to a well bypassed supply, it may immediately enter UVLO again. VREF: This pin is an accurate 5V voltage reference. This output is capable of delivering about 60mA to peripheral circuitry and is internally short circuit current limited. VREF is disabled while VIN is low enough to force the chip into UVLO. The circuit is also in UVLO until VREF reaches approximately 4.75V. For best results bypass VREF with a 0.1µF, low ESR, low ESL, capacitor to the GND pin. VIN (primary chip supply voltage): This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages. Connect VIN to a stable source above 12V for normal operation. To ensure proper chip functionality, these devices will be inactive until VIN exceeds the upper undervoltage lockout threshold. This pin should by bypassed directly to the GND pin with low ESR, low ESL capacitors. APPLICATION INFORMATION Undervoltage Lockout Section When power is applied to the circuit and VIN is below the upper UVLO threshold, IIN will be below 600µA, the reference generator will be off, the fault latch is reset, the soft-start pin is discharged, and the outputs are actively held low. When VIN exceeds the upper UVLO threshold, the reference generator turns on. All else remains in the shut-down mode until the output of the reference, VREF, exceeds 4.75V. VIN 10.75V/9.25V GATE REFERENCE GENERATOR INTERNAL BIAS VREF TO S OFTS TART LOGIC GND 4.75V UDG-99136 The high frequency oscillator may be either free-running or externally synchronized. For free-running operation, the frequency is set via an ex- ternal resistor and capacitor to ground from the FREQSET pin. Simplified Oscillator Schematic UDG-95077 UDG-95079 UDG-95078 7 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 APPLICATION INFORMATION (cont.) Synchronizing The Oscillator The CLOCKSYNC pin of the oscillator may be used to synchronize multiple UC1875 devices simply by connecting the CLOCKSYNC of each UC1875 to the others: 1875/6/7/8s only UDG-95080 All ICs will sync to chip with the fastest local oscillator. R1 & RN may be needed to keep sync pulse narrow due to capacitance on line. R1 & RN may also be needed to properly terminate RSYNC line. Syncing to external TTL/CMOS UDG-95081 ICs will sync to fastest chip or TTL clock if it is higher frequency. R & RN may be needed for same reasons as above Although each UC1875/6/7/8 has a local oscillator frequency, the group of devices will synchronize to the fastest oscillator driving the CLOCKSYNC pin. This arrangement allows the synchronizing connection between ICs to be broken without any local loss of functionality. Capacitive loading on the CLOCKSYNC pin will increase the clock pulse width, and may adversely effect system performance. Therefore, a resistor to ground from the CLOCKSYNC pin is optional, but may be required to offset capacitive loading on this pin. These resistors are shown in the oscillator schematics as R1, RN. Synchronizing the device to an external clock signal may be accomplished with a minimum of external circuitry, as shown in the previous figure. 8 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 APPLICATION INFORMATION (cont.) Delay Blocks And Output Stages In each of the output stages, transistors Q3 through Q6 form a high-speed totem-pole driver which will source or sink more than one amp peak with a total delay of approximately 30 nanoseconds. To ensure a low output level prior to turn-on, transistors Q7 through Q9 form a self-biased driver to hold Q6 on prior to the supply reaching its turn-on threshold. This circuit is operable when the chip supply is zero. Q6 is also turned on and held low with a signal from the fault logic portion of the chip. UDG-95082 The delay providing the dead-time is accomplished with C1 which must discharge to VTH before the output can go high. The time is defined by the current sources, I1, which is programmed by an external resistor, RTD. The voltage on the Delay Set pins is internally regulated to 2.5V and the range of dead time control is from 50 to 200 nanoseconds. NOTE: There is no way to disable the delay circuitry, and the delay time must be programmed. Output Switch Orientation The four outputs of the UC1875/6/7/8 interface to the full bridge converter switches as shown below: UDG-95083 3 Winding Bifilar, AWG 30 Kynar Insulation 9 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 APPLICATION INFORMATION (cont.) Fault/Soft-Start The fault control circuitry provides two forms of power shutdown: ceed while the phase-shift is advanced from zero to its nominal value with the time constant of the SOFT-START capacitor. • Complete turn-off of all four output power stages. The fault logic insures that a continuous fault will institute a low frequency “hiccup” retry cycle by forcing the SOFT-START capacitor to charge through its full cycle between each restart attempt. • Clamping the phase shift command to zero. Complete turn-off is ordered for an over-current fault or a low supply voltage. When the SOFTSTART pin reaches its low threshold, switching is allowed to pro- UDG-95084 UDG-95085 10 UC1875/6/7/8 UC2875/6/7/8 UC3875/6/7/8 APPLICATIONS INFORMATION (cont.) Slope/Ramp Pins The figure below shows a voltage-mode configuration. With RSLOPE tied to a stable voltage source, the waveform on CRAMP will be a constant-slope ramp, providing conventional voltage-mode control. If RSLOPE is connected to the power supply input voltage, a variable-slope ramp will provide voltage feedforward. The ramp generator may be configured for the following control methods: • Voltage Mode • Voltage Feedforward • Current Mode • Current Mode with Slope Compensation Voltage Mode Operation 1. Simple voltage mode operation achieved by placing RSLOPE between VIN and SLOPE. 2. Voltage Feedforward achieved by placing RSLOPE between supply voltage and SLOPE pin of UC1875. RAMP VR s lope dV ≈ dT R S LOPE • C R AMP UDG-95086 For current-mode control the ramp generator may be disabled by grounding the slope pin and using the ramp pin as a direct current sense input to the PWM comparator. CONTACT INFORMATION If you should have questions or need additional information, please contact Jody Bustamante at (903) 868-6132 or [email protected]. 11 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9455501M3A ACTIVE LCCC FK 28 1 TBD 5962-9455501MRA ACTIVE CDIP J 20 1 TBD POST-PLATE Level-NC-NC-NC A42 SNPB 5962-9455501MXA OBSOLETE TO-92 LP 28 TBD Call TI Call TI 5962-9455501V3A ACTIVE LCCC FK 28 1 TBD Call TI Level-NC-NC-NC 5962-9455501VRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC Level-NC-NC-NC UC1875J ACTIVE CDIP J 20 1 TBD A42 SNPB Level-NC-NC-NC UC1875J883B ACTIVE CDIP J 20 1 TBD A42 SNPB Level-NC-NC-NC UC1875JQMLV ACTIVE CDIP J 20 TBD Call TI Call TI UC1875L ACTIVE LCCC FK 28 1 TBD POST-PLATE Level-NC-NC-NC UC1875L883B ACTIVE LCCC FK 28 1 TBD POST-PLATE Level-NC-NC-NC UC2875DWP ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2875DWPG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2875DWPTR ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2875DWPTRG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2875J ACTIVE CDIP J 20 1 TBD A42 SNPB Level-NC-NC-NC UC2875N ACTIVE PDIP N 20 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-NC-NC-NC UC2875NG4 ACTIVE PDIP N 20 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-NA-NA-NA UC2875QP ACTIVE PLCC FN 28 37 TBD Call TI UC2876N ACTIVE PDIP N 20 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-NC-NC-NC UC3875DWP ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3875DWPG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3875DWPTR ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3875DWPTRG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3875N ACTIVE PDIP N 20 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-NC-NC-NC UC3875NG4 ACTIVE PDIP N 20 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-NC-NC-NC UC3875QP ACTIVE PLCC FN 28 37 TBD Call TI Level-2-220C-1 YEAR UC3875QPTR ACTIVE PLCC FN 28 750 TBD Call TI Level-2-220C-1 YEAR UC3876N ACTIVE PDIP N 20 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-NC-NC-NC UC3877DWPTR ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 Level-2-220C-1 YEAR PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2005 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. 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