Revised November 1999 74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. The ACTQ74 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features ■ ICC reduced by 50% ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Improved latch-up immunity ■ 4 kV minimum ESD immunity ■ TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74ACTQ74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACTQ74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. Connection Diagram Pin Descriptions Pin Names Description D1 , D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010920 www.fairchildsemi.com 74ACTQ74 Quiet Series Dual D-Type March 1993 74ACTQ74 Truth Table Logic Symbols (Each Half) Inputs Outputs SD CD CP D Q L H X X H L H L X X L H X H H H H L L L H L X Q0 Q0 L L H H H H H H X Q H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock IEEE/IEC Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate ∆V/∆t DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V 125 mV/ns DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ± 50 mA per Output Pin (ICC or IGND ) −65°C to +150°C DC Latch-Up Source or Sink Current ± 300 mA Junction Temperature (TJ) PDIP 140°C DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter VCC Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 Maximum Input Leakage Current Maximum 3-STATE Leakage Current V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V VIN = VIL or VIH IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA V VIN = VIL or VIH IOL = 24 mA IOL = 24 mA (Note 2) µA VI = VCC, GND VI = VIL, VIH µA mA VI = VCC − 2.1V 5.5 75 mA VOLD = 1.65V Max 5.5 −75 mA VOHD = 3.85V Min 20.0 µA VIN = VCC or GND IOLD Minimum Dynamic IOHD Output Current (Note 2) ICC Maximum Quiescent Supply Current 5.5 Dynamic VOL V 1.5 5.5 Quiet Output Minimum Conditions ± 5.0 Maximum ICC/Input Quiet Output Maximum ± 0.5 5.5 ICCT Dynamic VOL Units Guaranteed Limits Maximum LOW Level IIN VOLV TA = −40°C to +85°C Typ IOZ VOLP TA = +25°C (V) 0.6 2.0 5.0 1.1 1.5 V 5.0 −0.6 −1.2 V VO = VCC, GND Figure 1, Figure 2 (Note 4)(Note 5) Figure 1, Figure 2 (Note 4)(Note 5) VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 1.9 2.2 V (Note 4)(Note 6) VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2 0.8 V (Note 4)(Note 6) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: PDIP package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com 74ACTQ74 Absolute Maximum Ratings(Note 1) 74ACTQ74 AC Electrical Characteristics Symbol Parameter fMAX Maximum Clock Frequency tPLH Propagation Delay tPHL CDn or SDn to Qn or Qn tPLH Propagation Delay tPHL CPn to Qn or Qn tOSLH Output to Output tOSHL Skew (Note 8) VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Min Typ 5.0 145 200 5.0 3.0 7.0 8.5 3.0 9.0 ns 5.0 3.0 6.5 8.0 3.0 8.6 ns 0.5 1.0 1.0 ns 5.0 Max Min Units (Note 7) Max 125 MHz Note 7: Voltage Range 5.0 is 5.0V ± 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements Symbol tS Parameter Setup Time, HIGH or LOW Dn to CPn tH Hold Time, HIGH or LOW Dn to CPn tW CPn or CDn or SDn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 9) Typ Guaranteed Minimum 5.0 1.0 3.0 3.0 ns 5.0 −0.5 1.5 1.5 ns 5.0 3.0 4.0 4.0 ns 5.0 −2.5 1.5 1.5 ns Pulse Width tREC Recovery Time CDn or SDn to CP Note 9: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance www.fairchildsemi.com Typ Units 4.5 pF VCC = OPEN 60.0 pF VCC = 5.0V 4 Conditions The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/V OHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition for active and enable. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds V IL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ74 FACT Noise Characteristics 74ACTQ74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 6 74ACTQ74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 7 www.fairchildsemi.com 74ACTQ74 Quiet Series Dual D-Type Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8