74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs General Description Features The LVQ125 contains four independent non-inverting buffers with 3-STATE outputs. n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75Ω Ordering Code: Order Number Package Number Package Description 74LVQ125SC M14A 14-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC 74LVQ125SJ M14D 14-Lead Small Outline Package, SOIC EIAJ Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Assignment for SOIC JEDEC and EIAJ DS011349-1 DS011349-2 Pin Descriptions Pin Names Description An, Bn Inputs On Outputs Truth Table Inputs Output An Bn L L L L H H H X Z On H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial © 1998 Fairchild Semiconductor Corporation DS011349 www.fairchildsemi.com 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs May 1998 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 3.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to to VCC + 0.5V 2.0V to 3.6V 0V to VCC 0V to VCC −40˚C to +85˚C 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteritics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ± 50 mA ± 200 mA −65˚C to +150˚C Note 2: Unused inputs must be held HIGH or LOW. They may not float. ± 100 mA DC Electrical Characteristics Symbol Parameter VCC (V) TA = +25˚C TA = −40˚C to +85˚ C Typ VIH VIL VOH Minimum High Level Input Voltage 3.0 Maximum Low Level Input Voltage 3.0 Minimum High Level Output Voltage 1.5 Units Conditions Guaranteed Limits 2.0 2.0 V VOUT = 0.1V or VCC − 0.1V 1.5 0.8 0.8 V VOUT = 0.1V or VCC − 0.1V 2.9 2.9 V IOUT = −50 µA 2.58 2.48 V VIN = VIL or VIH (Note 3) 0.1 0.1 V IOUT = 50 µA 3.0 0.36 0.44 V VIN = VIL or VIH (Note 3) 3.6 ± 0.1 ± 1.0 µA VI = VCC, GND 3.6 ± 0.25 ± 2.5 µA VI = VCC, GND 3.6 36 mA VOLD = 0.8V Min (Note 5) 3.6 −25 mA VOHD = 2.0V Min (Note 5) 40.0 µA 3.0 2.99 3.0 IOH = −12 mA VOL Maximum Low Level Output Voltage 3.0 0.002 IOL = 12 mA IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Leakage Current VI (OE) = VIL, VIH VO = VCC, GND IOLD IOHD Minimum Dynamic (Note 4) Output Current 4.0 VIN = VCC Maximum Quiescent Supply Current 3.6 VOLP Quiet Output Maximum Dynamic VOL 3.3 0.6 1.0 V (Notes 6, 7) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.6 −1.0 V (Notes 6, 7) VIHD Maximum High Level Dynamic Input Voltage 3.3 1.7 2.0 V (Notes 6, 8) VILD Maximum Low Level Dynamic Input Voltage 3.3 1.5 0.8 V (Notes 6, 8) ICC or GND Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 AC Electrical Characteristics Symbol TA = +25˚C CL = 50 pF VCC (V) Parameter Min tPLH Propagation Delay Data to Output tPHL tPZH tPZL tPHZ tPLZ 7.8 12.7 1.0 14.0 6.5 9.0 1.0 10.0 2.7 1.0 7.8 12.7 1.0 14.0 3.3 ± 0.3 1.0 6.5 9.0 1.0 10.0 2.7 1.0 7.2 14.8 1.0 16.0 3.3 ± 0.3 1.0 6.0 10.5 1.0 11.0 2.7 1.0 9.0 14.0 1.0 16.0 3.3 ± 0.3 1.0 7.5 10.0 1.0 11.0 2.7 1.0 9.0 14.0 1.0 15.0 3.3 ± 0.3 1.0 7.5 10.0 1.0 10.5 Output Disable Time Data to Output Units Max 1.0 Output Disable Time Output to Output Skew (Note 9) Min 1.0 Output Enable Time tOSLH Max 2.7 Output Enable Time tOSHL, Typ 3.3 ± 0.3 Propagation Delay Data to Output TA = −40˚C to +85˚C CL = 50 pF 2.7 1.0 9.0 14.8 1.0 16.5 3.3 ± 0.3 1.0 7.5 10.5 1.0 11.5 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open Conditions CPD (Note 10) Power Dissipation Capacitance 34 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 4 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead (0.150" Wide) Small Outline Integrated Circuit Package Number M14A 14-Lead Small Outline Package EIAJ Package Number M14D 5 www.fairchildsemi.com 74LVQ125 Low Voltage Quad Buffer with 3-STATE Outputs LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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