FAIRCHILD 7N60B

SSP7N60B/SSS7N60B
SSP7N60B/SSS7N60B
600V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supplies.
•
•
•
•
•
•
•
7.0A, 600V, RDS(on) = 1.2Ω @VGS = 10 V
Low gate charge ( typical 38 nC)
Low Crss ( typical 23 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
TO-220F package isolation = 4.0kV (Note 6)
D
G
TO-220
G DS
GD S
SSP Series
TO-220F
SSS Series
S
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
SSP7N60B
SSS7N60B
Units
V
7.0
7.0 *
A
4.4
4.4 *
A
28
28 *
A
600
- Continuous (TC = 100°C)
IDM
Drain Current
VGSS
Gate-Source Voltage
EAS
Single Pulsed Avalanche Energy
(Note 2)
IAR
Avalanche Current
(Note 1)
7.0
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
(Note 1)
14.7
5.5
-55 to +150
mJ
V/ns
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
- Pulsed
(Note 1)
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
± 30
V
420
mJ
147
1.18
48
0.38
* Drain current limited by maximum junction temperature
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case Max.
RθCS
Thermal Resistance, Case-to-Sink Typ.
0.5
--
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient Max.
62.5
62.5
°C/W
©2002 Fairchild Semiconductor Corporation
SSP7N60B
0.85
SSS7N60B
2.6
Units
°C/W
Rev. B, June 2002
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
600
--
--
V
--
0.65
--
V/°C
VDS = 600 V, VGS = 0 V
--
--
10
µA
VDS = 480 V, TC = 125°C
--
--
100
µA
Gate-Body Leakage Current, Forward
VGS = 30 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -30 V, VDS = 0 V
--
--
-100
nA
2.0
--
4.0
V
--
1.0
1.2
Ω
--
8.2
--
S
--
1380
1800
pF
--
115
150
pF
--
23
30
pF
--
30
70
ns
--
80
170
ns
--
125
260
ns
--
85
180
ns
--
38
50
nC
--
6.4
--
nC
--
15
--
nC
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 3.5 A
gFS
Forward Transconductance
VDS = 40 V, ID = 3.5 A
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 300 V, ID = 7.0 A,
RG = 25 Ω
(Note 4, 5)
VDS = 480 V, ID = 7.0 A,
VGS = 10 V
(Note 4, 5)
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
7.0
A
ISM
--
--
28
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 7.0 A
Drain-Source Diode Forward Voltage
--
--
1.4
V
trr
Reverse Recovery Time
--
415
--
ns
Qrr
Reverse Recovery Charge
--
4.6
--
µC
VGS = 0 V, IS = 7.0 A,
dIF / dt = 100 A/µs
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 15.7mH, IAS = 7.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 7.0A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
6. Only for back side in Viso = 4.0kV and t = 0.3s
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
SSP7N60B/SSS7N60B
Electrical Characteristics
SSP7N60B/SSS7N60B
Typical Characteristics
VGS
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
Top :
ID, Drain Current [A]
10
1
10
ID, Drain Current [A]
1
0
10
o
150 C
0
10
o
25 C
o
-55 C
※ Notes :
1. 250μ s Pulse Test
2. TC = 25℃
-1
10
※ Notes :
1. VDS = 40V
2. 250μ s Pulse Test
-1
10
-1
0
10
2
1
10
10
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
5
1
10
VGS = 10V
3
IDR, Reverse Drain Current [A]
RDS(ON) [Ω ],
Drain-Source On-Resistance
4
VGS = 20V
2
1
0
10
150℃
25℃
※ Notes :
1. VGS = 0V
2. 250μ s Pulse Test
※ Note : TJ = 25℃
0
-1
0
5
10
15
20
25
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
3000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
2500
12
VDS = 120V
Ciss
1500
Coss
1000
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
Crss
500
VGS, Gate-Source Voltage [V]
10
2000
Capacitance [pF]
10
ID, Drain Current [A]
VDS = 300V
8
VDS = 480V
6
4
2
※ Note : ID = 7.0 A
0
0
-1
10
0
10
1
10
0
5
10
15
20
25
30
35
40
VDS, Drain-Source Voltage [V]
QG, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
SSP7N60B/SSS7N60B
Typical Characteristics
(Continued)
1.2
3.0
RDS(ON) , (Normalized)
Drain-Source On-Resistance
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μ A
0.9
0.8
-100
-50
0
50
100
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 3.5 A
0.5
150
0.0
-100
200
-50
0
50
100
150
200
o
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
2
10
2
10
Operation in This Area
is Limited by R DS(on)
Operation in This Area
is Limited by R DS(on)
100 µs10 µs
1
10 ms
DC
0
10
-1
1 ms
10 ms
100 ms
0
DC
10
-1
10
※ Notes :
10
100 µs
1
10
1 ms
ID, Drain Current [A]
ID, Drain Current [A]
10
※ Notes :
o
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
-2
-2
10
10
0
1
10
2
10
3
10
0
10
10
1
10
2
10
3
10
VDS, Drain-Source Voltage [V]
VDS, Drain-Source Voltage [V]
Figure 9-1. Maximum Safe Operating Area
for SSP7N60B
Figure 9-2. Maximum Safe Operating Area
for SSS7N60B
8
ID, Drain Current [A]
6
4
2
0
25
50
75
100
125
150
TC, Case Temperature [℃]
Figure 10. Maximum Drain Current
vs Case Temperature
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
(Continued)
0
D = 0 .5
※ N o te s :
1 . Z θ J C (t) = 0 .8 5 ℃ /W M a x .
2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C (t)
0 .2
10
-1
0 .1
0 .0 5
PDM
0 .0 2
0 .0 1
θ JC
(t), T h e r m a l R e s p o n s e
10
SSP7N60B/SSS7N60B
Typical Characteristics
t1
Z
s in g le p u ls e
10
t2
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
10
D = 0 .5
0
0 .2
※ N o te s :
1 . Z θ J C (t) = 2 .6 ℃ /W M a x .
2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C (t)
0 .1
0 .0 5
10
-1
0 .0 2
PDM
0 .0 1
θ JC
(t), T h e rm a l R e s p o n s e
Figure 11-1. Transient Thermal Response Curve for SSP7N60B
Z
t1
t2
s in g le p u ls e
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11-2. Transient Thermal Response Curve for SSS7N60B
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
SSP7N60B/SSS7N60B
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
VDS
90%
VDD
VGS
RG
VGS
DUT
10V
10%
td(on)
tr
td(off)
t on
tf
t off
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
BVDSS
IAS
ID
RG
VDD
DUT
10V
tp
©2002 Fairchild Semiconductor Corporation
ID (t)
VDS (t)
VDD
tp
Time
Rev. B, June 2002
SSP7N60B/SSS7N60B
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
Same Type
as DUT
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
I SD
( DUT )
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
TO-220
4.50 ±0.20
2.80 ±0.10
(3.00)
+0.10
1.30 –0.05
18.95MAX.
(3.70)
ø3.60 ±0.10
15.90 ±0.20
1.30 ±0.10
(8.70)
(1.46)
9.20 ±0.20
(1.70)
9.90 ±0.20
1.52 ±0.10
0.80 ±0.10
2.54TYP
[2.54 ±0.20]
10.08 ±0.30
(1.00)
13.08 ±0.20
)
(45°
1.27 ±0.10
+0.10
0.50 –0.05
2.40 ±0.20
2.54TYP
[2.54 ±0.20]
10.00 ±0.20
Dimensions in Millimeters
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
SSP7N60B/SSS7N60B
Package Dimensions
(Continued)
3.30 ±0.10
TO-220F
10.16 ±0.20
2.54 ±0.20
ø3.18 ±0.10
(7.00)
(1.00x45°)
15.87 ±0.20
15.80 ±0.20
6.68 ±0.20
(0.70)
0.80 ±0.10
)
0°
(3
9.75 ±0.30
MAX1.47
#1
+0.10
0.50 –0.05
2.54TYP
[2.54 ±0.20]
2.76 ±0.20
2.54TYP
[2.54 ±0.20]
9.40 ±0.20
4.70 ±0.20
0.35 ±0.10
Dimensions in Millimeters
©2002 Fairchild Semiconductor Corporation
Rev. B, June 2002
SSP7N60B/SSS7N60B
Package Dimensions
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
FACT Quiet series™
FAST®
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SLIENT SWITCHER®
SMART START™
SPM™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET®
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2002 Fairchild Semiconductor Corporation
Rev. H6
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST 
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC 
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench 
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER 
SMART START™
SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET 
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H7