RFD16N03L,
RFD16N03LSM
S E M I C O N D U C T O R
16A, 30V, Avalanche Rated N-Channel Logic Level
Enhancement-Mode Power MOSFETs
December 1995
Features
Packaging
• 16A, 30V
JEDEC TO-251AA
SOURCE
DRAIN
GATE
• rDS(ON) = 0.022Ω
• Temperature Compensating PSPICE Model
DRAIN (FLANGE)
• Can be Driven Directly from CMOS, NMOS,
and TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
oC
• +175
JEDEC TO-252AA
Operating Temperature
DRAIN (FLANGE)
Description
GATE
The RFD16N03L and RFD16N03LSM are N-channel power
MOSFETs manufactured using the MegaFET process. This
process, which uses feature sizes approaching those of
LSI circuits, gives optimum utilization of silicon, resulting in
outstanding performance. They were designed for use in
applications such as switching regulators, switching converters, motor drivers and relay drivers. This performance is
accomplished through a special gate oxide design which
provides full rated conductance at gate bias in the 3V - 5V
range, thereby facilitating true on-off power control directly
from logic level (5V) integrated circuits.
SOURCE
Symbol
DRAIN
GATE
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
BRAND
RFD16N03L
TO-251AA
16N03L
RFD16N03LSM
TO-252AA
16N03L
SOURCE
NOTE: When ordering, use the entire part number. Add the suffix
9A, to obtain the TO-252AA variant in tape and reel, e.g.
RFD16N03LSM9A.
Formerly developmental type TA49030.
Absolute Maximum Ratings
TC = +25oC
Drain-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
RMS Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Power Dissipation
TC = +25o C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate above +25o C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSTG, TJ
Soldering Temperature of Leads for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
RFD16N03L,
RFD16N03LSM
30
30
±10
16
Refer to Peak Current Curve
Refer to UIS Curve
A
90
0.606
-55 to +175
260
W
W/oC
oC
oC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
Copyright
© Harris Corporation 1995
5-31
UNITS
V
V
V
File Number
4013.1
Specifications RFD16N03L, RFD16N03LSM
Electrical Specifications
TC = +25oC, Unless Otherwise Specified
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
Drain-Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
30
-
-
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
Zero Gate Voltage Drain Current
1
-
2
V
TC = +25oC
-
-
1
µA
TC = +150oC
-
-
50
µA
VGS = ±10V
-
-
100
nA
ID = 16A, VGS = 5V
-
-
0.022
Ω
VDD = 15V, ID = 16A,
RL = 0.93Ω, VGS = 5V,
RGS = 5Ω
-
-
120
ns
-
15
-
ns
tR
-
95
-
ns
tD(OFF)
-
25
-
ns
tF
-
27
-
ns
tOFF
-
-
80
ns
-
50
60
nC
-
30
36
nC
IDSS
Gate-Source Leakage Current
IGSS
On Resistance
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
tD(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDS = 30V,
VGS = 0V
Total Gate Charge
QG(TOT)
VGS = 0V to 10V
Gate Charge at 5V
QG(5)
VGS = 0V to 5V
QG(TH)
VGS = 0V to 1V
-
1.5
1.8
nC
VDS = 25V, VGS = 0V,
f = 1MHz
-
1650
-
pF
-
575
-
pF
Threshold Gate Charge
VDD = 24V,
ID = 16A,
RL = 1.5Ω
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
-
200
-
pF
Thermal Resistance Junction-to-Case
RθJC
-
-
1.65
oC/W
Thermal Resistance Junction-to-Ambient
RθJA
-
-
100
oC/W
MIN
TYP
MAX
UNITS
TO-251 and TO-252
Source-Drain Diode Specifications
PARAMETERS
SYMBOL
TEST CONDITIONS
Forward Voltage
VSD
ISD = 16A
-
-
1.5
V
Reverse Recovery Time
tRR
ISD = 16A, dISD/dt = 100A/µs
-
-
75
ns
5-32
RFD16N03L, RFD16N03LSM
Typical Performance Curves
TC = +25oC
2
500
100
100µs
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
100ms
DC
VDSS MAX = 30V
ZθJC, NORMALIZED
THERMAL RESPONSE
ID, DRAIN CURRENT (A)
1
0.2
PDM
0.1
0.1
.05
t1
t2
.02
.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
SINGLE PULSE
1
10
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
1
0.5
0.01
10-5
50
FIGURE 1. SAFE OPERATING AREA CURVE
10-4
10-3
10-2
10-1
100
t, RECTANGULAR PULSE DURATION (s)
FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL
IMPEDANCE
TC = +25oC
20
IDM, PEAK CURRENT CAPABILITY (A)
ID, DRAIN CURRENT (A)
500
15
10
5
0
25
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
VGS = 10V
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
ID, DRAIN CURRENT (A)
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS = 5V
75
VGS = 4.5V
VGS = 4V
VGS = 3.5V
VGS = 3V
0
0
1.0
2.0
3.0
4.0
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
VDD = 15V
100
25
175 - TC
150
FIGURE 4. PEAK CURRENT CAPABILITY
PULSE DURATION = 250µs, TC = +25oC
50
= I25
100
10
10-5
175
FOR TEMPERATURES
ABOVE +25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
VGS = 10V
101
5.0
100
75
+25oC
50
25
PULSE TEST
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
0
0
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
+175oC
-55oC
1.5
3.0
4.5
6.0
VGS, GATE-TO-SOURCE VOLTAGE (V)
FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS
FIGURE 5. TYPICAL SATURATION CHARACTERISTICS
5-33
7.5
RFD16N03L, RFD16N03LSM
ID = 250µA
VGS = VDS, ID = 250µA
2.0
2.0
VGS(TH), NORMALIZED GATE
THRESHOLD VOLTAGE
1.5
1.0
0.5
0.0
-80
-40
0
40
80
120
160
1.5
1.0
0.5
0.0
-80
200
-40
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED DRAIN-SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
TJ = 25oC, PULSE DURATION = 250µs
rDS(ON), ON-STATE RESISTANCE (mΩ)
rDS(ON), NORMALIZED ON RESISTANCE
PULSE DURATION = 250µs, VGS = 5V, ID = 16A
1.5
1.0
0.5
0.0
-40
0
40
80
120
160
100
ID = 32A
75
ID = 16A
ID = 8A
50
ID = 2A
25
0
2.5
200
3.0
TJ, JUNCTION TEMPERATURE (oC)
30
VDS , DRAIN-SOURCE VOLTAGE (V)
tR
200
SWITCHING TIME (ns)
5.0
4.5
FIGURE 10. TYPICAL rDS(ON) FOR VARYING CONDITIONS OF
GATE VOLTAGE AND DRAIN CURRENT
VDD = 15V, IDD = 16A, RL = 0.93Ω
tF
150
tD(ON)
100
tD(OFF)
50
5
10
20
30
40
RGS, GATE-TO-SOURCE RESISTANCE (Ω)
50
FIGURE 11. TYPICAL SWITCHING TIME AS A FUNCTION OF
GATE RESISTANCE
VDD = BVDSS
VDD = BVDSS
24
4
18
3
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
12
2
RL = 1.875Ω
IG(REF) = 0.6mA
VGS = 5V
6
0
0
0
4.0
3.5
VGS, GATE-TO-SOURCE VOLTAGE (V)
FIGURE 9. NORMALIZED rDS(ON) vs JUNCTION
TEMPERATURE
250
200
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2.0
-80
160
20
IG(REF)
IG(ACT)
t, TIME (s)
1
80
IG(REF)
VGS , GATE-SOURCE VOLTAGE (V)
BVDSS, NORMALIZED DRAIN-TO-SOURCE
BREAKDOWN VOLTAGE
Typical Performance Curves (Continued)
0
IG(ACT)
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT. REFER TO HARRIS
APPLICATION NOTES AN7254 AND AN7260
5-34
RFD16N03L, RFD16N03LSM
Typical Performance Curves (Continued)
200
VGS = 0V, f = 1MHz
IAS, AVALANCHE CURRENT (A)
2000
CISS
1500
1000
COSS
500
100
STARTING TJ = +25oC
STARTING TJ = +150oC
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV=(L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
CRSS
1
0
0
0.001
25
5
10
15
20
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 13. TYPICAL CAPACITANCE vs VOLTAGE
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
1.0
0.8
0.6
0.4
0.2
0.0
0
25
100
FIGURE 14. UNCLAMPED INDUCTIVE SWITCHING. REFER TO
HARRIS APPLICATION NOTES AN9321 AND
AN9322
1.2
POWER DISSIPATION MULTIPLIER
C, CAPACITANCE (pF)
2500
50
75
100
125
TC , CASE TEMPERATURE (oC)
150
175
FIGURE 15. NORMALIZED POWER DISSIPATION vs TEMPERATURE DERATING CURVE
5-35
RFD16N03L, RFD16N03LSM
Test Circuits and Waveforms
VDS
BVDSS
tP
VDS
L
IAS
VARY tP TO OBTAIN
VDD
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
0V
IL
tAV
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VDD
tON
tOFF
tD(ON)
RL
tD(OFF)
tF
tR
VDS
90%
VDS
90%
VGS
10%
10%
0V
RGS
90%
DUT
VGS
10%
FIGURE 18. RESISTIVE SWITCHING TEST CIRCUIT
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
5-36
RFD16N03L, RFD16N03LSM
Temperature Compensated PSPICE Model for the RFD16N03L, RFD16N03LSM
.SUBCKT RFD16N03L 2 1 3;
rev 12/12/94
DPLCAP
CA 12 8 2.55e-9
CB 15 14 2.64e-9
CIN 6 8 1.45e-9
RSCL1
RSCL2
+ 51
5
51
6
8
ESG
IT 8 17 1
9
EBREAK
- VTO +
6
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 0.14e-3
RGATE 9 20 0.89
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 10.31e-3
RVTO 18 19 RVTOMOD 1
S1A
S1B
S2A
S2B
DBODY
MOS2
MOS1
8
RIN
CIN
8
RSOURCE
7
LSOURCE
3
SOURCE
S2A
S1A
12
+
17
18
-
21
LDRAIN 2 5 1e-9
LGATE 1 9 3.4e-9
LSOURCE 3 7 3.4e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
11
16
EVTO
20 +
18 -
LGATE RGATE
ESCL
RDRAIN
+
GATE
1
DBREAK
50
-
EBREAK 11 7 17 18 33.3
1
1
1
8 1
DRAIN
2
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
EDS 14 8 5 8
EGS 13 8 6 8
ESG 6 10 6 8
EVTO 20 6 18
5
10
13
8
S1B
RBREAK
15
14
13
17
18
S2B
13
CA
RVTO
CB
+
6
8
EGS
-
14
+
5
8
EDS
IT
19
VBAT
+
-
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.583
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/176,6))}
.MODEL DBDMOD D (IS = 3.61e-13 RS = 5.06e-3 TRS1 = 3.05e-3 TRS2 = 7.57e-6 CJO = 2.16e-9 TT = 2.18e-8)
.MODEL DBKMOD D (RS = 1.66e-1 TRS1 = -2.97e-3 TRS2 = 7.57e-6)
.MODEL DPLCAPMOD D (CJO = 0.96e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.313 KP = 53.82 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.95e-4 TC2 = -1e-7)
.MODEL RDSMOD RES (TC1 = 3.92e-3 TC2 = 1.29e-5)
.MODEL RSCLMOD RES (TC1 = 2.03e-3 TC2 = 0.45e-5)
.MODEL RVTOMOD RES (TC1 = -2.27e-3 TC2 = -5.75e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.82 VOFF= -2.82)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.82 VOFF= -4.82)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.67 VOFF= 2.33)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.33 VOFF= -2.67)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
5-37