MICROCHIP MCP606-IST

MCP606/7/8/9
2.5V to 6.0V Micropower CMOS Op Amp
Features
Description
• Low Input Offset Voltage: 250 µV (maximum)
• Rail-to-Rail Output
• Low Input Bias Current: 80 pA (maximum at
+85°C)
• Low Quiescent Current: 25 µA (maximum)
• Power Supply Voltage: 2.5V to 6.0V
• Unity-Gain Stable
• Chip Select (CS) Capability: MCP608
• Industrial Temperature Range: -40°C to +85°C
• No Phase Reversal
• Available in Single, Dual and Quad Packages
The MCP606/7/8/9 family of operational amplifiers (op
amps) from Microchip Technology Inc. are unity-gain
stable with low offset voltage (250 µV, maximum).
Performance characteristics include rail-to-rail output
swing capability and low input bias current (80 pA at
+85°C, maximum). These features make this family of
op amps well suited for single-supply, precision,
high-impedance, battery-powered applications.
Typical Applications
•
•
•
•
•
Battery Power Instruments
High-Impedance Applications
Strain Gauges
Medical Instruments
Test Equipment
Package Types
SPICE Macro Models
FilterLab® Software
Mindi™ Circuit Designer & Simulator
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
V OUT = V LM + I L R
RG
5 kΩ
SEN
( RF ⁄ RG )
RF
50 kΩ
IL
To Load
(VLP)
2.5V
to
6.0V
VOUT
RSEN
10Ω
MCP606
To Load
(VLM)
Low-Side Battery Current Sensor
© 2008 Microchip Technology Inc.
MCP606
SOT-23-5
MCP606
PDIP, SOIC,TSSOP
Design Aids
•
•
•
•
•
The single is available in standard 8-lead PDIP, SOIC
and TSSOP packages, as well as in a SOT-23-5
package. The single MCP608 with Chip Select (CS) is
offered in the standard 8-lead PDIP, SOIC and TSSOP
packages. The dual MCP607 is offered in the standard
8-lead PDIP, SOIC and TSSOP packages. Finally, the
quad MCP609 is offered in the standard 14-lead PDIP,
SOIC and TSSOP packages. All devices are fully
specified from -40°C to +85°C, with power supplies
from 2.5V to 6.0V.
NC
VIN–
VIN+
VSS
1
2
3
4
8
7
6
5
NC
VDD
VOUT
NC
MCP607
PDIP, SOIC,TSSOP
VOUTA
VINA–
VINA+
VSS
1
2
3
4
8
7
6
5
VOUT 1
VSS 2
VIN+ 3
5 VDD
4 VIN–
MCP608
PDIP, SOIC,TSSOP
NC 1
VDD
VOUTB VIN– 2
VINB– VIN+ 3
VINB+ VSS 4
8
7
6
5
CS
VDD
VOUT
NC
MCP609
PDIP, SOIC,TSSOP
VOUTA
VINA–
VINA+
VDD
VINB+
VINB–
VOUTB
1
2
3
4
5
6
7
14 VOUTD
13 VIND–
12 VIND+
11 VSS
10 VINC+
9 VINC–
8 VOUTC
DS11177E-page 1
MCP606/7/8/9
1.0
ELECTRICAL
CHARACTERISTICS
VDD – VSS ........................................................................7.0V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Current at Input Pins ....................................................±2 mA
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Absolute Maximum Ratings †
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature..................................–65° C to +150° C
Maximum Junction Temperature (TJ) ........................ .+150° C
ESD Protection On All Pins (HBM; MM) .............. ≥ 3 kV; 200V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
VOS
-250
—
+250
ΔVOS/ΔTA
—
±1.8
—
PSRR
80
93
—
Input Bias Current
IB
—
1
—
pA
At Temperature
IB
—
—
80
pA
Input Offset Bias Current
IOS
—
1
—
pA
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||6
—
Ω||pF
Common Mode Input Range
VCMR
VSS – 0.3
VDD – 1.1
V
CMRR ≥ 75 dB
Common Mode Rejection Ratio
CMRR
75
91
—
dB
VDD = 5V, VCM = -0.3V to 3.9V
DC Open-Loop Gain
(Large-signal)
AOL
105
121
—
dB
RL = 25 kΩ to VL,
VOUT = 50 mV to VDD – 50 mV
DC Open-Loop Gain
(Large-signal)
AOL
100
118
—
dB
RL = 5 kΩ to VL,
VOUT = 0.1V to VDD – 0.1V
VOL, VOH
VSS + 15
—
VDD – 20
mV
RL = 25 kΩ to VL,
0.5V input overdrive
VOL, VOH
VSS + 45
—
VDD – 60
mV
RL = 5 kΩ to VL,
0.5V input overdrive
VOUT
VSS + 50
—
VDD – 50
mV
RL = 25 kΩ to VL,
AOL ≥ 105 dB
VOUT
VSS + 100
—
VDD – 100
mV
RL = 5 kΩ to VL,
AOL ≥ 100 dB
ISC
—
7
—
mA
VDD = 2.5V
ISC
—
17
—
mA
VDD = 5.5V
VDD
2.5
—
6.0
V
IQ
—
18.7
25
µA
Input Offset Voltage
Input Offset Drift with Temperature
Power Supply Rejection Ratio
µV
µV/°C TA = -40°C to +85°C
dB
Input Bias Current and Impedance
TA = +85°C
Common Mode
Open-Loop Gain
Output
Maximum Output Voltage Swing
Linear Output Voltage Range
Output Short Circuit Current
Power Supply
Supply Voltage
Quiescent Current per Amplifier
Note 1:
IO = 0
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.5V and 5.5V.
DS11177E-page 2
© 2008 Microchip Technology Inc.
MCP606/7/8/9
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
155
—
kHz
Phase Margin
PM
—
62
—
°
Slew Rate
SR
—
0.08
—
V/µs
Input Noise Voltage
Eni
—
2.8
—
µVP-P
Input Noise Voltage Density
eni
—
38
—
nV/√Hz
f = 1 kHz
Input Noise Current Density
ini
—
3
—
fA/√Hz
f = 1 kHz
G = +1 V/V
Noise
f = 0.1 Hz to 10 Hz
MCP608 CHIP SELECT CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
CS Logic Threshold, Low
VIL
CS Input Current, Low
ICSL
CS Logic Threshold, High
VIH
CS Input Current, High
ICSH
Units
Conditions
VSS
—
0.2 VDD
V
-0.1
0.01
—
µA
0.8 VDD
—
VDD
V
—
0.01
0.1
µA
CS = VDD
ISS
-2
-0.05
—
µA
CS = VDD
IO(LEAK)
—
10
—
nA
CS = VDD
CS Low to Amplifier Output Turn-on Time
tON
—
9
100
µs
CS = 0.2VDD to VOUT = 0.9 VDD/2,
G = +1 V/V, RL = 1 kΩ to VSS
CS High to Amplifier Output Hi-Z
tOFF
—
0.1
—
µs
CS = 0.8VDD to VOUT = 0.1 VDD/2,
G = +1 V/V, RL = 1 kΩ to VSS
VHYST
—
0.6
—
V
VDD = 5.0V
CS Low Specifications
CS = 0.2VDD
CS High Specifications
CS Input High, GND Current
Amplifier Output Leakage, CS High
CS Dynamic Specifications
CS Hysteresis
VIH
VIL
CS
tOFF
tON
VOUT
Hi-Z
ISS
-50 nA
(typical)
ICS
-50 nA
(typical)
Hi-Z
-18.7 µA
(typical)
-50 nA
(typical)
-50 nA
(typical)
FIGURE 1-1:
Timing Diagram for the CS
Pin on the MCP608.
© 2008 Microchip Technology Inc.
DS11177E-page 3
MCP606/7/8/9
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SOT23
θJA
—
256
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-TSSOP
θJA
—
124
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note 1
Thermal Package Resistances
Note 1:
1.1
The MCP606/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the
Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5 “Supply Bypass”.
VDD
VIN
RN
0.1 µF 1 µF
VOUT
MCP60X
CL
VDD/2 RG
RL
RF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD
VDD/2
RN
0.1 µF 1 µF
VOUT
MCP60X
CL
VIN
RG
RL
RF
VL
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
DS11177E-page 4
© 2008 Microchip Technology Inc.
MCP606/7/8/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
16%
14%
12%
Percentage of Occurances
16%
1200 Samples
VDD = 5.5V
10%
8%
6%
4%
2%
250
200
150
100
50
0
-50
-100
-150
-200
0%
-250
Percentage of Occurances ( )
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
14%
206 Samples
VDD = 5.5V
12%
10%
8%
6%
4%
2%
0%
-8
-6
Input Offset Voltage (µV)
14%
12%
Input Offset Voltage at
18%
1200 Samples
VDD = 2.5V
10%
8%
6%
4%
2%
250
200
150
100
50
0
-50
-100
-150
-200
0%
16%
14%
10%
8%
6%
4%
2%
0%
-8
-6
-4
-2
0
2
4
6
Input Offset Voltage Drift (µV/°C)
8
FIGURE 2-5:
Input Offset Voltage Drift
Magnitude at VDD = 2.5V.
24
TA = +85°C
TA = +25°C
TA = -40°C
Quiescent Current
per Amplifier (µA)
Quiescent Current
per Amplifier (µA)
22
20
18
16
14
12
10
8
6
4
2
0
Input Offset Voltage at
206 Samples
VDD = 2.5V
12%
Input Offset Voltage (µV)
FIGURE 2-2:
VDD = 2.5V.
8
FIGURE 2-4:
Input Offset Voltage Drift
Magnitude at VDD = 5.5V.
Percentage of Occurances
16%
-250
Percentage of Occurances ( )
FIGURE 2-1:
VDD = 5.5V.
-4
-2
0
2
4
6
Input Offset Voltage Drift (µV/°C)
22
VDD = 5.5V
20
18
16
VDD = 2.5V
14
12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-3:
Quiescent Current vs.
Power Supply Voltage.
© 2008 Microchip Technology Inc.
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-6:
Quiescent Current vs.
Ambient Temperature.
DS11177E-page 5
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
120
Input Offset Voltage (µV)
VDD =2.5V
VDD = 5.5V
300
200
100
Representative Part
20
0
FIGURE 2-10:
Input Offset Voltage vs.
Common Mode Input Voltage.
0
Gain
60
-45
Phase
40
-90
20
-135
0
-180
-20
0.01 0.1
FIGURE 2-8:
vs. Frequency.
80
40
60
30
40
20
20
10
VDD = 5.0V
-50
-25
0
25
50
75
0
100
FIGURE 2-11:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
Input Noise Voltage Density
(nV/√Hz)
Channel to Channel
Separation (dB)
140
130
120
110
100
90
DS11177E-page 6
50
Ambient Temperature (°C)
Open-Loop Gain and Phase
FIGURE 2-9:
Channel-to-Channel
Separation (MCP607 and MCP609 only).
60
Phase Margin
100
10 100 1k 10k 100k 1M
Frequency (Hz)
Referred to Input
80
100
1k
10k
1.E+02
1.E+03
1.E+04
Frequency (Hz)
70
GBWP
120
0
-225
1
80
140
Phase Margin (°)
80
45
160
Gain Bandwidth Product
(kHz)
100
90
Open-Loop Phase (°)
Open-Loop Gain (dB)
RL = 25 kΩ
5.0
Common Mode Input Voltage (V)
FIGURE 2-7:
Input Offset Voltage vs.
Ambient Temperature.
120
4.5
100
4.0
75
3.5
50
3.0
25
Ambient Temperature (°C)
2.5
-20
2.0
0
40
1.5
-25
60
1.0
-50
TA = +85°C
TA = +25°C
TA = -40°C
80
0.5
0
VDD = 5.5V
100
0.0
400
-0.5
Input Offset Voltage (µV)
500
100k
1.E+05
1000
100
10
1
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k
0.1 1.E+00
1.E-01
1.E+01
Frequency (Hz)
FIGURE 2-12:
vs. Frequency.
Input Noise Voltage Density
© 2008 Microchip Technology Inc.
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
60
VDD = 5.5V
VCM = VDD
Input Bias and Offset
Currents
(pA)
Input Bias and Offset
Currents
(pA)
100
10
IB
1
| IOS |
0.1
40
20
10
IOS
0
-10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Ambient Temperature (°C)
FIGURE 2-13:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-16:
Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
135
DC Open-Loop Gain (dB)
150
130
125
120
VDD = 5.5V
115
110
VDD = 2.5V
105
1k
10k
1.E+03
1.E+04
Load Resistance (Ω)
FIGURE 2-14:
Load Resistance.
130
120
110
100
80
CMRR
60
Power Supply Voltage (V)
FIGURE 2-17:
DC Open-Loop Gain vs.
Power Supply Voltage.
100
PSRRPSRR+
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
100k
1.E+05
DC Open-Loop Gain vs.
120
40
20
0
0.1
1.E-01
RL = 25 kΩ
140
90
100
100
1.E+02
CMRR and PSRR (dB)
DC Open-Loop Gain (dB)
IB
30
25 30 35 40 45 50 55 60 65 70 75 80 85
CMRR and PSRR (dB)
TA = 85°C
VDD = 5.5V
50
95
PSRR
90
CMRR
85
80
75
1
1.E+00
FIGURE 2-15:
Frequency.
10
100
1.E+01
1.E+02
Frequency (Hz)
1k
1.E+03
CMRR, PSRR vs.
© 2008 Microchip Technology Inc.
10k
1.E+04
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-18:
Temperature.
CMRR, PSRR vs. Ambient
DS11177E-page 7
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
40
VDD = 2.5V
100
VDD = 5.5V
VDD - VOH
VOL - VSS
10
Output Voltage Headroom
(mV)
Output Voltage Headroom
(mV)
1000
1
1
10
Output Current (mA)
30
VDD - VOH
25
VDD = 5.5V
20
15
VDD = 2.5V
10
VOL - VSS
5
100
FIGURE 2-19:
Output Voltage Headroom
vs. Output Current Magnitude.
-50
VDD = 2.5V
1
0.1
100
1.E+02
1k
10k
1.E+03
1.E+04
Frequency (Hz)
100k
1.E+05
FIGURE 2-20:
Maximum Output Voltage
Swing vs. Frequency.
0.10
Low to High
0.08
High to Low
0.06
0.04
0.02
0.00
-50
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-21:
Temperature.
DS11177E-page 8
5
Slew Rate vs. Ambient
100
0
25
50
75
Ambient Temperature (°C)
100
G = +2 V/V
VDD = 5.0V
4
3
2
VIN
1
VOUT
0
-1
Time (100 µs/div)
FIGURE 2-23:
The MCP606/7/8/9 Show
No Phase Reversal.
Output Short Circuit Current
Magnitude (mA)
0.12
Input and Output Voltages (V)
6
VDD = 5.5V
-25
FIGURE 2-22:
Output Voltage Headroom
vs. Ambient Temperature at RL = 5 kΩ.
10
Maximum Output Voltage
Swing (V)
RL = 5 k8
0
0.1
Slew Rate (V/µs)
35
25
+ISC , VDD = 5.5V
| -ISC |, VDD = 5.5V
20
15
10
5
+ISC , VDD = 2.5V
| -ISC |, VDD = 2.5V
0
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-24:
Output Short Circuit Current
Magnitude vs. Ambient Temperature.
© 2008 Microchip Technology Inc.
MCP606/7/8/9
5.0
4.5
4.0
5.0
VDD = 5.0V
4.5
Output Voltage (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.0V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Time (50 µs/div)
Time (50 µs/div)
FIGURE 2-25:
Pulse Response.
Large-signal, Non-inverting
FIGURE 2-28:
Pulse Response.
VDD = 5.0V
Output Voltage (20 mV/div)
Output Voltage (20 mV/div)
RL = 25 kΩ
Time (50 µs/div)
Small-signal, Non-inverting
3.5
3.0
Time (50 µs/div)
Amplifier Output Active
1.5
CS Input
High to Low
CS Input
Low to High
1.0
0.5
Hysteresis
0.0
Amplifier Output Hi-Z
-0.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CS Input Voltage (V)
FIGURE 2-27:
(MCP608 only).
Chip Select (CS) Hysteresis
© 2008 Microchip Technology Inc.
5.0
VDD = 5.0V
2.5
2.0
FIGURE 2-29:
Response.
Small-signal, Inverting Pulse
15
G = +1 V/V
RL = 1 kΩ to VSS
4.5
Output Voltage (V)
FIGURE 2-26:
Pulse Response.
Internal CS Switch Output (V)
Large-signal, Inverting
4.0
10
CS
3.5
3.0
-10
2.0
-15
1.5
1.0
0.5
0
-5
Output Enabled
2.5
5
-20
VOUT
Output
Hi-Z
Output
Hi-Z
0.0
Chip Select Voltage (V)
Output Voltge (V)
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
-25
-30
-35
Time (5 µs/div)
FIGURE 2-30:
Amplifier Output Response
Times vs. Chip Select (CS) Pulse (MCP608
only).
DS11177E-page 9
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
Input Current Magnitude (A)
1.E-02
10m
1.E-03
1m
1.E-04
100µ
1.E-05
10µ
1.E-06
1µ
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-31:
Measured Input Current vs.
Input Voltage (below VSS).
DS11177E-page 10
© 2008 Microchip Technology Inc.
MCP606/7/8/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE.
MCP606
MCP607
MCP608
MCP609
Symbol
1
1
6
1
VOUT, VOUTA
Output (op amp A)
2
4
2
2
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
3
3
3
VIN+, VINA+
Non-inverting Input (op amp A)
7
5
4
7
4
VDD
—
—
5
—
5
VINB+
Non-inverting Input (op amp B)
—
—
6
—
6
VINB–
Inverting Input (op amp B)
—
—
7
—
7
VOUTB
Output (op amp B)
—
—
—
—
8
VOUTC
Output (op amp B)
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
10
VINC+
Non-inverting Input (op amp C)
PDIP, SOIC,
TSSOP
SOT-23-5
6
3.1
Negative Power Supply
4
2
8
4
11
VSS
—
—
—
12
VIND+
Non-inverting Input (op amp D)
—
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
—
14
VOUTD
Output (op amp D)
—
—
—
8
—
CS
Chip Select
1, 5, 8
—
—
1, 5
—
NC
No Internal Connection
Analog Outputs
Analog Inputs
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.3
Positive Power Supply
—
The output pins are low-impedance voltage sources.
3.2
Description
Chip Select Digital Input
The Chip Select (CS) pin is a Schmitt-triggered, CMOS
logic input. It is used to place the MCP608 op amp in a
Low-power mode, with the output(s) in a Hi-Z state.
© 2008 Microchip Technology Inc.
3.4
Power Supply Pins
The positive power supply pin (VDD) is 2.5V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the output pins are at voltages
between VSS and VDD; while the input pins are at
voltages between VSS – 0.3V and VDD + 0.3V.
Typically, these parts are used in a single-supply
(positive) configuration. In this case, VSS is connected
to ground and VDD is connected to the supply. VDD will
need bypass capacitors .
DS11177E-page 11
MCP606/7/8/9
4.0
APPLICATIONS INFORMATION
The MCP606/7/8/9 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process
These op amps are unity-gain stable and suitable for a
wide range of general purpose applications.
4.1
VDD
D1
R1
Rail-to-Rail Inputs
4.1.1
PHASE REVERSAL
R2
R3
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
Input
Stage
Bond V –
IN
Pad
VSS Bond
Pad
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
DS11177E-page 12
FIGURE 4-2:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-31. Applications that are
high impedance may need to limit the useable voltage
range.
VDD Bond
Pad
VIN+ Bond
Pad
MCP60X
V2
The MCP606/7/8/9 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-23 shows the input voltage exceeding the supply voltage without any phase reversal.
4.1.2
D2
V1
4.1.3
NORMAL OPERATION
The input stage of the MCP606/7/8/9 op amps use a
PMOS input stage. It operates at low common mode
input voltage (VCM), including ground. WIth this
topology, the device operates with VCM up to VDD –1.1V
and 0.3V below VSS.
Figure 4-3 shows a unity gain buffer. Since VOUT is the
same voltage as the inverting input, VOUT must be kept
below VDD–1.2V for correct operation.
VIN
+
MCP60X
–
VOUT
FIGURE 4-3:
Unity Gain Buffer has a
Limited VOUT Range.
© 2008 Microchip Technology Inc.
MCP606/7/8/9
4.2
Rail-to-Rail Output
10k
The second specification that describes the output-swing capability of these amplifiers (Linear Output
Voltage Range) defines the maximum output swing that
can be achieved while the amplifier still operates in its
linear region. To verify linear operation in this range, the
large-signal DC Open-Loop Gain (AOL) is measured at
points inside the supply rails. The measurement must
meet the specified AOL conditions in the specification
table.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
RISO
MCP60X
VIN
1k
1000
GN = +1
GN = +2
GN ≥ +4
100
10p
100
10
100
1000
10000
100p
1n
10n
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and simulations with the MCP606/7/8/9 SPICE macro model are
helpful.
4.4
MCP608 Chip Select
The MCP608 is a single op amp with Chip Select (CS).
When CS is pulled high, the supply current drops to
50 nA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 MΩ (typical)
pull-down resistor connected to VSS, so it will go low if
the CS pins is left floating. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
4.5
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other nearby analog parts.
VOUT
CL
FIGURE 4-4:
Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
© 2008 Microchip Technology Inc.
Recommended R ISO (Ω)
10000
There are two specifications that describe the
output-swing capability of the MCP606/7/8/9 family of
op amps. The first specification (Maximum Output
Voltage Swing) defines the absolute maximum swing
that can be achieved under the specified load
conditions. For instance, the output voltage swings to
within 15 mV of the negative rail with a 25 kΩ load to
VDD/2. Figure 2-23 shows how the output voltage is
limited when the input goes beyond the linear region of
operation.
4.6
Unused Op Amps
An unused op amp in a quad package (MCP609)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
DS11177E-page 13
MCP606/7/8/9
1.
¼ MCP604 (A)
¼ MCP604 (B)
VDD
R1
VDD
VDD
VREF
R2
2.
R2
V REF = V DD ⋅ -----------------R1 + R2
FIGURE 4-6:
4.7
Unused Op Amps.
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP606/7/8/9 family’s bias current at 25°C (1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in Figure 4-7.
VIN-
VIN+
VSS
Non-inverting Gain and Unity-gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
4.8
Application Circuits
4.8.1
LOW-SIDE BATTERY CURRENT
SENSOR
The MCP606/7/8/9 op amps can be used to sense the
load current on the low-side of a battery using the
circuit in Figure 4-8. In this circuit, the current from the
power supply (minus the current required to power the
MCP606) flows through a sense resistor (RSEN), which
converts it to voltage. This is gained by the the amplifier
and resistors, RG and RF . Since the non-inverting input
of the amplifier is at the load’s negative supply (VLM),
the gain from RSEN to VOUT is RF/RG .
V OUT = V LM + I L R
SEN
( RF ⁄ RG )
IL
RG
5 kΩ
Guard Ring
FIGURE 4-7:
for Inverting Gain.
RF
50 kΩ
2.5V
to
6.0V
VOUT
RSEN
10Ω
Example Guard Ring Layout
FIGURE 4-8:
Sensor.
To Load
(VLP)
MCP606
To Load
(VLM)
Low Side Battery Current
Since the input bias current and input offset voltage of
the MCP606 are low, and the input is capable of swinging below ground, there is very little error generated by
the amplifier. The quiescent current is very low, which
helps conserve battery power. The rail-to-rail output
makes it possible to read very low currents.
DS11177E-page 14
© 2008 Microchip Technology Inc.
MCP606/7/8/9
4.8.2
PHOTODIODE AMPLIFIERS
Sensors that produce an output current and have high
output impedance can be connected to a transimpedance amplifier. The transimpedance amplifier converts
the current into voltage. Photodiodes are one sensor
that produce an output current.
The key op amp characteristics that are needed for
these circuits are: low input offset voltage, low input
bias current, high input impedance and an input
common mode range that includes ground. The low
input offset voltage and low input bias current support
a very low voltage drop across the photodiode; this
gives the best photodiode linearity. Since the
photodiode is biased at ground, the op amp’s input
needs to function well both above and below ground.
4.8.2.1
operate at a much higher speed. This reverse bias also
increases the dark current and current noise, however.
Resistor R2 converts the current into voltage. Capacitor
C2 limits the bandwidth and helps stabilize the circuit
when D1’s junction capacitance is large.
VB < 0
V OUT = I D1 R 2
C2
R2
VOUT
ID1
VDD
Light
Photo-Voltaic Mode
D1
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D1) biased in the Photo-voltaic mode (0V
across D1), which is used for precision photodiode
sensing.
As light impinges on D1, charge is generated, causing
a current to flow in the reverse bias direction of D1. The
op amp’s negative feedback forces the voltage across
the D1 to be nearly 0V. Resistor R2 converts the current
into voltage. Capacitor C2 limits the bandwidth and
helps stabilize the circuit when D1’s junction
capacitance is large.
V OUT = I D1 R
VB
FIGURE 4-10:
Photodiode (in
Photo-conductive mode) and Transimpedance
Amplifier.
4.8.3
2
R2
VOUT
ID1
2R ⎞
R
⎛
VOUT = ( V 1 – V 2 ) ⎜1 + ------1 + ---------1- ⎟ + V REF
R
⎝
2 RG ⎠
VDD
D1
TWO OP AMP INSTRUMENTATION
AMPLIFIER
The two op amp instrumentation amplifier shown in
Figure 4-11 serves the function of taking the difference
of two input voltages, level-shifting it and gaining it to
the output. This configuration is best suited for higher
gains (i.e., gain > 3 V/V). The reference voltage (VREF)
is typically at mid-supply (VDD/2) in a single-supply
environment.
C2
Light
MCP606
MCP606
RG
R1
R2
R2
R1
VREF
FIGURE 4-9:
Photodiode (in Photo-voltaic
mode) and Transimpedance Amplifier.
4.8.2.2
Photo-Conductive Mode
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D1) biased in the Photo-conductive mode
(D1 is reverse biased), which is used for high-speed
applications.
As light impinges on D1, charge is generated, causing
a current to flow in the reverse bias direction of D1.
Placing a negative bias on D1 significantly reduces its
junction capacitance, which allows the circuit to
© 2008 Microchip Technology Inc.
V2
VOUT
½
MCP607
½
MCP607
V1
FIGURE 4-11:
Amplifier.
Two op amp Instrumentation
The key specifications that make the MCP606/7/8/9
family appropriate for this application circuit are low
input bias current, low offset voltage and high common-mode rejection.
DS11177E-page 15
MCP606/7/8/9
4.8.4
THREE OP AMP
INSTRUMENTATION AMPLIFIER
4.8.5
PRECISION GAIN WITH GOOD
LOAD ISOLATION
A classic, three op amp instrumentation amplifier is
illustrated in Figure 4-12. The two input op amps provide differential signal gain and a common mode gain
of +1. The output op amp is a difference amplifier,
which converts its input signal from differential to a single ended output; it rejects common mode signals at its
input. The gain of this circuit is simply adjusted with one
resistor (RG). The reference voltage (VREF) is typically
referenced to mid-supply (VDD/2) in single-supply
applications.
In Figure 4-13, the MCP606 op amps, R1 and R2
provide a high gain to the input signal (VIN). The
MCP606’s low offset voltage makes this an accurate
circuit.
2R ⎞ ⎛ R 4⎞
⎛
VOUT = ( V 1 – V 2 ) ⎜1 + ---------2 ⎟ ⎜ ------⎟ + V REF
R G ⎠ ⎝ R 3⎠
⎝
VOUT = V IN (1 + R 2 ⁄ R 1 )
V2
The MCP601 is configured as a unity-gain buffer. It
isolates the MCP606’s output from the load, increasing
the high-gain stage’s precision. Since the MCP601 has
a higher output current, with the two amplifiers being
housed in separate packages, there is minimal change
in the MCP606’s offset voltage due to loading effect.
MCP606
VIN
½
MCP607
MCP601
VOUT
R3
R4
VOUT
R2
RG
FIGURE 4-13:
Load Isolation.
MCP606
R2
R1
R2
Precision Gain with Good
VREF
R3
V1
R4
½
MCP607
FIGURE 4-12:
Three op amp
Instrumentation Amplifier.
DS11177E-page 16
© 2008 Microchip Technology Inc.
MCP606/7/8/9
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP606/7/8/9 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP606/7/8/9
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
5.4
5.5
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board
5.6
Application Notes
The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
© 2008 Microchip Technology Inc.
DS11177E-page 17
MCP606/7/8/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SOT-23 (MCP606)
XXNN
SB25
8-Lead PDIP (300 mil)
MCP606
I/P256
0722
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
OR
MCP606I
SN e3 0810
256
Example:
MCP606
I/SN0722
256
606
YYWW
I810
NNN
256
e3
DS11177E-page 18
MCP606
I/P e3256
0810
XXXX
Legend: XX...X
Y
YY
WW
NNN
Note:
OR
Example:
8-Lead TSSOP
*
Example:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
MCP606/7/8/9
Package Marking Information (Continued)
Example:
14-Lead PDIP (300 mil) (MCP609)
MCP609-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
0722256
MCP609
I/P e3
0810256
OR
14-Lead SOIC (150 mil) (MCP609)
Example:
MCP609ISL
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0722256
MCP609
e3
I/SL^^
0810256
OR
14-Lead TSSOP (MCP609)
Example:
XXXXXXXX
YYWW
609IST
0545
NNN
256
© 2008 Microchip Technology Inc.
DS11177E-page 19
MCP606/7/8/9
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DS11177E-page 22
© 2008 Microchip Technology Inc.
MCP606/7/8/9
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DS11177E-page 23
MCP606/7/8/9
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DS11177E-page 25
MCP606/7/8/9
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DS11177E-page 26
© 2008 Microchip Technology Inc.
MCP606/7/8/9
APPENDIX A:
REVISION HISTORY
Revision E (March 2008)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
Increased maximum operating VDD.
Added test circuits.
Updated performance curves.
Added Figure 2-31.
Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”, ad Section 4.1.3 “Normal Operation”.
Updated Section 5.0 “Design AIDS”
Updated Section 6.0 “Packaging Information”. Updated package outline drawings.
Revision D (February 2005)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
Added Section 3.0 “Pin Descriptions”.
Updated Section 4.0 “Applications Information”.
Added Section 4.3 “Capacitive Loads”
Updated Section 5.0 “Design AIDS” to include
FilterLab® and to point to the latest SPICE
macro model.
Corrected and updated Section 6.0 “Packaging
Information”.
Added Appendix A: “Revision History”.
Revision C (January 2001)
• Undocumented changes
Revision B (May 2000)
• Undocumented changes
Revision A (January 2000)
• Original Release of this Document.
© 2008 Microchip Technology Inc.
DS11177E-page 25
MCP606/7/8/9
NOTES:
DS11177E-page 26
© 2008 Microchip Technology Inc.
MCP606/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
c)
Device
MCP606 = Single Op Amp
MCP606T = Single Op Amp
Tape and Reel (SOIC, TSSOP)
MCP607 = Dual Op Amp
MCP607T = Dual Op Amp
Tape and Reel (SOIC, TSSOP)
MCP608 = Single Op Amp with CS
MCP608T = Single Op Amp with CS
Tape and Reel (SOIC, TSSOP)
MCP609 = Quad Op Amp
MCP609T = Quad Op Amp
Tape and Reel (SOIC, TSSOP)
Temperature Range
I
Package
OT
P
SN
SL
ST
=
-40°C to +85°C
=
=
=
=
=
Plastic SOT-23, 5-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (3.90 mm body), 8-lead
Plastic SOIC (3.90 mm body), 14-lead
Plastic TSSOP, 8-lead, 14-lead
d)
e)
a)
b)
c)
a)
Industrial Temperature,
8LD PDIP package.
MCP606-I/SN: Industrial Temperature,
8LD SOIC package.
MCP606T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
MCP606-I/ST:
Industrial Temperature,
8LD TSSOP package.
MCP606T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23 package.
MCP607-I/P:
Industrial Temperature,
8LD PDIP package.
MCP607T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
b)
Industrial Temperature,
8LD SOIC package.
MCP608T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
a)
MCP609-I/P:
b)
c)
© 2008 Microchip Technology Inc.
MCP606-I/P:
MCP608-I/SN:
Industrial Temperature,
14LD PDIP package.
MCP609T-I/SL: Tape and Reel,
Industrial Temperature,
14LD SOIC package.
DS11177E-page 27
MCP606/7/8/9
NOTES:
DS11177E-page 28
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS11177E-page 29
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS11177E-page 30
© 2008 Microchip Technology Inc.