NTLTD7900ZR2 Power MOSFET 9 A, 20 V, Logic Level, N--Channel Micro8™ Leadless This advanced Power MOSFET contains monolithic back--to--back Zener diodes. These Zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. This device is designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are DC--DC converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. http://onsemi.com 9 AMPERES 20 VOLTS RDS(on) = 26 mΩ (VGS = 4.5 V, ID = 6.5 A) RDS(on) = 31 mΩ (VGS = 2.5 V, ID = 5.8 A) Features • Pb--Free Package is Available D Applications • Zener Protected Gates Provide Electrostatic Discharge Protection • Designed to Withstand 4000 V Human Body Model • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life • Logic Level Gate Drive -- Can be Driven by Logic ICs • Micro8 Leadless Surface Mount Package -- Saves Board Space • IDSS Specified at Elevated Temperature 2.4 kΩ 2.4 kΩ G1 G2 Symbol Steady State 10 Sec N--Channel MARKING DIAGRAM Unit Drain--to--Source Voltage VDSS 20 V Gate--to--Source Voltage VGS ±12 V Continuous Drain Current (Note 1) TA = 25°C TA = 85°C Pulsed Drain Current (tp ≤ 10 ms) ID IDM Continuous Source--Diode Conduction (Note 1) Is Total Power Dissipation (Note 1) TA = 25°C TA = 85°C PD Operating Junction and Storage Temperature Range TJ, Tstg Thermal Resistance (Note 1) Junction--to--Ambient 9.0 6.4 RθJA A 6.0 4.3 30 A 2.9 1.4 3.2 1.7 1.5 0.79 A 38 1 1 Micro8 LEADLESS CASE 846C A Y WW G W --55 to 150 °C 82 S2 S1 N--Channel MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating D °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to 1″ x 1″ FR--4 board. 7900 AYWW G = Assembly Location = Year = Work Week = Pb--Free Package PIN ASSIGNMENT Drain 8 Drain 1 Source 1 7 2 Gate 1 Drain 6 3 Source 2 Drain 5 4 Gate 2 Drain (Bottom View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2009 October, 2009 -- Rev. 7 1 Publication Order Number: NTLTD7900ZR2/D NTLTD7900ZR2 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 20 24 -- --- --- 1.0 20 --- --- 1.0 500 0.4 0.67 1.0 --- 21 27 26 31 Ciss -- 7.4 15 Coss -- 237 400 Crss -- 4.1 10 pF td(on) -- 0.55 1.0 ms tr -- 1.17 2.0 td(off) -- 1.87 3.0 tf -- 4.8 7.0 ms QT -- 12 18 nC Q1 -- 0.7 -- Q2 -- 3.7 -- nC VSD --- 0.69 0.62 0.8 -- Vdc OFF CHARACTERISTICS Drain--to--Source Breakdown Voltage (Note 2) (VGS = 0 Vdc, ID = 250 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 85°C) IDSS Gate--Body Leakage Current (VGS = 4.5 Vdc, VDS = 0 Vdc) (VGS = 12 Vdc, VDS = 0 Vdc) IGSS Vdc mAdc mAdc mAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (Note 2) (VDS = VGS, ID = 250 mAdc) VGS(th) Static Drain--to--Source On--Resistance (Note 2) (VGS = 4.5 Vdc, ID = 6.5 Adc) (VGS = 2.5 Vdc, ID = 5.8 Adc) RDS(on) Vdc mΩ DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 16 Vdc, VGS = 0 V, f = 1.0 MHz) Output Capacitance Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3) Turn--On Delay Time Rise Time Turn--Off Delay Time (VGS = 4.5 Vdc, VDD = 10 Vdc, ID = 1.0 Adc, RG = 9.1 Ω) (Note 2) Fall Time Gate Charge Gate Charge (VGS = 4.5 Vdc, ID = 6.5 Adc, VDS = 10 Vdc) (Note 2) SOURCE--DRAIN DIODE CHARACTERISTICS Forward On--Voltage (IS = 1.0 Adc, VGS = 0 Vdc) IS = 1.0 Adc, VGS = 0 Vdc, TJ = 85°C) (Note 2) 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTLTD7900ZR2 TYPICAL ELECTRICAL CHARACTERISTICS 10,000 IGSS, GATE--CURRENT (mA) IGSS, GATE--CURRENT (mA) 8 6 4 2 0 0 3 6 9 12 15 VGS, GATE--TO--SOURCE VOLTAGE (V) 1000 100 1 TJ = 25°C 0.1 0.01 18 TJ = 150°C 10 0 Figure 1. Gate--Current versus Gate--Source Voltage ID, DRAIN CURRENT (A) 18 Figure 2. Gate--Current versus Gate--Source Voltage 2.2 V 2.8 V 3.5 V 24 2.0 V 4.5 V 10 V 1.8 V 12 1.6 V 1.4 V 6 24 18 12 TC = 25°C 6 VGS = 1.2 V 0 0 2 15 30 2.4 V 4 6 8 TC = 125°C 0 10 0.4 0 0.8 TC = --55°C 1.2 1.6 2.0 VDS, DRAIN--TO--SOURCE VOLTAGE (V) VGS, GATE--TO--SOURCE VOLTAGE (V) Figure 3. On--Region Characteristics Figure 4. Transfer Characteristics RDS(on), DRAIN--TO--SOURCE RESISTANCE (Ω) ID, DRAIN CURRENT (A) 30 3 6 9 12 VGS, GATE--TO--SOURCE VOLTAGE (V) 0.06 0.05 0.04 VGS = 2.5 V 0.03 0.02 VGS = 4.5 V 0.01 0 0 6 12 18 24 ID, DRAIN CURRENT (A) Figure 5. On--Resistance versus Drain Current http://onsemi.com 3 30 2.4 NTLTD7900ZR2 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain--gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off--state condition when calculating td(on) and is read at a voltage corresponding to the on--state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG -- VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn--on and turn--off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG -- VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1200 TJ = 25°C VGS = 0 V C, CAPACITANCE (pF) 1000 800 Coss 600 400 200 0 Ciss and Crss are below 10 pF 0 5 10 15 GATE--TO--SOURCE OR DRAIN--TO--SOURCE VOLTAGE (V) Figure 6. Capacitance Variation http://onsemi.com 4 20 5 10,000 TJ = 25°C ID = 6.5 A 4 tf td(off) t, TIME (ns) VGS, GATE--TO--SOURCE VOLTAGE (V) NTLTD7900ZR2 3 tr 1000 2 td(on) VDS = 10 V ID = 6.5 A VGS = 4.5 V 1 0 0 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC) 12 100 14 1 Figure 7. Gate--to--Source 1.8 RDS(on), DRAIN--TO--SOURCE RESISTANCE (NORMALIZED) IS, SOURCE CURRENT (A) TJ = 25°C VGS = 0 V 1 TJ = 150°C TJ = 25°C 0.2 0 0.4 0.6 0.8 ID = 9 A VGS = 4.5 V 1.6 1.4 1.2 1.0 0.8 0.6 --50 1 --25 0 25 50 75 125 100 150 TJ, JUNCTION TEMPERATURE (°C) VSD, SOURCE--TO--DRAIN VOLTAGE (V) Figure 10. On--Resistance Variation with Temperature 0.2 RDS(on), DRAIN--TO--SOURCE RESISTANCE (Ω) Figure 9. Diode Forward Voltage versus Current VGS(th), THRESHOLD VARIANCE (V) 100 Figure 8. Resistive Switching Time Variation versus Gate Resistance 10 0.1 10 RG, GATE RESISTANCE (Ω) 0.040 ID = 250 mA 0.035 0.1 TJ = 125°C 0.030 0 0.025 --0.1 TJ = 25°C 0.020 TJ = --55°C 0.015 --0.2 0.010 --0.3 --0.4 --50 0.005 --25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 0 0 Figure 11. Threshold Voltage 5 10 15 20 25 ID, DRAIN CURRENT (A) Figure 12. On--Resistance versus Drain Current and Temperature http://onsemi.com 5 30 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTLTD7900ZR2 1 D = 0.5 0.2 0.1 0.1 0.05 P(pk) t1 0.02 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 10--4 10--3 10--2 10--1 t, TIME (seconds) 1 RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) -- TC = P(pk) RθJC(t) 10 100 1000 Figure 13. Thermal Response ORDERING INFORMATION Package Shipping† NTLTD7900ZR2 Micro8 LL 3000 / Tape & Reel NTLTD7900ZR2G Micro8 LL (Pb--Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTLTD7900ZR2 PACKAGE DIMENSIONS Micro8 LEADLESS CASE 846C--01 ISSUE C SEATING PLANE T W Y A J NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95--1 SPP--012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 4. DIMENSION D APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 MM AND 0.30 MM FROM TERMINAL TIP. DIMENSION L1 IS THE TERMINAL PULL BACK FROM PACKAGE EDGE, UP TO 0.1 MM IS ACCEPTABLE. L1 IS OPTIONAL. 5. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 6. OPTIONAL SIDE VIEW CAN SHOW LEADS 5 AND 8 REMOVED. AA INDEX AREA 8 7 B NOTE 6 6 2X 5 0.15 T K AA C 2X TOP VIEW 0.15 T 0.10 T 8X DIM A B C D E F G H J K L L1 P U 0.08 T NOTE 4 0.10 T W Y 0.05 T W D G E L 8X SIDE VIEW 8X 6X 8 1 7 2 6 3 5 4 L1 NOTE 4 F P DETAIL Z DETAIL Z U 4X SOLDERING FOOTPRINT* H 2.75 VIEW AA--AA 1.23 1.50 0.40 8X 3.60 0.58 0.65 PITCH 8X 0.33 DIMENSIONS: MILLIMETERS *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 3.30 BSC 3.30 BSC 0.85 0.95 0.25 0.35 1.30 1.50 2.55 2.75 0.65 BSC 0.95 1.15 0.25 BSC 0.00 0.05 0.35 0.45 0.00 0.10 1.28 1.38 0.17 TYP NTLTD7900ZR2 Micro8 is a trademark of International Rectifier Corporation. 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