STHDLS101 AC coupled HDMI level shifter Features ■ Converts low-swing alternating current (AC) coupled differential input to high-definition multimedia interface (HDMI) rev 1.3 compliant ■ HDMI level shifting operation up to 2.7 Gbps per lane ■ Integrated 50 Ω termination resistors for AC-coupled differential inputs ■ Input/output transition minimized differential signaling (TMDS) enable/disable ■ Output slew rate control on TMDS outputs to minimize electromagnetic interference (EMI) ■ Fail-safe outputs for backdrive protection ■ No re-timing or configuration required ■ Inter-pair output skew < 250 ps Description ■ Intra-pair output skew < 10 ps ■ Single power supply of 3.3 V ■ ESD protection: ±6 KV HBM on all I/O pins ■ Integrated display data channel (DDC) level shifters. Pass-gate voltage limiters allow 3.3 V termination on graphics and memory controller hub (GMCH) pins and 5 V DDC termination on HDMI connector pins ■ Hot-plug detect (HPD) signal level shifter from HDMI/DVI connector ■ Integrated pull-down resistor on HPD_SINK and OE_N inputs The STHDLS101 is a high-speed high-definition multimedia interface (HDMI) level shifter that converts low-swing AC coupled differential input to HDMI 1.3 compliant open-drain current steering RX-terminated differential output. Through the existing PCI-E pins in the graphics and memory controller hub (GMCH) of PCs or notebook motherboards, the pixel clock provides the required bandwidth (1.65 Gbps, 2.25 Gbps) for the video supporting 720p, 1080i, 1080p with a total of 36-bit resolution. The HDMI is multiplexed onto the PCIe pins in the motherboard where the AC coupled HDMI at 1.2 V is output by GMCH. The AC coupled HDMI is then level shifter by this device to 3.3 V DC coupled HDMI output. The STHDLS101 supports up to 2.7 Gbps, which is enough for 12 bits of color depth per channel, as indicated in HDMI rev 1.3. The device operates from a single 3.3 V supply and is available in a 48-pin QFN package. Applications ■ Notebooks ■ PC motherboards and graphic cards ■ Dongles/cable adapters Table 1. QFN-48 (7 x 7 mm) Device summary Order code Package Packing STHDLS101QTR QFN-48 Tape and reel December 2008 Rev 4 1/25 www.st.com 25 Contents STHDLS101 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 6 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 STHDLS101 1 Block diagram Block diagram Figure 1. STHDLS101 block diagram 3/25 System interface 2 STHDLS101 System interface Figure 2. System inferface Graphics chipset (GMCH) on the motherboard PCI-Express SDVO HDMI Level shifter STHDLS101 HDMI output connector CS00374 Figure 3. Cable adapter ($-)$6) $ONGLEOR CABLE ADAPTER 34($,3 $0 !-6 4/25 STHDLS101 System interface HPD HDMI/DVI Transmitter AC_TMDS DDC HPD_SINK HPD_SOURCE AC_TMDS DDC STHDLS101 HDMI/DVI Cable Adaptor DC TMDS DDC HDMI/DVI Connector DP to HDMI/DVI cable adapter DP Connector Figure 4. PC chipset !-6 5/25 Pin configuration Pin configuration OUT_D2- 19 OUT_D2+ GND GND VCC33 OE_N 27 26 25 30 SDA_SINK HPD_SINK 31 SCL_SINK GND 32 29 DDC_EN 33 28 FUNCTION3 VCC33 34 FUNCTION4 35 12 OUT_D4+ GND 13 48 11 47 VCC33 OUT_D4- 10 VCC33 14 9 15 46 ANALOG2 45 SCL_SOURCE OUT_D3+ 8 OUT_D3- 16 SDA_SOURCE 17 44 7 18 HPD_SOURCE 42 43 6 IN_D4+ QFN-48 REXT IN_D4- 41 21 20 4 IN_D3+ VCC33 40 5 IN_D3- OUT_D1+ VCC33 GND GND 22 39 FUNCTION2 IN_D2+ OUT_D1- 3 IN_D2- 23 38 FUNCTION1 VCC33 GND 2 IN_D1+ 24 37 VCC33 IN_D1- GND GND 36 STHDLS101 pin configuration 1 Figure 5. GND 3 STHDLS101 CS000118 6/25 STHDLS101 3.1 Pin configuration Pin description Table 2. Pin description Pin number Name Type 1 GND Power Ground 2 VCC33 Power 3.3 V±10% DC supply Function FUNCTION1 Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. 4 FUNCTION2 Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. 5 GND 3 Power Ground 6 REXT Analog Connection to external resistor. Resistor value specified by device manufacturer. Acceptable connections to this pin are: - Resistor to GND - Resistor to 3.3 V - NC (direct connections to VCC or GND are through a 0 Ω resistor for layout compatibility 7 HPD_SOURCE Output 0 to 3.3 V (nominal) output signal. This is level-shifted version of the HPD_SINK signal. 8 SDA_SOURCE I/O 3.3 V DDC data I/O. Pulled-up by external termination to 3.3 V. Connected to SDA_SINK through voltagelimiting integrated NMOS pass-gate. 9 SCL_SOURCE Input 3.3 V DDC clock I/O. Pulled-up by external termination to 3.3 V. Connected to SCL_SINK through voltagelimiting integrated NMOS pass-gate. 10 ANALOG2 Analog Analog connection determined by vendor. Acceptable connections to this pin are: - Resistor or capacitor to GND - Resistor or capacitor to 3.3 V - Short to 3.3 V or to GND - NC 11 VCC33 Power 3.3 V ±10% DC supply 12 GND Power Ground 13 OUT_D4+ Output HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal with OUT_D4-. 7/25 Pin configuration Table 2. STHDLS101 Pin description (continued) Pin number Name Type 14 OUT_D4- Output HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output signal with OUT_D4+. 15 VCC33 Power 3.3 V±10% DC supply 16 OUT_D3+ Output HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal with OUT_D3-. 17 OUT_D3- Output HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output signal with OUT_D3+. 18 GND Power Ground 19 OUT_D2+ Output HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2-. 20 OUT_D2- Output HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output signal with OUT_D2+. 21 VCC33 Power 3.3 V±10% DC supply 22 OUT_D1+ Output HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal with OUT_D1-. 23 OUT_D1- Output HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output signal with OUT_D1+. 24 GND Power Ground Function Enable for level shifter path. 3.3 V tolerant low-voltage single-ended input. Internal pull-down enables the device when unconnected. 25 8/25 OE_N Input OE_N IN_D termination OUT_D Outputs 1 High-Z High-Z 0 50Ω Active 26 VCC33 Power 3.3 V±10% DC supply 27 GND Power Ground 28 SCL_SINK Output 5 V DDC clock I/O. Pulled-up by external termination to 5 V. Connected to SCL_SOURCE through voltagelimiting integrated NMOS pass-gate. 29 SDA_SINK I/O 5V DDC data I/O. Pulled-up by external termination to 5V. Connected to SDA_SOURCE through voltagelimiting integrated NMOS pass-gate. STHDLS101 Pin configuration Table 2. Pin number Pin description (continued) Name Type Function 30 HPD_SINK Input Low-frequency, 0 to 5 V (nominal) input signal. This signal comes from the HDMI connector. Voltage high indicates “plugged” state; voltage low indicates “unplugged” state. HPD_SINK is pulled down by an integrated 160 KΩ pull-down resistor. 31 GND Power Ground Enables bias voltage to the DDC pass-gate level shifter gates. (May be implemented as a bias voltage connection to the DDC pass-gate themselves). 32 33 DDC_EN VCC33 Input Power DDC_EN Pass-gate 0V Disabled 3.3 V Enabled 3.3 V ± 10% DC supply FUNCTION3 Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. 35 FUNCTION4 Function pins are to enable vendor-specific features or test modes. Vendor-specific For normal operation, these pins are tied to GND or control or test VCC33. pins For consistent interoperability, GND is the preferred default connection for these signals. 36 GND Power Ground 37 GND Power Ground 38 IN_D1- Input Low-swing differential input from GMCH PCIE outputs. IN_D1- makes a differential pair with IN_D1+. 39 IN_D1+ Input Low-swing differential input from GMCH PCIE outputs. IN_D1+ makes a differential pair with IN_D1-. 40 VCC33 Power 3.3 V±10% DC supply 41 IN_D2- Input Low-swing differential input from GMCH PCIE outputs. IN_D2- makes a differential pair with IN_D2+. 42 IN_D2+ Input Low-swing differential input from GMCH PCIE outputs. IN_D2+ makes a differential pair with IN_D2-. 43 GND Power Ground 44 IN_D3- Input Low-swing differential input from GMCH PCIE outputs. IN_D3- makes a differential pair with IN_D3+. 45 IN_D3+ Input Low-swing differential input from GMCH PCIE outputs. IN_D3+ makes a differential pair with IN_D3-. 34 9/25 Pin configuration Table 2. 10/25 STHDLS101 Pin description (continued) Pin number Name Type 46 VCC33 Power 3.3 V±10% DC supply 47 IN_D4- Input Low-swing differential input from GMCH PCIE outputs. IN_D4- makes a differential pair with IN_D4+. 48 IN_D4+ Input Low-swing differential input from GMCH PCIE outputs. IN_D4+ makes a differential pair with IN_D4-. Function STHDLS101 4 Functional description Functional description This section describes the basic functionality of the STHDLS101 device. Power supply The STHDLS101 is powered by a single DC power supply of 3.3 V ± 10%. Clocking This device does not retime any data. The device contains no state machines. No inputs or outputs of the device are latched or clocked. Reset This device acts as a level shifter, reset is not required. OE_N function When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input termination resistors are enabled and any internal bias circuits are turned on. The OE_N pin has an internal pull-down that enables the chip if left unconnected. When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state. The IN_D input buffers are disabled and the IN_D termination resistors are disabled. Internal bias circuits for the differential inputs and outputs are turned off. Power consumption of the chip is minimized. The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and SDA pass-gates are not affected by OE_N. Table 3. OE_N description OE_N Device state Asserted Differential input buffers and output (low level) buffers enabled. Input impedance = or unconnected 50 Ω De-asserted (high level) Low-power state. Differential input buffers and terminations are disabled. Differential input buffers are in high-impedance state. OUT_D level shifting outputs are disabled. OUT_D level shifting outputs are in a high-impedance state. Internal bias currents are turned off. Comments Normal functioning state for IN_D to OUT_D level shifting function. Intended for lowest power condition when: • No display is plugged in or • The level shifted data path is disabled HPD_SINK input and HPD_SOURCE output are not affected by OE_N. SCL_SOURCE, SCL_SINK, SDA_SOURCE and SDA_SINK signals and functions are not affected by OE_N. 11/25 Functional description Table 4. STHDLS101 OE_N function OE_N 12/25 IN_Dx OUT_Dx (TMDS outputs) Notes Device disabled. Low power state. Internal bias currents are disabled. De-asserted (high level) High-Z High-Z Asserted (low level) or unconnected 50 Ω termination Enabled Level shifting mode enabled. STHDLS101 5 Maximum ratings Maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Parameter VCC VI Value Unit Supply voltage to ground potential -0.5 to +4.0 V DC input voltage (TMDS and PCIe ports) -0.5 to +4.0 V Control pins -0.5 to +4.0 V -0.5 to +6 V SDA_SINK, SCL_SINK, HPD_SINK pins IO DC output current 120 mA PD Power dissipation 1 W -65 to +150 °C 300 °C ±6 kV Storage temperature TSTG TL Lead temperature (10 sec) Electrostatic discharge voltage on IOs(1) VESD Human body model 1. In accordance with the MIL standard 883 method 3015 Table 6. Symbol θJA Thermal data Parameter Junction-ambient thermal coefficient QFN-48 Unit 48 °C/W 13/25 Maximum ratings STHDLS101 5.1 Recommended operating conditions 5.1.1 Power supply and temperature range Table 7. Power supply and temperature range Symbol VCC33 ICC T Parameter Comments 3.3 V power supply Maximum power supply current Max Unit 3.0 3.3 3.6 V 100 mA -40 5.1.2 Differential inputs (IN_D signals) Table 8. Differential input characteristics for IN_D signals Comments Min Unit interval Tbit is determined by the display mode. Nominal bit rate ranges from 250 Mbps to 2.5 Gbps per lane. Nominal Tbit at 2.5 Gbps = 400 ps. 360 ps = 400 ps – 10% 360 Differential input peak to peak voltage VRX-DIFFp-p=2*|VRX-D+ VRX-D-|. Applies to IN_D signals. Minimum eye width at IN_D input pair The level shifter may add a maximum of 0.02UI jitter AC peak common mode input voltage VCM-AC-pp=|VRX-D+ + VRX-D-|/2 – VRX-CM-DC. VRX-CM-DC=DC(avg) of |VRX-D+ + VRX-D-|/2 VCM-AC-pp includes all frequencies above 30 kHz. ZRX-DC DC single-ended input impedance Applies to IN_D+ as well as IN_D- pins (50 Ω ± 20% tolerance) 40 VRX-Bias RX input termination voltage Intended to limit power-up stress on chipset’s PCIE output buffers 0 Single-ended input resistance for IN_Dx when inputs are in high-Z state Differential inputs must be in a high impedance state 100 Tbit VRX-DIFFp-p TRX-EYE VCM-AC-pp ZRX-HIGH-Z 14/25 Parameter Typ Total current from VCC 3.3 V power supply Operating temperature range Symbol Min 85 Typ Max o C Unit ps 0.175 1.2 0.8 V Tbit 50 100 mV 60 Ω 2 V KΩ STHDLS101 5.2 Maximum ratings TMDS outputs (OUT_D signals) The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The HDMI 1.3 specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3 specification. Table 9. Differential output characteristics for TMDS OUT_D signals Symbol Parameter Comments Min Typ Max Unit VH Single-ended high level output voltage AVCC is the DC termination voltage in the HDMI or DVI sink. AVCC is nominally 3.3 V AVCC-10 mV AVCC AVCC+10 mV V VL Single-ended low The open-drain output level output pulls down form AVCC voltage AVCC-500 mV AVCC-400 mV V Single-ended VSWING output swing voltage Swing down from TMDS termination voltage (3.3 V±10%) AVCC-600 mV 400 mV 500 mV 600 mV V 10 µA Single-ended current in high-Z state Measured with TMDS outputs pulled up to AVCC max (3.6 V) through 50 Ω resistors TR Rise time Maximum rise/fall time @ 2.7 Gbps = 148 ps. 125 ps = 148 – 15% 125 ps 0.4 Tbit ps TF Fall time Maximum rise/fall time @ 2.7 Gbps = 148 ps. 125 ps = 148 – 15% 125 ps 0.4 Tbit ps Intra-pair differential skew This differential skew budget is in addition to the skew presented between D+ and D- paired input pins. 10 ps This lane-to-lane skew Inter-pair lane to budget is in addition to the lane output skew skew between differential input pairs. 250 ps 7.4 ps IOFF TSKEWINTRA TSKEWINTER TJIT Jitter added to TMDS signals Jitter budget for TMDS signals as they pass through the level shifter. 7.4 ps = 0.02 Tbit at 2.7 Gbps 15/25 Maximum ratings STHDLS101 5.3 HPD input and output characteristics Table 10. HPD_SINK input and HPS_SOURCE output Symbol Parameter Comment Min Typ Max Unit Low speed input changes state on cable plug/unplug 2 5.0 5.3 V 0.8 V 50 µA 2.5 VCC V 0 0.02 V 200 ns 20 ns VIH-HPD_SINK HPD_SINK input high level VIL-HPD_SINK HPD_SINK input low level IIN-HPD_SINK HPD_SINK input leakage current Measured with HPD_SINK at VIH-HPD max and VILHPD min HPD_SOURCE output high level VCC = 3.3 V±10% VOHHPD_SOURCE VOL- 0 HPD_SOURCE output low level HPD_SOURCE THPD TRF-HPD HPD_SINK to HPD_SOURCE propagation delay HPD_SOURCE rise/fall time Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time CL = 10 pF Time required to transition from VOH-HPD_SOURCE to VOLHPD_SOURCE or from VOLHPD_SOURCE to VOHHPD_SOURCE CL=10 pF 16/25 1 STHDLS101 Maximum ratings 5.4 DDC input and output chatacteristics Table 11. SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics Symb ol Max Unit 0 5.5 V ILKG VCC = 3.3 V VI = 0.1 VDD to 0.9 VDD to isolated DDC inputs Input leakage current on SDA_SINK, SCL_SINK VDD = external pull-up pins resistor voltage on SDA_SINK and SCL_SINK inputs (maximum of 5.5 V) -10 10 µA IOFF Power-down leakage current on SDA_SINK, SCL_SINK pins VCC = 0.0 V VI = 0.1 VDD to 0.9 VDD to DDC sink inputs VDD = external pull-up resistor voltage on SDA_SINK and SCL_SINK inputs (maximum of 5.5 V) SDA_SOURCE, SCL_SOURCE = 0.0 V -10 10 µA CI/O Input/output capacitance (switch off) VI(pp) = 1 V, 100 KHz VCC = 3.3 V, T = 25 ° C CI/O Input/output capacitance (switch on) VI(pp) = 1 V, 100 KHz VCC = 3.3 V, T = 25 ° C RON Switch resistance IO=3 mA, VO = 0.4 V VCC = 3.3 V TPD Time from DDC_SINK changing state to DDC_SOURCE changing state while the pass gate is DDC_SINK to DDC_SOURCE propagation delay enabled. CL=10 pF RPU=1.5 K (min), 2.0 K (max) TSX Switch time from DDC_EN to the valid state on DDC_SOURCE VI Parameter Input voltage on SDA_SINK, SCL_SINK pins Comment Min Voltage on the DDC pins on connector end CL = 10 pF RPU = 1.5 K (min), 2.0 K (max) Typ 5 pF 10 pF 27 40 Ω 8 15 ns 8 15 ns 17/25 Maximum ratings STHDLS101 5.5 OE_ input characteristics Table 12. OE_N input characteristics Symbol Parameter Comment VIH-OE_N Input high level VIL-OE_N Input low level IIN-OE_N Input leakage current 5.6 HPD input resistor Table 13. HDP input resistor Symbol RHPD Parameter HPD_SINK input pull-down resistor 5.7 ESD performance Table 14. ESD performance Symbol Parameter ESD MIL STD 883 method 3015 (all pins) 18/25 Min Typ Max Unit 2 VCC33 V 0 0.8 V 200 µA Measured with OE_N at VIH-OE_N max and VIL-OE_N mix Comment Guarantees HPD_SINK is LOW when no display is plugged in Test condition Human body model (HBM) Min Typ Max Unit 130 K 160 K 190 K Ω Min -6 Typ Max Unit +6 kV STHDLS101 Application information 6 Application information 6.1 Power supply sequencing A proper power supply sequencing is advised for all CMOS devices. It is recommended to always apply VCC before applying any signals to the input/output or control pins. 6.2 Supply bypassing Bypass each of the VCC pins with 0.1µF and 1nF capacitors in parallel as close to the device as possible, with the smaller valued capacitor as close to the VCC pin of the device as possible. 6.3 Differential traces The high-speed inputs and TMDS outputs are the most critical parts for the device. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device. a) Maintain 100 Ω differential transmission line impedance into and out of the device. b) Keep an uninterrupted ground plane below the high-speed I/Os. c) Keep the ground-path vias to the device as close as possible to allow the shortest return current path. d) Layout of the TMDS differential outputs should be with the shortest stubs from the connectors. Output trace characteristics affect the performance of the STHDLS101. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. Run the differential traces close together to minimize the effects of the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the differential trace layout. Avoid 90 ° C turns and minimize the number of vias to further prevent impedance discontinuities. 19/25 Package mechanical data 7 STHDLS101 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 20/25 STHDLS101 Package mechanical data Figure 6. QFN-48 (7 x 7 mm) package outline 21/25 Package mechanical data Table 15. STHDLS101 QFN-48 (7 x 7 mm) package mechanical data Millimeters Inches Symbol Min Typ Max Min Typ Max 0.80 0.90 1.00 0.80 0.85 1.00 A1 0.02 0.05 0.01 0.05 A2 0.65 1.00 0.65 A3 0.25 A b 0.18 0.23 0.30 0.18 0.23 0.30 D 6.85 7.00 7.15 6.90 7.00 7.10 D2 2.25 4.70 5.25 E 6.85 7.00 7.15 E2 2.25 4.70 5.25 e 0.45 0.50 0.55 0.45 0.50 0.55 L 0.30 0.40 0.50 0.30 0.40 0.50 ddd Figure 7. 22/25 0.20 0.08 QFN-48 tape information See exposed pad variations 6.90 7.00 7.10 See exposed pad variations 0.08 STHDLS101 Package mechanical data Figure 8. Reel information 0084694_J Table 16. Reel mechanical data (dimensions in mm) A C N T 330.2 13 ±0.25 100 16.4 23/25 Revision history 8 STHDLS101 Revision history Table 17. Document revision history Date Revision 15-Apr-2008 1 Initial release. 23-Apr-2008 2 Modified: Figure 5. 10-Jun-2008 3 Document status promoted from preliminary data to datasheet. 4 Updated: Features section, Table 2: Pin description on page 7 and Chapter 4 and Chapter 5: Maximum ratings on page 13. Added: Figure 3: Cable adapter on page 4, Figure 4: DP to HDMI/DVI cable adapter on page 5, Figure 8: Reel information on page 23 and Table 16: Reel mechanical data (dimensions in mm) on page 23. 01-Dec-2008 24/25 Changes STHDLS101 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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