FREESCALE MPC17510

Freescale Semiconductor
Advance Information
Document Number: MPC17510
Rev. 3.0, 1/2007
1.2 A 15 V H-Bridge Motor
Driver IC
17510
The 17510 is a monolithic H-Bridge designed to be used in
portable electronic applications such as digital and SLR cameras to
control small DC motors.
The 17510 can operate efficiently with supply voltages as low as
2.0 V to as high as 15 V. Its low RDS(ON) H-Bridge output MOSFETs
(0.45 Ω typical) can provide continuous motor drive currents of 1.2 A
and handle peak currents up to 3.8 A. It is easily interfaced to lowcost MCUs via parallel 5.0 V compatible logic. The device can be
pulse width modulated (PWM-ed) at up to 200 kHz.
This device contains an integrated charge pump and level shifter
(for gate drive voltages), integrated shoot-through current protection
(cross-conduction suppression logic and timing), and undervoltage
detection and shutdown circuitry.
The 17510 has four operating modes: Forward, Reverse, Brake,
and Tri-Stated (High Impedance).
H-BRIDGE MOTOR DRIVER
MTB SUFFIX
EJ SUFFIX (Pb-FREE)
98ASH70455A
24-LEAD TSSOP
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
•
Device
2.0 V to 15 V Continuous Operation
Output Current 1.2 A (DC), 3.8 A (Peak)
450 mΩ RDS(ON) H-Bridge MOSFETs
5.0 V TTL- / CMOS-Compatible Inputs
PWM Frequencies up to 200 kHz
Undervoltage Shutdown
Cross-Conduction Suppression
Pb-Free Packaging Designated by Suffix Code EJ
Package
-30°C to 65°C
24 TSSOPW
MPC17510EJ/R2
MPC17510MTB
MPC17510MTBEL
5.0 V
15 V
17510
VDD
VM
C1L
GOUT
C1H
C2L
C2H
CRES
OUT1
MCU
Temperature
Range (TA)
EN
GIN
IN1
IN2
MOTOR
OUT2
GND
Figure 1. 17510 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CRES
3
C2H
C2L
C1H
C1L
TOUT
14
13
11
12
15
Charge Pump
21 VM1
VDD
23
IN1
9
IN2
10
Low Voltage
Detector
Level
Shifter
Predriver
16
TINB
24
VM2
1
OUTA
5
OUTA'
H-Bridge
17 OUTB'
18 OUTB
Control
Logic
EN
8
6
LGND
PGND1
19 PGND2
2
4
7
20 22
NC
Figure 2. 17510 Simplified Internal Block Diagram
17510
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
OUT1
1
24
GIN
LGND
2
23
VDD
CRES
3
22
NC
NC
4
21
VM
OUT1
5
20
NC
PGND
6
19
PGND
NC
7
18
OUT2
VM
8
17
OUT2
IN1
9
16
EN
IN2
10
15
GOUT
C1H
11
14
C2H
C1L
12
13
C2L
Figure 3. 17510 Pin Connections
Table 1. 17510 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 8.
Pin Number
Pin Name
Formal Name
Definition
1, 5
OUT1
Output 1
2
LGND
Logic Ground
3
CRES
Charge Pump Output
Capacitor Connection
4, 7,
20, 22
NC
No Connect
17, 18
OUT2
Output 2
6, 19
PGND
Power Ground
8, 21
VM
Motor Drive Power
Supply
9
IN1
Input Control 1
Control signal input 1 pin.
10
IN2
Input Control 2
Control signal input 2 pin.
11
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
12
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
13
C2L
Charge Pump 2L
Charge pump bucket capacitor 2 (negative pole).
14
C2H
Charge Pump 2H
Charge pump bucket capacitor 2 (positive pole).
15
GOUT
Gate Driver Output
16
EN
Enable Control
Enable control signal input pin.
23
VDD
Logic Supply
Control circuit power supply pin.
24
GIN
Gate Driver Input
Driver output 1 pins.
Logic ground.
Charge pump reservoir capacitor pin.
No connection to these pins.
Driver output 2 pins.
Power ground.
Motor power supply voltage input pins.
Output gate driver signal to external MOSFET switch.
LOW = True control signal for GOUT pin.
17510
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Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Motor Supply Voltage
Symbol
Value
Unit
VM
- 0.5 – - 16
V
VCRES
-0.5 to 13
V
Logic Supply Voltage
VDD
-0.5 to 16
V
Signal Input Voltage (EN, IN1, IN2, GIN)
VIN
-0.5 to VDD + 0.5
V
IO
1.2
IOPK
3.8
Human Body Model
VESD1
±1900
Machine Model
VESD2
± 130
Storage Temperature
TSTG
-65 to 150
°C
Operating Junction Temperature
TJ
-30 to 150
°C
Operating Ambient Temperature
TA
-30 to 65
°C
PD
1.0
W
RθJA
120
°C/W
TSOLDER
260
°C
Charge Pump Output Voltage
(1)
Driver Output Current
A
Continuous
Peak (2)
ESD Voltage
(3)
Power Dissipation
V
(4)
Thermal Resistance
Soldering Temperature
(5)
Notes
1. When supplied externally, connect via 3.0 kΩ resistor.
2. TA = 25°C, 10 ms pulse at 200 ms interval.
3.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4.
TA = 25°C, RθJA = 120°C/W, 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB).
5.
Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Motor Supply Voltage
VM
2.0
–
15
V
Logic Supply Voltage
VDD
4.0
–
5.5
V
C1, C2, C3
0.001
–
0.1
µF
POWER
Capacitor for Charge Pump
Standby Power Supply Current (6)
Motor Supply Standby Current
I
Logic Supply Standby Current
I
VMSTBY
–
–
1.0
µA
VDDSTBY
–
0.3
1.0
mA
I VDD
–
3.3
4.0
mA
VDDDET
1.5
2.5
3.5
VMDET
4.0
5.0
6.0
–
0.45
0.55
12
13
13.5
10
11.2
–
V
CRES 0.5
V
CRES 0.1
LGND
LGND + 0.1
VIN
0
–
High-Level Input Voltage
VIH
VDD x 0.7
Low-Level Input Voltage
VIL
–
High-Level Input Current
IIH
Low-Level Input Current
Logic Supply Current (7)
Low-Voltage Detection Circuit
Detection Voltage (VDD)
(8)
Detection Voltage (VM)
Driver Output ON Resistance (9)
V
Ω
RDS(ON)
VM = 2.0 V, 8.0 V, 15 V
GATE DRIVE
Gate Drive Voltage (10)
VCRES
No Current Load
Gate Drive Ability (Internally Supplied)
I
V
VCRESLOAD
CRES = -1.0 mA
V
Gate Drive Output
V
IOUT = -50 µA
VGOUTHIGH
IIN = 50 µA
VGOUTLOW
V
CRES
LGND +0.5
CONTROL LOGIC
Logic Input Voltage (EN, IN1, IN2, GIN)
VDD
V
–
–
V
–
VDD x 0.3
V
–
–
1.0
µA
IIL
-1.0
–
–
µA
IIL
- 200
- 50
–
µA
Logic Input Function (4.0 V < VDD < 5.5 V)
EN / GIN Pin
Notes
6. Excluding pull-up resistor current, including current of gate-drive circuit.
7. fIN = 100 kHz.
8.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate
voltage VCRES is applied from an external source, VCRES = 7.5 V.
9.
IO = 1.2 A source + sink.
10.
Input logic signal not present.
17510
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VM = 15 V, VDD = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
fIN
–
–
200
kHz
tR
–
–
1.0
µs
tF
–
Turn-ON Time
tPZH
–
0.3
1.0
Turn-ON Time
tPLH
–
1.2
2.0
Turn-OFF Time
tPHL
–
0.5
1.0
Turn-ON Time
tTON
–
–
10
Turn-OFF Time
tTOFF
–
–
10
fOSC
INPUT (EN, IN1, IN2, GIN)
Pulse Input Frequency
Input Pulse Rise Time
(11)
Input Pulse Fall Time (13)
(12)
–
1.0
µs
(12)
OUTPUT
µs
Propagation Delay Time
GOUT Output Delay Time
(14)
µs
Charge Pump Circuit
Oscillator Frequency
Rise Time (15)
Low-Voltage Detection Time
Notes
11.
12.
13.
14.
15.
100
200
400
kHz
CRESON
–
0.1
1.0
ms
tVDDDET
–
–
10
ms
tV
Time is defined between 10% and 90%.
That is, the input waveform slope must be steeper than this.
Time is defined between 90% and 10%.
Load is 500 pF.
Time to charge CRES to 11 V after application of VDD.
17510
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
IN1, IN2, EN
(GIN)
VDDDETON
50%
VDDDETOFF
3.5 V
VDD
50%
tPZH*,
tPLH
(tTON)
tPHL
1.5 V
(tTOFF)
t
tV
VDDDET
90%
OUTn
(GOUT)
DDDET
90%
10%
IM
0%
(<1.0 µA)
* The last state is “Z”.
Figure 4. tPLH, tPHL, and tPZH Timing
Figure 5. Low-Voltage Detection Timing
Table 5. Truth Table
INPUT
OUTPUT
EN
IN1
IN2
GIN
OUT1
OUT2
GOUT
H
L
L
X
Z
Z
X
H
H
L
X
H
L
X
H
L
H
X
L
H
X
H
H
H
X
L
L
X
L
X
X
X
L
L
L
H
X
X
L
X
X
H
H
X
X
H
X
X
L
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
The GIN pin and EN pin are pulled up to VDD with internal resistance.
17510
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17510 is a monolithic H-Bridge power IC applicable to
small DC motors used in portable electronics. The 17510 can
operate efficiently with supply voltages as low as 2.0 V to as
high as 15 V, and it can provide continuos motor drive
currents of 1.2 A while handling peak currents up to 3.8 A. It
is easily interfaced to low-cost MCUs via parallel 5.0 Vcompatible logic. The device can be pulse width modulated
(PWM-ed) at up to 200 kHz. The 17510 has four operating
modes: Forward, Reverse, Brake, and Tri-Stated (High
Impedance).
Basic protection and operational features (direction,
dynamic braking, PWM control of speed and torque, main
power supply undervoltage detection and shutdown, logic
power supply undervoltage detection and shutdown), in
addition to the 1.0 A rms output current capability, make the
17510 a very attractive, cost-effective solution for controlling
a broad range of small DC motors. In addition, a pair of 17510
devices can be used to control bipolar stepper motors. The
17510 can also be used to excite transformer primary
windings with a switched square wave to produce secondary
winding AC currents.
As shown in Figure 2, 17510 Simplified Internal Block
Diagram, page 2, the 17510 is a monolithic H-Bridge with
built-in charge pump circuitry. For a DC motor to run, the
input conditions need to be set as follows: ENable input logic
HIGH, one INput logic LOW, and the other INput logic HIGH
(to define output polarity). The 17510 can execute dynamic
braking by setting both IN1 and IN2 logic HIGH, causing both
low-side MOSFETs in the output H-Bridge to turn ON.
Dynamic braking can also implemented by taking the ENable
logic LOW. The output of the H-Bridge can be set to an opencircuit high-impedance (Z) condition by taking both IN1 and
IN2 logic LOW. (refer to Table 5, Truth Table, page 7).
The 17510 outputs are capable of providing a continuous
DC load current of up to 1.2 A. An internal charge pump
supports PWM frequencies to 200 kHz. The EN pin also
controls the charge pump, turning it off when EN = LOW, thus
allowing the 17510 to be placed in a power-conserving sleep
mode.
FUNCTIONAL PIN DESCRIPTION
OUTPUT 1 AND OUTPUT2 (OUT1, OUT2)
MOTOR SUPPLY VOLTAGE INPUT (VM)
The OUT1 and OUT2 pins provide the connection to the
internal power MOSFET H-Bridge of the IC. A typical load
connected between these pins would be a small DC motor.
These outputs will connect to either VM or PGND, depending
on the states of the control inputs (refer to Table 5, Truth
Table, page 7).
The VM pins carry the main supply voltage and current into
the power sections of the IC. This supply then becomes
controlled and/or modulated by the IC as it delivers the power
to the load attached between OUT1 and OUT2. All VM pins
must be connected together on the printed circuit board with
as short as possible traces offering as low impedance as
possible between pins.
VM has an undervoltage threshold. If the supply voltage
drops below the undervoltage threshold, the output power
stage switches to a tri-state condition. When the supply
voltage returns to a level that is above the threshold, the
power stage automatically resumes normal operation
according to the established condition of the input pins.
POWER GROUND AND LOGIC GROUND (PGND,
LGND)
The power and logic ground pins (PGND and LGND)
should be connected together with a very low-impedance
connection.
CHARGE PUMP RESERVOIR CAPACITOR (CRES)
The CRES pin provides the connection for the external
reservoir capacitor (output of the charge pump). Alternatively
this pin can also be used as an input to supply gate-drive
voltage from an external source via a series current-limiting
resistor. The voltage at the CRES pin will be approximately
three times the VDD voltage, as the internal charge pump
utilizes a voltage tripler circuit. The VCRES voltage is used by
the IC to supply gate drive for the internal power MOSFET
H-Bridge.
CONTROL SIGNAL INPUT AND ENABLE CONTROL
SIGNAL INPUT (IN1, IN2, EN)
The IN1, IN2, and EN pins are input control pins used to
control the outputs. These pins are 5.0 V CMOS-compatible
inputs with hysteresis. The IN1, IN2, and EN work together to
control OUT1 and OUT2 (refer to Table 5, Truth Table).
GATE DRIVER INPUT (GIN)
The GIN input controls the GOUT pin. When GIN is set
logic LOW, GOUT supplies a level-shifted high-side gate
drive signal to an external MOSFET. When GIN is set logic
HIGH, GOUT is set to GND potential.
17510
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CHARGE PUMP BUCKET CAPACITOR (C1L, C1H,
C2L, C2H)
These two pairs of pins, the C1L and C1H and the C2L and
C2H, connect to the external bucket capacitors required by
the internal charge pump. The typical value for the bucket
capacitors is 0.1 µF.
GATE DRIVER OUTPUT (GOUT)
The GOUT output pin provides a level-shifted, high-side
gate drive signal to an external MOSFET with CISS up to
500 pF.
CONTROL CIRCUIT POWER SUPPLY (VDD)
The VDD pin carries the 5.0 V supply voltage and current
into the logic sections of the IC. VDD has an undervoltage
threshold. If the supply voltage drops below the undervoltage
threshold, the output power stage switches to a tri-state
condition. When the supply voltage returns to a level that is
above the threshold, the power stage automatically resumes
normal operation according to the established condition of
the input pins.
17510
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
TYPICAL APPLICATIONS
FUNCTIONAL PIN DESCRIPTION
TYPICAL APPLICATIONS
Figure 6 shows a typical application for the 17510.
5.0 V
17510
VDD
C1L
C1H
C2L
C2H
CRES
MCU
VM
GOUT
OUT1
Motor
EN
GIN
IN1
IN2
Solenoid
OUT2
GND
Figure 6. 17510 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients by placing a capacitor or zener at the
supply pin (VM) (see Figure 7).
5.0 V
15 V
17510
VM
VDD
5.0 V
15 V
17510
VM
VDD
C1L
C1H OUT1
C2L
C2H
CRES
C1L
C1H OUT1
C2L
C2H
CRES
GND
GND
OUT2
OUT2
Figure 7. CEMF Snubbing Techniques
17510
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
MTB SUFFIX
EJ SUFFIX (PB-FREE)
24-PIN
PLASTIC PACKAGE
98ASH70455A
ISSUE B
17510
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (continued)
MTB SUFFIX
EJ SUFFIX (PB-FREE)
24-PIN
PLASTIC PACKAGE
98ASH70455A
ISSUE B
17510
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
2.0
7/2006
• Implemented a Revision History page.
• Converted to Freescale format, and updated to the prevaiing form and style
• Added EJ Pb-FREE package
3.0
1/2007
• Corrected symbol in Table 3, Driver Output ON Resistance from “W” to "Ω"
17510
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13
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MPC17510
Rev. 3.0
1/2007
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