Freescale Semiconductor Technical Data MPC17529 Rev 2.0, 09/2005 Document order number: 0.7 A Dual H-Bridge Motor Driver with 3.0 V/5.0 V Compatible Logic I/O 17529 DUAL H-BRIDGE The 17529 is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar step motors and/or brush DC-motors (e.g., cameras and disk drive head positioners). The 17529 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 V- and 5.0 Vcompatible logic). The device features on-board charge pump, as well as built-in shoot-through current protection and an undervoltage shutdown function. The 17529 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17529 has a low total RDS(ON) of 1.2 Ω (max @ 25°C). The 17529’s low output resistance and high slew rates provide efficient drive for many types of micromotors. ORDERING INFORMATION Features • Low Total RDS(ON) 0.7 Ω (Typ), 1.2 Ω (Max) @ 25°C • Output Current 0.7 A (DC), 1.4 A (Peak) • Shoot-Through Current Protection Circuit • 3.0 V/ 5.0 V CMOS-Compatible Inputs • PWM Control Input Frequency up to 200 kHz • Built-In Charge Pump Circuit • Low Power Consumption • Undervoltage Detection and Shutdown Circuit • Pb-Free Packaging Designated by Suffix Code EV 5.0 V EV SUFFIX (PB-FREE) 98ASA10616D 20-TERMINAL VMFP Device Temperature Range (TA) Package MPC17529EV/EL -20°C to 65°C 20 VMFP 5.0 V 17529 VDD VM 1/2 C1L C1H C2L OUT1A C2H CRES OUT1B MCU IN1A IN1B IN2A IN2B OE OUT2A GND PGND1/2 OUT2B N S Bipolar Step Motor Figure 1. 17529 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM CRES C2H Charge Pump C1H C1L C2L LowVoltage Shutdown VDD VM1 IN1A OUT1A H-Bridge OUT1B IN1B VDD OE Control Logic PGND1 Level Shifter Predriver VM2 IN2A OUT2A H-Bridge OUT2B IN2B PGND2 LGND Figure 2. 17529 Simplified Internal Block Diagram 17529 2 Analog Integrated Circuit Device Data Freescale Semiconductor TERMINAL CONNECTIONS TERMINAL CONNECTIONS VDD 1 20 LGND IN1A 2 19 IN2A IN1B 3 18 IN2B OE 4 17 VM2 OUT2A 5 16 OUT2B PGND1 6 15 PGND2 OUT1A 7 14 OUT1B VM1 8 13 C2L CRES 9 12 C1L 10 11 C1H C2H Figure 3. 17529 Terminal Connections Table 1. Terminal Function Description Terminal Terminal Name Formal Name 1 VDD Control Circuit Power Supply 2 IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 5, Truth Table, page 7). 3 IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 5, Truth Table, page 7). 4 OE Output Enable 5 OUT2A H-Bridge Output 2A 6 PGND1 Power Ground 1 7 OUT1A H-Bridge Output 1A 8 VM1 Motor Drive Power Supply 1 9 CRES Predriver Power Supply 10 C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole). 11 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole). 12 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole). 13 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole). 14 OUT1B H-Bridge Output 1B 15 PGND2 Power Ground 2 16 OUT2B H-Bridge Output 2B 17 VM2 Motor Drive Power Supply 2 18 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 5, Truth Table, page 7). 19 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 5, Truth Table, page 7). 20 LGND Logic Ground Definition Positive power source connection for control circuit. Logic output Enable control of H-Bridges (Low = True). Output A of H-Bridge channel 2. High-current power ground 1. Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Internal triple charge pump output as predriver power supply. Output B of H-Bridge channel 1. High-current power ground 2. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Low-current logic signal ground. 17529 Analog Integrated Circuit Device Data Freescale Semiconductor 3 MAXIMUM RATINGS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit VM -0.5 to 8.0 V VCRES -0.5 to 14 V Logic Supply Voltage VDD -0.5 to 7.0 V Signal Input Voltage VIN -0.5 to VDD + 0.5 V IO 0.7 IOPK 1.4 Human Body Model (2) VESD1 ±1500 Machine Model (3) VESD2 ± 200 Operating Junction Temperature TJ -20 to 150 °C Operating Ambient Temperature TA -20 to 65 °C TSTG -65 to 150 °C RθJA 120 °C/W PD 1040 mW TSOLDER 260 °C Motor Supply Voltage Charge Pump Output Voltage Driver Output Current A Continuous Peak (1) ESD Voltage V Storage Temperature Range Thermal Resistance Power Dissipation (4) (5) Soldering Temperature (6) Notes 1. TA = 25°C, 10 ms pulse at 200 ms interval. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). 3. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 4. 5. Mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB). TA = 25°C. 6. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 17529 4 Analog Integrated Circuit Device Data Freescale Semiconductor STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Characteristic Symbol Min Typ Max Unit Motor Supply Voltage VM 2.0 5.0 6.8 V Logic Supply Voltage VDD 2.7 5.0 5.6 V Driver Quiescent Supply Current (No Signal Input) IQM – – 1.0 µA IQVDD – – 1.0 mA Logic Supply Current (8) IDVDD – – 3.0 Charge Pump Circuit Supply Current (9) ICRES – – 0.7 VDDDET 1.5 2.0 2.5 V RDS(ON) – 0.7 1.2 Ohms VCRES 12 13 13.5 V CCP 0.01 0.1 1.0 µF VIN 0.0 – VDD V High-Level Input Voltage VIH VDD x 0.7 – – V Low-Level Input Voltage VIL – – VDD x 0.3 V High-Level Input Current IIH – – 1.0 µA IIL -1.0 – – µA OILOE – 50 100 µA POWER (VM1, VM2, VDD) Logic Quiescent Supply Current (No Signal Input) (7) Operating Power Supply Current Low VDD Detection Voltage (10) Driver Output ON Resistance (11) mA GATE DRIVE (C1L – C1H, C2L – C2H, CRES) Gate Drive Voltage Recommended External Capacitance (C1L – C1H, C2L – C2H, CRES – GND) CONTROL LOGIC (OE, N1A, N1B, N2A, N2B) Logic Input Voltage Logic Inputs (2.7 V < VDD < 5.7 V) Low-Level Input Current OE Terminal Input Current Low I Notes 7. IQVDD includes the current to predriver circuit. 8. IVDD includes the current to predriver circuit at fIN = 100 kHz. 9. At fIN = 20 kHz. 10. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate 11. voltage VCRES is applied from an external source, VCRES = 7.5 V. Source + sink at IO = 0.7 A. 17529 Analog Integrated Circuit Device Data Freescale Semiconductor 5 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Characteristic Symbol Min Typ Max Unit f IN – – 200 kHz – (13) µs INPUT (IN1A, IN1B, OE, IN2A, IN2B) Pulse Input Frequency Input Pulse Rise Time (12) Input Pulse Fall Time (14) tR – tF – 1.0 – (13) µs 1.0 OUTPUT (OUT1A, OUT1B, OUT2A, OUT2B) Propagation Delay Time (15) Turn-ON Time Turn-OFF Time Charge Pump Wake-Up Time (16) Low-Voltage Detection Time Notes 12. 13. 14. 15. 16. µs t PLH t PHL – 0.1 0.5 – 0.1 0.5 t VGON tVDDDET – 1.0 3.0 ms – – 10 ms Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load of Output is 8.0 Ω resistance. CCP = 0.1 µF. 17529 6 Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS TIMING DIAGRAMS VDD IN1, IN2, OE 50% tPLH t VGON tPHL OUTA, OUTB 10% Figure 6. Charge Pump Timing Diagram Figure 4. tPLH, tPHL, and tPZH Timing V VCRES 11 V 90% DDDETON 2.5 V/3.5 V VDD 0.8 V/ 1.5 V V DDDETOFF 50% tVDDDET tVDDDET 90% 0% (<1.0 µA) IM Figure 5. Low-Voltage Detection Timing Diagram Table 5. Truth Table INPUT OUTPUT OE IN1A IN2A IN1B IN2B OUT1A OUT2A OUT1B OUT2B L L L L L L H L H L L L H L H L H H Z Z H X X Z Z H = High. L = Low. Z = High impedance. X = Don’t care. OE terminal is pulled up to VDD with internal resistance. 17529 Analog Integrated Circuit Device Data Freescale Semiconductor 7 SYSTEM / APPLICATION INFORMATION INTRODUCTION SYSTEM / APPLICATION INFORMATION INTRODUCTION The 17529 is a monolithic dual H-Bridge ideal for portable electronic applications to control bipolar step motors and brush DC motors such as those found in camera lens assemblies, camera shutters, optical disk drives, etc. The 17529 operates from 2.0 V to 6.8 V, providing dual H-bridge motor drivers with parallel 3.0 V- or 5.0 V-compatible I/O. The device features an on-board charge pump, as well as built-in shoot-through current protection and undervoltage shutdown. The 17529 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The MOSFETs comprising the output bridge have a total source + sink RDS(ON) ≤ 1.2 Ω. The 17529 can simultaneously drive two brush DC motors or, as shown in the simplified application diagram on page 1, one bipolar step motor. The drivers are designed to be PWM’ed at frequencies up to 200 kHz. FUNCTIONAL TERMINAL DESCRIPTION CONTROL CIRCUIT POWER SUPPLY (VDD) MOTOR DRIVE POWER SUPPLY (VM1 AND VM2) The VDD terminal carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input terminals. The VM terminals carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the loads attached between the output terminals. All VM terminals must be connected together on the printed circuit board. LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND IN2B) These logic input terminals control each H-Bridge output. IN1A logic HIGH = OUT1A HIGH. However, if all inputs are taken HIGH, the outputs bridges are both tri-stated (refer to Table 5, Truth Table, page 7). OUTPUT ENABLE (OE) The OE terminal is a LOW = TRUE enable input. When OE = HIGH, all H-Bridge outputs (OUT1A, OUT1B, OUT2A, and OUT2B) are tri-stated (high-impedance), regardless of logic input (IN1A, IN1B, IN2A, and IN2B) states. H-BRIDGE OUTPUT (OUT1A, OUT1B, OUT2A, AND OUT2B) These terminals provide connection to the outputs of each of the internal H-Bridges (see Figure 2, 17529 Simplified Internal Block Diagram, page 2). CHARGE PUMP (C1L AND C1H, C2L AND C2H) These two pairs of terminals, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 µF. PREDRIVER POWER SUPPLY (CRES) The CRES terminal is the output of the internal charge pump. Its output voltage is approximately three times the VDD voltage. The VCRES voltage is power supply for internal predriver circuit of H-Bridges. POWER GROUND (PGND) Power ground terminals. They must be tied together on the PCB. LOGIC GROUND (LGND) Logic ground terminal. 17529 8 Analog Integrated Circuit Device Data Freescale Semiconductor APPLICATIONS FUNCTIONAL TERMINAL DESCRIPTION This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values APPLICATIONS TYPICAL APPLICATION The internal charge pump of this device is generated from the VDD supply; therefore, care must be taken to provide sufficient gate-source voltage for the high-side MOSFETs when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement of the high-side MOSFET channels. Figure 7 shows a typical application for the 17529. When applying the gate voltage to the CRES terminal from an external source, be sure to connect it via a resistor equal to, or greater than, RG = VCRES / 0.02 Ω. 5.0 V 17529 V CRES < 14 V RG > VCRES /0.02 Ω RG NC NC NC NC C1L C1H C2L C2H CRES 0.01 µF VM OUT1A OUT1B IN1A IN1B IN2A IN2B MCU VDD OE OUT2A OUT2B GND NC = No Connect Figure 7. 17529 Typical Application Diagram CONDUCTED ELECTROMOTIVE FORCE (CEMF) SNUBBING TECHNIQUES Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the supply terminal (VM) (see Figure 8). 5.0 V 5.0 V 175XX VDD VM PCB LAYOUT When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground terminals to ensure proper filtering from transients. For all high-current paths, use wide copper traces and shortest possible distances. 5.0 V 5.0 V 175XX VDD VM C1L C1L C1H C1H C2L C2H OUT CRES OUT C2L C2H CRES GND OUT OUT GND Figure 8. CEMF Snubbing Techniques 17529 Analog Integrated Circuit Device Data Freescale Semiconductor 9 APPLICATIONS PACKAGE DIMENSIONS PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below. . EV (Pb-FREE) SUFFIX 20-LEAD VMFP PLASTIC PACKAGE 98ASA10616D ISSUE A 17529 10 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY Revision 2.0 Date 9/2005 Description of Changes • • Implemented Revision History page Converted to Freescale format 17529 Analog Integrated Circuit Device Data Freescale Semiconductor 11 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. 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