TI TPS79501DCQR

TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
ULTRALOW-NOISE, HIGH PSRR, FAST RF 500-mA
LOW-DROPOUT LINEAR REGULATORS
FEATURES
•
•
•
•
•
•
•
•
•
DESCRIPTION
500-mA Low-Dropout Regulator With Enable
Available in 1.6-V, 1.8-V, 2.5-V, 3-V, 3.3-V, and
Adjustable (1.2-V to 5.5-V)
High PSRR (50 dB at 10 kHz)
Ultralow Noise (33 µVRMS, TPS79530)
Fast Start-Up Time (50 µs)
Stable With a 1-µF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (110 mV at Full
Load, TPS79530)
6-Pin SOT223-6 Package
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth™, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
The TPS795xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power-supply rejection ratio (PSRR), ultralow noise,
fast start-up, and excellent line and load transient
responses in a small outline, SOT223-6, package.
Each device in the family is stable with a small 1-µF
ceramic capacitor on the output. The family uses an
advanced, proprietary BiCMOS fabrication process to
yield extremely low dropout voltages (for example,
110 mV at 500 mA). Each device achieves fast
start-up times (approximately 50 µs with a 0.001-µF
bypass capacitor) while consuming very low quiescent current (265 µA typical). Moreover, when the
device is placed in standby mode, the supply current
is reduced to less than 1 µA. The TPS79530 exhibits
approximately 33 µVRMS of output voltage noise at
3.0 V output with a 0.1-µF bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the
high PSRR and low noise features, as well as the fast
response time.
TPS79530
TPS79530
RIPPLE REJECTION
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
80
1
2
3
4
5
6
GND
60
Output Spectral Noise Density − µV/Hz
EN
IN
GND
OUT
NR/FB
0.5
VIN = 4 V
COUT = 10 µF
CNR = 0.01 µF
70
Ripple Rejection − dB
DCQ PACKAGE
SOT223-6
(TOP VIEW)
IOUT = 1 mA
50
40
IOUT = 500 mA
30
20
10
0
1
10
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
VIN = 5.5 V
COUT = 2.2 µF
CNR = 0.1 µF
0.4
0.3
IOUT = 1 mA
0.2
0.1
0
100
IOUT = 0.5 A
1k
10 k
Frequency (Hz)
100 k
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AVAILABLE OPTIONS
PRODUCT
VOLTAGE
PACKAGE
TJ
SYMBOL
TPS79501
1.2 to 5.5 V
PS79501
TPS79516
1.6 V
PS79516
TPS79518
1.8 V
PS79518
TPS79525
2.5 V
PS79525
TPS79530
3V
PS79530
TPS79533
3.3 V
PS79533
SOT223-6
-40°C to 125°C
PART NUMBER
TRANSPORT MEDIA,
QUANTITY
TPS79501DCQ
Tube, 78
TPS79501DCQR
Tape and Reel, 2500
TPS79516DCQ
Tube, 78
TPS79516DCQR
Tape and Reel, 2500
TPS79518DCQ
Tube, 78
TPS79518DCQR
Tape and Reel, 2500
TPS79525DCQ
Tube, 78
TPS79525DCQR
Tape and Reel, 2500
TPS79530DCQ
Tube, 78
TPS79530DCQR
Tape and Reel, 2500
TPS79533DCQ
Tube, 78
TPS79533DCQR
Tape and Reel, 2500
ABSOLUTE MAXIMUM RATINGS
over operating temperature (unless otherwise noted) (1)
UNIT
VIN range
-0.3 V to 6 V
VEN range
-0.3 V to VIN + 0.3 V
VOUT range
6V
Peak output current
Internally limited
ESD rating, HBM
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
See Dissipation Rating Table
Junction temperature range, TJ
-40°C to 150°C
Storage temperature range, Tstg
-65°C to 150°C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATING TABLE
(1)
2
PACKAGE
BOARD
RΘJC
RΘJA
SOT223
Low K (1)
15°C/W
53°C/W
The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch (7.5 cm × 7.5cm), two-layer board with 2-ounce
copper traces on top of the board.
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = -40°C to 125°C), VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1mA,
COUT = 10µF, CNR = 0.01 µF, unless otherwise noted. Typical values are at 25°C.
PARAMETER
TEST CONDITIONS
Input voltage, VIN (1)
Continuous output current, IOUT
Output voltage
500
mA
1.6
1.632
TPS79518
0 µA< IOUT < 500 mA,
2.8 V < VIN < 5.5 V
1.764
1.8
1.836
TPS79525
0 µA< IOUT < 500 mA,
3.5 V < VIN < 5.5 V
2.45
2.5
2.55
TPS79530
0 µA< IOUT < 500 mA,
4 V < VIN < 5.5 V
2.94
3.0
3.06
TPS79533
0 µA< IOUT < 500 mA,
4.3 V < VIN < 5.5 V
3.3
3.366
0.05
0.12
3.234
TJ = 25°C
3
IOUT = 500 mA
110
170
TPS79533
IOUT = 500 mA
105
160
VOUT = 0 V
Ground pin current
0 µA< IOUT < 500 mA
Shutdown current (3)
VEN = 0 V,
FB pin current
VFB = 1.8 V
TPS79530
Output noise voltage (TPS79530)
2.4
2.7 V < VIN < 5.5 V
A
µA
0.07
1
µA
1
µA
f = 100 Hz,
IOUT = 500 mA
58
f = 10 kHz,
IOUT = 500 mA
50
f = 100 kHz,
IOUT = 500 mA
39
CNR = 0.001 µF
46
CNR = 0.0047 µF
41
CNR = 0.01 µF
35
CNR = 0.1 µF
33
CNR = 0.001 µF
50
µVRMS
µs
110
High-level enable input voltage
2.7 V < VIN < 5.5 V
Low-level enable input voltage
2.7 V < VIN < 5.5 V
EN pin current
VEN = 0 V
1
UVLO threshold
VCC rising
2.25
UVLO hysteresis
dB
75
CNR = 0.01 µF
(1)
(2)
(3)
4.2
385
59
CNR = 0.0047 µF
mV
2.8
IOUT = 10 mA
RL = 6 Ω, COUT = 1 µF
%/V
265
f = 100 Hz,
BW = 100 Hz to 100 kHz,
IOUT = 500 mA
V
mV
TPS79530
Output current limit
Time, start-up (TPS79530)
V
0
1.568
0 µA < IOUT < 500 mA,
UNIT
5.5
2.6 V < VIN < 5.5 V
Load regulation (∆VOUT%/∆IOUT)
Power supply ripple rejection
MAX
0 µA< IOUT < 500 mA,
VOUT + 1 V < VIN ≤ 5.5 V
Dropout
VIN = VOUT(nom) - 0.1 V
TYP
2.7
TPS79516
Output voltage line regulation (∆VOUT%/∆VIN) (1)
voltage (2)
MIN
1.7
VIN
V
1
µA
2.65
100
V
0.7
V
mV
Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
Dropout is not measured for the TPS79501 and TPS79525 since minimum VIN = 2.7 V.
For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
3
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
IN
OUT
UVLO
Current
Sense
SHUTDOWN
ILIM
_
GND
R1
+
FB
EN
UVLO
R2
Thermal
Shutdown
Quickstart
Bandgap
Reference
1.225 V
VIN
250 kΩ
External to
the Device
VREF
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
IN
OUT
UVLO
Current
Sense
GND
SHUTDOWN
ILIM
_
EN
R1
+
UVLO
Thermal
Shutdown
R2
Quickstart
VIN
Bandgap
Reference
1.225 V
R2 = 40k
250 kΩ
VREF
NR
Table 1. Terminal Functions
TERMINAL
NAME
DESCRIPTION
ADJ
FIXED
NR
N/A
5
Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This
improves power-supply rejection and reduces output noise.
EN
1
1
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. EN can be connected to IN if not used.
FB
5
N/A
3, TAB
3, TAB
IN
2
2
Unregulated input to the device.
OUT
4
4
Output of the regulator.
GND
4
This terminal is the feedback input voltage for the adjustable device.
Regulator ground
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
TPS79530
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS79530
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
TPS79530
GROUND CURRENT
vs
JUNCTION TEMPERATURE
3.005
3.02
276
VIN = 4 V
COUT = 10 µF
3
3.01
272
IOUT = 1 mA
2.995
VIN = 4 V
COUT = 10 µF
274
IOUT = 1 mA
3
IGND (µA)
VOUT (V)
VOUT (V)
270
2.99
IOUT = 0.5 A
2.985
2.98
2.99
0
0.1
0.2
0.3
IOUT (mA)
0.4
2.97
0.5
262
−40 −25 −10 5
260
−40 −25 −10 5
20 35 50 65 80 95 110 125
20 35 50 65 80 95 110 125
TJ (°C)
TJ (°C)
Figure 1.
Figure 2.
Figure 3.
TPS79530
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
TPS79530
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
TPS79530
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
IOUT = 1 mA
0.2
0.1
0
100
IOUT = 0.5 A
1k
10 k
Frequency (Hz)
Figure 4.
100 k
VIN = 5.5 V
COUT = 10 µF
CNR = 0.1 µF
0.5
0.4
Output Spectral Noise Density − µV/Hz
Output Spectral Noise Density − µV/Hz
VIN = 5.5 V
COUT = 2.2 µF
CNR = 0.1 µF
0.4
0.3
2.5
0.6
0.5
Output Spectral Noise Density − µV/Hz
IOUT = 0.5 A
266
264
2.975
2.98
268
IOUT = 1 mA
0.3
0.2
IOUT = 0.5 A
0.1
0
100
1k
10 k
100 k
2
1.5
CNR = 0.001 µF
VIN = 5.5 V
IOUT = 500 mA
COUT= 10 µF
CNR = 0.0047 µF
CNR = 0.01 µF
1
CNR = 0.1 µF
0.5
0
100
1k
10 k
Frequency (Hz)
Frequency (Hz)
Figure 5.
Figure 6.
100 k
5
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
TPS79530
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
50
175
IOUT = 500 mA
COUT= 10 µF
150
40
VIN = 2.9 V
COUT = 10 µF
IOUT = 500 mA
125
30
VDO (mV)
RMS − Root Mean Squared Output Noise − µVRMS
TPS79530
ROOT MEAN SQUARED OUTPUT NOISE
vs
CNR
20
100
75
50
10
25
BW = 100 Hz to 100 kHz
0
0.001
0.01
0.0047
CNR (µF)
0
−40 −25 −10 5
0.1
20 35 50 65 80 95 110 125
TJ (°C)
Figure 7.
Figure 8.
TPS79530
RIPPLE REJECTION
vs
FREQUENCY
TPS79530
RIPPLE REJECTION
vs
FREQUENCY
80
VIN = 4 V
COUT = 10 µF
CNR = 0.1 µF
70
IOUT = 1 mA
60
Ripple Rejection − dB
50
40
IOUT = 500 mA
30
40
IOUT = 500 mA
50
40
30
IOUT = 500 mA
20
10
10
10
0
0
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
0
1
10
1 k 10 k 100 k 1 M
Frequency (Hz)
100
1 k 10 k 100 k 1 M
Frequency (Hz)
10 M
Figure 11.
TPS79530
RIPPLE REJECTION
vs
FREQUENCY
TPS79530
START-UP TIME
TPS79518
LINE TRANSIENT RESPONSE
20
CNR = 0.001 µF
2.75
2.50
IOUT = 1 mA
60
CNR = 0.0047 µF
2.25
CNR = 0.01 µF
2
VIN (V)
50
40
30
IOUT = 500 mA
Enable
1.75
1 k 10 k 100 k 1 M 10 M
Frequency (Hz)
Figure 12.
COUT = 10 µF, CNR = 0.01 µF,
IOUT = 0.5 A, dv/dt = 1 V/µs
4
VIN = 4 V
COUT = 10 µF
IOUT = 0.5 A
0
100
−10
1
0.25
0
0
−20
1.25
0.50
10
10
1.50
0.75
20
10
10
Figure 10.
3
1
1
10 M
Figure 9.
VIN = 4 V
COUT = 2.2 µF
CNR = 0.1 µF
70
100
VOUT (mV)
10
IOUT = 1 mA
60
20
80
Ripple Rejection − dB
50
20
1
6
IOUT = 1 mA
60
30
VIN = 4 V
COUT = 2.2 µF
CNR = 0.01 µF
70
0
100
200
300
400
t (µs)
Figure 13.
500 600
VIN (V)
Ripple Rejection − dB
70
80
VIN = 4 V
COUT = 10 µF
CNR = 0.01 µF
Ripple Rejection − dB
80
TPS79530
RIPPLE REJECTION
vs
FREQUENCY
3
2
0
50
100
t (µs)
Figure 14.
150
200
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
TPS79530
LINE TRANSIENT RESPONSE
TPS79530
LOAD TRANSIENT RESPONSE
VOUT (mV)
30
10
60
4.5
40
4
20
3.5
0
−20
−10
−40
COUT = 10 µF, CNR = 0.01 µF,
IOUT = 0.5 A, dv/dt = 1 V/µs
5
−60
IOUT (A)
VIN (V)
−20
4
3
0
50
100
t (µs)
150
COUT = 10 µF, CNR = 0.01 µF,
VL = 3.8 V, dv/dt = 0.5 A/µs
2.5
2
1.5
VOUT
0.5
0
0
−0.5
−0.5
200
400
600
800
1000
0
TPS79530
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
180
2
3
100
150
ESR ()
TJ = 25°C
VDO (mV)
9
10
COUT = 1 µF
Region of
Instability
10
100
TJ = −40°C
8
TPS79501
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
TJ = 125°C
40
7
TPS79530
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
OUTPUT CURRENT
120
60
6
Figure 17.
160
80
5
Figure 16.
COUT = 10 µF,
CNR = 0.01 µF,
IOUT = 50 mA
TJ = 125°C
4
200 µs/Div
200
140
1
t (µs)
Figure 15.
VDO (mV)
VIN
1
0.5
0
200
VOUT = 2.5 V,
RL = 10 Ω
3
0
500 mV/Div
VOUT (mV)
20
TPS79525
POWER UP/POWER DOWN
100
TJ = 25°C
50
1
Region of Stability
0.1
TJ = −40°C
20
0.01
0
0
0
100
200
300
IOUT (mA)
Figure 18.
400
500
2.5
3
3.5
4
VIN (V)
Figure 19.
4.5
5
0
100
200
300
IOUT (mA)
400
500
Figure 20.
7
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
TPS79530
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
OUTPUT CURRENT
100
TPS79530
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
OUTPUT CURRENT
100
COUT = 2.2 µF
10
ESR ()
ESR ()
10
1
Region of Stability
0.1
Region of
Instability
1
Region of Stability
0.1
0.01
0.01
1
10
100
IOUT (mA)
Figure 21.
8
COUT = 10 µF
Region of
Instability
1000
0
100
200
300
IOUT (A)
Figure 22.
400
500
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
APPLICATION INFORMATION
The TPS795xx family of low-dropout (LDO) regulators
has been optimized for use in noise-sensitive equipment. The device features extremely low dropout
voltages, high PSRR, ultralow output noise, low
quiescent current (265 µA typically), and enable input
to reduce supply currents to less than 1 µA when the
regulator is turned off.
A typical application circuit is shown in Figure 23.
VIN
IN
VOUT
OUT
TPS795xx
1 µF
EN
GND
2.2µF
NR
0.01µF
because any leakage current creates an IR drop
across the internal resistor thus creating an output
error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor
should be no more than 0.1-µF in order to ensure that
it is fully charged during the quickstart time provided
by the internal switch shown in the functional block
diagram.
For example, the TPS79530 exhibits only 33 µVRMS
of output voltage noise using a 0.1-µF ceramic
bypass capacitor and a 10-µF ceramic output capacitor. Note that the output starts up slower as the
bypass capacitance increases due to the RC time
constant at the bypass pin that is created by the
internal 250-kΩ resistor and external capacitor.
Figure 23. Typical Application Circuit
Board Layout Recommendation to Improve
PSRR and Noise Performance
External Capacitor Requirements
A 1-µF or larger ceramic input bypass capacitor,
connected between IN and GND and located close to
the TPS795xx, is required for stability and improves
transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary
if large, fast-rise-time load transients are anticipated
and the device is located several inches from the
power source.
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
Regulator Mounting
Like most low dropout regulators, the TPS795xx
requires an output capacitor connected between OUT
and GND to stabilize the internal control loop. The
minimum recommended capacitance is 1 µF. Any
1 µF or larger ceramic capacitor is suitable.
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat dissipation.
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS795xx has an NR
pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a
low pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
order for the regulator to operate properly, the current
flow out of the NR pin must be at a minimum,
Solder pad footprint recommendations for the devices
are presented in an application bulletin Solder Pad
Recommendations for Surface-Mount Devices, literature number AB-132, available from the TI web site
(www.ti.com).
9
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
Programming the TPS79501 Adjustable LDO
Regulator
C1 The output voltage of the TPS79501 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 24. The output voltage is
calculated using Equation 1:
V OUT VREF 1 R1
R2
(1)
Regulator Protection
The TPS795xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (e.g.,
during power down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting might be appropriate.
Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors
can be used for improved noise performance, but the
device wastes more power. Higher values should be
avoided, as leakage current at FB increases the
output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider
current at 40 µA, C1 = 15 pF for stability, and then
calculate R1 using Equation 2:
V OUT
R1 1 R2
V REF
The TPS795xx features internal current limiting and
thermal protection. During normal operation, the
TPS795xx limits output current to approximately 2.8
A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition
ends. While current limiting is designed to prevent
gross device failure, care should be taken not to
exceed the power dissipation ratings of the package.
If the temperature of the device exceeds approximately 165°C, thermal-protection circuitry shuts it
down. Once the device has cooled down to below
approximately 140°C, regulator operation resumes.
(2)
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB. The
approximate value of this capacitor can be calculated
as Equation 3:
VIN
IN
1 µF
OUT
TPS79501
EN
NR
0.01 µF
GND
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VOUT
R1
FB
R2
C1
1 µF
OUTPUT
VOLTAGE
R1
R2
C1
1.8 V
14.0 kΩ
30.1 kΩ
22 pF
3.6V
61.9 kΩ
30.1 kΩ
15 pF
Figure 24. TPS79501 Adjustable LDO Regulator Programming
10
(3)
The suggested value of this capacitor for several
resistor ratios is shown in the table below. If this
capacitor is not used (such as in a unity-gain configuration) then the minimum recommended output
capacitor is 2.2 µF instead of 1 µF.
where:
• VREF = 1.2246 V typ (the internal reference
voltage)
(3 x 10 –7) x (R1 R2)
(R1 x R2)
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
THERMAL INFORMATION
The amount of heat that an LDO linear regulator
generates is directly proportional to the amount of
power it dissipates during operation. All integrated
circuits have a maximum allowable junction temperature (TJ(max)) above which normal operation is not
assured. A system designer must design the
operating environment so that the operating junction
temperature (TJ) does not exceed the maximum
junction temperature (TJ(max)). The two main environmental variables that a designer can use to improve
thermal performance are air flow and external
heatsinks. The purpose of this information is to aid
the designer in determining the proper operating
environment for a linear regulator that is operating at
a specific power level.
In general, the maximum expected power (PD(max))
consumed by a linear regulator is computed as
Equation 4:
P D max VIN(avg) VOUT(avg) I OUT(avg) V I(avg) I (Q)
(4)
where:
• VIN(avg) is the average input voltage
• VOUT(avg) is the average output voltage
• IOUT(avg) is the average output current
• I(Q) is the quiescent current
For most TI LDO regulators, the quiescent current is
insignificant compared to the average output current;
therefore, the term VIN(avg) x I(Q) can be neglected.
The operating junction temperature is computed by
adding the ambient temperature (TA) and the increase in temperature due to the regulator's power
dissipation. The temperature rise is computed by
multiplying the maximum expected power dissipation
by the sum of the thermal resistances between the
junction and the case (RΘJC), the case to heatsink
(RΘCS), and the heatsink to ambient (RΘSA). Thermal
resistances are measures of how effectively an object
dissipates heat. Typically, the larger the device, the
more surface area available for power dissipation and
the lower the object's thermal resistance.
Figure 25 illustrates these thermal resistances for (a)
a SOT223 package mounted in a JEDEC low-K
board.
A
TJ
RθJC
CIRCUIT BOARD COPPER AREA
C
B
B
TC
RθCS
A
C
RθSA
SOT223 Package
(a)
TA
Figure 25. Thermal Resistances
Equation 5 summarizes the computation:
T J T A PD max RθJC RθCS RθSA
(5)
The RΘJC is specific to each regulator as determined
by its package, lead frame, and die size provided in
the regulator's data sheet. The RΘSA is a function of
the type and size of heatsink. For example, black
body radiator type heatsinks can have RΘCS values
ranging from 5°C/W for very large heatsinks to
50°C/W for very small heatsinks. The RΘCS is a
function of how the package is attached to the
heatsink. For example, if a thermal compound is used
to attach a heatsink to a SOT223 package, RΘCS of
1°C/W is reasonable.
Even if no external black body radiator type heatsink
is attached to the package, the board on which the
regulator is mounted provides some heatsinking
through the pin solder connections. Some packages,
like the DDPAK and SOT223 packages, use a copper
plane underneath the package or the circuit board's
ground plane for additional heatsinking to improve
their thermal performance. Computer aided thermal
modeling can be used to compute very accurate
approximations of an integrated circuit's thermal performance in different operating environments (e.g.,
different types of circuit boards, different types and
sizes of heatsinks, and different air flows, etc.). Using
these models, the three thermal resistances can be
combined into one thermal resistance between junction and ambient (RΘJA). This RΘJA is valid only for the
specific operating environment used in the computer
model.
11
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C – OCTOBER 2002 – REVISED JANUARY 2005
° C/W
Rearranging Equation 6 gives Equation 7:
T TA
R θJA J
PD max
180
(6)
(7)
Using Equation 6 and the computer model generated
curves shown in Figure 26, a designer can quickly
compute the required heatsink thermal resistance/board area for a given ambient temperature,
power dissipation, and operating environment.
SOT223 Power Dissipation
The SOT223 package provides an effective means of
managing power dissipation in surface mount applications. The SOT223 package dimensions are provided in the Mechanical Data section at the end of
the data sheet. The addition of a copper plane
directly underneath the SOT223 package enhances
the thermal performance of the package.
To illustrate, the TPS79525 in a SOT223 package
was chosen. For this example, the average input
voltage is 3.3 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient temperature 55°C, no air flow is present, and the operating
environment is the same as documented below.
Neglecting the quiescent current, the maximum average power is Equation 8:
P D max (3.3 2.5)V 1A 800mW
(8)
Rθ JA - Thermal Resistance -
Equation 5 simplifies into Equation 6:
T J T A PD max RθJA
No Air Flow
160
140
120
100
80
60
40
20
0
0.1
1
PCB Copper Area - in2
Figure 26. SOT223 Thermal Resistance vs PCB
Copper Area
From the data in Figure 26 and rearranging equation
6, the maximum power dissipation for a different
ground plane area and a specific ambient temperature can be computed (see Figure 27).
6
TA = 25°C
5
Substituting TJmax for TJ into Equation 4 gives
Equation 9:
R θJA max (125 55)°C800mW 87.5°CW
4
4 in2 PCB Area
PD (W)
(9)
From Figure 26, RΘJA vs PCB Copper Area, the
ground plane needs to be 0.55 in2 for the part to
dissipate 800 mW. The operating environment used
to construct Figure 26 consisted of a board with 1 oz.
copper planes. The package is soldered to a 1 oz.
copper pad on the top of the board. The pad is tied
through thermal vias to the 1 oz. ground plane.
10
3
0.5 in2 PCB Area
2
1
0
0
25
50
75
100
125
150
TA (°C)
Figure 27. SOT223 Maximum Power Dissipation
vs Ambient Temperature
12
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TPS79501DCQ
ACTIVE
SOP
DCQ
6
78
None
Call TI
Call TI
TPS79501DCQR
ACTIVE
SOP
DCQ
6
2500
None
Call TI
Call TI
TPS79516DCQ
ACTIVE
SOP
DCQ
6
78
None
Call TI
Level-3-235C-168 HR
TPS79516DCQR
ACTIVE
SOP
DCQ
6
2500
None
Call TI
Level-3-235C-168 HR
TPS79518DCQ
ACTIVE
SOP
DCQ
6
78
None
Call TI
Level-3-235C-168 HR
TPS79518DCQR
ACTIVE
SOP
DCQ
6
2500
None
Call TI
Level-3-235C-168 HR
TPS79525DCQ
ACTIVE
SOP
DCQ
6
78
None
Call TI
Level-3-235C-168 HR
TPS79525DCQR
ACTIVE
SOP
DCQ
6
2500
None
Call TI
Level-3-235C-168 HR
TPS79530DCQ
ACTIVE
SOP
DCQ
6
78
None
Call TI
Level-3-235C-168 HR
TPS79530DCQR
ACTIVE
SOP
DCQ
6
2500
None
Call TI
Level-3-235C-168 HR
TPS79533DCQ
ACTIVE
SOP
DCQ
6
78
None
Call TI
Level-3-235C-168 HR
TPS79533DCQR
ACTIVE
SOP
DCQ
6
2500
None
Call TI
Level-3-235C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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