LT1010 Fast ±150mA Power Buffer U FEATURES DESCRIPTIO ■ The LT®1010 is a fast, unity-gain buffer that can increase the output capability of existing IC op amps by more than an order of magnitude. This easy-to-use part makes fast amplifiers less sensitive to capacitive loading and reduces thermal feedback in precision DC amplifiers. ■ ■ ■ ■ ■ ■ ■ ■ 20MHz Bandwidth 75V/µs Slew Rate Drives ±10V into 75Ω 5mA Quiescent Current Drives Capacitive Loads > 1µF Current and Thermal Limit Operates from Single Supply ≥ 4.5V Very Low Distortion Operation Available in 8-Pin miniDIP, Plastic TO-220 and Tiny 3mm × 3mm × 0.75mm 8-Pin DFN Packages Designed to be incorporated within the feedback loop, the buffer can isolate almost any reactive load. Speed can be improved with a single external resistor. Internal operating currents are essentially unaffected by the supply voltage range. Single supply operation is also practical. U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ ■ This monolithic IC is supplied in 8-pin miniDIP, plastic TO-220 and 8-pin DFN packages. The low thermal resistance power package is an aid in reducing operating junction temperatures. Boost Op Amp Output Isolate Capacitive Loads Drive Long Cables Audio Amplifiers Video Amplifiers Power Small Motors Operational Power Supply FET Driver , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO Very Low Distortion Buffered Preamplifier R1 1k 3 R2 1M C1 22pF + – 4 R7 50Ω V+ 7 6 LT1056CN8 2 R3 1k 0.4 C2 22pF R6 100Ω IN LT1010CT R4 10k V BOOST OUT – V+ NOTE 1: ALL RESISTORS 1% METAL FILM NOTE 2: SUPPLIES WELL BYPASSED AND LOW ZO V+ –18V LM334 ISET = 2mA V – RSET 33.2Ω 1% R8 100Ω OUTPUT HARMONIC DISTORTION (%) V+ 18V VOUT = 10VP-P RL = 400Ω 0.3 0.2 0.1 0 10 1010 TA01 100 1k 10k FREQUENCY (Hz) 100k 1010 TA02 1010fc 1 LT1010 U U W W W AXI U UU ABSOLUTE PRECO DITIO I G RATI GS (Note 1) Total Supply Voltage .............................................. ±22V Continuous Output Current .............................. ±150mA Input Current (Note 3) ....................................... ±40mA Operating Junction Temperature Range LT1010C ............................................... 0°C to 100°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C 100% Thermal Limit Burn In–LT1010CT U U W PACKAGE/ORDER I FOR ATIO TOP VIEW FRONT VIEW TOP VIEW V+ 1 8 INPUT BIAS 2 7 NC 6 V – 5 NC OUT 3 9 NC 4 V+ 1 8 INPUT BIAS 2 7 NC OUT 3 6 V– NC 4 5 NC V– 5 OUTPUT 4 BIAS 3 V – (TAB) 2 V+ 1 INPUT DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN N8 PACKAGE 8-LEAD PDIP TJMAX = 100°C, θJC = 3°C/W, θJA = 40°C/W EXPOSED PAD (PIN 9) V– CAN BE SOLDERED TO PCB TO REDUCE THERMAL RESISTANCE (NOTE 7) TJMAX = 100°C, θJC = 45°C/W, θJA = 100°C/W TJMAX = 125°C, θJC = 3°C/W, θJA = 50°C/W ORDER PART NUMBER LT1010CN8 ORDER PART NUMBER LT1010CT ORDER PART NUMBER LT1010CDD DD PART MARKING LBWZ T PACKAGE 5-LEAD PLASTIC TO-220 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Note 4. Typical values in curves.) SYMBOL PARAMETER CONDITIONS (Note 4) VOS Output Offset Voltage (Note 4) MIN MAX UNITS 0 –20 150 220 mV mV VS = ±15V, VIN = 0V 20 100 mV IOUT = 0mA IOUT ≤ 150mA ● 0 0 0 250 500 800 µA µA µA ● 0.995 1.00 V/V 5 5 10 10 12 Ω Ω Ω ● IB Input Bias Current AV Large-Signal Voltage Gain ROUT Output Resistance IOUT = ±1mA IOUT = ±150mA ● Slew Rate VS = ±15V, VIN = ±10V, VOUT = ±8V, RL = 100Ω 75 TYP V/µs 1010fc 2 LT1010 ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Note 4. Typical values in curves.) SYMBOL PARAMETER CONDITIONS (Note 4) VSOS+ Positive Saturation Offset IOUT = 0 (Note 5) VSOS– RSAT VBIAS Negative Saturation Offset Saturation Resistance Bias Terminal Voltage MIN MAX UNITS ● 1.0 1.1 V V ● 0.2 0.3 V V ● 22 28 Ω Ω 840 880 mV mV 9 10 mA mA IOUT = 0 (Note 5) IOUT = ±150mA (Note 5) RBIAS = 20Ω (Note 6) ● IS Supply Current IOUT = 0, IBIAS = 0 ● Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: For case temperatures above 25°C, dissipation must be derated based on a thermal resistance of 25°C/W for the T package, 130°C/W for the N8 package and 40°C/W for the DD package for ambient temperatures above 25°C. See Applications Information. Note 3: In current limit or thermal limit, input current increases sharply with input-output differentials greater than 8V; so input current must be limited. Input current also rises rapidly for input voltages 8V above V + or 0.5V below V –. Note 4: Specifications apply for 4.5V ≤ VS ≤ 40V, V – + 0.5V ≤ VIN ≤ V + – 1.5V and IOUT = 0, unless otherwise stated. Temperature range is 0°C ≤ TJ ≤ 100°C, TC ≤ 100°C. 700 560 TYP Note 5: The output saturation characteristics are measured with 100mV output clipping. See Applications Information for determining available output swing and input drive requirements for a given load. Note 6: The output stage quiescent current can be increased by connecting a resistor between the BIAS pin and V +. The increase is equal to the bias terminal voltage divided by this resistance. Note 7: Thermal resistance varies depending upon the amount of PC board metal attached to the pin (Pin 9) of the device. θJA is specified for a certain amount of 1oz copper metal trace connecting to Pin 9 as described in the thermal resistance tables in the Applications Information section. 1010fc 3 LT1010 U W TYPICAL PERFOR A CE CHARACTERISTICS Bandwidth Phase Lag Phase Lag 50 50 50 RL = 200Ω RL = 50Ω 30 20 VIN = 100mVP-P CL 100pF AV = –3dB TJ = 25°C 10 0 0 30 20 10 QUIESCENT CURRENT (mA) 20 RL = 50Ω RL = 200Ω 10 CL = 100pF RS = 50Ω IBIAS = 0 TJ = 25°C 5 2 40 5 10 FREQUENCY (MHz) 20 RL = 50Ω Small-Step Response 10 CL = 100pF RS = 50Ω RBIAS = 20Ω TJ = 25°C 5 2 20 RL = 100Ω TJ = 25°C IBIAS = 0 TJ = 25°C 0 –50 VOLTAGE GAIN (dB) OUTPUT IMPEDANCE (Ω) VOLTAGE CHANGE (mV) OUTPUT 20 Capacitive Loading 10 RS = 50Ω IBIAS = 0 TJ = 25°C 100 INPUT 5 10 FREQUENCY (MHz) 1010 G03 Output Impedance 100 50 RL = 200Ω 1010 G02 1010 G01 150 PHASE LAG (DEGREES) PHASE LAG (DEGREES) FREQUENCY (MHz) 40 10 0 3nF 100pF –10 0.1µF –100 1 0 10 0.1 30 20 TIME (ns) 1 10 FREQUENCY (MHz) Slew Response 400 IBIAS = 0 –5 NEGATIVE –10 RL = 200Ω 300 SLEW RATE (V/µs) OUTPUT VOLTAGE (V) POSITIVE 0 100 Supply Current 80 VS = ±15V 0 ≥ VIN ≥ –10V 15 VS = ±15V RL = 100Ω TJ = 25°C f ≤ 1MHz 1 10 FREQUENCY (MHz) 1010 G06 Negative Slew Rate 20 5 0.1 1010 G05 1010 G04 10 –20 100 SUPPLY CURRENT (mA) –150 RL = 100Ω 200 RL = 50Ω 100 VS = ±15V VIN = ±10V IL = 0 TC = 25°C 60 40 20 RBIAS = 20Ω –15 –20 –50 0 50 150 100 TIME (ns) 200 250 1010 G07 0 0 0 20 10 30 QUIESCENT CURRENT (mA) 40 1010 G08 0 1 2 3 FREQUENCY (MHz) 4 5 1010 G09 1010fc 4 LT1010 U W TYPICAL PERFOR A CE CHARACTERISTICS Output Offset Voltage Input Bias Current 200 150 V + = 38V V – = –2V 100 V + = 2V V – = –38V 50 0 –50 0 VIN = 0 150 V + = 38V – = –2V V 100 V + = 2V V – = –38V 50 50 0 –50 150 100 TEMPERATURE (°C) Input Bias Current 200 0 50 100 TEMPERATURE (°C) VS = ±15V RL = 75Ω 150 TJ = 125°C TJ = 25°C 100 TJ = –55°C 50 0 –150 150 –100 –50 50 100 0 OUTPUT CURRENT (mA) 1010 G10 1010 G10 Voltage Gain 1.000 BIAS CURRENT (µA) VIN = 0 BIAS CURRENT (µA) OFFSET VOLTAGE (mV) 200 1010 G12 Output Resistance 12 IOUT = 0 150 Output Noise Voltage 200 IOUT ≤ 150mA TJ = 25°C OUTPUT RESISTANCE (Ω) VS = 40V GAIN (V/V) 0.999 VS = 4.5V 0.998 NOISE VOLTAGE (nV/√Hz) 10 8 6 4 150 100 RS = 1k 50 RS = 50Ω 2 0 100 50 TEMPERATURE (°C) 0 –50 150 0 100 50 TEMPERATURE (°C) Positive Saturation Voltage SATURATION VOLTAGE (V) SATURATION VOLTAGE (V) Supply Current 4 IL = 150mA 2 IL = 50mA IL = 5mA 1 0 50 100 TEMPERATURE (°C) 150 1010 G16 7 IL = –150mA 3 2 IL = –50mA IL = –5mA 1 0 –50 0 50 100 TEMPERATURE (°C) 10k 1010 G15 Negative Saturation Voltage 4 3 100 1k FREQUENCY (Hz) 10 1010 G14 1010 G13 0 –50 0 150 SUPPLY CURRENT (mA) 0.997 –50 150 1010 G16 VIN = 0 IOUT = 0 IBIAS = 0 TJ = –55°C 6 TJ = 25°C 5 TJ = 125°C 4 3 0 20 10 30 TOTAL SUPPLY VOLTAGE (V) 40 1010 G18 1010fc 5 LT1010 U W TYPICAL PERFOR A CE CHARACTERISTICS Bias Terminal Voltage Total Harmonic Distortion 0.9 0.8 RBIAS = 100Ω RBIAS = 20Ω 0.6 0.5 –50 0 100 50 TEMPERATURE (°C) RL = 50Ω f = 10kHz VS = ±15V TC = 25°C 0.3 0.2 IBIAS = 0 RBIAS = 50Ω 0.1 0 0.1 150 0.8 1010 G22 1000 Peak Output Current TC = 85°C VS = ±15V VOUT = 0 0.4 6 TO-220 4 SINK 0.3 SOURCE 0.2 0.1 0 15 10 100 FREQUENCY (kHz) 0.5 2 10 RL = 100Ω 1010 G21 OUTPUT CURRENT (A) PEAK POWER (W) INUPT CURRENT (mA) –25 5 0 INPUT VOLTAGE (V) 0.2 1 8 –5 RL = 50Ω 100 25 –10 0.4 Peak Power Capability 10 VS = ±15V VOUT = 0 TJ = 25°C –50 –15 0.6 1010 G20 Shorted Input Characteristics 0 IBIAS = 0 VS = ±15V VOUT = ±10V TC = 25°C 0 1 10 OUTPUT VOLTAGE (VP-P) 1010 G19 50 HARMONIC DISTORTION (%) VS = ±20V 0.7 Total Harmonic Distortion 0.4 HARMONIC DISTORTION (%) BIAS TERMINAL VOLTAGE (V) 1.0 1 10 PULSE WIDTH (ms) 100 1010 G23 0 –50 0 100 50 TEMPERATURE (°C) 150 1010 G24 1010fc 6 LT1010 U W U U APPLICATIO S I FOR ATIO General These notes briefly describe the LT1010 and how it is used; a detailed explanation is given elsewhere1. Emphasis here will be on practical suggestions that have resulted from working extensively with the part over a wide range of conditions. A number of applications are also outlined that demonstrate the usefulness of the buffer beyond that of driving a heavy load. idealized buffer with the unloaded gain specified for the LT1010. Otherwise, it has zero offset voltage, bias current and output resistance. Its output also saturates to the internal supply terminals2. V+ VSOS+ IB R′ VOS Design Concept INPUT The schematic below describes the basic elements of the buffer design. The op amp drives the output sink transistor, Q3, such that the collector current of the output follower, Q2, never drops below the quiescent value (determined by I1 and the area ratio of D1 and D2). As a result, the high frequency response is essentially that of a simple follower even when Q3 is supplying the load current. The internal feedback loop is isolated from the effects of capacitive loading by a small resistor in the output lead. BIAS I2 – + A1 INPUT Q1 OUTPUT I1 Q3 V– 1010 AI01 The scheme is not perfect in that the rate of rise of sink current is noticeably less than for source current. This can be mitigated by connecting a resistor between the bias terminal and V +, raising quiescent current. A feature of the final design is that the output resistance is largely independent of the follower quiescent current or the output load current. The output will also swing to the negative rail, which is particularly useful with single supply operation. Equivalent Circuit Below 1MHz, the LT1010 is quite accurately represented by the equivalent circuit shown here for both small- and large-signal operation. The internal element, A1, is an 1010 AI02 Loaded voltage gain can be determined from the unloaded gain, AV, the output resistance, ROUT, and the load resistance, RL, using: A VRL ROUT + RL Maximum positive output swing is given by: + R1 R′ = RSAT – ROUT V– VOUT = Q2 OUTPUT VSOS– V+ D2 ROUT A1 R′ A VL = D1 + ( V + – VSOS+ )RL RSAT + RL The input swing required for this output is: ⎞ ⎛ R + VIN = VOUT + ⎜ 1 + OUT ⎟ – VOS + ∆VOS RL ⎠ ⎝ where ∆VOS is the 100mV clipping specified for the saturation measurements. Negative output swing and input drive requirements are similarly determined. Supply Bypass The buffer is no more sensitive to supply bypassing than slower op amps as far as stability is concerned. The 0.1µF disc ceramic capacitors usually recommended for op amps are certainly adequate for low frequency work. As always, keeping the capacitor leads short and using a 1R. J. Widlar, “Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,” Linear Technology Corp. TP-1, April, 1984. 2See electrical characteristics section for guaranteed limits. 1010fc 7 LT1010 U W U U APPLICATIO S I FOR ATIO ground plane is prudent, especially when operating at high frequencies. without limiting. Because of this, it is capable of power dissipation in excess of its continuous ratings. The buffer slew rate can be reduced by inadequate supply bypass. With output current changes much above 100mA/µs, using 10µF solid tantalum capacitors on both supplies is good practice, although bypassing from the positive to the negative supply may suffice. Normally, thermal overload protection will limit dissipation and prevent damage. However, with more than 30V across the conducting output transistor, thermal limiting is not quick enough to ensure protection in current limit. The thermal protection is effective with 40V across the conducting output transistor as long as the load current is otherwise limited to 150mA. When used in conjunction with an op amp and heavily loaded (resistive or capacitive), the buffer can couple into supply leads common to the op amp causing stability problems with the overall loop and extended settling time. Adequate bypassing can usually be provided by 10µF solid tantalum capacitors. Alternately, smaller capacitors could be used with decoupling resistors. Sometimes the op amp has much better high frequency rejection on one supply, so bypass requirements are less on this supply. Power Dissipation In many applications the LT1010 will require heat sinking. Thermal resistance, junction to still air is 100°C/W for the TO-220 package and 130°C/W for the miniDIP package. Circulating air, a heat sink or mounting the package to a printed circuit board will reduce thermal resistance. In DC circuits, buffer dissipation is easily computed. In AC circuits, signal waveshape and the nature of the load determine dissipation. Peak dissipation can be several times average with reactive loads. It is particularly important to determine dissipation when driving large load capacitance. With AC loading, power is divided between the two output transistors. This reduces the effective thermal resistance, junction to case to 15°C/W for the TO-220 package as long as the peak rating of neither output transistor is exceeded. The typical curves indicate the peak dissipation capabilities of one output transistor. Overload Protection The LT1010 has both instantaneous current limit and thermal overload protection. Foldback current limiting has not been used, enabling the buffer to drive complex loads Drive Impedance When driving capacitive loads, the LT1010 likes to be driven from a low source impedance at high frequencies. Certain low power op amps (e.g., the LM10) are marginal in this respect. Some care may be required to avoid oscillations, especially at low temperatures. Bypassing the buffer input with more than 200pF will solve the problem. Raising the operating current also works. Parallel Operation Parallel operation provides reduced output impedance, more drive capability and increased frequency response under load. Any number of buffers can be directly paralleled as long as the increased dissipation in individual units caused by mismatches of output resistance and offset voltage is taken into account. When the inputs and outputs of two buffers are connected together, a current, ∆IOUT, flows between the outputs: ∆IOUT = VOS1 – VOS2 ROUT1 + ROUT2 where VOS and ROUT are the offset voltage and output resistance of the respective buffers. Normally, the negative supply current of one unit will increase and the other decrease, with the positive supply current staying the same. The worst-case (VIN → V +) increase in standby dissipation can be assumed to be ∆IOUTVT, where VT is the total supply voltage. Offset voltage is specified worst case over a range of supply voltages, input voltage and temperature. It would 1010fc 8 LT1010 U W U U APPLICATIO S I FOR ATIO be unrealistic to use these worst-case numbers above because paralleled units are operating under identical conditions. The offset voltage specified for VS = ±15V, VIN = 0V and TA = 25°C will suffice for a worst-case condition. V+ IS Stability depends upon the RFCF time constant or the closed-loop bandwidth. With an 80kHz bandwidth, ringing is negligible for CL = 0.068µF and damps rapidly for CL = 0.33µF. The pulse response is shown in the graph. IS A1 LT1010 VIN At lower frequencies, the buffer is within the feedback loop so that its offset voltage and gain errors are negligible. At higher frequencies, feedback is through CF, so that phase shift from the load capacitance acting against the buffer output resistance does not cause loop instability. VOUT Pulse Response ∆IOUT CL = 0.068µF 5 IS – ∆IOUT OUTPUT VOLTAGE (V) A2 LT1010 IS + ∆IOUT 1010 AI03 V– Output load current will be divided based on the output resistance of the individual buffers. Therefore, the available output current will not quite be doubled unless output resistances are matched. As for offset voltage, the 25°C limits should be used for worst-case calculations. Parallel operation is not thermally unstable. Should one unit get hotter than its mates, its share of the output and its standby dissipation will decrease. As a practical matter, parallel connection needs only some increased attention to heat sinking. In some applications, a few ohms equalization resistance in each output may be wise. Only the most demanding applications should require matching, and then just of output resistance at 25°C. RF 20k RS VIN + CL = 0.33µF 5 –5 0 50 CF 100pF A2 LT1010 VOUT CL 1010 AI04 100 200 150 TIME (µs) 1010 AI05 Small-signal bandwidth is reduced by CF, but considerable isolation can be obtained without reducing it below the power bandwidth. Often, a bandwidth reduction is desirable to filter high frequency noise or unwanted signals. RF 2k – The inverting amplifier below shows the recommended method of isolating capacitive loads. Noninverting amplifiers are handled similarly. A1 LT1007 –5 0 Isolating Capacitive Loads – 0 RS 2k VIN A1 LT118A + CF 1nF A2 LT1010 VOUT CL 1010 AI06 The follower configuration is unique in that capacitive load isolation is obtained without a reduction in smallsignal bandwidth, although the output impedance of the buffer comes into play at high frequencies. The precision unity-gain buffer above has a 10MHz bandwidth without capacitive loading, yet it is stable for all load capacitance to over 0.3µF, again determined by RFCF. 1010fc 9 LT1010 U W U U APPLICATIO S I FOR ATIO This is a good example of how fast op amps can be made quite easy to use by employing an output buffer. Integrator A lowpass amplifier can be formed just by using large C F in the inverter described earlier, as long as the increasing closed-loop output impedance above the cutoff frequency is not a problem and the op amp is capable of supplying the required current at the summing junction. stage. Feedback is arranged in the conventional manner, although the 68µF-0.01µF combination limits DC gain to unity for all gain settings. For applications sensitive to NTSC requirements, dropping the 25Ω output stage bias value will aid performance. R2 800Ω C1 15pF – A1 HA2625 CI VIN IIN RF 20k A2 LT1010 + VOUT 1010 AI09 R1 100Ω – A1 LT1012 + A2 LT1010 VOUT 1010 AI07 This shows the buffer being used with a wideband amplifier that is not unity-gain stable. In this case, C1 cannot be used to isolate large capacitive loads. Instead, it has an optimum value for a limited range of load capacitances. CF 500pF If the integrating capacitor must be driven from the buffer output, the circuit above can be used to provide capacitive load isolation. As before, the stability with large capacitive loads is determined by RFCF. Wideband Amplifiers This simple circuit provides an adjustable gain video amplifier that will drive 1VP-P into 75Ω. The differential pair provides gain with the LT1010 serving as an output 15V 25Ω 8.2k + BIAS + 22µF 22µF The buffer can cause stability problems in circuits like this. With the TO-220 packages, behavior can be improved by raising the quiescent current with a 20Ω resistor from the bias terminal to V +. Alternately, devices in the miniDIP can be operated in parallel. It is possible to improve capacitive load stability by operating the buffer class A at high frequencies. This is done by using quiescent current boost and bypassing the bias terminal to V – with more than 0.02µF. TYPICAL SPECIFICATIONS 1VP-P INTO 75Ω AT A = 2 0.5dB TO 10MHz 3dB DOWN AT 16MHz AT A = 10 0.5dB TO 4MHz –3dB = 8MHz OUTPUT (75Ω) LT1010 R2 1.6k – A1 HA2625 INPUT + A2 LT1010 OUTPUT 1010 AI10 R1 400Ω –15V INPUT Q1 PEAKING 5pF to 25pF 900Ω Q2 1k GAIN SET Q1, Q2: 2N3866 5.1k –15V + 0.01µF 68µF 1010 AI08 Putting the buffer outside the feedback loop as shown here will give capacitive load isolation, with large output capacitors only reducing bandwidth. Buffer offset, referred to the op amp input, is divided by the gain. If the load resistance is known, gain error is determined by the output resistance tolerance. Distortion is low. 1010fc 10 LT1010 U W U U APPLICATIO S I FOR ATIO current boost. The appearance is always worse with fast rise signal generators than in practical applications. R3 800Ω C1 20pF – INPUT R4 39Ω A2 LT1010 A1 HA2625 Track and Hold OUTPUT 1 + R1 50Ω R2 200Ω R5 39Ω A3 LT1010 OUTPUT 2 1010 AI11 The 5MHz track and hold shown here has a 400kHz power bandwidth driving ±10V. A buffered input follower drives the hold capacitor, C4, through Q1, a low resistance FET switch. The positive hold command is supplied by TTL logic with Q3 level shifting to the switch driver, Q2. The output is buffered by A3. The 50Ω video line splitter here puts feedback on one buffer with the others slaved. Offset and gain accuracy of slaves depend on their matching with master. When the gate is driven to V – for HOLD, it pulls charge out of the hold capacitor. A compensating charge is put into the hold capacitor through C3. The step into hold is made independent of the input level with R7 and adjusted to zero with R10. When driving long cables, including a resistor in series with the output should be considered. Although it reduces gain, it does isolate the feedback amplifier from the effects of unterminated lines which present a resonant load. Since internal dissipation can be quite high when driving fast signals into a capacitive load, using a buffer in a power package is recommended. Raising buffer quiescent current to 40mA with R3 improves frequency response. When working with wideband amplifiers, special attention should always be paid to supply bypassing, stray capacitance and keeping leads short. Direct grounding of test probes, rather than the usual ground lead, is absolutely necessary for reasonable results. This circuit is equally useful as a fast acquisition sample and hold. An LT1056 might be used for A3 to reduce drift in hold because its lower slew rate is not usually a problem in this application. The LT1010 has slew limitations that are not obvious from standard specifications. Negative slew is subject to glitching, but this can be minimized with quiescent Current Sources OTHER SLAVES A standard op amp voltage to current converter with a buffer to increase output current is shown here. As usual, V+ + A2 LT1010 A1 LT118A – C1 50pF R5 1k HOLD R6 1k OUTPUT + D2* 6V A4 LT118A D1 HP2810 Q3 2N2907 A3 LT118A C3 100pF R2 2k C2 150pF – Q1 2N5432 S D R4 2k Q2 2N2222 C4 1nF R8 5k C5 10pF R7 200k V– – INPUT R3 20Ω + R1 2k R9 10k R10 50k R11 6.2k 1010 AI12 *2N2369 EMITTER BASE JUNCTION 1010fc 11 LT1010 U W U U APPLICATIO S I FOR ATIO excellent matching of the feedback resistors is required to get high output resistance. Output is bidirectional. R1 100k 0.01% R2 100k 0.01% IOUT = A1 LT118A R2(V2 – V1) R1R4 R2 2k C1 1nF – R3 2Ω A2 LT1010 + OUTPUT R4 2k 0.1% V1 IOUT + R3 100k 0.01% 1010 AI13 V2 R4 100k 0.01% A2 LT1010 IOUT = VIN – 2 + 7 C2 10pF D2 1N457 R7 99.8k 0.1% VV 1V/V R6 99.8k 0.1% VI 10mA/V 1010 AI15 This circuit uses an instrumentation amplifier to eliminate the matched resistors. The input is not high impedance and must be driven from a low impedance source like an op amp. Reversal of output sense can be obtained by grounding Pin 7 of the LM163 and driving Pin 5. 6 R1 2k R5 2k 0.1% A3 LT118A + A2 LT1010 – R4 10Ω 0.1% – A1 LT1012 D1 1N457 3 A1 LM163 ×10 5 VIN 10R1 enables the current regulator to get control of the output current from the buffer current limit within a microsecond for an instantaneous short. In the voltage regulation mode, A1 and A2 act as a fast voltage follower using the capacitive load isolation technique described earlier. Load transient recovery as well as capacitive load stability are determined by C1. Recovery from short circuit is clean. Bidirectional current limit can be obtained by adding another op amp connected as a complement to A3. R1 10Ω 0.1% IOUT 1010AI14 Output resistances of several megohms can be obtained with both circuits. This is impressive considering the ±150mA output capability. High frequency output characteristics will depend on the bandwidth and slew rate of the amplifiers. Both these circuits have an equivalent output capacitance of about 30nF. Supply Splitter Dual supply op amps and comparators can be operated from a single supply by creating an artificial ground at half the supply voltage. The supply splitter shown here can source or sink 150mA. The output capacitor, C2, can be made as large as necessary to absorb current transients. An input capacitor is also used on the buffer to avoid high frequency instability that can be caused by high source impedance. V+ Voltage/Current Regulator This circuit regulates the output voltage at VV until the load current reaches a value programmed by VI. For heavier loads, it is a precision current regulator. With output currents below the current limit, the current regulator is disconnected from the loop by D1 with D2 keeping its output out of saturation. This output clamp C3 0.1µF R1 10k A1 LT1010 C1 1nF R2 10k V +/2 C2 0.01µF 1010 AI16 1010fc 12 LT1010 U W U U APPLICATIO S I FOR ATIO High Current Booster 5V 15pF 10k 15V 0.18Ω + 68pF 22µF 10k INPUT 1k Q3 2N3906 33Ω Q1 MJE2955 – LT1056 OUTPUT LT1010 + OUTPUT 10M –5V 0.1µF 4 Q2 2N2222 10M 100Ω 10k 6 0.01µF 7 2000pF –5V A1 LTC1050 3 2 5V 1k 0.1µF 1010 AI18 signal. The amplified difference between these signals is used to set Q2’s bias, and hence, Q1’s channel current. This forces Q1’s VGS to whatever voltage is required to match the circuit’s input and output potentials. The 2000pF capacitor at A1 provides stable loop compensation. The RC network in A1’s output prevents it from seeing high speed edges coupled through Q2’s collector-base junction. A2’s output is also fed back to the shield around Q1’s gate lead, bootstrapping the circuit’s effective input capacitance down to less than 1pF. Gain-Trimmable Wideband FET Amplifier Q2 MJE3055 Q4 2N3904 1k –15V 1010 AI17 22µF B A2 LT1010 100Ω 100Ω 33Ω A – The 33Ω resistors sense the LT1010’s supply current with the grounded 100Ω resistor supplying a load for the LT1010. The voltage drop across the 33Ω resistors biases Q1 and Q2. Another 100Ω value closes a local feedback loop, stabilizing the output stage. Feedback to the LT1056 control amplifier is via the 10k value. Q3 and Q4, sensing across the 0.18Ω units, furnish current limiting at about 3.3A. Q1 2N5486 INPUT + The circuit below uses a discrete stage to get 3A output capacity. The configuration shown provides a clean, quick way to increase LT1010 output power. It is useful for high current loads such as linear actuator coils in disk drives. 0.18Ω + HEAT SINK OUTPUT TRANSISTORS Wideband FET Input Stabilized Buffer The figure below shows a highly stable unity-gain buffer with good speed and high input impedance. Q1 and Q2 constitute a simple, high speed FET input buffer. Q1 functions as a source follower with the Q2 current source load setting the drain-source channel current. The LT1010 buffer provides output drive capability for cables or whatever load is required. Normally, this open-loop configuration would be quite drifty because there is no DC feedback. The LTC®1050 contributes this function to stabilize the circuit. It does this by comparing the filtered circuit output to a similarly filtered version of the input A potential difficulty with the previous circuit is that the gain is not quite unity. The figure labeled A on the next page maintains high speed and low bias while achieving a true unity-gain transfer function. This circuit is somewhat similar except that the Q2-Q3 stage takes gain. A2 DC stabilizes the input-output path and A1 provides drive capability. Feedback is to Q2’s emitter from A1’s output. The 1k adjustment allows the gain to be precisely set to unity. With the LT1010, output stage slew and full power bandwidth (1VP-P) are 100V/µs and 10MHz respectively. – 3dB bandwidth exceeds 35MHz. At A = 10 (e.g., 1k adjustment set at 50Ω), full power bandwidth stays at 10MHz while the –3dB point falls to 22MHz. With the optional discrete stage, slew exceeds 1000V/µs and full power bandwidth (1VP-P) is 18MHz. – 3dB bandwidth is 58MHz. At A = 10, full power is available to 10MHz, with the – 3dB point at 36MHz. 1010fc 13 LT1010 U W U U APPLICATIO S I FOR ATIO Figures A and B show response with both output stages. The LT1010 is used in Figure A (Trace A = input, Trace B = output). Figure B uses the discrete stage and is slightly faster. Either stage provides more than adequate performance for driving video cable or data converters and the LT1012 maintains DC stability under all conditions. Thermal Considerations for the MiniDIP Package The miniDIP package requires special thermal considerations since it is not designed to dissipate much power. Be aware that for applications requiring large output currents, another package should be used. Gain-Trimmable Wideband FET Amplifier 15V 10pF 1k 470Ω Q3 2N3906 Q1 2N5486 INPUT Q2 2N3904 15V A 0.01µF B A2 LT1010 OUTPUT 3k 1k 10M 10k 2k 1k GAIN ADJ 300Ω 2N3904 3Ω A 50Ω 5.6k 3k B 10M 3Ω 2N3906 0.1µF –15V + A1 LT1012 3k 0.1µF 1k –15V – 0.002µF 1010 AI19 (A) (B) A = 0.2V/DIV B = 0.2V/DIV A = 0.2V/DIV B = 0.2V/DIV 1010 AI20 1010 AI21 10ns/DIV 10ns/DIV Figure A. Waveforms Using LT1010 Figure B. Waveforms Using Discrete Stage 1010fc 14 LT1010 U W U U APPLICATIO S I FOR ATIO Typical thermal calculations for the miniDIP package are detailed in the following paragraphs. For 4.8mA supply current (typical at 50°C, 30V supply voltage—see supply current graphs) to the LT1010 at ±15V, PD = power dissipated in the part is equal to: (30V)(0.0048A) = 0.144W The rise in junction is then: (0.144W)(130°C/W—This is θJA for the N package) = 18.7°C. This means that the junction temperature in 50°C ambient air without driving any current into a load is: 18.7°C + 50°C = 68.7°C Using the LT1010 to drive 8V DC into a 200Ω load using ±15V power supplies dissipates PD in the LT1010 where: PD = ( V+ )( ) – VOUT VOUT to be dissipated, resulting in another (0.130W) (0.130°C/W) = 16.9°C rise in junction temperature to 89°C + 16.9°C = 105.9°C. Caution: This exceeds the maximum operating temperature of the device. Thermal Resistance of DFN Package For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following table lists thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper. Table 1. DFN Measured Thermal Resistance COPPER AREA RL 15V – 8 V 8 V TOPSIDE BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500 sq mm 2500 sq mm 2500 sq mm 40°C/W 1000 sq mm 2500 sq mm 2500 sq mm 45°C/W 200Ω 225 sq mm 2500 sq mm 2500 sq mm 50°C/W 100 sq mm 2500 sq mm 2500 sq mm 62°C/W ( = )( ) = 0.280W This causes the LT1010 junction temperature to rise another (0.280W)(0.130°C/W) = 36.4°C. This heats the junction to 68.7°C + 36.4°C = 105.1°C. Caution: This exceeds the maximum operating temperature of the device. An example of 1MHz operation further shows the limitations of the N (or miniDIP) package. For ±15V operation: PD at IL = 0 at 1MHz* = (10mA)(30V) = 0.30W This power dissipation causes the junction to heat from 50°C (ambient in this example) to 50°C + (0.3W) (130°C/W) = 89°C. Driving 2VRMS of 1MHz signal into a 200Ω load causes an additional ⎛ 2V ⎞ PD = ⎜ ⎟ • 15 – 2 = 0.130W ⎝ 200Ω ⎠ ( ) For the DFN package, the thermal resistance junction-tocase (θJC), measured at the exposed pad on the back of the die, is 16°C/W. Continuous operation at the maximum supply voltage and maximum load current is not practical due to thermal limitations. Transient operation at the maximum supply is possible. The approximate thermal time constant for a 2500sq mm 3/32" FR-4 board with maximum topside and backside area for one ounce copper is 3 seconds. This time constant will increase as more thermal mass is added (i.e. vias, larger board, and other components). For an application with transient high power peaks, average power dissipation can be used for junction temperature calculations as long as the pulse period is significantly less than the thermal time constant of the device and board. *See Supply Current vs Frequency graph. 1010fc 15 LT1010 W W SCHE ATIC DIAGRA (Excluding protection circuits) R6 15Ω Q11 R5 1.5k V+ R10 200Ω R7 300Ω Q18 BIAS Q17 R2 1k Q5 R3 1k Q6 Q7 R4 1k Q20 Q21 R12 3k R14 7Ω OUTPUT Q12 R8 1k Q15 Q2 Q4 R1 4k Q1 R11 200Ω C1 30pF Q8 Q3 Q19 R13 200Ω Q13 Q9 Q10 Q14 Q22 R9 Q16 4k INPUT 1010 SD V– W U U DEFI ITIO OF TER S Output Offset Voltage: The output voltage measured with the input grounded (split supply operation). Input Bias Current: The current out of the input terminal. Saturation Resistance: The ratio of the change in output saturation voltage to the change in current producing it, going from no load to full load.* Large-Signal Voltage Gain: The ratio of the output voltage change to the input voltage change over the specified input voltage range.* Slew Rate: The average time rate of change of output voltage over the specified output range with an input step between the specified limits. Output Resistance: The ratio of the change in output voltage to the change in load current producing it.* Bias Terminal Voltage: The voltage between the bias terminal and V +. Output Saturation Voltage: The voltage between the output and the supply rail at the limit of the output swing toward that rail. Supply Current: The current at either supply terminal with no output loading. *Pulse measurements (~1ms) as required to minimize thermal effects. Saturation Offset Voltage: The output saturation voltage with no load. 1010fc 16 LT1010 U PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 3.00 ±0.10 (4 SIDES) 0.38 ± 0.10 8 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD) DFN 1203 0.200 REF 0.75 ±0.05 0.00 – 0.05 4 0.25 ± 0.05 1 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 1010fc 17 LT1010 U PACKAGE DESCRIPTIO N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.889 –0.381 ) .045 – .065 (1.143 – 1.651) .130 ± .005 (3.302 ± 0.127) .065 (1.651) TYP .100 (2.54) BSC .120 (3.048) .020 MIN (0.508) MIN .018 ± .003 (0.457 ± 0.076) N8 1002 NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1010fc 18 LT1010 U PACKAGE DESCRIPTIO T Package 5-Lead Plastic TO-220 (Standard) (Reference LTC DWG # 05-08-1421) .390 – .415 (9.906 – 10.541) .165 – .180 (4.191 – 4.572) .147 – .155 (3.734 – 3.937) DIA .045 – .055 (1.143 – 1.397) .230 – .270 (5.842 – 6.858) .460 – .500 (11.684 – 12.700) .570 – .620 (14.478 – 15.748) .330 – .370 (8.382 – 9.398) .620 (15.75) TYP .700 – .728 (17.78 – 18.491) SEATING PLANE .152 – .202 .260 – .320 (3.861 – 5.131) (6.60 – 8.13) .095 – .115 (2.413 – 2.921) .155 – .195* (3.937 – 4.953) .013 – .023 (0.330 – 0.584) BSC .067 (1.70) .028 – .038 (0.711 – 0.965) .135 – .165 (3.429 – 4.191) * MEASURED AT THE SEATING PLANE T5 (TO-220) 0801 1010fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LT1010 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1206 250mA, 60MHz Current Feedback Amplifier 900V/µs, Excellent Video Characteristics LT1210 1.1A, 35MHz Current Feedback Amplifier 900V/µs Slew Rate, Stable with Large Capacitive Loads LT1795 Dual 500mA, 50MHz CFA 500mA IOUT ADSL Driver LT1886 Dual 700MHz, 200mA Op Amp DSL Driver 1010fc 20 Linear Technology Corporation LT/LWI 0806 REV C • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 1991