MICREL SY87702LHI

Micrel, Inc.
3.3V 28Mbps-2.5Gbps AnyRate®
CLOCK AND DATA RECOVERY
FEATURES
SY87702L
SY87702L
DESCRIPTION
■ 3.3V power supply
■ Complies with Bellcore, ITU/CCITT and ANSI
specifications for applications such as OC-1, OC-3,
OC-12, OC-48*, and ATM
■ Compatible with FDDI, Gigabit Ethernet, Fibre
Channel, 2X Fibre Channel, SMPTE 259 and 292, and
proprietary applications
■ Low power
■ Clock and data recovery from 28Mbps up to 2.5Gbps
NRZ data stream
■ Selectable reference frequencies via programmable
multiplier
■ Differential PECL and CML high-speed serial outputs
■ Line receiver input: no external buffering needed
■ Link fault indication
■ 100K ECL compatible I/O
■ Available in 64-Pin EP-TQFP package
■ Product obsolete. Use SY87721L for new designs
The SY87702L is a complete Clock Recovery and Data
retiming integrated circuit for data rates from 28Mbps up to
2.5Gbps NRZ. The device is ideally suited for SONET/SDH/
ATM, Fibre Channel, and Gigabit Ethernet applications, as
well as other high-speed data transmission applications.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming data
stream. The VCO center frequency is controlled by the
reference clock frequency and the selected divide ratio. Onchip clock generation is performed through the use of a
frequency multiplier PLL and can be used as a Clock
Multiplier Unit (CMU). The integrated CMU can provide this
clock signal at the TCLK outputs. Additionally, the TCLK
output can be selected to provide a copy of the RCLK
frequency.
For SONET/SDH applications, the SY87702L includes a
Link Fault Detection circuit. This circuit, enabled by the output
of an optical module driving the CD input low, causes the
recovery PLL of the SY87702L to lock to the reference
clock's multiplied frequency under Loss-of-Signal conditions.
This low jitter clock is provided at the RCLK outputs and is
at the same frequency as that provided at the TCLK output.
*Meets OC-48 Jitter Tolerance and Transfer
APPLICATIONS
■ Transponders and section repeaters
■ Multiplexer's: access, add drop (ADM), and terminal
(TM)
■ SONET/SDH/ATM: -based transmission systems,
modules, and test equipment
■ Terabit routers and broadband cross-connects
■ Fibre optic test equipment
■ HDTV switching and transmission
AnyRate® is a registered trademark of Micrel, Inc.
M9999-072706
[email protected] or (408) 955-1690
1
Rev.: D
Amendment: /0
Issue Date: July 2006
Micrel, Inc.
SY87702L
PACKAGE/ORDERING INFORMATION
RDIN–
RDIN+
LFIN
NC
NC
VCCO
VCC
GND
GND
VCC
GND
CD
FREQSEL3
VCOSEL2
FREQSEL2
FREQSEL1
Ordering Information(1)
VCOSEL1
1
48
PLLRN+
PLLRN–
NC
2
47
3
46
GND
ENPECL
RDOUTE+
4
45
PLLRW+
PLLRW–
5
44
6
43
NC
VCCA
7
42
8
64-Pin
EPAD-TQFP
41
GNDA
9
PLLSW–
PLLSW+
10
11
38
NC
PLLSN–
12
37
13
36
PLLSN+
NC
14
35
NC
16
40
39
15
Package Operating
Type
Range
Part Number
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Lead
Finish
SY87702LHI
H64-1
Industrial
SY87702LHI
Sn-Pb
RDOUTE–
SY87702LHITR(2)
H64-1
Industrial
SY87702LHI
Sn-Pb
RDOUTC+
RDOUTC–
SY87702LHG(3)
H64-1
Industrial
SY87702LHG with
NiPdAu
Pb-Free bar line indicator Pb-Free
SY87702LHGTR(2, 3)
H64-1
Industrial
SY87702LHG with
NiPdAu
Pb-Free bar line indicator Pb-Free
VCCO
RCLKE+
RCLKE–
RCLKC+
RCLKC–
VCCO
TCLKE+
TCLKE–
TCLKC+
TCLKC–
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
GND
REFCLK+
VCC
REFCLK–
NC
NC
GND
VCC
GND
NC
GND
CLKSEL
DIVSEL3
DIVSEL2
DIVSEL1
NC
64-Pin EPAD TQFP (H63-1)
M9999-072706
[email protected] or (408) 955-1690
Package
Marking
2
Micrel, Inc.
SY87702L
SYSTEM BLOCK DIAGRAM
Code Group Data
(4, 5, 8, 10, Bits)
TX Data Stream
Optical
Module
TXCLK
RX Data
Stream
SY877XXL
Mux/Demux
Carrier Detect
Serial
EEPROM
SY877XXL
Frame
Detector
SY877XXL
Programmable
Protocol
Selector
Reference
Timing (8)
M9999-072706
[email protected] or (408) 955-1690
Note:
Add second SY877XXL
for 16 or 20 bit parallel
input and output.
Align
Ref Sel CD Lock
RX Clock
RX Data
SY87702L
CDR/CMU
3
Code Group Strobe
Code Group
Rate Clock
Alignment
Detect
Micrel, Inc.
SY87702L
NC*
PLLRW–
PLLRW+
PLLRN+
PLLRN–
FUNCTIONAL BLOCK DIAGRAM
RDOUTE+
RDOUTE–
RDIN+
RDIN–
Phase
Detector
RDOUTC+
Mux
Charge
Pump
N/W
VCO
N/W1/W2/W3
RDOUTC–
Phase/
Frequency
Detector
RCLKE+
RCLKE–
RCLKC+
RCLKC–
Link Fault
Detector
CD
LFIN
REFCLK+
Phase/
Frequency
Detector
Charge
Pump
N/W
Mux
REFCLK–
VCO
N/W1/W2/W3
TCLKE+
Divide by 1, 2,
4, 8, 10, 16,
20, 32
TCLKE–
TCLKC+
* Do not connect.
M9999-072706
[email protected] or (408) 955-1690
4
CLKSEL
ENPECL
FREQSEL3
FREQSEL2
FREQSEL1
PLLSW–
PLLSW+
PLLSN+
PLLSN–
VCOSEL2
VCOSEL1
DIVSEL2
DIVSEL1
DIVSEL3
TCLKC–
Micrel, Inc.
SY87702L
PIN NAMES
FUNCTIONAL DESCRIPTION
INPUTS
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The clock is
phase aligned by a PLL so that it samples the data in the
center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability, without incoming data, is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the multiplied frequency
of the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30µs data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
RDIN± [Serial Data Input] – Differential PECL
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN– pin has an
internal 75KΩ resistor tied to VCC.
REFCLK± [Reference Clock] – Differential PECL
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 325MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK– pin has an
internal 75KΩ resistor tied to VCC.
CD [Carrier Detect] – PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW, the
data on the RDIN input will be internally forced to a constant
LOW, the data output RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW, and the clock
recovery PLL forced to lock onto the clock frequency
generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select] – TTL Inputs
These inputs select the VCO frequency range via either
one of three wide-band PLLs, or a SONET/SDH specific
narrow-band PLL. Only the selected PLL is enabled. All
other PLL’s are disabled. Please refer to Table 1.
VCOSEL1
0
0
1
1
VCOSEL2
0
1
0
1
Table. 1
M9999-072706
[email protected] or (408) 955-1690
5
Choice
SONET/SDH
1.8 to 2.5GHz
1.25 to 1.8GHz
0.650 to 1.30GHz
Micrel, Inc.
SY87702L
FREQSEL1, ..., FREQSEL3 [Frequency Select] – TTL
Inputs
These inputs select the output clock frequency range, as
shown in Table 2.
FREQSEL1
0
0
FREQSEL2
0
0
FREQSEL3
0
1
VCOCLK
Divider
1
2
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
4
6
8
12
16
24
OUTPUTS
LFIN [Link Fault Indicate] – O.C. TTL Output
This output indicates the status of the input data stream
RDIN. LFIN will go HIGH if CD is HIGH and RDIN is within
the frequency range of the Receive PLL (as per ALRSEL).
LFIN is an asynchronous output.
RDOUTE± [Receive Data Out] – Differential PECL
These ECL 100K outputs represent the recovered data
from the input data stream (RDIN). This recovered data is
sampled on the falling edge of RCLK.
RDOUTC± [Receive Data Out] – Differential CML
This is the CML version of RDOUTE±.
RCLKE± [Receive Clock Out] – Differential PECL
These ECL 100K outputs represent the recovered clock
used to sample the recovered data (RDOUT).
Table 2.
RCLKC± [Receive Clock Out] – Differential CML
This is the CML version of RCLKE±.
DIVSEL1, ..., DIVSEL3 [Divider Select] – TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in Table 3. Please note that the divide by 32
selection, “011”, is only available for use when FREQSEL
are set to “000.”
TCLKE± [Transmit Clock Out] – Differential PECL
These ECL 100K outputs represent either the recovered
clock (CLKSEL = HIGH) used to sample the recovered data
(RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
REFCLK
DIVSEL1
0
0
0
0
1
1
1
1
DIVSEL2
0
0
1
1
0
0
1
1
DIVSEL3
0
1
0
1
0
1
0
1
TCLKC± [Transmit Clock Out] – Differential CML
This is the CML version of TCLKE±.
Multiplier
1
2
4
32
8
10
16
20
INPUTS/OUTPUTS
PLLSN+, PLLSN– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis narrowband PLL.
PLLSW+, PLLSW– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis wide-band
PLLs.
Table 3.
PLLRN+, PLLRN– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery narrowband PLL.
CLKSEL [Clock Select] – TTL Input
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
PLLRW+, PLLRW– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery wide-band
PLLs.
ENPECL [Enable PECL] – TTL Input
This input, when HIGH (ENPECL = 1), enables the
differential PECL outputs TCLKE± RDOUTE±, and RCLKE±.
It also disables the CML outputs, by setting TCLKC+,
RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC–,
RDOUTC–, and RCLKC– logic LOW.
When set LOW (ENPECL = 0), this signal enables the
differential CML outputs TCLKC±, RDOUTC±, and RCLKC±.
It also disables the PECL outputs by setting TCLKE+,
RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE–,
RDOUTE–, and RCLKE– logic LOW.
M9999-072706
[email protected] or (408) 955-1690
OTHERS
VCC
VCCO
VCCA
GND
GNDA
NC
6
Supply Voltage
Output Supply Voltage
Analog Supply Voltage
Ground
Analog Ground
These pins are for factory test, and are to be
left unconnected during normal use.
Micrel, Inc.
SY87702L
DESCRIPTION
General
The SY87702L is a complete clock and data recovery
circuit, capable of dealing with NRZ data rates from 28Mbps
through to 2.5Gbps. A reference PLL is used as a frequency
synthesizer, both to multiply a clock to the desired transmit
rate, and to train the recovery PLL in preparation for actual
data recovery.
ranges. However, to extend the range of the device, the
output of the VCO may be divided down.
In the case of the two highest frequency VCO, this divisor
is always set to 1. For the lowest frequency VCO, the
FREQSEL pins select which divisor, and hence, which range
of frequencies the VCO will work over.
In addition, for SONET/SDH applications, there is a narrow
band, extremely low jitter PLL. It also uses the FREQSEL
divisor to choose the correct SONET/SDH frequency.
The various combinations of FREQSEL and VCOSEL
are not arbitrary, but are limited to the subset shown in
Table 4, where the range column indicates frequency in
Mbps.
VCO Selection
SY87702L has four complete VCO circuits. Depending
of the application and the frequency range, any one of
these four perform data recovery.
As indicated by the VCO selection table, there are three
general purpose VCOs, covering one of three frequency
VCOSEL1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
VCOSEL2
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
FREQSEL1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
FREQSEL2
0
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
FREQSEL3
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
Range (Mbps)
2488 (OC48)
1244
622 (OC12)
311
155 (OC3)
1800–2500
900–1250(1)
1250–1800
650–1300(2)
325–650(3)
163–325
109–216
82–162
55–108
41–81
28–54
Table 4.(4)
NOTES:
1. Suggested range for Fibre Channel applications.
2. REFCLK multiplier of 2 is not allowed in this range.
3. REFCLK multiplier of 1 is not allowed in this range.
4. Combinations of VCOSEL and FREQSEL other then those in this table result in undefined behavior, and should not be
used.
M9999-072706
[email protected] or (408) 955-1690
7
Micrel, Inc.
SY87702L
LOOP FILTER COMPONENTS(1)
CML OUTPUT DIAGRAM
VCC
R1
C1
100Ω
VCC
100Ω
100Ω
100Ω
100Ω
PLLSN+
or
PLLSW+
PLLSN–
or
PLLSW–
SY87702L
R1 = 1.2kΩ
C1 = 1.0µF (X7R Dielectric)
Figure 1. R1 Filter Component
Figure 3. 50Ω Load CML Output
R2
VCC
C2
100Ω
PLLRN+
or
PLLRW+
PLLRN–
or
PLLRW–
100Ω
200Ω
R2 = 1.8kΩ
C2 = 1.0µF (X7R Dielectric)
SY87702L
Figure 2. R2 Filter Component
NOTE:
1. Suggested Values. Values may vary for different applications.
Figure 4. 100Ω Load CML Output
TIMING WAVEFORMS
tCPWL
tCPWH
REFCLK±
tDV
tDH
RDOUT
tODC
tODC
RCLK
M9999-072706
[email protected] or (408) 955-1690
8
Micrel, Inc.
SY87702L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Rating
Unit
VCC
Power Supply Voltage
–0.5 to +7.0
V
VIN
Input Voltage
–0.5 to VCC
V
IOUT
ECL Output Current
50
100
mA
ICMLOUT
CML Output Current
30
mA
Tstore
Storage Temperature Range
–65 to +150
°C
TA
Operating Temperature Range
–40 to +85
°C
–Continuous
–Surge
NOTE:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Power Supply Voltage
3.15
3.3
3.45
V
ICC
Power Supply Current
—
400
—
mA
Condition
100K PECL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
VIH
Input HIGH Voltage
VCC – 1.165
—
VCC – 0.880
V
VIL
Input LOW Voltage
VCC – 1.810
—
VCC – 1.475
V
IIL
Input LOW Current
0.5
—
—
µA
VIN = VIL(Min)
VOH
Output HIGH Voltage
VCC – 1.075
—
VCC – 0.830
V
50Ω to VCC –2V
VOL
Output LOW Voltage
VCC – 1.860
—
VCC – 1.570
V
50Ω to VCC –2V
Condition
CML DC ELECTRICAL CHARACTERISTICS(1)
VCC = VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
Symbol
Parameter
Min.
Typ.
Max.
Unit
VOH
Output HIGH Voltage
—
VCC – 0.025
—
V
VOL
Output LOW Voltage
—
VCC – 0.400
VCC – 0.200
—
V
100Ω Environment
50Ω Environment
NOTE:
1. Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in the 100Ω environment
and a 200mV swing in the 50Ω environment. Refer to the “CML Output” diagram for more details.
M9999-072706
[email protected] or (408) 955-1690
9
Micrel, Inc.
SY87702L
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
VIH
Input HIGH Voltage
2.0
—
—
V
VIL
Input LOW Voltage
—
—
0.8
V
IIH
Input HIGH Current
—
—
—
—
+20
+100
µA
µA
VIN = 2.7V, VCC = Max.
VIN = VCC, VCC = Max.
IIL
Input LOW Current
—
—
–300
µA
VIN = 0.5V, VCC = Max.
IOLK
Output Leakage Current
—
—
500
µA
VOUT = VCC
VOL
Output LOW Voltage
—
—
0.5
V
IOL = 4mA
AC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
Symbol
Parameter
Min.
Typ.
Max.
Unit
—
—
0.010
UI rms
1000
—
—
ppm
Acquisition Lock Time
—
15
—
µs
RDIN Maximum Data Rate
2.5
—
—
Gbps
REFCLK Maximum Frequency
—
—
325
MHz
tCPWH
REFCLK Pulse Width High
1.2
—
—
ns
tCPWL
REFCLK Pulse Width Low
1.2
—
—
ns
tIRF
REFCLK Input Rise/Fall Time
(20% to 80%)
—
—
1.0
ns
tODC
Output Duty Cycle (RCLK/TCLK)
45
—
55
% of UI
tRE
tFE
ECL Output Rise/Fall Time
(20% to 80%)
—
200
300
ps
50Ω to VCC–2V
tRC
tFC
CML Output Rise/Fall Time
(20% to 80%)
—
65
120
ps
No Load
tDV
Data Valid
100
—
—
ps
tDH
Data Hold
100
—
—
ps
RCLK, TCLK Output
Jitter(1)
Lock Range/Training Range
NOTE:
1. Except at OC-48.
M9999-072706
[email protected] or (408) 955-1690
10
Condition
REFCLK Multiplier = 16
> 25% transition density
Micrel, Inc.
SY87702L
EVALUATION BOARD SCHEMATIC
L2
D2
1
3
5
C3
D3
RDIN+: FORCE
RDIN+: SENSE
NC: PIN 52
NC: PIN 53
VEE: PIN 56
VCC
VCC
49
50
51
52
R16,
5kΩ
RDIN–
RDIN+
LFIN
NC
VCC
GND
GND
53 NC
54 VCCO
55
56
57
C8
PLLRN+
JP2
ENPECL
3 PLLRN–
4 NC
RDOUTE+
RDOUTE–
5 PLLRW+
C42
6
PLLRW–
7 NC
RDOUTC+
RDOUTC–
VCCO
RCLKE+
SY87702L
VEE: PIN 48
VEE
47
46
RDOUTE+
45
RDOUTE–
44
RDOUTC+
43
RDOUTC–
42
VCCO: PIN 42
41
RCLKE+
RCLKE– 40
RCLKE–
10 PLLSW–
C43
11
PLLSW+
12 NC
RCLKC+ 39
RCLKC+
13 PLLSN–
C44
14
PLLSN+
15
NC
16
NC
TCLKE+ 36
TCLKE– 35
RCLKC– 38
VCCO
RCLKC–
37
VCCO: PIN 37
TCLKE+
TCLKE–
TCLKC+ 34
TCLKC– 33
TCLKC+
TCLKC–
GND
REFCLK–
VCC
NC
NC
GND
VCC
GND
GND
CLKSEL
32
31
30
29
28
27
26
25
24
23
22
NC 21
DIVSEL3 20
DIVSEL2 19
NC 17
DIVSEL1 18
REFCLK+
VCC
VEE: PIN 57
R10
VCC
C7
R23, 5kΩ
R22, 5kΩ
R21, 5kΩ
R20, 5kΩ
R19, 5kΩ
VEE
R18, 5kΩ
SW DIP-6
R9
R17,
1.7kΩ
GND 48
8 VCCA
9 GNDA
12
11
10
9
8
7
58
1
2
3
4
5
6
GND
S3
59
C6
VCC: PIN 58
VEE: PIN 59
R8
CD
C41
C5
2
4
6
8
10
12
VCOSEL1
2
60
HEADER
6X2
JP1
C10
FREQSEL3
R7
C9
61
VCCA
FREQSEL2
1
62
VCOSEL2
L3
FREQSEL1
VCC
63
64
R5, 5kΩ
R4, 5kΩ
R3, 5kΩ
R2, 5kΩ
R1, 5kΩ
SW DIP-5
VEE
C1
LED
VEE
10
9
8
7
6
C2
2
4
6
VCC
1
2
3
4
5
C4
RDIN–: FORCE
RDIN–: SENSE
R47,
130Ω
1
3
5
7
9
11
VCCO
HEADER
3X2 JP4
VCC
S1
L1
VCC
D1
R48,
20Ω
L7
VEE
VEE
VEE:PIN 32
REFCLK+: FORCE
REFCLK+: SENSE
JP3
REFCLK–: FORCE
REFCLK–: SENSE
11
R11, 1.2kΩ
M9999-072706
[email protected] or (408) 955-1690
R12, 1.2kΩ
VEE
R13, 1.2kΩ
VCC
R14, 1.2kΩ
SW DIP-5
R15, 1.2kΩ
10
9
8
7
6
R46, 100Ω
VEE:PIN 26
S2
1
2
3
4
5
VCC:PIN 24
C17
VEE:PIN 25
VEE:PIN 23
C18
L4
VCC
C11
C12
Micrel, Inc.
SY87702L
EVALUATION BOARD I/O TERMINATION SCHEMES
TCLK
OUTPUTS
RCLK
OUTPUTS
RDOUT
INPUTS
RDIN
INPUTS
VCC
C19
TCLKC–
1
J14
2
R26,
100Ω
C23 J10
RCLKC–
2
R25,
100Ω
R36,
83Ω
J6
1
C31
RDIN+:FORCE
2
R29,
100Ω
VCC
VCC
C27
RDOUTC–
1
J1
1
2
R37,
125Ω
VCC
VEE
C20
TCLKC+
J13
1
2
R27,
100Ω
C24
RCLKC+
J9
1
2
R24,
100Ω
J5
1
C32
RDIN+: SENSE
J2
1
2
R28,
100Ω
VCC
VCC
C28
RDOUTC+
2
VCC
VCC
R38,
83Ω
C21
TCLKE–
J12
1
2
R30,
330Ω
J11
1
2
2
VEE
2
VEE
VEE
NOTES:
1. For AC coupling, include capacitors C19 thru C31, C33, C35 and C37.
2. If DC coupling, remove resistors R36 thru R43.
3. For 50Ω CML systems, include resistors R24–R29.
4. For 100Ω CML systems, see Figure 3.
M9999-072706
[email protected] or (408) 955-1690
12
2
R39,
125Ω
J3
1
R35,
330Ω
J17
1
VEE
C30
RDOUTE+
C33
RDIN–:FORCE
2
R34,
330Ω
J7
1
R33,
330Ω
J4
1
VEE
C26
RCLKE+
C29
RDOUTE+
VEE
C22
R31,
330Ω
J8
1
R32,
330Ω
VEE
TCLKE+
C25
RCLKE–
2
RDIN–: SENSE
C34
J18
1
2
Micrel, Inc.
SY87702L
REFCLK
NC (FUTURE
INPUTS
REV. OUTPUT)
VCC
R40,
83Ω
REFCLK+:FORCE
C39
NC: PIN 52
C35
J15
1
VEE: PIN 59
VCC: PIN 58
VEE
VEE
VEE: PIN 57
VEE: PIN 56
C36
REFCLK+: SENSE
J16
1
2
C40
NC: PIN 53
J22
1
R45,
DNI
VEE: PIN 48
2
VCCO: PIN 42
VEE
VCCO: PIN 37
VCC
VEE: PIN 32
R42,
83Ω
C37
REFCLK–:FORCE
J19
1
VEE: PIN 26
2
R43,
125Ω
VEE: PIN 25
VEE
VCC: PIN 24
REFCLK–: SENSE
VEE: PIN 23
C38
J20
1
C46
0.01µF
C47
0.01µF
C48
0.01µF
C49
0.01µF
C50
0.01µF
C51
0.01µF
C52
0.01µF
C53
0.01µF
C54
0.01µF
C55
0.01µF
C56
0.01µF
2
M9999-072706
[email protected] or (408) 955-1690
C45
0.01µF
2
R44,
DNI
2
R41,
125Ω
J21
1
13
Micrel, Inc.
SY87702L
64-PIN EPAD H QUAD FLATPACK (H64-1)
Rev. 02
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
VEE
Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
M9999-072706
[email protected] or (408) 955-1690
14