ONSEMI NCP3488DR2G

NCP3488
MOSFET Driver with Dual
Outputs for Synchronous
Buck Converters
The NCP3488 is a single Phase 12 V MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
http://onsemi.com
MARKING
DIAGRAMS
8
SO−8
D SUFFIX
CASE 751
8
1
A
L
Y
W
G
• Thermal Shutdown for System Protection
• Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
Anti Cross−Conduction Protection Circuitry
Floating Top Driver Accommodates Boost Voltages of up to 30 V
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM10.x and VRM11.x Specifications
Undervoltage Lockout
Thermal Shutdown
Thermally Enhanced Package Available
This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Features
•
•
•
•
•
•
•
•
•
1
N3488
ALYW
G
1
BST
1
8
DRVH
IN
OD
SWN
PGND
VCC
DRVL
ORDERING INFORMATION
Device
NCP3488DR2G
Package
Shipping †
SO−8
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NCP3488/D
NCP3488
OD
3
V CC
TSD
1
BST
8
DRVH
7
SWN
4
V CC
5
DRVL
6
PGND
UVLO
IN
2
START
STOP
FALLING
EDGE
DELAY
MONITOR
FALLING
EDGE
DELAY
MONITOR
NON−OVERLAP
TIMERS
MIN DRVL
OFF TIMER
Figure 1. Block Diagram
PIN DESCRIPTION
Pin No.
Symbol
Description
1
BST
2
IN
Logic−Level Input. This pin has primary control of the drive outputs.
3
OD
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
4
VCC
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
5
DRVL
Output drive for the lower MOSFET.
6
PGND
Power Ground. Should be closely connected to the source of the lower MOSFET.
7
SWN
Switch Node. Connect to the source of the upper MOSFET.
8
DRVH
Output drive for the upper MOSFET.
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this
bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between
100 nF and 1.0 mF. An external diode is required with the NCP3488.
http://onsemi.com
2
NCP3488
MAXIMUM RATINGS
Rating
Value
Unit
Operating Ambient Temperature, TA
0 to 85
°C
Operating Junction Temperature, TJ (Note 1)
0 to 150
°C
45
123
°C/W
°C/W
−65 to 150
°C
Package Thermal Resistance: SO−8
Junction−to−Case, RqJC
Junction−to−Ambient, RqJA (2−Layer Board)
Storage Temperature Range, TS
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
Pb−Free (Note 3)
260 peak
°C
JEDEC Moisture Sensitivity Level
(260 peak profile)
1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Internally limited by thermal shutdown, 150°C min.
2. 2 layer board, 1 in2 Cu, 1 oz thickness.
3. 60−180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
Pin Name
VMAX
VMIN
VCC
Main Supply Voltage Input
15 V
−0.3 V
BST
Bootstrap Supply Voltage Input
30 V wrt/PGND
35 V v 50 ns wrt/PGND
15 V wrt/SW
−0.3 V wrt/SW
SW
Switching Node
(Bootstrap Supply Return)
30 V
−1.0 V DC
−10 V< 200 ns
DRVH
High−Side Driver Output
BST + 0.3 V
35 V v 50 ns wrt/PGND
15 V wrt/SW
−0.3 V wrt/SW
DRVL
Low−Side Driver Output
VCC + 0.3 V
−0.3 V DC
−2.0 V < 200 ns
IN
DRVH and DRVL Control Input
VCC + 0.3 V
−0.3 V
OD
Output Disable
VCC + 0.3 V
−0.3 V
PGND
Ground
0V
0V
NOTE:
All voltages are with respect to PGND except where noted.
http://onsemi.com
3
NCP3488
ELECTRICAL CHARACTERISTICS (Note 4) (VCC = 12 V, TA = 0°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Supply Voltage Range
VCC
−
4.6
−
13.2
V
Supply Current
ISYS
BST = 12 V, IN = 0 V
−
2.0
6.0
mA
Input Voltage High
−
−
2.0
−
−
V
Input Voltage Low
−
−
−
−
0.8
V
Hysteresis
−
−
−
500
−
mV
Input Current
−
No internal pull−up or pull−down resistors
−1.0
−
+1.0
mA
tpdlOD
tpdhOD
−
30
30
50
50
60
60
ns
ns
Input Voltage High
−
−
2.0
−
−
V
Input Voltage Low
−
−
−
−
0.8
V
Hysteresis
−
−
−
500
−
mV
Input Current
−
No internal pull−up or pull−down resistors
−1.0
−
+1.0
mA
Output Resistance, Sourcing Current
−
VBST − VSW = 12 V (Note 7)
−
1.8
−
W
Output Resistance, Sinking Current
−
VBST − VSW = 12 V (Note 7)
−
1.0
−
W
trDRVH
tfDRVH
VBST − VSW = 12 V, CLOAD = 3.0 nF
(See Figure 3)
−
−
16
11
−
−
ns
ns
tpdhDRVH
tpdlDRVH
VBST − VSW = 12 V
−
−
30
25
−
−
ns
ns
Output Resistance, Sourcing Current
−
VCC = 12 V (Note 7)
−
1.8
−
W
Output Resistance, Sinking Current
−
VCC − VSW = 12 V (Note 7)
−
1.0
−
W
Timeout Delay
−
DRVH−SW = 0
−
85
−
ns
trDRVL
tfDRVL
CLOAD = 3.0 nF
(See Figure 3)
−
−
16
11
−
−
ns
ns
tpdhDRVL
tpdlDRVL
(See Figure 3)
−
−
30
20
−
−
ns
ns
UVLO Startup
−
−
3.7
3.9
4.4
V
UVLO Shutdown
−
−
3.2
3.5
3.9
V
Hysteresis
−
−
0.3
0.4
0.7
V
−
(Note 7)
150
170
−
°C
(Note 7)
−
20
−
°C
Supply
OD Input
Propagation Delay Time (Note 5)
PWM Input
High−Side Driver
Transition Times (Note 5)
Propagation Delay (Notes 5 & 6)
Low−Side Driver
Transition Times
Propagation Delay
Undervoltage Lockout
Thermal Shutdown
Over Temperature Protection
Hysteresis
4.
5.
6.
7.
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
AC specifications are guaranteed by characterization, but not production tested.
For propagation delays, “tpdh’’ refers to the specified signal going high; “tpdl’’ refers to it going low.
GBD: Guaranteed by design; not tested in production.
Specifications subject to change without notice.
http://onsemi.com
4
NCP3488
OD
tpdlOD
tpdhOD
90%
DRVH
or
DRVL
10%
Figure 2. Output Disable Timing Diagram
IN
DRVL
tpdlDRVL
tfDRVL
90%
90%
2V
10%
10%
tpdhDRVH
trDRVH
tpdlDRVH
90%
trDRVL
tfDRVH
90%
DRVH−SW
2V
10%
10%
tpdhDRVL
SW
Figure 3. Nonoverlap Timing Diagram
APPLICATIONS INFORMATION
Theory of Operation
High−Side Driver
The NCP3488 is a single phase MOSFET driver designed
for driving two N−channel MOSFETs in a synchronous buck
converter topology. The NCP3488 will operate from 5 V or
12 V, but it has been optimized for high current multi−phase
buck regulators that convert 12 Volt rail directly to the core
voltage required by complex logic chips. A single PWM input
signal is all that is required to properly drive the high−side and
the low−side MOSFETs. Each driver is capable of driving a
3.3 nF load at frequencies up to 500 kHz.
The high−side driver is designed to drive a floating low
RDS(on) N−channel MOSFET. The gate voltage for the high
side driver is developed by a bootstrap circuit referenced to
Switch Node (SW) pin.
The bootstrap circuit is comprised of an external diode,
and an external bootstrap capacitor. When the NCP3488 is
starting up, the SW pin is at ground, so the bootstrap
capacitor will charge up to VCC through the bootstrap diode
See Figure 4. When the PWM input goes high, the high−side
driver will begin to turn on the high−side MOSFET using the
stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin will rise. When the high−side
MOSFET is fully on, the switch node will be at 12 volts, and
the BST pin will be at 12 volts plus the charge of the
bootstrap capacitor (approaching 24 volts).
The bootstrap capacitor is recharged when the switch
node goes low during the next cycle.
Low−Side Driver
The low−side driver is designed to drive a
ground−referenced low RDS(on) N−Channel MOSFET. The
voltage rail for the low−side driver is internally connected to
the VCC supply and PGND.
http://onsemi.com
5
NCP3488
Safety Timer and Overlap Protection Circuit
Input Pins
It is very important that MOSFETs in a synchronous buck
regulator do not both conduct at the same time. Excessive
shoot−through or cross conduction can damage the
MOSFETs, and even a small amount of cross conduction
will cause a decrease in the power conversion efficiency.
The NCP3488 prevents cross conduction by monitoring
the status of the external MOSFETs and applying the
appropriate amount of “dead−time” or the time between the
turn off of one MOSFET and the turn on of the other
MOSFET.
When the PWM input pin goes high, DRVL will go low
after a propagation delay (tpdlDRVL). The time it takes for
the low−side MOSFET to turn off (tfDRVL) is dependent on
the total charge on the low−side MOSFET gate. The
NCP3488 monitors the gate voltage of both MOSFETs and
the switchnode voltage to determine the conduction status of
the MOSFETs. Once the low−side MOSFET is turned off an
internal timer will delay (tpdhDRVH) the turn on of the
high−side MOSFET
Likewise, when the PWM input pin goes low, DRVH will
go low after the propagation delay (tpdDRVH). The time to
turn off the high−side MOSFET (tfDRVH) is dependent on
the total gate charge of the high−side MOSFET. A timer will
be triggered once the high−side MOSFET has stopped
conducting, to delay (tpdhDRVL) the turn on of the
low−side MOSFET
The PWM input and the Output Disable pins of the
NCP3488 have internal protection for Electro Static
Discharge (ESD), but in normal operation they present a
relatively high input impedance. If the PWM controller does
not have internal pull−down resistors, they should be added
externally to ensure that the driver outputs do not go high
before the controller has reached its under voltage lockout
threshold. The NCP5388 controller does include a passive
internal pull−down resistor on the drive−on output pin.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and the internal (or an external) diode. Selection of
these components can be done after the high−side MOSFET
has been chosen. The bootstrap capacitor must have a
voltage rating that is able to withstand twice the maximum
supply voltage. A minimum 50 V rating is recommended.
The capacitance is determined using the following equation:
Q
CBST + GATE
DVBST
where QGATE is the total gate charge of the high−side
MOSFET, and DVBST is the voltage droop allowed on the
high−side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
The bootstrap diode must be rated to withstand the
maximum supply voltage plus any peak ringing voltages
that may be present on SW. The average forward current can
be estimated by:
Power Supply Decoupling
The NCP3488 can source and sink relatively large
currents to the gate pins of the external MOSFETs. In order
to maintain a constant and stable supply voltage (VCC) a low
ESR capacitor should be placed near the power and ground
pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC)
is usually sufficient.
IF(AVG) + QGATE
fMAX
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in−circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of CBST.
12 V
12 V
NCP3488
4
Output Enable
PWM in
BST
DRVH
3
SW
OD
DRVL
2
IN PGND
Vcc
1
8
7
5
6
Vout
Figure 4. NCP3488 Example Circuit
http://onsemi.com
6
NCP3488
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: order[email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP3488/D