VRS51C1000 Datasheet Rev 1.9 Versa 8051 MCU with 64KB of IAP/ISP Flash Overview Feature Set The VRS51C1000 is based on the standard 8051 microcontroller family architecture and is pin compatible and a drop-in replacement for most 8051 MCUs. The VRS51C1000 is ideal for a range of applications requiring a large amount of program/data memory with non-volatile data storage and/or code/field based firmware upgrade capability coupled with comprehensive peripheral support. It features 64KB of In-System/In-Application Programmable Flash memory, IKB of SRAM, 5 PWM output channels, a UART, three 16-bit timers, a Watchdog timer and power down features. The VRS51C1000 is available with firmware that enables In-System Programming (firmware based bootloader) of the Flash memory via the UART interface (ISPVx version). General Flash memory programming is supported by device programmers available from Ramtron or other 3rd party suppliers. The device also includes a fifth, 4-bit, I/O port mapped into the “no connect” pins of the standard 8051/52 package, providing a total of 36 I/Os while maintaining compatibility with standard 8051/82 pin outs. The VRS51C1000 is available in PLCC-44, QFP-44 and DIP-40 packages and function over the industrial temperature range. • • • • • • • • • • • • • • • • • • • 8051/8052 pin compatible 64KB Flash memory In-System / In-Application Flash Programming (ISP/IAP) Program voltage: 5V 1024 Bytes on chip data SRAM Four 8-bit I/Os + one 4-bit I/O 5 PWM outputs on P1.3 to P1.7 One Full Duplex UART serial port Three 16-bit Timers/Counters Watchdog Timer Bit operation instruction 8-bit Unsigned Multiply and Division instructions BCD arithmetic Direct and Indirect Addressing Two Levels of Interrupt Priority and Nested Interrupts Power saving modes Code protection function Low EMI (inhibit ALE) Operating Temperature Range -40ºC to +85ºC P2.6/A14 P2.5/A13 #PSEN P2.7/A15 P4.1 ALE P0.7/AD7 #EA P0.5/AD5 P0.6/AD6 P0.4/AD4 FIGURE 2: VRS51C1000 QFP-44 AND PLCC-44 PIN OUT DIAGRAMS 33 P0.3/AD3 23 22 34 P0.2/AD2 P0.1/AD1 P2.3/A11 P2.2/A10 P0.0/AD0 VDD P2.1/A9 P2.0/A8 VRS51C1000 QFP-44 P4.2 T2/P1.0 P4.0 VSS T2EX/P1.1 P1.2 PWM0/P1.3 PWM1/P1.4 XTAL1 XTAL2 44 12 11 UART PORT 2 8 PORT 3 8 TXD/P3.1 T0/P3.4 T1/P3.5 #INT1/P3.3 #INT0/P3.2 #PSEN P2.7/A15 4 T1/P3.5 17 29 Ramtron International Corporation 1850 Ramtron Drive Colorado Springs Colorado, USA, 80921 ♦ ♦ ♦ P2.1/A9 P2.2/A10 P2.3/A11 5 P2.0/A8 PWM P2.6/A14 P2.5/A13 28 18 VSS P4.0 WATCHDOG TIMER P4.1 ALE #INT0/P3.2 #INT1/P3.3 T0/P3.4 XTAL1 RESET PORT 4 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA VRS51C1000 PLCC-44 RXD/P3.0 P4.3 #WR/P3.6 TIMER 2 POWER CONTROL 39 PWM4/P1.7 RES TIMER 0 TIMER 1 40 7 PWM3/P1.6 #RD/P3.7 XTAL2 2 INTERRUPT INPUTS P4.3 TXD/P3.1 1 6 PWM2/P1.5 #RD/P3.7 #WR/P3.6 P2.4/A12 8 P0.2/AD2 PORT 1 P0.1/AD1 1024 Bytes of SRAM VDD P0.0/AD0 8 T2/P1.0 P4.2 PORT 0 T2EX/P1.1 64KB FLASH PWM4/P1.7 RE S RXD/P3.0 PWM2/P1.5 ADDRESS/ DATA BUS PWM1/P1.4 PWM0/P1.3 P1.2 8051 PROCESSOR PWM3/P1.6 1 P0.3/AD3 FIGURE 1: VRS51C1000 FUNCTIONAL DIAGRAM P2.4/A12 http://www.ramtron.com MCU customer service: 1-800-943-4625, 1-514-871-2447 x 208 1-800-545-FRAM, 1-719-481-7000 page 1 of 48 VRS51C1000 Pin Descriptions for QFP-44/PLCC-44 TABLE 1: PIN DESCRIPTIONS FOR QFP-44/PLCC-44 16 11 17 12 18 13 19 14 15 16 17 20 21 22 23 18 24 19 25 20 26 21 27 22 28 23 PWM1/P1.4 29 6 PWM2/P1.5 7 1 44 43 42 41 40 39 PWM3/P1.6 8 38 9 37 10 11 36 PWM4/P1.7 RES RXD/P3.0 P4.3 5 4 3 2 VRS51C1000 PLCC-44 12 35 34 TXD/P3.1 13 #INT0/P3.2 #INT1/P3.3 T0/P3.4 14 32 15 31 T1/P3.5 17 33 16 30 29 P2.4/A12 P2.1/A9 P2.2/A10 P2.3/A11 VSS P4.0 P2.0/A8 XTAL1 #RD/P3.7 XTAL2 18 19 20 21 22 23 24 25 26 27 28 #WR/P3.6 38 33 39 34 40 35 41 36 42 37 43 38 39 44 1 40 2 41 3 42 4 43 5 44 6 P1.3 I/O Bit 3 of Port 1 PWM1 O PWM Channel 1 P1.4 I/O Bit 4 of Port 1 6 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 PWM2/P1.5 7 1 44 43 42 41 40 39 PWM3/P1.6 8 38 PWM4/P1.7 RES RXD/P3.0 P4.3 5 P0.2/AD2 10 32 P0.1/AD1 15 37 P0.3/AD3 9 31 4 3 2 9 37 36 10 11 VRS51C1000 PLCC-44 12 35 34 TXD/P3.1 13 #INT0/P3.2 #INT1/P3.3 T0/P3.4 14 32 15 31 16 30 T1/P3.5 17 33 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 18 19 20 21 22 23 24 25 26 27 28 P2.4/A12 14 36 VDD P0.0/AD0 8 30 P2.0/A8 13 32 33 34 35 P2.1/A9 P2.2/A10 P2.3/A11 7 31 26 27 28 29 T2/P1.0 P4.2 12 25 Function Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable Bit 1 of Port 4 External Access Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory VCC Bit 2 of Port 4 Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 Bit 2 of Port 1 PWM Channel 0 VSS P4.0 6 30 I/O I/O O I/O O O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I/O O XTAL1 11 24 Name P2.6 A14 P2.7 A15 #PSEN ALE P4.1 #EA P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0. 1 AD1 P0.0 AD0 VDD P4.2 T2 P1.0 T2EX P1.1 P1.2 PWM0 PWM1/P1.4 10 5 VDD P0.0/AD0 4 T2/P1.0 P4.2 9 PWM0/P1.3 P1.2 T2EX/P1.1 3 PWM Channel 2 Bit 5 of Port 1 PWM Channel 3 Bit 6 of Port 1 PWM Channel 4 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Bit 3 of Port 4 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground Bit 0 of Port 4 Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address PLCC - 44 PWM0/P1.3 P1.2 T2EX/P1.1 8 O I/O O I/O O I/O I I I/O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O I/O O I/O O I/O O I/O O I/O O I/O O QFP - 44 #RD/P3.7 XTAL2 2 PWM2 P1.5 PWM3 P1.6 PWM4 P1.7 RES RXD P3.0 P4.3 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS P4.0 P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 Function #WR/P3.6 7 I/O P0.2/AD2 1 Name P0.1/AD1 PLCC - 44 P0.3/AD3 QFP - 44 ______________________________________________________________________________________________ page 2 of 48 www.ramtron.com VRS51C1000 VRS51C1000 DIP-40 Pin Descriptions DIP40 21 TABLE 2: VRS51C1000 PIN DESCRIPTIONS FOR DIP40 PACKAGE DIP40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name I/O T2 P1.0 T2EX P1.1 P1.2 PWM0 P1.3 PWM1 P1.4 PWM2 P1.5 PWM3 P1.6 PWM4 P1.7 RESET RXD P3.0 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS I I/O I I/O I/O O I/O O I/O O I/O O I/O O I/O I I I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I - 22 Function Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 Bit 2 of Port 1 PWM Channel 0 Bit 3 of Port 1 PWM Channel 1 Bit 4 of Port 1 PWM Channel 2 Bit 5 of Port 1 PWM Channel 3 Bit 6 of Port 1 PWM Channel 4 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 T2 / P1.0 1 40 VDD T2EX / P1.1 2 39 P0.0 / AD0 P1.2 3 38 P0.1 / AD1 PWM0 / P1.3 4 37 P0.2 / AD2 PWM1 / P1.4 5 36 P0.3 / AD3 PWM2 / P1.5 6 35 P0.4 / AD4 PWM3 / P1.6 7 34 P0.5 / AD5 PWM4 / P1.7 8 33 P0.6 / AD6 RESET 9 32 P0.7 / AD7 31 #EA / VPP 30 ALE VRS51C1000 DIP-40 RXD / P3.0 10 TXD / P3.1 11 #INT0 / P3.2 12 29 PSEN #INT1 / P3.3 13 28 P2.7 / A15 T0 / P3.4 14 27 P2.6 / A14 T1 / P3.5 15 26 P2.5 / A13 #WR / P3.6 16 25 P2.4 / A12 #RD / P3.7 17 24 P2.3 / A11 XTAL2 18 23 P2.2 / A10 XTAL1 19 22 P2.1 / A9 VSS 20 21 P2.0 / A8 40 Name I/O P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P2.6 A14 P2.7 A15 #PSEN ALE #EA / VPP P0.7 I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O O AD7 I/O P0.6 I/O AD6 I/O I I/O P0.5 I/O AD5 I/O P0.4 I/O AD4 I/O P0.3 I/O AD3 I/O P0.2 I/O AD2 I/O P0. 1 AD1 P0.0 AD0 VDD I/O I/O I/O I/O - Function Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable External Access Flash programming voltage input Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory Supply input ______________________________________________________________________________________________ www.ramtron.com page 3 of 48 VRS51C1000 Instruction Set Mnemonic The following table describes the instruction set of the VRS51C1000. The instructions are function and binary code compatible with industry standard 8051s. Table 3: Legend for Instruction Set Table Symbol A Rn Direct @Ri rel bit #data #data 16 addr 16 addr 11 Function Accumulator Register R0-R7 Internal register address Internal register pointed to by R0 or R1 (except MOVX) Two's complement offset byte Direct bit address 8-bit constant 16-bit constant 16-bit destination address 11-bit destination address TABLE 4: VRS51C1000 INSTRUCTION SET Mnemonic Description Arithmetic instructions Add register to A ADD A, Rn Add direct byte to A ADD A, direct Add data memory to A ADD A, @Ri Add immediate to A ADD A, #data Add register to A with carry ADDC A, Rn Add direct byte to A with carry ADDC A, direct Add data memory to A with carry ADDC A, @Ri Add immediate to A with carry ADDC A, #data Subtract register from A with borrow SUBB A, Rn Subtract direct byte from A with borrow SUBB A, direct Subtract data mem from A with borrow SUBB A, @Ri Subtract immediate from A with borrow SUBB A, #data Increment A INC A Increment register INC Rn Increment direct byte INC direct Increment data memory INC @Ri Decrement A DEC A Decrement register DEC Rn Decrement direct byte DEC direct Decrement data memory DEC @Ri Increment data pointer INC DPTR Multiply A by B MUL AB Divide A by B DIV AB Decimal adjust A DA A Logical Instructions AND register to A ANL A, Rn AND direct byte to A ANL A, direct AND data memory to A ANL A, @Ri AND immediate to A ANL A, #data AND A to direct byte ANL direct, A AND immediate data to direct byte ANL direct, #data OR register to A ORL A, Rn OR direct byte to A ORL A, direct OR data memory to A ORL A, @Ri OR immediate to A ORL A, #data OR A to direct byte ORL direct, A OR immediate data to direct byte ORL direct, #data Exclusive-OR register to A XRL A, Rn Exclusive-OR direct byte to A XRL A, direct Exclusive-OR data memory to A XRL A, @Ri Exclusive-OR immediate to A XRL A, #data Exclusive-OR A to direct byte XRL direct, A Exclusive-OR immediate to direct byte XRL direct, #data Clear A CLR A Compliment A CPL A Swap nibbles of A SWAP A Rotate A left RL A Rotate A left through carry RLC A Rotate A right RR A Rotate A right through carry RRC A Size (bytes) Instr. Cycles 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 Description Boolean Instruction Clear Carry bit CLR C Clear bit CLR bit Set Carry bit to 1 SETB C Set bit to 1 SETB bit Complement Carry bit CPL C Complement bit CPL bit Logical AND between Carry and bit ANL C,bit Logical AND between Carry and not bit ANL C,#bit Logical ORL between Carry and bit ORL C,bit Logical ORL between Carry and not bit ORL C,#bit Copy bit value into Carry MOV C,bit Copy Carry value into Bit MOV bit,C Data Transfer Instructions Move register to A MOV A, Rn Move direct byte to A MOV A, direct Move data memory to A MOV A, @Ri Move immediate to A MOV A, #data Move A to register MOV Rn, A Move direct byte to register MOV Rn, direct Move immediate to register MOV Rn, #data Move A to direct byte MOV direct, A Move register to direct byte MOV direct, Rn Move direct byte to direct byte MOV direct, direct Move data memory to direct byte MOV direct, @Ri Move immediate to direct byte MOV direct, #data Move A to data memory MOV @Ri, A Move direct byte to data memory MOV @Ri, direct Move immediate to data memory MOV @Ri, #data Move immediate to data pointer MOV DPTR, #data MOVC A, @A+DPTR Move code byte relative DPTR to A Move code byte relative PC to A MOVC A, @A+PC Move external data (A8) to A MOVX A, @Ri Move external data (A16) to A MOVX A, @DPTR Move A to external data (A8) MOVX @Ri, A Move A to external data (A16) MOVX @DPTR, A Push direct byte onto stack PUSH direct Pop direct byte from stack POP direct Exchange A and register XCH A, Rn Exchange A and direct byte XCH A, direct Exchange A and data memory XCH A, @Ri Exchange A and data memory nibble XCHD A, @Ri Branching Instructions Absolute call to subroutine ACALL addr 11 Long call to subroutine LCALL addr 16 Return from subroutine RET Return from interrupt RETI Absolute jump unconditional AJMP addr 11 Long jump unconditional LJMP addr 16 Short jump (relative address) SJMP rel Jump on carry = 1 JC rel Jump on carry = 0 JNC rel Jump on direct bit = 1 JB bit, rel Jump on direct bit = 0 JNB bit, rel Jump on direct bit = 1 and clear JBC bit, rel Jump indirect relative DPTR JMP @A+DPTR Jump on accumulator = 0 JZ rel Jump on accumulator 1= 0 JNZ rel Compare A, direct JNE relative CJNE A, direct, rel Compare A, immediate JNE relative CJNE A, #d, rel Compare reg, immediate JNE relative CJNE Rn, #d, rel Compare ind, immediate JNE relative CJNE @Ri, #d, rel Decrement register, JNZ relative DJNZ Rn, rel Decrement direct byte, JNZ relative DJNZ direct, rel Miscellaneous Instruction No operation NOP Size (bytes) Instr. Cycles 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Rn: Any of the register R0 to R7 @Ri: Indirect addressing using Register R0 or R1 #data: immediate Data provided with Instruction #data16: Immediate data included with instruction bit: address at the bit level rel: relative address to Program counter from +127 to –128 Addr11: 11-bit address range Addr16: 16-bit address range #d: Immediate Data supplied with instruction ______________________________________________________________________________________________ www.ramtron.com page 4 of 48 VRS51C1000 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS51C1000 Special Function Registers. TABLE 5: SPECIAL FUNCTION REGISTERS (SFR) SFR Register P0 SP DPL DPH RCON DBANK PCON TCON TMOD TL0 TL1 TH0 TH1 P1 SCON SBUF PWME WDTC P2 PWMC PWMD0 PWMD1 PWMD2 PWMD3 IE PWMD4 P3 IP SYSCON T2CON RCAP2L RCAP2H TL2 TH2 PSW P4 ACC B IAPFADHI IAPFADLO IAPFDATA IAPFCTRL SFR Adrs 80h 81h 82h 83h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 90h 98h 99h 9Bh 9Fh A0h A3h A4h A5h A6h A7h A8h ACh B0h B8h BFh C8h CAh CBh CCh CDh D0h D8h E0h F0h F4h F5h F6h F7h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSE SMOD TF1 GATE1 SM0 PWM4E WDTE PWMD0.4 PWMD1.4 PWMD2.4 PWMD3.4 EA PWMD4.4 WDR TF2 - TR1 C/T1 SM1 PWM3E PWMD0.3 PWMD1.3 PWMD2.3 PWMD3.3 PWMD4.3 EXF2 - TF0 M1.1 SM2 PWM2E CLEAR PWMD0.2 PWMD1.2 PWMD2.2 PWMD3.2 ET2 PWMD4.2 PT2 RCLK - TR0 M0.1 REN PWM1E PWMD0.1 PWMD1.1 PWMD2.1 PWMD3.1 ES PWMD4.1 PS TCLK - BS3 GF1 IE1 GATE0 TB8 PWM0E PWMD0.0 PWMD1.0 PWMD2.0 PWMD3.0 ET1 PWMD4.0 PT1 EXEN2 - BS2 GF0 IT1 C/T0 RB8 PS2 NP0.2 NP1.2 NP2.2 NP3.2 EX1 NP4.2 PX1 IAPE TR2 - RAMS1 BS1 PDOWN IE0 M1.0 TI PS1 PDCK1 NP0.1 NP1.1 NP2.1 NP3.1 ET0 NP4.1 PT0 XRAME C/T2 - RAMS0 BS0 IDLE IT0 M0.0 RI PS0 PDCK0 NP0.0 NP1.0 NP2.0 NP3.0 EX0 NP4.0 PX0 ALEI CP/RL2 - CY FA15 FA7 FD7 IAPSTART AC FA14 FA6 FD6 F0 FA13 FA5 FD5 RS1 FA12 FA4 FD4 RS0 P4.3 FA11 FA3 FD3 OV P4.2 FA10 FA2 FD2 P4.1 FA9 FA1 FD1 P P4.0 FA8 FA0 FD0 IAPFCT1 IAPFCT0 Reset Value 1111 1111b 0000 0111b 0000 0000b 0000 0000b 0000 0000b 0000 0001b 0000 0000b 0000 0010b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0111 1111b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1011b 0000 0000b 0000 1010b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0001b ****1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b ______________________________________________________________________________________________ www.ramtron.com page 5 of 48 VRS51C1000 VRS51C1000 Program Memory The VRS51C1000 includes 64KB of on-chip Flash memory that can be used as program memory or as general non-volatile data storage memory using the InApplication Programming feature (IAP). ISP Boot Program Memory Zone The upper portion of the VRS51C1000 Flash memory can be reserved to store an ISP (In-System Programmable) boot loader program. This boot program can be used to program the Flash memory via the serial interface (or via any other method) by making use of the In-Application Programming (IAP) feature of the VRS51C1000. This allows the processor to load the program from an external device or system, and program it into the Flash memory (See the VRS51C1000 IAP feature section) The size of the memory block reserved for the ISP boot loader program (when activated) is adjustable from 512 Bytes up to 4K bytes in increments of 512 bytes. When programming the ISP boot program into the VRS51C1000, the “lock bit” option should be activated in order to protect the ISP flash memory zone from being inadvertently erased (can happen when the Flash Erase operations are performed under the control of the ISP boot program) or to prevent the VRS51C1000 flash memory from being read back using a parallel programmer. If an Erase operation is performed using a parallel programmer, the entire flash memory, including the ISP Boot program memory zone will be erased. ISP Program Start Conditions Setting the ISP page configuration to a value other than 0 will result in the Processor jumping to the base address of the ISP boot code when a hardware reset is performed (provided that the value FFh is present at program address 0000h). When the ISP page configuration is set to 0 at the moment the device is programmed using a parallel programmer, the ISP boot feature will be disabled. FIGURE3: VRS51C1000-ISP PROGRAM SIZE VS ISP CONFIG. VALUE FA00h ISPCFG=8 ISPCFG=6 FC00h ISPCFG=7 ISPCFG=5 ISPCFG=3 FE00h ISPCFG=4 ISPCFG=1 ISP Program Size = ISP Config value x 512Bytes ISPCFG=2 FFFFh F800h F600h F400h F200h F000h 0000h Programming the ISP Boot Program The ISP boot program must be programmed into the device using a parallel programmer (such as the VERSAMCU-PPR) or a commercial parallel programmer that supports the VRS51C1000. The Flash memory reserved for the ISP program is defined by the parallel programmer software at the moment the device is programmed. ______________________________________________________________________________________________ www.ramtron.com page 6 of 48 VRS51C1000 VRS51C1000 ISPVx Firmware boot program An ISP boot loader program is available for the VRS51C1000 (ISPVx Firmware, x = revision, see Ramtron website for latest revision). The ISPVx Firmware enables In-System-Programming of the VRS51C1000 on the final application PCB using the device’s UART interface. See the following figure for a hardware configuration example. Other configurations are also possible. FIGURE 4: VRS51C1000 INTERFACE FOR IN-SYSTEM PROGRAMMING System Control Register By default upon reset, the IAP feature of the VRS51C1000 is de-activated. The IAPE bit of the SYSCON register is used to enable (and disable) the VRS51C1000 IAP function. TABLE 6: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH 7 WDR 6 5 4 Unused Bit 7 Mnemonic WDR 6 5 4 3 2 1 0 Unused Unused Unused Unused IAPE XRAME ALEI 51k RS232 interf. To PC RS232 Transceiver VRS51C1000 PNP (with ISPV2 Firmware) TXD RXD Creset 150k 3 2 IAPE 1 XRAME 0 ALEI Description This is the Watchdog Timer reset bit. It will be set to 1 when the reset signal generated by WDT overflows. IAP function enable bit 768 byte on-chip enable bit ALE output inhibit bit, which is used to reduce EMI. RES IAP Flash Address and Data Registers Rreset See Ramtron’s website in order to download the “Versa Ware ISP” Window’s™ application which allows communication with the ISPVx firmware. The VRS51C1000 can be ordered with or without the ISPVx bootloader firmware (see Ordering information section of this Datasheet for part number information). The ISPVx bootloader firmware can also be programmed into the VRS51C1000 by the user. Source code is included with the Versa Ware ISP application software. The IAPFADHI and IAPADLO registers are used to specify the address at which the IAP function will be performed. TABLE 7:IAP FLASH ADDRESS HIGH - SFR F4H 7 6 5 4 3 2 IAPFADHI[15:8] 1 0 1 0 TABLE 8:IAP FLASH ADDRESS LOW - SFR F5H 7 6 5 4 3 2 IAPFADLO[15:8] The IAPFDATA SFR register contains the Data byte required to perform the IAP function. TABLE 9:IAP FLASH DATA REGISTER - SFR F6H For more information on the ISPVx firmware, please consult the “VRS51C1000 ISPVx Firmware User Guide.pdf” available on the Ramtron web site. VRS51C1000 IAP feature The VRS51C1000 IAP feature refers to the ability of the processor to self-program the Flash memory from within the user program. Five SFR registers serve to control the IAP operation. The description of these registers is provided below. 7 6 5 4 3 2 IAPFDATA[7:0] 1 0 IAP Flash Control Register The VRS51C1000 IAP function operation is controlled by the IAP Flash Control register, IAPFCTRL. Setting the IAPSTART bit to 1, starts the execution of the IAP command specified by the IAPFCT[1:0] bits of the IAP Flash Control register. ______________________________________________________________________________________________ www.ramtron.com page 7 of 48 VRS51C1000 TABLE 10:IAP FLASH CONTROL REGISTER - SFR F7H 7 Bit 7 6 5 4 3 2 1 0 6 5 4 3 2 IAPFCTRL[15:8] 1 Mnemonic IAPSTART Unused Unused Unused Unused Unused Description IAP Selected operation Start sequence - IAPFCT[1:0] Flash Memory IAP Function 0 The IAP sub-system handles four different functions. The IAP function performed is controlled by the IAPFCT bits as follows: TABLE 11:IAP FUNCTIONS IAPFCT[1:0] Bits value 00 01 10 11 IAP Function Flash Byte Program Flash Erase Protect Flash Page Erase Flash Erase IAP_PROG: MOV MOV MOV MOV MOV MOV MOV MOV IAPFDATA,#55H IAPFDATA,#0AAH IAPFDATA,#55H ;Sequence to Enable Writing ; the IAPSTART bit SYSCON,#04H IAPFADHI, FADRSH IAPFADLO,FADRSL IAPFDATA,FDATA IAPFCTRL,#80H ;ENABLE IAP FUNCTION ;Set MSB of address to program ;Set LSB of address to program ;Set Data to Program ;Set the IAP Start bit ;**The program Counter will stop until the IAP function is completed IAP Page Erase Function By using the IAP feature, it is possible to perform a Page erase of the VRS51C1000 Flash memory (note that the memory area occupied by the ISP boot program cannot be page erased). Each page is 512 Bytes in size. To perform a flash page erase, the page address is specified by the XY (hex) value written into the IAPFADHI register (The value 00h must be written into the IAPFADLO registers) If the “Y” portion of the IAPFADHI register represents an even number, the page that will be erased corresponds to the range XY00h to X(Y+1)FFh It is important to note that for security reasons, the IAPSTART bit of the IAPFCTRL register is configured as read-only by default. If the “Y” portion of the IAPFADHI register represents an odd number, the page that will be erased corresponds to the range X(Y-1)00h to XYFFh In order to set the IAPSTART bit to 1, the following operation sequence must be performed first: The following program example erases the page corresponding to the address B000h-CFFFh MOV MOV MOV IAPFDATA,#55h IAPFDATA,#AAh IAPFDATA,#55h The IAPSTART bit can be set to 1. Once the start bit is set to 1, the IAP sub-system will read the contents of the IAP Flash Address and Data registers and hold the VRS51C1000 program counter at its current value until the IAP operation is completed. When the IAP operation is complete, the IAPSTART bit is cleared and the program will continue executing. ;** Erase Flash page located at address B000h to CFFFh. PageErase: MOV IAPFDATA,#55H ;Sequence to Enable Writing MOV IAPFDATA,#0AAH ; the IAPSTART bit MOV IAPFDATA,#55H MOV MOV MOV MOV SYSCON,#04H IAPFADHI, #0B0h IAPFADLO,#00h IAPFCTRL,#82H ;ENABLE IAP FUNCTION ;Set MSB of Page address to erase ;Set LSB of address = 00 ;SET THE IAP START BIT IAP Chip Erase Function The IAP chip erase function will erase the entire flash memory contents with the exception of the ISP boot program area. Running this function will also automatically unprotect the Flash memory. IAP Byte Program Function The IAP byte program function is used to program a byte into the specified Flash memory location under the control of the IAP feature. See the following program example: IAP Chip Protect Function When the chip protect function is enabled, values read back from Flash memory will be 00h. ______________________________________________________________________________________________ www.ramtron.com page 8 of 48 VRS51C1000 Program Status Word Register Data Memory The PSW register is a bit addressable register that contains the status flags (CY, AC, OV, P), user flag (F0) and register bank select bits (RS1, RS0) of the 8051 processor. The VRS51C1000 has total of 1KB of on-chip SRAM with a 256 byte subset of this block mapped as the internal memory structure of a standard 8052. The remaining 768 byte sub-block can be accessed using external memory addressing via the MOVX instruction. TABLE 12: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH 7 CY Bit 7 6 5 4 3 2 1 0 RS1 0 0 1 1 6 AC 5 F0 Mnemonic CY AC F0 RS1 RS0 OV P RS0 0 1 0 1 4 RS1 3 RS0 2 OV 1 - 0 P Description Carry Bit Auxiliary Carry Bit from bit 3 to 4. User definer flag R0-R7 Registers bank select bit 0 R0-R7 Registers bank select bit 1 Overflow flag Parity flag Active Bank 0 1 2 3 Address 00h-07h 08h-0Fh 10h-17h 18-1Fh Data Pointer The VRS51C1000 has one 16-bit data pointer. The DPTR is accessed via two SFR addresses: DPL located at address 82h and DPH located at address 83h. FIGURE 5: VRS51C1000 DATA MEMORY 02FF Expanded 768 bytes (accessed by direct external addressing mode, using the MOVX instruction) (XRAME=1) FF 80 7F Upper 128 bytes (Indirect addressing mode only) SFR (Direct addressing mode only) Lower 128 bytes 00 0000 By default after reset, the expanded SRAM area is disabled. It can be enabled by setting the XRAME bit of the SYSCON register located at address BFh in the SFR. Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1) The lower 128 bytes of data memory (from 00h to 7Fh) can is summarized as follows: o Address range 00h to 7Fh can be accessed in direct and indirect addressing modes. o Address range 00h to 1Fh includes R0-R7 registers area. o Address range 20h to 2Fh is bit addressable. o Address range 30h to 7Fh is not bit addressable and can be used as generalpurpose storage. Upper 128 bytes (80h to FFh, Bank 2 & Bank 3) The upper 128 bytes of the data memory ranging from 80h to FFh can be accessed using indirect addressing or by using the bank mapping in direct addressing mode. Stack Pointer The Stack Pointer is a register located at address 81h of the SFR register area whose value corresponds to the address of the last item that was put on the processor stack. Each time new data is put on the Stack Pointer, the value of the Stack Pointer is incremented. By default, the Stack Pointer value is 07h, but it is possible to program the processor stack pointer to ______________________________________________________________________________________________ www.ramtron.com page 9 of 48 VRS51C1000 point anywhere in the 00h to FFh range of SRAM memory. When a function call is performed or an interrupt is serviced, the 16-bit return address (two bytes) is stored on the stack. Data can be placed manually on the Stack by using the PUSH and POP functions. Example: Expanded SRAM Access Using the MOVX @DPTR Instruction (0000-02FF, Bank4-Bank15) Note that when both RAM1 and RAM0 are set to 1, the value of P2 defines the upper byte and Rn defines the lower byte of the external address. In this case the device will access off-chip memory in the external memory space using the external memory control signals, Off chip peripherals can therefore be mapped into the “P2value”00h to “P2value”FFh address range The 768 bytes of the expanded SRAM data memory occupies addresses 0000h to 02FFh. This can be accessed using external direct addressing (i.e. using the MOVX instruction) or by using bank mapping direct addressing. Note that in the case of indirect addressing using the MOVX @DPTR instruction, if the address is larger than 02FFh, the VRS51C1000 will access off-chip memory in the external memory space using the external memory control signals Internal SRAM Control Register The 768 bytes of expanded SRAM of the VRS51C1000 can also be accessed using the MOVX @Rn instruction (where n = 0 or 1). This instruction can only access data in a range of 256 bytes. The internal SRAM Control Register, RCON, allows users to select which part of the expanded SRAM will be accessed by this instruction by configuring the value of the RAMS0 and RAMS1 bits. The default setting of the RAMS1 and RAMS0 bits is 00 (page 0). Each page has 256 bytes. Suppose that RAMS1, RAMS0 are set to 0 and 1 respectively and Rn has a value of 45h. Performing MOVX @Rn, A, (where n is 0 or 1) allows the user to transfer the value of A to the expanded SRAM at address 145h (page 1). Data Bank Control Register The DBANK register allows the user to enable the Data Bank Select function and map the entire contents of the SRAM memory in the range of 40h to 7Fh for applications that would require direct addressing of the expanded SRAM. The Data Bank Select function is activated by setting the Data Bank Select enable bit (BSE) to 1. Setting this bit to zero disables this function. The lower nibble of this register controls the mapping of the entire 1K byte on-chip SRAM space into the 040h-07Fh range. TABLE 14: DATA BANK CONTROL REGISTER (DBANK) – SFR 86H 7 BSE 6 5 Unused 4 3 BS3 2 BS2 1 BS1 0 BS0 TABLE 13: INTERNAL SRAM CONTROL REGISTER (RCON) - SFR 85H 7 Bit 7 6 5 4 3 2 1 0 6 5 4 Unused Mnemonic Unused Unused Unused Unused Unused Unused RAMS1 RAMS0 3 2 1 RAMS1 0 RAMS0 Description These two bits are used with Rn of instruction OVX @Rn, n=1,0 for mapping (see section on extended 768 bytes) RAMS1, RAMS0 Mapped area 00 000h-0FFh 01 100h-1FFh 10 200h-2FFh 11 XY00h-XYFF* *Externally generated Bit 7 Mnemonic BSE 6 5 4 3 2 1 0 Unused Unused Unused BS3 BS2 BS1 BS0 Description Data Bank Select Enable Bit BSE=1, Data Bank Select enabled BSE=0, Data Bank Select disabled Allows the mapping of the 1KB of SRAM into the 040h - 07Fh SRAM space ______________________________________________________________________________________________ www.ramtron.com page 10 of 48 VRS51C1000 Windowed access to all the 1KB on-chip SRAM in the range of 40h-7Fh is described in the following table. Description of Peripherals TABLE 15: BANK MAPPING DIRECT ADDRESSING MODE System Control Register BS3 BS2 BS1 BSO 040h~07fh mapping address 0 0 0 0 000h-03Fh 0 0 0 1 040h-07Fh 0 0 1 0 080h-0BFh 0 0 1 1 0C0h-0FFh 0 1 0 0 0000h-003Fh 0 1 0 1 0040h-007Fh 0 1 1 0 0080h-00BFh 0 1 1 1 00C0h-00FFh 1 0 0 0 0100h-013Fh 1 0 0 1 0140h-017Fh 1 0 1 0 0180h-01BFh 1 0 1 1 01C0h-01FFh 1 1 0 0 0200h-023Fh 1 1 0 1 0240h-027Fh 1 1 1 0 0280h-02BFh 1 1 1 1 02C0h-02FFh Note Lower 128 bytes SRAM Lower 128 bytes SRAM Upper 128 bytes SRAM Upper 128 bytes SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 byte SRAM On-chip expanded 768 byte SRAM On-chip expanded 768 byte SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 bytes SRAM On-chip expanded 768 bytes SRAM Example: User writes #55h to address 203h: MOV DBANK, #8CH MOV A, #55H ;Set bank mapping 40h-07Fh 0200h-023Fh ;Store #55H to A MOV 43H, A ;Write #55H to 0203h ;address to The following table describes the System Control Register (SYSCON). The WDRESET bit (7) indicates whether a reset was due to the Watchdog Timer overflow. The IAPE bit is used to enable and disable the IAP function. When set to 1, the XRAME bit allows the user to enable the on-chip expanded 768 bytes of SRAM. By default, upon reset, the XRAME bit is set to 0. Bit 0 of the SYSCON register is the ALE output inhibit bit. Setting this bit to 1 will inhibit the Fosc/6 clock signal output to the ALE pin. TABLE 16: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH 7 WDR 6 5 4 Unused Bit 7 Mnemonic WDR 6 5 4 3 2 1 0 Unused Unused Unused Unused IAPE XRAME ALEI 3 2 IAPE 1 XRAME 0 ALEI Description This is the Watchdog Timer reset bit. It will be set to 1 when the reset signal generated by WDT overflows. IAP function enable bit 768 bytes on-chip SRAM enable bit ALE output inhibit bit, which is used to reduce EMI. ______________________________________________________________________________________________ www.ramtron.com page 11 of 48 VRS51C1000 Power Control Register Input/Output Ports The VRS51C1000 provides two power saving modes, Idle and Power Down, which are controlled by the PDOWN and IDLE bits of the PCON register at address 87h. The VRS51C1000 has 36 bi-directional lines grouped into four 8-bit I/O ports and one 4-bit I/O port. These I/Os can be individually configured as input or output. TABLE 17: POWER CONTROL REGISTER (PCON) - SFR 87H 7 Bit 7 6 5 4 Unused Mnemonic SMOD 3 2 1 RAMS1 0 RAMS0 Description 1: Double the baud rate of the serial port frequency that was generated by Timer 1. 0: Normal serial port baud rate generated by Timer 1. 6 5 4 3 2 1 0 GF1 GF0 PDOWN IDLE General Purpose Flag General Purpose Flag Power down mode control bit Idle mode control bit In Idle mode, the processor is stopped but the oscillator continues to run. The content of the SRAM, I/O state and SFR registers are maintained and the Timer and external interrupts are left operational. The processor will be woken up when an external event, triggering an interrupt, occurs. In Power Down mode, the oscillator and peripherals are disabled. The contents of the SRAM and the SFR registers, however, are maintained. The only way to exit from the Power Down mode is via a hardware Reset (note that the Watchdog Timer is stopped in Power Down). When the VRS51C1000 is in power down, its current consumption drops to about 150uA. The SMOD bit of the PCON register controls the oscillator divisor applied to the Timer 1 when used as a baud rate generator for the UART. Setting this bit to 1 doubles the UART’s baud rate generator frequency. Except for the P0 I/Os, which are of the open drain type, each I/O is made of a transistor connected to ground and a weak pull-up resistor (transistor based). Writing a 0 in a given I/O port bit register will activate the transistor connected to VSS, this will bring the I/O to a LOW level. Writing a 1 into a given I/O port bit register de-activates the transistor between the pin and ground. In this case an internal weak pull-up resistor will bring the pin to a HIGH level (except for Port 0 which is open-drain). To use a given I/O as an input, a 1 must be written into its associated port register bit. By default, upon reset all I/Os are configured as inputs. The VRS51C1000 I/O ports are not designed to source current. Structure of the P1, P2, P3 and P4 Ports The following figure provides the general structure of the P1, P2 and P3 port I/Os. For these ports, the output stage is composed of a transistor (X1) and a transistor set configured as a weak pull-up. Note that the figure below does not show the intermediary logic that connects the output of the register and the output stage together because this logic varies with the auxiliary function of each port. FIGURE 6: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2, P3 AND P4 Read Register Vcc Pull-up Network Internal Bus Q IC Pin D Flip-Flop Write to Register Q X1 Read Pin Each I/O may be used independently as a logical input or output. When used as an input, as mentioned in previously, the corresponding bit register must be high. This corresponds to #Q=0 in the above figure. ______________________________________________________________________________________________ www.ramtron.com page 12 of 48 VRS51C1000 The transistor would be off (open-circuited) and current would flow from the VCC to the pin, generating a logical high at the output. Note that if an external device with a logical low value is connected to the pin, current will flow out of the pin. The presence of the pull-up resistance even when the I/O’s are configured as inputs means that a small current is likely to flow from the VRS51C1000 I/O’s pull-up resistors to the driving circuit when the inputs are driven low. For this reason, the VRS51C1000 I/O ports P1, P2, P3 and P4 are called “quasi bidirectional”. TABLE 18: PORT 0 REGISTER (P0) - SFR 80H 7 P0.7 Bit 7 6 5 4 3 2 1 0 6 P0.6 5 P0.5 Mnemonic P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 4 P0.4 3 P0.3 2 P0.2 1 P0.1 0 P0.0 Description For each bit of the P0 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. Port 2 Structure of Port 0 The internal structure of P0 is shown in the next figure. As opposed to the other ports, P0 is truly bi-directional. In other words, when used as an input, it is considered to be in a floating logical state (high impedance state). This arises from the absence of the internal pull-up resistance. The pull-up resistance is actually replaced by a transistor that is only used when the port is configured for accessing external memory/data bus (EA=0). When used as an I/O port, P0 acts as an open drain port and the use of an external pull-up resistor is likely to be required for most applications. FIGURE 7: PORT P0’S PARTICULAR STRUCTURE Address A0/A7 Read Register Control Port P2 is similar to Port 1 and Port 3, the difference being that P2 is used to drive the A8-A15 lines of the address bus when the EA line of the VRS51C1000 is held low at reset time or when a MOVX instruction is executed. Like the P0, P1 and P3 registers, the P2 register is bit addressable. TABLE 19: PORT 2 REGISTER (P2) - SFR A0H 7 P2.7 Bit 7 6 5 4 3 2 1 0 6 P2.6 5 P2.5 Mnemonic P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 4 P2.4 3 P2.3 2 P2.2 1 P2.1 0 P2.0 Description For each bit of the P2 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. Vcc Internal Bus Q IC Pin D Flip-Flop Write to Register Q X1 Read Pin When P0 is used as an external memory bus input (for a MOVX instruction, for example), the outputs of the register are automatically forced to 1. The bit addressable P0 register, located at address 80h, controls the P0 pin directions when used as I/O (see following table). ______________________________________________________________________________________________ www.ramtron.com page 13 of 48 VRS51C1000 Auxiliary Port 1 Functions Port P0 and P2 as Address and Data Bus The output stage may receive data from two sources: o The outputs of register P0 or the bus address itself multiplexed with the data bus for P0. o The outputs of the P2 register or the high byte (A8 through A15) of the bus address for the P2 port. FIGURE 8: P2 PORT STRUCTURE Read Register The Port 1 I/O pins are shared with the PWM outputs, Timer 2 EXT and T2 inputs as shown below: Pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 PWM0 PWM1 PWM2 PWM1 output PWM2 output PWM3 PWM3 output PWM4 PWM4 output PWM0 output Port 3 Pull-up Network Q IC Pin D Flip-Flop Write to Register Function Timer 2 counter input Timer2 Auxiliary input Vcc Address Internal Bus Mnemonic T2 T2EX structure of Port 3 is similar to that of Port 1. X1 Q TABLE 21: PORT 3 REGISTER (P3) - SFR B0H Control 7 P3.7 6 P3.6 5 P3.5 4 P3.4 3 P3.3 2 P3.2 1 P3.1 0 P3.0 Read Pin When the ports are used as an address or data bus, the special function registers P0 and P2 are disconnected from the output stage, the 8 bits of the P0 register are forced to 1 and the content of the P2 register remains constant. Port 1 The P1 register controls the direction of the Port 1 I/O pins. Writing a 1 into the P1.x bit (see following table) of the P1 register configures the bit as an output, presenting a logic 1 to the corresponding I/O pin, or enables use of the I/O pin as an input. Writing a 0 activates the output “pull-down” transistor which will force the corresponding I/O line to a logic Low. Bit 7 6 5 4 3 2 1 0 Mnemonic P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 Description For each bit of the P3 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. To configure P3 pins as input or use alternate P3 function the corresponding bit must be set to 1. Auxiliary P3 Port Functions The Port 3 I/O pins are shared with the UART interface, INT0 and the INT1 interrupts, Timer 0 and Timer 1 inputs and finally the #WR and #RD lines when external memory accesses are performed. TABLE 20: PORT 1 REGISTER (P1) - SFR 90H 7 P1.7 Bit 7 6 5 4 3 2 1 0 6 P1.6 5 P1.5 Mnemonic P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0 Description For each bit of the P1 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up bring the I/O to 5V. ______________________________________________________________________________________________ www.ramtron.com page 14 of 48 VRS51C1000 FIGURE 9: P3 PORT STRUCTURE Port 4 Auxiliary Function: Output Read Register Port 4 has four related I/O pins and its port address is located at 0D8H. Vcc IC Pin Q Internal Bus X1 TABLE 23: PORT 4 (P4) - SFR D8H 7 D Flip-Flop Write to Register Auxiliary Function: Input The following table describes the auxiliary function of the Port 3 I/O pins. TABLE 22: P3 AUXILIARY FUNCTION TABLE Pin P3.0 Mnemonic RXD P3.1 TXD P3.3 P3.4 P3.5 P3.6 P3.7 4 3 P4.3 2 P4.2 1 P4.1 0 P4.0 Q Read Pin P3.2 6 5 Unused INT0 INT1 T0 T1 WR RD Function Serial Port: Receive data in asynchronous mode. Input and output data in synchronous mode. Serial Port: Transmit data in asynchronous mode. Output clock value in synchronous mode. External Interrupt 0 Timer 0 Control Input External Interrupt 1 Timer 1 Control Input Timer 0 Counter Input Timer 1 Counter Input Write signal for external memory Read signal for external memory Bit 7 6 5 4 3 2 1 0 Mnemonic Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0 Description Used to output the setting to pins P4.3, P4.2, P4.1, P4.0 respectively. On the VRS51C1000, the Port 4 output buffers can sink up to 20mA, which allow direct drive of LED displays. Software Port Control Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the content of the associated port register. These instructions are called read-modify-write instructions. A list of these instructions may be found in the table below. Upon execution of these instructions, the content of the port register (at least 1 bit) is modified. The other read instructions take the present state of the input into account. For example, the instruction ANL P3,#01h obtains the value in the P3 register; performs the desired logic operation with the constant 01h; and recopies the result into the P3 register. When users want to take the present state of the inputs into account, they must first read these states and perform an AND operation between the read value and the constant. MOV A, P3; State of the inputs in the accumulator ANL A, #01; AND operation between P3 and 01h ______________________________________________________________________________________________ www.ramtron.com page 15 of 48 VRS51C1000 When the port is used as an output, the register contains information on the state of the output pins. Measuring the state of an output directly on the pin is inaccurate because the electrical level depends mostly on the type of charge that is applied to it. The functions shown below take the value of the register rather than that of the pin. TABLE 24: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER VALUES Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV P.,C CLR P.x SETB P.x Function Logical AND ex: ANL P0, A Logical OR ex: ORL P2, #01110000B Exclusive OR ex: XRL P1, A Jump if the bit of the port is set to 0 Complement one bit of the port Increment the port register by 1 Decrement the port register by 1 Decrement by 1 and jump if the result is not equal to 0 Copy the held bit C to the port Set the port bit to 0 Set the port bit to 1 I/O Ports Driving Capability The maximum allowable continuous current that the device can sink on an I/O port is described in the following table. Maximum sink current on one given I/O Maximum total sink current for P0 Maximum total sink current for P1, 2, 3 Maximum total sink current for P4 Maximum total sink current on all I/O 10mA 26mA 15mA 20mA 91mA As explained previously, the Port 4 output buffers can sink up to 20mA, which allow driving of LED displays. It is not recommended to exceed the sink current outlined in the above table. Doing so is likely to make the low-level output voltage exceed the device’s specification and it is likely to affect the device’s reliability. The VRS51C1000 I/O ports are not designed to source current. Port Operation Timing Writing to a Port (Output) VRS51C1000 Timers When an operation results in a modification of the content in a port register, the new value is placed at the output of the D flip-flop during the last machine cycle that the instruction needed to execute. The VRS51C1000 includes three 16-bit timers: Timer 0, Timer 1 and Timer 2. Reading a Port (Input) In order to be sampled, the signal duration present on the I/O inputs must be longer than Fosc/12. The Timers can operate in two modes: o Event counting mode o Timer mode When operating in event counting mode, the counter is incremented each time an external event, such as a transition in the logical state of the Timer input (T0, T1, T2 input), is detected. When operating in Timer mode, the counter is incremented by the microcontroller’s system clock (Fosc/12) or by a divided version of it. ______________________________________________________________________________________________ www.ramtron.com page 16 of 48 VRS51C1000 Timer 0 and Timer 1 Timer 0, Timer 1 Counter / Timer Functions Timers 0 and 1 have four Modes of operation. These Modes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. Timer 1 can also be used as a baud rate generator to generate communication frequencies for the serial interface. Timing Function Timer 1 and Timer 0 are configured by the TMOD and TCON registers. TABLE 25: TIMER MODE CONTROL REGISTER (TMOD) – SFR 89H 7 6 5 4 3 2 1 0 GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 Bit 7 6 5 4 3 Mnemonic GATE1 C/T1 T1M1 T1M0 GATE0 2 C/T0 1 0 T0M1 T0M0 Description 1: Enables external gate control (pin INT1 for Counter 1). When INT1 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T1IN input pin. Selects timer or counter operation (Timer 1). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects the operating mode of Timer/Counter 1 If set, enables external gate control (pin INT0 for Counter 0). When INT0 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T0IN input pin. Selects timer or counter operation (Timer 0). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects the operating mode of Timer/Counter 0. The table below summarizes the four modes of operation of Timers 0 and 1. The timer operating mode is selected by the bits T1M1/T1M0 and T0M1/T0M0 of the TMOD register. When Timer 1 or Timer 0 is configured to operate as a Timer, its value is automatically incremented at every machine cycle. Once the Timer value rolls over, a flag is raised and the counter acquires a value of zero. The overflow flags (TF0 and TF1) are located in the TCON register. The TR0 and TR1 bit of the TCON register gates the corresponding timer operation. In order for the Timer to run, the corresponding TRx bit must be set to 1. The IT0 and IT1 bits of the TCON register control the event that will trigger the External Interrupt as follows: IT0 = 0: The INT0, if enabled, occurs if a Low Level is present on P3.2 IT0 = 1: The INT0, if enabled, occurs if a High to Low transition is detected on P3.2 IT1 = 0: The INT1, if enabled, occurs if a Low Level is present on P3.3 IT1 = 1: The INT1, if enabled, occurs if a High to Low transition is detected on P3.3 The IE0 and IE1 bits of the TCON register are External flags that indicate that a transition has been detected on the INT0 and INT1 interrupt pins, respectively. If the external interrupt is configured as edge sensitive, the corresponding IE0 and IE1 flag is automatically cleared when the corresponding interrupt is serviced. If the external interrupt is configured as level sensitive, then the corresponding flag must be cleared by the software. TABLE 26: TIMER/COUNTER MODE DESCRIPTION SUMMARY M1 M0 Mode Function 0 0 1 0 1 0 Mode 0 Mode 1 Mode 2 1 1 Mode 3 13-bit Counter 16-bit Counter 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, the value of THx is copied to TLx. If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. ______________________________________________________________________________________________ www.ramtron.com page 17 of 48 VRS51C1000 TABLE 27: TIMER 0 AND 1 CONTROL REGISTER (TCON) –SFR 88H 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit 7 Mnemonic TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Description Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Timer 0 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Interrupt Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 1 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Counting Function When operating as a counter, the Timer’s register is incremented at every falling edge of the T0 and T1 signals located at the input of the timer. When the sampling circuit sees a high immediately followed by a low in the next machine cycle, the counter is incremented. Two machine cycles are required to detect and record an event. In order to be properly sampled, the duration of the event presented to the Timer input should be greater than 1/24 of the oscillator frequency. Timer 0 / Timer 1 Operating Modes to 1. The count value is validated as soon as TRx goes to 1 and the GATE bit is 0, or when INTx is 1. FIGURE 10: TIMER/COUNTER 1 MODE 0: 13-BIT COUNTER Fosc ÷12 0 TL1 / TL0 C/T1 / C/T0 =0 CLK 1 0 4 7 Mode 0 C/T1 / CT0 =1 Control T1/T0 pin Mode 1 TR1/TR0 GATE1 / GATE0 0 TH1 / TH0 7 INT1 / INT0 pin TF1 / TF0 INT Mode 1 Mode 1 is almost identical to Mode 0, with the difference being that in Mode 1, the counter/timer uses the full 16-bits of the Timer. Mode 2 In this Mode, the register of the Timer is configured as an 8-bit auto-re-loadable Counter/Timer. In Mode 2, the TLx is used as the counter. In the event of a counter overflow, the TFx flag is set to 1 and the value contained in THx, which is preset by software, is reloaded into the TLx counter. The value of THx remains unchanged. FIGURE 11: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD Fosc ÷12 0 1 T1 / T0 Pin The user may change the operating mode by setting the M1 and M0 bits of the TMOD SFR. C/T1 / C/T0 = 1 TL1 / TL0 0 7 C/T1 / C/T0 = 1 Control Reload 0 TH1 / TH0 7 TR1 / TR0 Mode 0 A schematic representation of this mode of operation is presented in the figure below. In Mode 0, the Timer operates as 13-bit counter made up of 5 LSBs from the TLx register and the 8 upper bits coming from the THx register. When an overflow causes the value of the register to roll over to 0, the TFx interrupt signal goes GATE1 / GATE0 TF1 / TF0 INT INT1 / INT0 pin ______________________________________________________________________________________________ www.ramtron.com page 18 of 48 VRS51C1000 Mode 3 In Mode 3, Timer 1 is blocked as if its’ control bit, TR1, was set to 0. In this mode, Timer 0’s registers TL0 and TH0 are configured as two separate 8-bit counters. The TL0 counter uses Timer 0’s control bits (C/T, GATE, TR0, INT0, TF0), the TH0 counter is held in Timer Mode (counting machine cycles) and gains control over TR1 and TF1 from Timer 1. At this point, TH0 controls the Timer 1 interrupt. 5 4 RCLK TCLK FIGURE 12: TIMER/COUNTER 0 MODE 3 TH0 CLK 0 7 3 EXEN2 2 TR2 Control TF1 TR1 Fosc INTERRUPT ÷12 0 TL0 C/T =0 CLK 1 0 7 C/T =1 Control T0PIN TF0 INTERRUPT 1 C/T2 TR0 GATE 0 INT0 PIN CP/RL2 Timer 2 Timer 2 of the VRS51C1000 is a 16-bit Timer/Counter and is similar to Timers 0 and 1 in that it can operate either as an event counter or as a timer. This is controlled by the C/T2 bit in the T2CON special function register. Timer 2 has three operating modes Auto-Load, Capture and Baud Rate Generator. These modes are selected via the T2CON SFR. The following table describes T2CON special function register bits. Serial Port Receive Clock Source. 1: Causes Serial Port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port receive clock. Serial Port Transmit Clock. 1: Causes Serial Port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port transmit clock. Timer 2 External Mode Enable. 1: Allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. 0: Causes Timer 2 to ignore events at T2EX. Start/Stop Control for Timer 2. 1: Start Timer 2 0: Stop Timer 2 Timer or Counter Select (Timer 2) 1: External event counter falling edge triggered. 0: Internal Timer (OSC/12) Capture/Reload Select. 1: Capture of Timer 2 value into RCAP2H, RCAP2L is performed if EXEN2=1 and a negative transitions occurs on the T2EX pin. The capture mode requires RCLK and TCLK to be 0. 0: Auto-reload reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2=1. When either RCK =1 or TCLK =1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. The Timer 2 Mode selection bits and their function are described in the following table. TABLE 29: TIMER 2 MODE SELECTION BITS RCLK + TCLK CP/RL2 TR2 CP/RL2 0 0 1 Description Timer 2 Overflow Flag: Set by an overflow of Timer 2 and must be cleared by software. TF2 will not be set when either RCLK =1 or TCLK =1. Timer 2 external flag change in state occurs when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. When Timer 2 is enabled, EXF=1 will cause the CPU to Vector to the Timer 2 interrupt routine. Note that EXF2 must be cleared by software. 0 1 1 1 X 1 X X 0 TABLE 28: TIMER 2 CONTROL REGISTER (T2CON) –SFR C8H 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 Bit Mnemonic 7 TF2 6 EXF2 MODE 16-bit AutoReload Mode 16-bit Capture Mode Baud Rate Generator Mode Timer 2 stops The modes are discussed in the following sections. ______________________________________________________________________________________________ www.ramtron.com page 19 of 48 VRS51C1000 If EXEN2=1, Timer 2 still performs the above operation, however, additionally, a 1 to 0 transition at the external T2EX input will also trigger an anticipated reload of Timer 2 with the value stored in RCAP2L, RCAP2H and set EXF2. Timer 2 Capture Mode In Capture Mode, the EXEN2 bit of the T2CON register controls whether an external transition on the T2EX pin will trigger capture of the timer value. FIGURE 14: TIMER 2 IN AUTO-RELOAD MODE When EXEN2 = 0, Timer 2 acts as a 16-bit timer or counter, which, upon overflowing, will set the TF2 bit (Timer 2 overflow bit). This overflow can be used to generate an interrupt. FOSC ÷12 0 TIMER 0 C/T2 1 FIGURE 13: TIMER 2 IN CAPTURE MODE TL2 TH2 7 0 7 0 7 COUNTER T2 pin 0 TR2 RCAP2L RCAP2H 7 TF2 FOSC T2EX pin ÷12 0 EXF2 EXEN2 TIMER 0 TL2 7 TH2 0 7 C/T2 Timer 2 Interrupt 1 COUNTER T2 pin 0 RCAP2L 7 0 RCAP2H 7 TR2 TF2 EXF2 T2EX pin EXEN2 Timer 2 Interrupt When EXEN2 = 1, the above still applies, however, in addition, it is possible to allow a 1 to 0 transition at the T2EX input to cause the current value stored in the Timer 2 registers (TL2 and TH2) to be captured into the RCAP2L and RCAP2H registers. Furthermore, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Note that both EXF2 and TF2 share the same interrupt vector. Timer 2 Auto-Reload Mode In this mode, there are also two options controlled by the EXEN2 bit in the T2CON register. If EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value in the RCAP2L and RCAP2H registers previously initialised. In this mode, Timer 2 can be used as a baud rate generator source for the serial port. ______________________________________________________________________________________________ www.ramtron.com page 20 of 48 VRS51C1000 Serial Port Control Register Timer 2 Baud Rate Generator Mode Timer 2 can be used for UART Baud Rate generation. This Mode is activated when RCLK is set to 1 and/or TCLK is set to 1. This Mode is described further in the serial port section. The SCON (serial port control) register contains control and status information, and includes the 9th data bit for transmit/receive (TB8/RB8 if required), mode selection bits and serial port interrupt bits (TI and RI). TABLE 30: SERIAL PORT CONTROL REGISTER (SCON) – SFR 98H 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI FIGURE 15: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE FOSC ÷2 0 TIMER TL2 0 C/T2 1 TH2 7 0 7 0 7 Bit 7 Mnemonic SM0 6 SM1 5 SM2 COUNTER T2 pin 0 RCAP2L TR2 RCAP2H 1 0 0 Timer 1 Overflow ÷2 ÷16 TX Clock ÷16 RX Clock 1 0 1 SMOD T2EX pin TCLK 7 In Modes 2 or 3 if SM2 is set to 1, RI will th not be activated if the received 9 data bit (RB8) is 0. RCLK EXF2 Timer 2 Interrupt Request 4 REN 3 TB8 2 RB8 In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. Serial Reception Enable Bit This bit must be set by software and cleared by software. 1: Serial reception enabled 0: Serial reception disabled th 9 data bit transmitted in Modes 2 and 3 This bit must be set by software and cleared by software. th 9 data bit received in Modes 2 and 3. TI In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, this bit is not used. This bit must be cleared by software. Transmission Interrupt flag. RI Automatically set to 1 when: th • The 8 bit has been sent in Mode 0. • Automatically set to 1 when the stop bit has been sent in the other modes. This bit must be cleared by software. Reception Interrupt flag EXEN2 UART Serial Port The VRS51C1000’s serial port can operate in full duplex mode (it can transmit and receive data simultaneously). This occurs at the same speed if one timer is assigned as the clock source for both transmission and reception, and at different speeds if transmission and reception are each controlled by their own timer. The VRS51C1000 serial port includes a double buffer for the reciever, which allows reception of a byte even if the previously received one has not been retrieved from the receive register by the processor. However, if the first byte still has not been read by the time reception of the second byte is complete, the byte present in the receive buffer will be lost. 1 0 The SBUF register provides access to the transmit and receive registers of the serial port. Reading from the SBUF register will access the receive register, while a write to the SBUF loads the transmit register. Description Bit to select mode of operation (see table below) Bit to select mode of operation (see table below) Multiprocessor communication is possible in Modes 2 and 3. Automatically set to 1 when: th • The 8 bit has been received in Mode 0. • Automatically set to 1 when the stop bit has been sent in the other modes (see SM2 exception). This bit must be cleared by software. ______________________________________________________________________________________________ www.ramtron.com page 21 of 48 VRS51C1000 TABLE 31: SERIAL PORT MODES OF OPERATION SM0 SM1 Mode Description Baud Rate 0 0 1 0 1 0 0 1 2 Shift Register 8-bit UART 9-bit UART 1 1 3 9-bit UART Fosc/12 Variable Fosc/64 or Fosc/32 Variable UART Operating Modes The VRS51C1000’s serial port can operate in four different Modes. In all four Modes, a transmission is initiated by an instruction that uses the SBUF register as a destination register. In Mode 0, reception is initiated by setting RI to 0 and REN to 1. An incoming start bit initiates reception in the other modes, provided that REN is set to 1. The following paragraphs describe these four Modes. UART Operation in Mode 0 In this Mode, the serial data exits and enters through the RXD pin. TXD is used to output the shift clock. The signal is composed of 8 data bits starting with the LSB. The baud rate in this mode is 1/12 the oscillator frequency. FIGURE 16: SERIAL PORT MODE 0 BLOCK DIAGRAM Internal Bus 1 Write to SBUF Q S SBUF Shift CLK ZERO DETECTOR Send TI Serial Port Interrupt RI RX Clock At every machine cycle in which SEND is active, the contents of the transmit shift register are shifted to the right by one position. Zeros come in from the left as data bits shift out to the right. The TX control block sends its final shift and deactivates SEND while setting T1 after one condition is fulfilled. When the MSB of the data byte is at the output position of the shift register; the 1 that was initially loaded into the 9th position is just to the left of the MSB; and all positions to the left of that contain zeros. Once these conditions are met, the deactivation of SEND and the setting of T1 occurs at T1 of the 10th machine cycle after the “write to SBUF” pulse. TXD P3.1 When REN and R1 are set to 1 and 0, respectively, reception is initiated. The bits 11111110 are written to the receive shift register at the end of the next machine cycle by the RX control unit. In the following phase, the RX control unit will activate RECEIVE. Shift TX Clock The SEND signal enables the output of the shift register to the alternate output function line of P3.0 and enables SHIFT CLOCK to the alternate output function line of P3.1. UART Reception in Mode 0 Shift Clock TX Control Unit Fosc/12 Any instruction that uses SBUF as a destination register may initiate a transmission. The “write to SBUF” signal also loads a 1 into the 9th position of the transmit shift register and informs the TX control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between a write to SBUF instruction and the activation of SEND. RXD P3.0 D Start UART Transmission in Mode 0 Receive RX Control Unit RI REN Start Shift 1 RXD P3.0 Input Function 1 1 1 1 1 1 0 Shift Register RXD P3.0 SBUF READ SBUF Internal Bus The contents of the receive shift register are shifted one position to the left at the end of every machine cycle during which RECEIVE is active. The value that comes in from the right is the value that was sampled at the P3.0 pin. 1’s are shifted out to the left as data bits are shifted in from the right. The RX control block is flagged to do one last shift and load SBUF when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register. ______________________________________________________________________________________________ www.ramtron.com page 22 of 48 VRS51C1000 UART Operation in Mode 1 UART Transmission in Mode 1 Transmission in this mode is initiated by any instruction that makes use of SBUF as a destination register. The 9th bit position of the transmit shift register is loaded by the “write to SBUF” signal. This event also flags/informs the TX Control Unit that a transmission has been requested. In Mode 1 operation, 10 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low); 8 data bits (LSB first) and one Stop bit (high). The reception is completed once the Stop bit sets the RB8 flag in the SCON register. Either Timer 1 or Timer 2 controls the baud rate in this mode. It is after the next rollover in the divide-by-16 counter when transmission actually begins. It follows that the bit times are synchronized to the divide-by-16 counter and not to the “write to SBUF” signal. The following diagram shows the serial port structure when configured in Mode 1. FIGURE 17: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM Internal Bus 1 Write to SBUF Timer 1 Overflow Q S SBUF TXD D CLK Timer 2 Overflow ÷2 ZERO DETECTOR 0 1 SMOD 0 Shift Start 1 ÷16 0 TX Clock 1 RCLK Send TI ÷16 Serial Port Interrupt RX Clock 1-0 Transition Detector RXD Data TX Control Unit TCLK Start Bit Detector RI Load SBUF RX Control Unit SHIFT 9-Bit Shift Register Shift LOAD SBUF SBUF READ SBUF Internal Bus When a transmission begins, it places the start bit at TXD. Data transmission is activated one bit time later. This activation enables the output bit of the transmit shift register to TXD. One bit time after that, the first shift pulse occurs. In this Mode, zeros are clocked in from the left as data bits are shifted out to the right. When the most significant bit of the data byte is at the output position of the shift register, the 1 that was initially loaded into the 9th position is to the immediate left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control Unit to shift one more time. UART Reception in Mode 1 A one to zero transition at pin RXD will initiate reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. The divide-by-16 counter is reset in order to align its rollovers with the boundaries of the incoming bit times. In total, there are 16 states in the counter. During the 7th, 8th and 9th counter states of each bit time; the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. The purpose of doing this is for noise rejection. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. All false start bits are rejected by doing this. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1’s shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register, (9- ______________________________________________________________________________________________ www.ramtron.com page 23 of 48 VRS51C1000 bit register), it causes the UART’s receive controller block to perform one last shift operation: to set RI and to load SBUF and RB8. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: o o Either SM2 = 0 or the received stop bit = 1 RI = 0 FIGURE 18: SERIAL PORT MODE 2 BLOCK DIAGRAM Internal Bus 1 Write to SBUF Q S Fosc/2 SBUF CLK ZERO DETECTOR ÷2 If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. If one of these conditions is not met, the received frame is completely lost. At this time, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition in RXD. TXD D 0 1 Shift Stop Start SMOD ÷16 TX Clock Send TI ÷16 Sample 1-0 Transition Detector Start Data TX Control Unit Serial Port Interrupt RX Clock Control RI Load SBUF RX Control Unit SHIFT UART Operation in Mode 2 RXD In Mode 2 a total of 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). th For transmission, the 9 data bit comes from the TB8 bit of SCON. For example, the parity bit P in the PSW could be moved into TB8. Bit Detector 9-Bit Shift Register Shift LOAD SBUF SBUF READ SBUF Internal Bus In the case of receive, the 9th data bit is automatically written into RB8 of the SCON register. In Mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. ______________________________________________________________________________________________ www.ramtron.com page 24 of 48 VRS51C1000 UART Operation in Mode 3 UART in Mode 2 and 3: Additional Information In Mode 3, 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). As mentioned previously, for an operation in Modes 2 and 3, 11 bits are transmitted (through TXD) or received (through RXD). The signal comprises: a logical low Start bit, 8 data bits (LSB first), a programmable 9th data bit, and one logical high Stop bit. On transmit, (TB8 in SCON) can be assigned the value of 0 or 1. On receive; the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from either Timer 1 or Timer 2 depending on the states of TCLK and RCLK. Mode 3 is identical to Mode 2 in all respects but one: the baud rate. Either Timer 1 or Timer 2 generates the baud rate in Mode 3. FIGURE 19: SERIAL PORT MODE 3 BLOCK DIAGRAM Internal Bus 1 Write to SBUF Timer 1 Overflow Q S UART Transmission in Mode 2 and Mode 3 SBUF TXD D CLK Timer 2 Overflow ÷2 ZERO DETECTOR 0 1 SMOD 0 Start 1 Shift ÷16 0 Data TX Control Unit TCLK TX Clock 1 RCLK Send TI ÷16 SAMPLE RX Clock 1-0 Transition Detector Start RXD Bit Detector Serial Port Interrupt RI Load SBUF RX Control Unit SHIFT 9-Bit Shift Register Shift LOAD SBUF SBUF READ SBUF Internal Bus The transmission is initiated by any instruction that makes use of SBUF as the destination register. The 9th bit position of the transmit shift register is loaded by the “write to SBUF” signal. This event also informs the UART transmission control unit that a transmission has been requested. After the next rollover in the divide-by16 counter, a transmission actually starts at the beginning of the machine cycle. It follows that the bit times are synchronized to the divide-by-16 counter and not to the “write to SBUF” signal, as in the previous mode. Transmissions begin when the SEND signal is activated, which places the Start bit on TXD pin. Data is activated one bit time later. This activation enables the output bit of the transmit shift register to the TXD pin. The first shift pulse occurs one bit time after that. The first shift clocks a Stop bit (1) into the 9th bit position of the shift register on TXD. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition signals to the TX control unit to shift one more time and set TI, while deactivating SEND. This occurs at the 11th divide-by16 rollover after “write to SBUF”. ______________________________________________________________________________________________ www.ramtron.com page 25 of 48 VRS51C1000 UART Reception in Mode 2 and Mode 3 UART Baud Rates One to zero transitions on the RXD pin initiate reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, the 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. In Mode 0, the baud rate is fixed and can be represented by the following formula: During the 7th, 8th and 9th counter states of each bit time; the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1’s shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register (9-bit register), it tells the RX control block to do one more shift, to set RI, and to load SBUF and RB8. The signal to set RI and to load SBUF and RB8 will be generated if, and only if, the following conditions are satisfied at the instance when the final shift pulse is generated: - Either SM2 = 0 or the received 9th bit equal 1 RI = 0 If both conditions are met, the 9th data bit received goes into RB8, and the first 8 data bits go into SBUF. If one of these conditions is not met, the received frame is completely lost. One bit time later, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition at the RXD input. Please note that the value of the received stop bit is unrelated to SBUF, RB8 or RI. Mode 0 Baud Rate = Oscillator Frequency 12 In Mode 2, the baud rate depends on the value of the SMOD bit in the PCON SFR. From the formula below, we can see that if SMOD = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = 2SMOD x (Oscillator Frequency) 64 The Timer 1 and/or Timer 2 overflow rate determines the baud rates in Modes 1 and 3. Generating UART Baud Rate with Timer 1 When Timer 1 functions as a baud rate generator, the baud rate in Modes 1 and 3 are determined by the Timer 1 overflow rate. Mode 1,3 Baud Rate = 2SMODx Timer 1 Overflow Rate 32 Timer 1 must be configured as an 8-bit timer (TL1) with auto-reload with TH1 value when an overflow occurs (Mode 2). In this application, the Timer 1 interrupt should be disabled. The two following formulas can be used to calculate the baud rate and the reload value to be written into the TH1 register. Mode 1,3 Baud Rate = SMOD x Fosc 2 32 x 12(256 – TH1) ______________________________________________________________________________________________ www.ramtron.com page 26 of 48 VRS51C1000 The value to write into the TH1 register is defined by the following formula: TH1 = 256 - 2SMODx Fosc 32 x 12x (Baud Rate) The following formula can be used to calculate the baud rate in modes 1 and 3 using the Timer 2: (NTD where are the Modes 1, 3 Baud Rateformulas?) = Oscillator Frequency 32x[65536 – (RCAP2H, RCAP2L)] Generating UART Baud Rates with Timer 2 Timer 2 is often preferred to generate the baud rate, as it can be easily configured to operate as a 16-bit timer with auto-reload. This allows for much better resolution than using Timer 1 in 8-bit auto-reload mode. The baud rate using Timer 2 is defined as: The formula below is used to define the reload value to put into the RCAP2h, RCAP2L registers to achieve a given baud rate. (RCAP2H, RCAP2L) = 65536 - Fosc 32x[Baud Rate] Mode 1,3 Baud Rate = Timer 2 Overflow Rate 16 The timer can be configured as either a timer or a counter in any of its 3 running modes. In most typical applications, it is configured as a timer (C/T2 is set to 0). To make the Timer 2 operate as a baud rate generator, the TCLK and RCLK bits of the T2CON register must be set to 1. The baud rate generator mode is similar to the autoreload mode in that an overflow in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. However, when Timer 2 is configured as a baud rate generator, its clock source is Osc/2. In the above formula, RCAP2H and RCAP2L are the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt and because of this, Timer 2 interrupt does not have to be disabled when Timer 2 is configured in baud rate generator mode. Furthermore, when Timer 2 is configured as UART baud rate generator and running (TR2 is set to 1), the user should not try to perform read or write operations to the TH2 or TL2 and RCAP2H, RCAP2L registers ______________________________________________________________________________________________ www.ramtron.com page 27 of 48 VRS51C1000 Timer 1 Reload Value in Modes 1 & 3 for UART Baud Rate The following table provides examples of Timer 1, 8-bit reload value when used as a UART Baud Rate generator and the SMOD bit of the PCON register is set to 1. 115200bps 57600bps 38400bps 31250bps 19200bps 9600bps 2400bps 1200bps 300bps 22.184MHz FFh Feh FDh FAh F4h D0h A0h - 16.000MHz DDh BBh - 14.745MHz FEh FCh F8h E0h C0h 00h 12.000MHz FEh E6h CCh 30h 11.059MHz FFh FDh FAh E8h D0h 40h 8.000MHz DDh 75h 3.57MHz C2h Timer 2 Reload Value in Modes 1 & 3 for UART Baud Rate The following are examples of [RCAP2H, RCAP2L] reload values for Timer 2 when it is used as baud rate generator for the VRS51C1000 UART 230400bps 115200bps 57600bps 38400bps 31250bps 19200bps 9600bps 2400bps 1200bps 300bps 22.184MHz FFFDh FFFAh FFF4h FFEEh FFEAh FFDCh FFB8h FEE0h FDC0h F700h 16.000MHz FFF3h FFF0h FFE6h FFCCh FF30h FE5Fh F97Dh 14.745MHz FFFEh FFFCh FFF8h FFF4h FFF1h FFE8h FFD0h FF40h FE80h FA00h 12.000MHz FFF4h FFD9h FF64h FEC7h FB1Eh 11.059MHz FFFDh FFFAh FFF7h FFF5h FFEEh FFDCh FF70h FEE0h FB80h 8.000MHz FFF8h FFF3h FFE6h FF98h FF30h FCBEh 3.57MHz FFD1h FFA3h FE8Bh UART INITIALIZATION in Mode 3 using Timer 1 UART Initialization in Mode 3, Using Timer 2 ;*** INTIALIZE THE UART @ 9600BPS, Fosc=11.0592MHz ;*** INTIALIZE THE UART @57600BPS, Fosc=11.0592MHz INISER0T1I: MOV A,T2CON ANL A,#11001111B MOV T2CON,A MOV PCON,#80H MOV TL1,#0FAH MOV TH1,#0FAH INISER0T2I: MOV ;RETRIEVE CURRENT VALUE OF T2CON ;RCLK & TCLK BIT = 0 -> TO USE TIMER1 ;BAUD RATE GENERATOR SOURCE FOR UART ;SET THE SMOD BIT TO 1 ;CONFIG TIMER1 AT 8BIT WITH AUTO-RELOAD ;CALCULATE THE TIMER 1 RELOAD VALUE ;TH1 = [(2^SMOD) * Fosc] / (32 * 12 * Fcomm) ;TH1 FOR 9600BPS @ 11.059MHz = FAh MOV SCON,#05Ah ;CONFIG SCON_0 MODE_1 MOV TMOD,#00100000B ;CONFIG TIMER 1 IN MODE 2, 8BIT ; + AUTO RELOAD MOV TCON,#01000000B ;START TIMER1 CLR CLR SCON.0 SCON.1 ;CLEAR UART RX, TX FLAGS MOV SBUF,#DATA ;SEND ONE BYTE ON THE SERIAL PORT MOV MOV SCON,#05Ah ;CONFIG SCON_0 MODE_1, ;CALCULATE RELOAD VALUE WITH T2 ;RCAP2H,RCAP2L = 65536 - [ Fosc / (32*Fcomm)] RCAP2H,#0FFh RCAP2L,#0DCh ;RELOAD VALUE 57600bps, 11.059MHz =FFFAh ; MOV T2CON,#034h ;SERIAL PORT0, TIMER2 RELOAD START CLR CLR SCON.0 SCON.1 ;CLEAR UART RX, TX FLAGS MOV SBUF,#DATA ;SEND ONE BYTE ON THE SERIAL PORT ______________________________________________________________________________________________ www.ramtron.com page 28 of 48 VRS51C1000 Interrupts Interrupt Vectors The VRS51C1000 has 8 interrupt sources (9 if we include the WDT) and 7 interrupt vectors (including reset) for handling. The following table specifies each interrupt source, its flag and its vector address. The interrupts are enabled via the IE register shown below: TABLE 32: IE INTERRUPT ENABLE REGISTER –SFR A8H 7 6 5 4 3 EA - ET2 ES ET1 Bit 7 Mnemonic EA 6 - 5 4 3 2 1 0 ET2 ES ET1 EX1 ET0 EX0 2 EX1 1 0 ET0 EX0 Description Disables All Interrupts 0: no interrupt acknowledgment 1: Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Timer 2 Interrupt Enable Bit Serial Port Interrupt Enable Bit Timer 1 Interrupt Enable Bit External Interrupt 1 Enable Bit Timer 0 Interrupt Enable Bit External Interrupt 0 Enable Bit The following figure illustrates the various interrupt sources on the VRS51C1000. IT0 Interrupt Source RESET (+ WDT) INT0 Timer 0 INT1 Timer 1 Serial Port Timer 2 Flag WDR IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 Vector Address 0000h* 0003h 000Bh 0013h 001Bh 0023h 002Bh *If location 0000h = FFh, the PC jump to the ISP program. External Interrupts The VRS51C1000 has two external interrupt inputs (INT0 and INT1). These interrupt lines are shared with the P3.2 and P3.3 I/Os. Bits IT0 and IT1 of the TCON register determine whether the external interrupts are level or edge sensitive. If ITx = 1, the interrupt will be raised when a 1 to 0 transition occurs at the interrupt pin. The duration of the transition must be at least equal to 12 oscillator cycles. FIGURE 20: INTERRUPT SOURCES INT0 TABLE 33: INTERRUPT VECTOR ADDRESS IE0 If ITx = 0, the interrupt will occur when a logic low condition is present on the interrupt pin. TF0 INT1 TF1 T1 RI TF2 EXF2 IT1 IE1 INTERRUPT SOURCES The state of the external interrupt, when enabled, can be monitored using the flags, IE0 and IE1 of the TCON register and will be set when the interrupt condition occurs. In the case where the interrupt was configured as edge sensitive, the associated flag is automatically cleared when the interrupt is serviced. If the interrupt is configured as level sensitive, then the interrupt flag must be cleared by the software. ______________________________________________________________________________________________ www.ramtron.com page 29 of 48 VRS51C1000 Timer 0 and Timer 1 Interrupt Execution of an Interrupt Both Timer 0 and Timer 1 can be configured to generate an interrupt when a rollover of the timer/counter occurs (except Timer 0 in Mode 3). When the processor receives an interrupt request, an automatic jump to the desired subroutine occurs. This jump is similar to executing a branch to a subroutine instruction: the processor automatically saves the address of the next instruction on the stack. An internal flag is set to indicate that an interrupt is taking place, and then the jump instruction is executed. An interrupt subroutine must always end with the RETI instruction. This instruction allows users to retrieve the return address placed on the stack. The TF0 and TF1 flags serve to monitor timer overflow occurring in Timer 0 and Timer 1. These interrupt flags are automatically cleared when the interrupt is serviced. Timer 2 interrupt A Timer 2 interrupt can occur if TF2 and/or EXF2 flags are set to 1 and if the Timer 2 interrupt is enabled. The RETI instruction also allows updating of the internal flag that will take into account an interrupt with the same priority. The TF2 flag is set when a rollover of the Timer 2 Counter/Timer occurs. The EXF2 flag can be set by a 1 to 0 transition on the T2EX pin by the software. Interrupt Enable and Interrupt Priority Note that neither flag is cleared by the hardware upon execution of the interrupt service routine. The service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt. These flag bits will have to be cleared by the software. When the VRS51C1000 is initialized, all interrupt sources are inhibited by the bits of the IE register being reset to 0. It is necessary to start by enabling the interrupt sources that the application requires. This is achieved by setting bits in the IE register, as discussed previously. Every bit that generates interrupts can either be cleared or set by the software, yielding the same result as when the operation is done by the hardware. In other words, pending interrupts can be cancelled and interrupts can be generated by the software. This register is part of the bit addressable internal SRAM. For this reason, it is possible to modify each bit individually in one instruction without having to modify the other bits of the register. All interrupts can be inhibited by setting EA to 0. Serial Port Interrupt The order in which interrupts are serviced is shown in the following table: The serial port can generate an interrupt upon byte reception or once the byte transmission is completed. TABLE 34: INTERRUPT PRIORITY Those two conditions share the same interrupt vector and it is up to the user developed interrupt service routine software to ascertain the cause of the interrupt by looking at the serial interrupt flags RI and TI. Note that neither of these flags are cleared by the hardware upon execution of the interrupt service routine. The software must clear these flags. Interrupt Source RESET + WDT (Highest Priority) IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 (Lowest Priority) ______________________________________________________________________________________________ www.ramtron.com page 30 of 48 VRS51C1000 Modifying the Order of Priority The VRS51C1000 allows the user to modify the natural priority of the interrupts. One may modify the order by programming the bits in the IP (Interrupt Priority) register. When any bit in this register is set to 1, it gives the corresponding source a greater priority than interrupts coming from sources that don’t have their corresponding IP bit set to 1. The IP register is represented in the table below. TABLE 35: IP INTERRUPT PRIORITY REGISTER –SFR B8H 7 6 5 4 3 EA - ET2 ES ET1 2 EX1 1 0 ET0 EX0 Bit 7 6 Mnemonic - Description 5 4 3 2 1 0 PT2 PS PT1 PX1 PT0 PX0 Gives Timer 2 Interrupt Higher Priority Gives Serial Port Interrupt Higher Priority Gives Timer 1 Interrupt Higher Priority Gives INT1 Interrupt Higher Priority Gives Timer 0 Interrupt Higher Priority Gives INT0 Interrupt Higher Priority Watchdog Timer The Watchdog Timer (WDT) is a 16-bit free-running counter that generates a reset signal if the counter overflows. The WDT is useful for systems that are susceptible to noise, power glitches and other conditions that can cause the software to go into infinite dead loops or runaways. The WDT function gives the user software a recovery mechanism from abnormal software conditions. The WDT is different from Timer 0, Timer 1 and Timer 2 of the standard 8051. Once the WDT is enabled, the user software must clear it periodically. In the case where the WDT is not cleared, its overflow will trigger a reset of the VRS51C1000. The user should check the WDR bit of the SYSCON register whenever an unpredicted reset has taken place. The WDT timeout delay can be adjusted by configuring the clock divider input for the time base source clock of the WDT. To select the divider value, bit2-bit0 (PS2PS0) of the Watchdog Timer Control Register (WDTC) should be set accordingly. To enable the WDT, the user must set bit 7 (WDTE) of the WDTC register to 1. Once WDTE has been set to 1, the 16-bit counter will start to count with the selected time base source clock configured in PS2~PS0. The Watchdog Timer will generate a reset signal if an overflow has taken place. The WDTE bit will be cleared to 0 automatically when VRS51C1000 has been reset by either the hardware or a WDT reset. Clearing the WDT is accomplished by setting the CLR bit of the WDTC to 1. This action will clear the contents of the 16-bit counter and force it to restart. Watchdog Timer Registers Two of the registers of the VRS51C1000 are associated with the Watchdog Timer: WDTC and SYSCON. The WDTC register allows the user to enable the WDT, clear the counter and to divide the clock source. The WDR bit of the SYSCON register indicates whether the Watchdog Timer caused the device reset. TABLE 36: WATCHDOG TIMER REGISTERS: WDTC – SFR 9FH 7 WDTE Bit 7 6 5 [4:3] 2 1 0 6 Unused Mnemonic WDTE Unused CLR Unused PS2 PS1 PS0 5 CLR 4 3 Unused 2 PS2 1 PS1 0 PS0 Description Watchdog Timer Enable Bit Watchdog Timer Counter Clear Bit Clock Source Divider Bit 2 Clock Source Divider Bit 1 Clock Source Divider Bit 0 The following table provides timeout periods associated with different values of the PSx bits of the Watchdog Timer Register. TABLE 37: TIME PERIOD AT 40MHZ, 22.184MHZ AND 11.059MHZ PS [2:0] Divider (OSC in) WDT Period 40MHz WDT Period 22.18MHz WDT Period 12MHz 000 8 13.11 23.63 43.69 001 16 26.21 47.27 87.38 010 32 52.43 94.53 174.76 011 64 104.86 189.07 349.53 100 128 209.72 378.14 699.05 101 256 419.43 756.28 1398.10 110 512 838.86 1512.55 2796.20 111 1024 1677.72 3025.10 5592.41 ______________________________________________________________________________________________ www.ramtron.com page 31 of 48 VRS51C1000 TABLE 38: WATCHDOG TIMER REGISTER-SYSTEM CONTROL REGISTER (SYSCON)–SFR BFH 7 WDR Bit 7 [6:3] 2 1 0 6 Mnemonic WDR Unused IAPE XRAME ALEI 5 4 Unused 3 2 IAPE 1 XRAME 0 ALEI Description Watchdog Timer Reset Bit ISP Overall Enable Bit 1: Enables ISP Function 0: Disables ISP Function 1: Enable Electromagnetic Interference Reducer 0: Disable Electromagnetic Interference Reducer As previously mentioned, bit 7 (WDR) of SYSCON is the Watchdog Timer Reset bit. It will be set to 1 when a reset signal is generated by the WDT overflow. The user should check the WDR bit whenever an unpredicted reset has taken place. Reduced EMI Function The VRS51C1000 can also be set up for reduced EMI (electromagnetic interference) by setting bit 0 (ALEI) of the SYSCON register to 1. This function will inhibit the Fosc/6Hz clock signal output to the ALE pin. Pulse Width Modulation (PWM) The Pulse Width Modulation (PWM) module consists of five 8-bit channels. Each channel uses an 8-bit PWM data register (PWMD) to set the number of continuous pulses within a PWM frame cycle. PWM Function Description: Each 8-bit PWM channel is composed of an 8-bit register that consists of a 5-bit PWM (5 MSBs) and a 3-bit (LSBs) Narrow Pulse Generator (NP). The 5-bit PWM determines the duty cycle of the output. The 3-bit NPx generates and inserts narrow pulses among the PWM frame made of 8 cycles. The number of pulses generated is equal to the number programmed intp the 3-bit NP. The NP is used to generate an equivalent 8-bit resolution PWM type DAC with a reasonably high repetition rate through a 5bit PWM clock speed. The PDCK[1:0] settings of the PWMC (A3h) register is used to derive the PWM clock from Fosc. PWM Clock = Fosc (PDCK [1:0] +1) 2 The PWM output cycle frame repetition rate (frequency) is calculated using the following formula: PWM Clock = Fosc 32 x 2(PDCK [1:0] +1) ______________________________________________________________________________________________ www.ramtron.com page 32 of 48 VRS51C1000 PWM Registers - Port1 Configuration Register PWM Data Registers TABLE 39: PORT1 CONFIGURATION REGISTER (PWME, $9B) The following tables describe the PWM Data Registers. The PWMDx bits hold the content of the PWM Data Register and determine the duty cycle of the PWM output waveforms. The NP[2:0] bits will insert narrow pulses into the 8-PWM-cycle frame. 7 PWM4E 6 PWM3E 5 PWM2E 4 PWM1E 3 PWM0E 2 1 Unused 0 Bit 7 6 5 4 3 Mnemonic PWM4E PWM3E PWM2E PWM1E PWM0E [2:0] Unused TABLE 41: PWM DATA REGISTER 0 (PWMD0) – SFR A4H Description When bit is set to one, the corresponding PWM pin is active as a PWM function. When the bit is cleared, the corresponding PWM pin is active as an I/O pin. These five bits are cleared upon reset. - PWM Registers -PWM Control Register The following table describes the PWM Control Register. 7 PWMD0.4 3 PWMD0.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD0.4 PWMD0.3 PWMD0.2 PWMD0.1 PWMD0.0 NP0.2 NP0.1 NP0.0 6 PWMD0.3 5 PWMD0.2 4 PWMD0.1 2 NP0.2 1 NP0.1 0 NP0.0 Description Contents of PWM Data Register 0 Bit 4 Contents of PWM Data Register 0 Bit 3 Contents of PWM Data Register 0 Bit 2 Contents of PWM Data Register 0 Bit 1 Contents of PWM Data Register 0 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame TABLE 42: PWM DATA REGISTER 1 (PWMD1) – SFR A5H TABLE 40: PWM CONTROL REGISTER (PWMC) – SFR A3H 7 6 Bit [7:2] 1 0 5 4 Unused Mnemonic Unused PDCK1 PDCK0 3 2 1 0 PDCK1 PDCK0 Description Input Clock Frequency Divider Bit 1 Input Clock Frequency Divider Bit 0 The following table describes the relationship between the values of PDCK1/PDCK0 and the value of the divider. Numerical values of the corresponding frequencies are also provided. PDCK1 PDCKO Divider 0 0 1 1 0 1 0 1 2 4 8 16 PWM clock, Fosc=20MHz 10MHz 5MHz 2.5MHz 1.25MHz PWM clock, Fosc=24MHz 12MHz 6MHz 3MHz 1.5MHz 7 PWMD1.4 6 PWMD1.3 5 PWMD1.2 4 PWMD1.1 3 PWMD1.0 2 NP1.2 1 NP1.1 0 NP1.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD1.4 PWMD1.3 PWMD1.2 PWMD1.1 PWMD1.0 NP1.2 NP1.1 NP1.0 Description Contents of PWM Data Register 1 Bit 4 Contents of PWM Data Register 1 Bit 3 Contents of PWM Data Register 1 Bit 2 Contents of PWM Data Register 1 Bit 1 Contents of PWM Data Register 1 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame TABLE 43: PWM DATA REGISTER 2 (PWMD2) – SFR A6H 7 PWMD2.4 6 PWMD2.3 5 PWMD2.2 4 PWMD2.1 3 PWMD2.0 2 NP2.2 1 NP2.1 0 NP2.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD2.4 PWMD2.3 PWMD2.2 PWMD2.1 PWMD2.0 NP2.2 NP2.1 NP2.0 Description Contents of PWM Data Register 2 Bit 4 Contents of PWM Data Register 2 Bit 3 Contents of PWM Data Register 2 Bit 2 Contents of PWM Data Register 2 Bit 1 Contents of PWM Data Register 2 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame ______________________________________________________________________________________________ www.ramtron.com page 33 of 48 VRS51C1000 TABLE 44: PWM DATA REGISTER 3 (PWMD1) – SFR A7H 7 PWMD3.4 3 PWMD3.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD3.4 PWMD3.3 PWMD3.2 PWMD3.1 PWMD3.0 NP3.2 NP3.1 NP3.0 6 PWMD3.3 5 PWMD3.2 4 PWMD3.1 2 NP3.2 1 NP3.1 0 NP3.0 Description Contents of PWM Data Register 3 Bit 4 Contents of PWM Data Register 3 Bit 3 Contents of PWM Data Register 3 Bit 2 Contents of PWM Data Register 3 Bit 1 Contents of PWM Data Register 3 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame 6 5 4 3 2 1 0 PWMD4.3 PWMD4.2 PWMD4.1 PWMD4.0 NP4.2 NP4.1 NP4.0 Contents of PWM Data Register 4 Bit 3 Contents of PWM Data Register 4 Bit 2 Contents of PWM Data Register 4 Bit 1 Contents of PWM Data Register 4 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame The table below shows the number of PWM cycles inserted in an 8-cycle frame when we vary the NP number. N = NP[4:0][2:0] XX1 X1X 1XX Number of PWM cycles inserted in an 8-cycle frame 1 2 3 TABLE 45: PWM DATA REGISTER 4 (PWMD1) – SFR ACH 7 PWMD4.4 6 PWMD4.3 5 PWMD4.2 4 PWMD4.1 3 PWMD4.0 2 NP4.2 1 NP4.1 0 NP4.0 Bit 7 Mnemonic PWMD4.4 Description Contents of PWM Data Register 4 Bit 4 ______________________________________________________________________________________________ www.ramtron.com page 34 of 48 VRS51C1000 Example of PWM Timing Diagram MOV PWMD0 #83H MOV PWME, #08H ; PWMD04:0]=10h (=16T high, 16T low), NP02:0] = 3 ; Enable P1.3 as PWM output pin FIGURE 21: PWM TIMING DIAGRAM 1st Cycle frame 2nd Cycle frame 32T 32T 16 3rd Cycle frame 4th Cycle frame 32T 32T 16 1T 5th Cycle frame 32T 16 1T 6th Cycle frame 7th Cycle frame 8th Cycle frame 32T 32T 32T 16 16 1T (Narrow pulse inserted by NP0[2:0]=3) PWM clock= 1/T= Fosc / 2^(PDIV+1) The SPWM output cycle frame frequency = SPWM clock/32 = [Fosc/2^(PDIV+1)]/32 If Fosc = 20MHz, PDCK[1:0] of PWMC = #03H, then PWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz. PWM output cycle frame frequency = (20MHz/2^4)/32 = 39.1 kHz. ______________________________________________________________________________________________ www.ramtron.com page 35 of 48 VRS51C1000 Crystal consideration The crystal connected to the VRS51C1000 oscillator input should be of a parallel type, operating in fundamental mode. The user should check the specific crystal or ceramic resonator technical literature available or contact the manufacturer to select the appropriate values for the external components. XTAL1 The following table provides suggested capacitor and resistor feedback values for different operating frequencies. Valid for VRS51C1000 XTAL 3MHz C1 30 pF C2 30 pF R open XTAL C1 C2 R 16MHz 30 pF 30 pF open 6MHz 30 pF 30 pF open 9MHz 30 pF 30 pF open 12MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62KΩ 33MHz 10 pF 10 pF 6.8KΩ 40MHz 2 pF 2 pF 4.7KΩ XTAL VRS51C1000 R XTAL2 C1 C2 Note: Oscillator circuits may differ with different crystals or ceramic resonators in higher oscillator frequencies. Crystals or ceramic resonator characteristics vary from one manufacturer to the other. ______________________________________________________________________________________________ www.ramtron.com page 36 of 48 VRS51C1000 Operating Conditions TABLE 46: OPERATING CONDITIONS Symbol TA TS VCC5 Fosc 40 Description Operating temperature Storage temperature Supply voltage Oscillator Frequency Min. -40 -55 4.5 3.0 Typ. 25 25 5.0 - Max. +85 155 5.5 40 Unit ºC ºC V MHz Remarks Ambient temperature under bias For 5V application DC Characteristics TABLE 47: DC CHARACTERISTICS Symbol VIL1 VIL2 VIH1 VI H2 VOL1 VOL2 Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Valid P o r t 0 ,1,2,3,4,#EA RES, XTAL1 P o r t 0,1,2,3,4,#EA RES, XTAL1 Port 0, ALE, #PSEN P o r t 1,2,3,4 VOH1 Output High Voltage Port 0 VOH2 Output High Voltage Port 1,2,3,4,ALE,#PSEN IIL Logical 0 Input Current ITL ILI R RES C -10 IC C Max. 1.0 0.8 VCC+0.5 VCC+0.5 0.45 0.45 Unit V V V V V V V V V V Test Conditions VCC=5V VCC=5V VCC=5V VCC=5V IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA P o r t 1,2,3,4 -75 uA Vin=0.45V P o r t 1,2,3,4 -650 uA Vin=2.OV P o r t 0, #EA +10 uA 0.45V<Vin<VCC 300 Kohm Pin Capacitance 10 pF Fre=1 MHz, Ta=25°C Power Supply Current 20 15 10 10 7.5 6 150 mA mA mA mA mA mA uA Active mode, 40MHz Active mode 25MHz Active mode 16MHz Idle mode, 40MHz Idle mode 25MHz Idle mode, 16MHz Power down mode Logical Transition Current Input Leakage Current Reset Pull-down Resistance RES Min. -0.5 0 2.0 70% VCC 2.4 90%VCC 2.4 90% VCC 50 VDD FIGURE 22: ICC ACTIVE MODE TEST CIRCUIT FIGURE 23: ICC IDLE MODE TEST CIRCUIT Vcc Vcc Vcc Vcc Icc RST VCC PO EA VCC 8 RST VRS51C1000 (NC) Clock Signal XTAL2 XTAL1 VSS Icc PO EA 8 VRS51C1000 (NC) Clock Signal XTAL2 XTAL1 VSS ______________________________________________________________________________________________ www.ramtron.com page 37 of 48 VRS51C1000 AC Characteristics TABLE 48: AC CHARACTERISTICS Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVI V T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T , T C LCL Parameter ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to #PSEN low #PSEN Pulse Width #PSEN Low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN Low to Address Float #RD Pulse Width #WR Pulse Width #RD Low to Valid Data In Data Hold after #RD Data Float after #RD ALE Low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD Low Address Valid to #WR or #RD Low Data Valid to #WR High Data Valid to #WR Transition Data Hold after #WR #RD Low to Address Float #W R or #RD High to ALE High Clock Fall Time Clock Low Time Clock Rise Time Clock High Time Clock Period Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT Fosc 16 Min. 115 43 53 Type Max. Variable Fosc Min. 2xT - 10 T - 20 T - 10 Type 240 53 173 4xT - 10 T - 10 3xT - 15 177 0 3xT -10 0 87 292 10 365 365 T + 25 5xT - 20 10 6xT - 10 6xT - 10 302 0 178 230 403 38 73 53 63 Max. 5xT - 10 0 145 590 542 197 72 2xT + 20 8xT - 10 9xT - 20 3xT + 10 3xT - 10 4xT - 20 7xT - 35 T - 25 T + 10 5 T+10 T -10 1/fosc Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS ______________________________________________________________________________________________ www.ramtron.com page 38 of 48 VRS51C1000 Data Memory Read Cycle Timing The following timing diagram provides Data Memory Read Cycle timing information. FIGURE 24: DATA MEMORY READ CYCLE TIMING T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 OSC 1 ALE 2 #PSEN 5 #RD 7 3 ADDRESS A15-A8 PORT2 3 PORT0 INST in Float A7-A0 4 6 Float 8 Data in Float ADDRESS or Float ______________________________________________________________________________________________ www.ramtron.com page 39 of 48 VRS51C1000 Program Memory Read Cycle Timing The following timing diagram provides Program Memory Read Cycle timing information FIGURE 25: PROGRAM MEMORY READ CYCLE T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 OSC ALE 1 2 5 #PSEN 7 #RD,#WR 3 ADDRESS A15-A8 PORT2 PORT0 Float 3 4 6 A7-A0 Float INST in ADDRESS A15-A8 8 Float A7-A0 Float INST in Float ______________________________________________________________________________________________ www.ramtron.com page 40 of 48 VRS51C1000 Data Memory Write Cycle Timing The following timing diagram provides Data Memory Write Cycle timing information. FIGURE 26: DATA MEMORY WRITE CYCLE TIMING T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 OSC ALE 1 #PSEN 6 5 #WR 2 ADDRESS A15-A8 PORT2 2 PORT0 INST in Float A7-A0 3 4 Data out ADDRESS or Float ______________________________________________________________________________________________ www.ramtron.com page 41 of 48 VRS51C1000 I/O Ports Timing The following timing diagram provides I/O Port Timing information. FIGURE 27: I/O PORTS TIMING T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8 X1 Sampled Inputs P0,P1 Sampled Inputs P2,P3 Output by Mov Px, Src RxD at Serial Port Shift Clock Mode 0 Current Data Next Data Sampled ______________________________________________________________________________________________ www.ramtron.com page 42 of 48 VRS51C1000 Timing Requirement of the External Clock (VSS = 0v is assumed) FIGURE 28: TIMING REQUIREMENT OF EXTERNAL CLOCK (VSS= 0.0V IS ASSUMED) TCLCL Vdd - 0.5V 0.45V 70% Vdd 20% Vdd-0.1V TCLCX TCHCX TCHCL TCLCH External Program Memory Read Cycle The following timing diagram provides External Program Memory Read Cycle timing information. FIGURE 29: EXTERNAL PROGRAM MEMORY READ CYCLE TPLPH #PSEN TLLPL ALE TLHLL TAVLL PORT 0 TPXIZ TLLAX A0-A7 TPLIV TPLAZ TPXIX Instruction IN A0-A7 TAVIV PORT2 P2.0-P2.7 or AB-A15 from DPH A8-A15 ______________________________________________________________________________________________ www.ramtron.com page 43 of 48 VRS51C1000 External Data Memory Read Cycle The following timing diagram provides External Data Memory Read Cycle timing information. FIGURE 30: EXTERNAL DATA MEMORY READ CYCLE #PSEN TYHLH ALE TLLDV TRLRH TLLYL #RD TAVLL PORT 0 TRLDV TLLAX TRLAZ A0-A7 From Ri or DPL TRHDZ TRHDX DATA IN A0-A7 From PCL INSTRL IN TAVYL TAVDV PORT 2 P2.0-P2.7 or A8 -A15 from DPH A8-A15 from PCH ______________________________________________________________________________________________ www.ramtron.com page 44 of 48 VRS51C1000 External Data Memory Write Cycle The following timing diagram provides External Data Memory Write Cycle timing information. FIGURE 31: EXTERNAL DATA MEMORY WRITE CYCLE #PSEN TYHLH ALE TLHLL TLLYL #WR TAVLL TWLWH TQVWX TWHQX TLLAX TQVWH PORT 0 A0-A7 From Ri or DPL DATA OUT A0-A7 From PCL INSTRL IN TAVYL PORT 2 P2.0-P2.7 or A8-A15 from DPH A8-A15 from PCH . ______________________________________________________________________________________________ www.ramtron.com page 45 of 48 VRS51C1000 Plastic Chip Carrier (PLCC-44) L GE VRS51C1000 PLCC-44 E HE Y A2 A1 A D TABLE 49: DIMENSIONS OF PLCC-44 CHIP CARRIER HD Symbol C e b1 b GD Note: 1. Dimensions D & E do not include interlead Flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inch 4. General appearance spec should be based on final visual inspection spec. A Al A2 bl b C D E e GD GE HD HE L θ ∆y Dimension in inch Minimal/Maximal -/0.185 0.020/0.145/0.155 0.026/0.032 0.016/0.022 0.008/0.014 0.648/0.658 0.648/0.658 0.050 BSC 0.590/0.630 0.590/0.630 0.680/0.700 0.680/0.700 0.090/0.110 -/0.004 / Dimension in mm Minimal/Maximal -/4.70 0.51/ 3.68/3.94 0.66/0.81 0.41/0.56 0.20/0.36 16.46/16.71 16.46/16.71 1.27 BSC 14.99/16.00 14.99/16.00 17.27/17.78 17.27/17.78 2.29/2.79 -/0.10 / ______________________________________________________________________________________________ www.ramtron.com page 46 of 48 VRS51C1000 C Plastic Quad Flat Package (QFP-44) L L1 S S VRS51C1000 QFP-44 b D2 D1 D 2 A2 R1 A1 A Gage Plane 0.25mm 3 R2 E2 E1 TABLE 50: DIMENSIONS OF QFP-44 CHIP CARRIER E Symbol e1 Seating Plane e Note: 1. Dimensions D1 and E1 do not include mold protrusion. 2. Allowance protrusion is 0.25mm per side. 3. Dimensions D1 and E1 do not include mold mismatch and are determined datum plane. 4. Dimension b does not include dambar protrusion. 5. Allowance dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the lead foot. C A Al A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 0 θ1 θ2 θ3 ∆C Dimension in in. Minimal/Maximal -/0.100 0.006/0.014 0.071 / 0.087 0.012/0.018 0.004 / 0.009 0.520 BSC 0.394 BSC 0.315 0.520 BSC 0.394 BSC 0.315 0.031 BSC 0.029 / 0.041 0.063 0.005/0.005/0.012 0.008/0˚/7˚ 0˚/ 10˚ REF 7˚ REF 0.004 Dimension in mm Minimal/Maximal -/2.55 0.15/0.35 1.80/2.20 0.30/0.45 0.09/0.20 13.20 BSC 10.00 BSC 8.00 13.20 BSC 10.00 BSC 8.00 0.80 BSC 0.73/1.03 1.60 0.13/0.13/0.30 0.20/as left as left as left as left 0.10 ______________________________________________________________________________________________ www.ramtron.com page 47 of 48 VRS51C1000 Ordering Information Device Number Structure VRS51C1000 Ordering Options (No ISPV2 Firmware preprogrammed) Device Number VRS51C1000-40-L VRS51C1000-40-Q VRS51C1000-40-P VRS51C1000-40-LG VRS51C1000-40-QG VRS51C1000-40-PG Flash Size SRAM Size Package Option Voltage Temperature Frequency 64KB 64KB 64KB 64KB 64KB 64KB 1KB 1KB 1KB 1KB 1KB 1KB PLCC-44 QFP-44 DIP-40 PLCC-44 QFP-44 DIP-40 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C 40MHz 40MHz 40MHz 40MHz 40MHz 40MHz VRS51C1000 Ordering Options (With ISPV2 Firmware preprogrammed) Device Number VRS51C1000-40-L-ISPV2 VRS51C1000-40-Q-ISPV2 VRS51C1000-40-P-ISPV2 VRS51C1000-40-LG-ISPV2 VRS51C1000-40-QG-ISPV2 VRS51C1000-40-PG-ISPV2 Flash Size SRAM Size Package Option Voltage Temperature Frequency 64KB 64KB 64KB 64KB 64KB 64KB 1KB 1KB 1KB 1KB 1KB 1KB PLCC-44 QFP-44 DIP-40 PLCC-44 QFP-44 DIP-40 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C 40MHz 40MHz 40MHz 40MHz 40MHz 40MHz Disclaimers Right to make change - Ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. Customers should obtain the most current and relevant information before placing orders. Use in applications - Ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using Ramtron parts. Ramtron assumes no liability for applications assistance or customer product design. Life support – Ramtron products are not designed for use in life support systems or devices. Ramtron customers using or selling Ramtron products for use in such applications do so at their own risk and agree to fully indemnify Ramtron for any damages resulting from such applications. I²C is a trademark of Koninklijke Philips Electronics NV. ______________________________________________________________________________________________ www.ramtron.com page 48 of 48