Ordering number : EN5946 CMOS IC LC7982A LCD Dot Matrix Graphics Display Controller Overview The LC7982A is an LCD dot matrix graphics display controller IC. It stores display data sent from an 8-bit microcontroller in external display RAM and generates dot matrix LCD drive signals. Applications can select either of two modes: graphics mode, in which each bit in external RAM controls the on/off state of an individual pixel (dot) on the LCD, and character mode, in which character codes are stored in external RAM and the dot pattern is generated using the built-in character generator ROM. Thus the LC7982A can support a wide range of applications. The LC7982A is fabricated in a CMOS process, and in conjunction with a CMOS microcontroller, can implement low-power LCD display systems. This device differs from the LC7981 only in the data stored in the built-in character generator ROM. • Extensive set of command functions — Scroll, cursor on/off/blink, character blinking, bit manipulation • Display methods : Method A and method B (program selectable) • Built-in oscillator circuit (Using an external resistor and capacitor) • Low power • +5V single-voltage power supply Package Dimensions unit: mm 3055A-QFP60C [LC7982A] Features • LCD dot matrix and graphics display controller • Display control capacity Graphics mode 512 K dots (216 bytes) Character mode 4096 characters (212 bytes) • Character generator ROM 7360 bits · European character support Character font: 5 × 7 dots 160 characters 192 characters Character font: 5 × 11 dots 32 characters total (Can be expanded by up to 4 KB using external ROM.) • Supports interfacing with 8-bit microcontrollers. • Display duty (program selectable) — From static to 1/256 duty SANYO: QFP60C (QIP60C) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O1698RM (OT) No. 5946-1/18 LC7982A Specifications Absolute Maximum Ratings at Ta = 25°C, GND = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings VDD max Input voltage VI Output voltage VO Allowable power dissipation Unit –0.3 to +7.0 V –0.3 to VDD +0.3 V –0.3 to VDD +0.3 Pd max Ta = 75°C V 200 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –20 to +75°C, GND = 0 V Parameter Symbol Conditions Ratings min typ Unit max Supply voltage VDD 4.75 5.25 V High-level input voltage VIH1 Input and I/O pins other than SYNC and CR. 2.2 VDD V Low-level input voltage VIL1 Input and I/O pins other than SYNC and CR. 0 0.8 V High-level input voltage VIH2 SYNC, CR 0.7 VDD VDD V Low-level input voltage VIL2 SYNC, CR 0 0.3 VDD V 2.4 VDD V 0 0.4 V VDD – 0.4 VDD V 0 0.4 V High-level output voltage VOH1 Low-level output voltage VOL1 High-level output voltage VOH2 Low-level output voltage VOL2 IOH = –0.6 mA, DB0 to DB7, WE, MA0 to MA15, MD0 to MD7 IOL = 1.6 mA, DB0 to DB7, WE, MA0 to MA15, MD0 to MD7 IOH = –0.6 mA, SYNC, CPO, FLM, CL1, CL2, D1, D2, MA, MB IOL = 0.6 mA, SYNC, CPO, FLM, CL1, CL2, D1, D2, MA, MB [Internal Clock Operation] Clock oscillator frequency fOSC Cf = 15 pF ±5%, Rf = 39 kΩ ±2%*1 500 600 700 kHz 2.5 MHz 47.5 50 52.5 % [External Clock Operation] fCP *2 Clock duty Duty *3 Clock rise time trcp *3 50 ns Clock fall time tfcp *3 50 ns Clock operating frequency Electrical Characteristics at Ta = –20 to +75°C, GND = 0 V, VDD = 5 V ±5% Parameter Input leakage current Current drain Pull-up current Symbol IIN Conditions VIN = 0 to VDD, CS, E, RS, R/W, RES ICC1 RC oscillator, fOSC = 600 kHz ICC2 External clock, fCP = 2.5 MHz IPL Ratings min 5 µA 4 mA 3 5 mA 10 20 µA 2 (Note 2) Unit max –5 VIN = GND, DB0 to DB7, RD0 to RD7, MD0 to MD7 (Note 1) typ (Note 3) Open Open Oscillator circuit Cf = 15 pF ±5% Rf = 39 kΩ ±2% (When fOSC = 600 kHz (typical)) Duty = Th × 100% Th + T1 No. 5946-2/18 LC7982A Timing Characteristics • Bus read/write operation 1 Read cycle DB0 to DB7 Write cycle DB0 to DB7 Ta = –20 to +75°C, VDD = 5V ±5%, GND = 0 V Parameter Symbol Conditions Ratings min Address setup time tAS 90 Address hold time tAH 10 typ max Unit ns ns Data delay time (read) tDDR Data hold time (read) tDHR 10 Data setup time (write) tDSW 220 ns Data hold time (write) tDHW 20 ns CL = 50 pF 140 ns ns Note: Test waveform definition Measurement point Input pins are driven to 2.4 V and 0.45 V, and the timing is measured at 1.5 V No. 5946-3/18 LC7982A • Bus read/write operation 2 Data read cycle Data write cycle Ta = –20 to +75°C, VDD = 5V ±5%, GND = 0 V Parameter Symbol Instruction register value Ratings min typ Unit max 0DH (HP+2) × 103 +200 fOSC ns tWCY1 0EH, 0FH (2HP+2) × 103 +200 fOSC ns Write cycle time tWCY2 0CH (HP+2) × 103 +200 fOSC ns Write cycle time tWCY3 2000 +200 fOSC ns Read cycle time tRCY Write cycle time 00H, 01H, 02H, 03H, 04H, 08H, 09H, 0AH, 0BH Notes: • For character display, HP is the number of dots in the horizontal direction per character, and for graphics mode, HP is the number of bits shown on the display from each byte of display data. • fOSC is the oscillator frequency, in units of MHz. • All measurements are made at 1.5 V. • Parallel operation (master mode) Ta = –20 to +75°C, VDD = 5V ±5%, GND = 0 V Parameter Symbol SYNC delay time tDSY SYNC pulse width tWSY Conditions Ratings min typ max 100 350 Unit ns ns Notes: • With no loads on any of the output pins. • Measurements are made at 0.5 VDD. No. 5946-4/18 LC7982A • External RAM and ROM interface MA0 to MA15 MD0 to MD7 RD0 to RD7 Read Cycle at Ta = –20 to +75°C, VDD = 5 V ±5%, GND = 0 V Parameter Symbol MA0 to MA15 read address delay time tDMAR MD0 to MD7, RD0 to RD7 setup time tSMDR Conditions Ratings min typ max 95 105 Unit ns ns Write Cycle at Ta = –20 to +75°C, VDD = 5 V ±5%, GND = 0 V Parameter Symbol Conditions Ratings min typ max Unit Memory address setup time tSMAW 50 ns WE pulse width tWWE 350 ns Memory data setup time tSMDW 250 ns Memory address hold time tHMAW 50 ns Memory data hold time tHMDW 50 ns Notes: • With no loads on any of the output pins. • All measurements are made at 1.5 V. • Driver IC interface D1, D2 Ta = –20 to +75°C, VDD = 5 V ±5%, GND = 0 V Parameter Symbol Conditions Ratings min typ max Unit Clock cycle time tCYC Clock phase difference tDCL 100 ns Clock rise and fall times tCRF 30 ns D1 and D2 phase difference tDD 100 ns MA and MB phase difference tDMA 200 ns FLM phase difference tDFM 200 ns 400 ns Notes: • With no loads on any of the output pins. • Measurements other than those with a specified measurement point are made at 0.5 VDD. No. 5946-5/18 LC7982A Pin Assignment Top view Block Diagram DB0 to DB7 Input and output interface circuit Dot counter Data input register Refresh address counter (2) Dot register MD0 to MD7 Expansion ROM Line address counter Data output register Busy flag Cursor address counter Multiplexer Refresh address counter (1) Instruction register Control signal Mode control register Control signal Oscillator circuit Cursor signal generator Character generator ROM RD0 to RD7 Multiplexer Parallel to series converter Parallel to series converter • When expansion ROM is used, MA0 to MA11 are used as the RAM address and MA12 to MA15 are used as the expansion ROM address. No. 5946-6/18 LC7982A Block Functions Registers The LC7982A has five internal registers: the instruction register, the data input register, the data output register, the dot register, and the mode control register. • The instruction register holds the instruction code, which includes the start address and the cursor address. This register is a 4-bit register, and the lower 4 bits (DB0 to DB3) of the data bus are written to this register. • The data input register is used to temporarily hold data for external RAM, the dot register, the mode control register, and other registers. It is an 8-bit register. • The data output register is used to temporarily hold data read output from external RAM, and is an 8-bit register. The cursor address passes through the data input register and is written to the cursor address counter, and when a memory readout instruction is loaded into the instruction register, IC internal operations read from external RAM and load it into the data output register. Data transfer to the microcontroller completes when the microcontroller reads the data output register at the next instruction. • The dot register holds the character pitch, the number of dots in the vertical direction, and other display data. Data from the microcontroller passes through the data input register and is written to this register. • The mode control register holds display state information for the LCD, such as display on/off state and the cursor on/off/blinking state. It is a 6-bit register. Data from the microcontroller passes through the data input register and is written to this register. Busy Flag This flag is set to 1 when the LC7982A is performing internal operations. In this state, the next instruction cannot be accepted. The state of the busy flag is output from DB7 when RS is 1 and R/W is 1. The microcontroller application software must first verify that the busy flag is 0 before writing the next instruction. However, after a data read instruction or a data write instruction, the microcontroller may execute the next instruction without checking the busy flag after the maximum value of the read cycle or write cycle elapses, respectively. Dot Counter The dot counter generates LCD display timing according to the contents of the dot register. Refresh Address Counter The refresh address counters control the addresses of the external RAM, the character generator ROM, and expansion ROM. There are two refresh address counters, refresh address counter (1) and refresh address counter (2). Refresh address counter (1) is used for the upper screen, and refresh address counters (2) is used for the lower screen. In graphics mode, these registers output 16-bit data that is used as the external RAM address signals. In character mode, the upper 4 bits are ignored and the 4 bits of the line address counter are output in place of those four bits. These 4 bits are used as the expansion ROM address. Character Generator ROM The character generator ROM holds the data for 192 characters, a total of 7360 bits. It takes a character code from external RAM and a line code from the line address counter as its address signals, and outputs 5 bits of dot data. Although this ROM holds a font with 192 characters, of which 160 are 5 × 7 dot characters and 32 are 5 × 11 dot characters, up to 256 8 × 16 dot characters can be supported by using expansion ROM. Cursor Address Counter Instructions can be used to set up this 16-bit counter in advance. This counter holds the address when reading or writing external RAM (either display dot data or character codes). The cursor address counter is automatically incremented after reading or writing display data or after executing a bit set or bit clear instruction. Cursor Signal Generator A cursor can be displayed in character mode under instruction control. A cursor is automatically generated when the cursor address counter and the line address counter reach the stipulated values. Parallel to Serial Converter Parallel data from external RAM, the character generator, or expansion RAM is converted to series data by the two parallel to series converter circuits and output at the same time to the LCD drive circuits for the upper and lower screens as series data. No. 5946-7/18 LC7982A Pin Functions Pin No. Pin 21 to 28 DB0 to DB7 15 CS 17 R/W 18 RS 16 E 6, 7, 8 CR, R, C 14 RES 1 to 4 49 to 60 MA0 to MA15 Function Data bus. These are 3-state shared I/O pins and are used for data transfers to and from the microcontroller. Chip select: The IC is set to the selected state when CS = 0. Read/write: R/W = 1 ..........Microcontroller ← LC7982A R/W = 0 ..........Microcontroller → LC7982A Register select: RS = 1 ....Instruction register RS = 0 ....Data register Enable: Data writes are performed when E falls from high to low. Data can be read when E = 1. RC oscillator connections Reset: When this pin is set 0, the display is turned off and slave mode and HP = 6 are selected. Display RAM address outputs In character display mode, MA12 to MA15 are output as the external CG raster address. 30 to 37 MD0 to MD7 Display data bus: Three-state shared input and output signals 38 to 45 RD0 to RD7 ROM data inputs: Dot data from an external character generator is input using these pins. 13 WE Write enable: The RAM write signal 46 CL2 Display data shift clock 11 CL1 Display data latch signal 10 FLM Frame signal 19 MA 5 MB LCD drive signal: Alternation signal .....Method A LCD drive signal: Alternation signal .....Method B 47, 48 D1, D2 9 CPO 12 SYNC Display data serial output: D1 ..............Upper screen D2 ..............Lower screen Slave mode clock Parallel operation synchronizing signal: Three-state shared input and output signal. Master mode: Outputs a synchronizing signal. Slave mode: Inputs a synchronizing signal. No. 5946-8/18 LC7982A Display Control Instructions The display is controlled by writing data to the instruction register and the 13 data registers. The instruction register and the data registers are differentiated using the RS signal. First, with RS set to 1 the application writes 8-bit data to the instruction register and specifies the code for the data register. Then, with RS set to 0, the application writes 8-bit data to the data register, and the specified instruction is executed. Note that another instruction cannot be written while the previous instruction is executing. Since the busy flag is set during this period, applications must verify that the busy flag is 0 before writing an instruction. However, after a data read instruction or a data write instruction, the microcontroller may execute the next instruction without checking the busy flag after the maximum value of the read cycle or write cycle elapses, respectively • Mode control Applications specify the mode control register by writing 00H to the instruction register. (The form "00H" is used to express values in hexadecimal.) RS 0 1 0 0 Mode control register 0 0 0 0 DB5 DB4 DB3 DB2 DB1 DB0 1/0 1/0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 Cursor/blinking CG Cursor on Cursor off/character blinking Cursor blinking 0 Cursor off Cursor on 1 Cursor off/character blinking Cursor blinking 1 0 0 0 0 Mode data Cursor off 0 0 Graphics/character display Internal CG Register Character display mode External CG R/W Instruction register Graphics mode 0 Internal/ Display Master/ Blinking Cursor Mode external on/of slave CG 1: Master mode 0: Slave mode 1: Display on 0: Display off • Character pitch setting R/W RS Instruction register Register 0 1 Character pitch register 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 (VP - 1) binary 0 0 0 (HP - 1) binary 0 1 VP indicates the number of dots in the vertical direction per character. Applications should determine this value based on the desired vertical separation between characters. This setting is only meaningful in character display mode, and is ignored in graphics mode. In character display mode, HP indicates the number of dots in the horizontal direction per character, and also includes the gap between the current character and the character displayed to the right. In graphics mode, HP indicates the number of bits displayed from each byte of display data from RAM. HP can be set to one of three values. Hp DB2 DB1 DB0 Setting 6 1 0 1 Horizontal character pitch of 6 dots 7 1 1 0 Horizontal character pitch of 7 dots 8 1 1 1 Horizontal character pitch of 8 dots No. 5946-9/18 LC7982A • Character count setting R/W RS Instruction register Register 0 1 Character count register 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 (HN – 1) binary In character display mode, HN specifies the number of characters displayed in the horizontal direction. In graphics mode, HN specifies the number of bytes displayed in the horizontal direction. The total number of dots displayed on the screen in the horizontal direction is given by the following formula. n = HP × HN HN can be set to an even number in the range 2 to 256 (decimal). • Time division setting (display duty) R/W RS Instruction register Register 0 1 Duty register 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 (NX – 1) binary NX specifies the time division setting. That is, the display duty is set to 1/NX. NX can be set to a value in the range 1 to 256 (decimal). • Cursor position setting R/W RS Instruction register Register 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 Cursor position register 0 0 0 0 0 0 0 1 0 0 (CP – 1) binary In character display mode, CP specifies the line where the cursor is displayed. For example, if CP is set to 8 (decimal), the cursor will be displayed under the character for a 5 × 7 font. The length of the cursor in the horizontal direction will be equal to horizontal direction character pitch HP. While CP can be set to any value in the range 1 to 16 (decimal), if it is set to a value less than or equal to the vertical direction character pitch VP (CP ≤ VP), the cursor display will take priority when cursor display is enabled. Note that if CP > VP, the cursor will not be displayed. The length of the cursor in the horizontal direction will be equal to HP. • Display start position low-order address R/W RS Instruction register Register 0 1 Display start address register (Low-order byte) 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 0 (Start address low-order byte) binary • Display start position high-order address R/W RS Instruction register Register 0 1 Display start address register (High-order byte) 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 1 (Start address high-order byte) binary These instructions together write the display start address value into the display start address register. The display start address specifies the RAM address where the data to be displayed at the upper left of the screen is stored. The start address is a 16-bit value formed from high-order and low-order bytes. • Cursor address (low order) setting (RAM read/write low-order address) R/W RS Instruction register Register 0 1 Cursor address counter (Low-order byte) 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 0 (Cursor address low-order byte) binary No. 5946-10/18 LC7982A • Cursor address (high order) setting (RAM read/write high-order address) R/W RS Instruction register Register 0 1 Cursor address counter (High-order byte) 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 1 (Cursor address high-order byte) binary These instructions together write the cursor address value into the cursor address register. The cursor address indicates the address used for refering to RAM for the display data or character code. That is, the data at the address specified by the cursor address will be read or written. In character display mode, the cursor is displayed at the position specified by the cursor address. While the cursor address is a 16-bit value formed from high-order and low-order bytes, applications must only use cursor addresses that obey the following restrictions. 1 When the application rewrites (sets) both the low-order and high-order bytes. The application must first set the low-order byte and then set the high-order byte. 2 When the application only needs to rewrite the low-order byte After writing the low-order byte, the application must also write the high-order byte. 3 When the application only needs to rewrite the high-order byte The application should simply write the high-order byte. There is no need for it to write the low-order byte. The cursor address counter is a 16-bit increment-only counter with set and reset functions. When the nth bit changes from 1 to 0, bit n+1 is incremented. When the low-order byte is set, if the set caused the MSB in the low-order byte to change from 1 to 0, the LSB in the high-order byte will be incremented. Therefore, applications must set both the loworder and the high-order bytes in that order when setting the cursor address. • Display data write R/W RS Instruction register Register 0 1 RAM 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 0 MSB (Pattern data or character code) LSB When 8 bits of data are written by writing the instruction code 0CH to the instruction register when RS is 0, that data will be written as either display data or a character code to the RAM address specified by the cursor address counter. The value of the cursor address counter is incremented by 1 after the write. • Display data read R/W RS Instruction register Register 0 1 RAM 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 0 1 MSB (Pattern data or character code) LSB Applications can read out data in RAM after the LC7982A has been set to the readout state by writing the instruction code 0DH to the instruction register when RS is 0. The data readout procedure is described below. When this instruction is executed, the contents of the data output register will be output from the pins DB0 to DB7. After that, the RAM data specified by the cursor address will be transferred to the data output register. Additionally, the cursor address will be incremented by 1. As a result, the correct data will not be read out on the first readout after the cursor address is set, but the specified data will be read out on the second read. Accordingly, applications that read data out after setting the cursor address must perform a single dummy read operation. • Bit clear R/W RS Instruction register Register 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 Bit clear 0 0 0 0 0 0 0 (NB – 1) binary 1 0 • Bit set R/W RS Instruction register Register 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 Bit set 0 0 0 0 0 0 0 (NB – 1) binary 1 1 The bit clear and bit set instructions set a specified bit in a byte in display data RAM to 0 or 1, respectively. The bit clear instruction clears the bit specified by NB to 0, and the bit set instruction sets the bit to 1. The RAM address is determined by the cursor address, and the cursor address is automatically incremented by 1 after the instruction is executed. NB must be a value in the range 1 to 8. A value of 1 specifies the LSB and a value of 8 specifies the MSB. No. 5946-11/18 LC7982A • Busy flag readout Register R/W RS 1 1 Busy flag DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1/0 * When the LC7982A is set to readout mode when RS is 1, the state of the busy flag will be output from DB7. The busy flag will be 1 during the execution of any of the above thirteen instructions, and will be 0 when instruction execution has completed and the LC7982A can accept the next instruction. When the busy flag is 1, the LC7982A cannot accept instructions. Therefore, applications must check the busy flag and verify that it is 0 before executing an instruction or writing data to the LC7982A. However, after a data read instruction or a data write instruction, the microcontroller may execute the next instruction without checking the busy flag after the maximum value of the read cycle or write cycle, respectively. The busy flag is not changed by writes to the instruction register when RS is 1. Therefore, it is not necessary to check the busy flag immediately after writing the instruction register. It is not necessary to issue any instruction register commands to read out the busy flag. Relationship between HP, HN, VP, CP, and NX and the LCD Panel HN (Character positions) Symbol Function Description Value HP Horizontal character pitch Character pitch in the horizontal direction 6 to 8 dots HN Horizontal characters Number of characters per line in the horizontal direction or number of words per line (in graphics mode) An even number in the range 2 to 256 VP Vertical character pitch Character pitch in the vertical direction 1 to 16 dots CP Cursor position Number of the line where the cursor will be displayed 1 to 16 lines NX Vertical lines Display duty 1 to 256 lines Note: If m is the number of dots in the vertical direction on the screen, and n is the number of dots in the horizontal direction, then the following relationships will be held: 1/m = 1/NX = Display duty n = HP × HN m/VP = Number of lines displayed CP ≤ VP No. 5946-12/18 LC7982A Display Modes Display mode Display data from the microcontroller Character mode Display patterns (8 bits) RAM LCD panel Start address HP: 6, 7, or 8 dots Graphics mode 8 dots Character codes (8 bits) 8 dots Start address HP: 8 dots No. 5946-13/18 LC7982A Sample Application Circuit 1 DB0 to DB7 MA0 to MA15 MD0 to MD7 MA12 to MA15 RD0 to RD7 LCD module No. 5946-14/18 LC7982A Sample Application Using Combined Graphic and Character Display MA0 to MA10 A0 to A10 MD0 to MD7 I/O0 to I/O7 MA0 to MA10 A0 to A10 MD0 to MD7 I/O0 to I/O7 DB0 to DB7 DB0 to DB7 No. 5946-15/18 LC7982A Sample Structures • Graphics mode LCD module MD0 to MD7 MA0 to MA15 • Character display mode (1) (On-chip character generator) LCD module MD0 to MD7 MA0 to MA11 • Character display mode (2) (External character generator) LCD module RD0 to RD7 MA12 to MA15 MA0 to MA11 MD0 to MD7 • Parallel operation (Master) LCD module (1) LCD module (2) Common signals are shared (Slave) No. 5946-16/18 LC7982A • LC7982A Built-in Character Generator (Only the characters enclosed in the heavy broken line differ from the LC7981.) Upper 4 bits Lower 4 bits A10943 No. 5946-17/18 LC7982A Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1998. Specifications and information herein are subject to change without notice. PS No. 5946-18/18