SEMTECH SC1104XEVB

SC1104A/B
Simple, Synchronous
Voltage Mode PWM Controller
POWER MANAGEMENT
Description
Features
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SC1104A/B features include temperature compensated ‹
The SC1104A/B is a versatile voltage-mode PWM controller designed for use in single ended DC/DC power
supply applications. A simple, fixed frequency high efficiency buck regulator can be implemented using the
SC1104A/B with a minimum of external components.
Internal level shift and drive circuitry eliminates the need
for an expensive P-channel, high-side switch. The small
device footprint allows for compact circuit design.
voltage reference, triangle wave oscillator, current limit
comparator and an externally compensated error amplifier. Current limit is implemented by sensing the voltage
drop across the top FET’s RDS(ON).
Up to +14V input, 300kHz operation (SC1104A)
Up to +7V input, 600kHz operation (SC1104B)
High efficiency (>90%)
1% Reference voltage accuracy
Hiccup mode over current protection
Robust output drive
RDS(ON) Current sensing
Industrial temperature range
8-Lead SOIC package. Pb-free package available,
fully WEEE and RoHS compliant
Applications
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The SC1104 operates at fixed frequencies of
300kHz(A) or 600kHz(B) providing an optimum compromise between efficiency, external component size,
and cost. 600kHz switching frequency is reserved for
the SC1104B, +5VCC operation only.
Termination supplies
Low cost microprocessor supplies
Peripheral card supplies
Industrial power supplies
High density DC/DC conversion
SC1104A/B has a thermal protection circuit, which is
activated if the junction temperature exceeds 150°C.
Typical Application Circuit
Typical Distributed Power Supply
+
C3
1
C1
510-1500pF
R1
200-2k
C4
10.0
D1
MBRA130L
C5
47/16V
C6
47/16V
C7
47/16V
U1
SC1104A/B
C2
0.01
1
2
3
4
COMP/SS
GND
Vin 5 to 12V
_
SENSE
VCC
DL
PHASE
DH
BST
R4
2.32k
8
7
R3
1.00k
R5
200-1k
C8
0.1-0.33
6
5
R6
1-5.1
R7
1-5.1
R8
opt
Q1
Si4884DY
C9
0.1
L1
1.5-6.8uH
+
Q2
Si4874DY
D2
(opt)
C10
220/4V
C11
220/4V
C12
220/4V
C13
220/4V
C14-17
1.0
3.3V
_
Figure 1
Revision: November 22, 2006
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SC1104A/B
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum
Units
VCC to GND
+20
V
BST to PHASE
+20
V
PHASE to GND
-0.5 to +20
V
COMP/SS to GND
+7
V
SENSE to GND
+7
V
Thermal Resistance Junction to Case
θJC
40
°C/W
Thermal Resistance Junction to Ambient
θJ A
160
°C/W
Operating Junction Temperature Range
TJ
-40 to +125
°C
Operating Ambient Temperature Range
TA
-40 to +85
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Soldering) 10 Sec.
TLead
300
°C
ESD Rating (Human Body Model)
V ESD
2
kV
Electrical Characteristics
Unless specified: A: VCC = 12 ± 0.6V, VBST = 23 ± 1V, VOUT = 3.3V, TJ = TA = 25oC. B: VCC = 5 ± 0.25V, VBST = 12 ± 0.6V, VOUT = 2.0V, TJ = TA = 25oC
Parameter
Symbol
Conditions
Min
VCC
FSW = 300kHz (nom.), SC1104A
V CC
FSW = 600kHz (nom.), SC1104B
ICC
VCOMP ≤ 0.4V
Typ
Max
Units
4.5
14
V
4.5
7
Pow er Supply
Supply Voltage
Supply Current
11
14
mA
Error Amplifier
E/A Transconductance(1)
gm
12
mS
Open Loop DC Gain(1)
AO
42
dB
Bandwidth - 3dB(1)
FBW
400
kHz
Input Bias Current
IFB
1
Output Sink Current
ISIK
VSENSE ≥ 1.1V; VCOMP = 1.5V
0.65
0.7
Source Current
ISC
VSENSE ≥ 0.9V; VCOMP = 1.5V
0.95
1.1
FOSC
VCC = 12V ± 0.6V
255
300
345
VCC = 5V ± 0.25V
510
600
690
3
µA
mA
Oscillator
Switching Frequency
© 2006 Semtech Corp.
2
kHz
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SC1104A/B
POWER MANAGEMENT
Electrical Characteristics
Unless specified: A: VCC = 12 ± 0.6V, VBST = 23 ± 1V, VOUT = 3.3V, TJ = TA = 25oC. B: VCC = 5 ± 0.25V, VBST = 12 ± 0.6V, VOUT = 2.0V, TJ = TA = 25oC
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Ramp Peak Voltage(1)
VP-K
4.75V ≤ VCC ≤ 12.6V
2.0
V
Ramp Valley Voltage(1)
VV
4.75V ≤ VCC ≤ 12.6V
1.0
V
Maximum Duty Cycle(2)
dcMAX
VCC = 12V (300kHz, SC1104A)
90
95
%
VCC = 5V (600kHz, SC1104B)
85
90
MOSFET Drivers
DH Sink/Source Current
SC1104A
IDH
d.c. < 2%, tPW < 100µs
VGS = 4.5V (src)
0.6
0.8
DL Sink/Source Current
SC1104A
IDL
VGS = 2.5V (snk)
0.6
0.7
DH Sink/Source Current
SC1104B
IDH
d.c. < 2%, tPW < 100µs
VGS = 4.5V (src)
0.45
0.6
DL Sink/Source Current
SC1104B
IDL
VGS = 2.5V (snk)
0.45
0.6
DH Rise/Fall Time
tr, tf
CL = 3000pF, See Fig. 2
50
DL Rise/Fall Time
tr, tf
CL = 4000pF, See Fig. 2
50
tdt
S ee F i g. 2
80
tOFF
4.75V ≤ Vcc ≤ 12.6V
160
VREF
4.75V ≤ Vcc ≤ 12.6V
0.990
∆VREF
0 < TJ < +70°C
-40 < TJ < +85°C
Dead Time
DH Minimum Off Time
A
A
ns
ns
Reference Section
Reference Voltage
Temp Variance
Long Term Stability
1.000
1.010
V
-1
1
%
-1.5
1.5
TJ = 125°C, 1000 hrs.
5
mV
220
mV
Current Limit
Trip Voltage
VTRIP
4.75V < Vcc < 12.6V
Vtrp = Vcc - VPHASE
180
SS Source Current
ISRC
VCOMP < 2.5V
0.5
1.8
µA
SS Sink Current
ISNK
VCOMP > 0.5V
0.5
1.8
µA
1.00
1.35
V
2
mA
200
Soft-Start/Enable
Enable Input Threshold
Enable Input Current
©
2006 Semtech Corp.
VCOMP = 0.8V
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SC1104A/B
POWER MANAGEMENT
Electrical Characteristics
Unless specified: A: VCC = 12 ± 0.6V, VBST = 23 ± 1V, VOUT = 3.3V, TJ = TA = 25oC. B: VCC = 5 ± 0.25V, VBST = 12 ± 0.6V, VOUT = 2.0V, TJ = TA = 25oC
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Vth
-40 < TJ < 85°C
3.9
4.15
4.5
V
160
°C
Under Voltage Lockout
UVLO Threshold
Thermal Shutdow n
Over Temperature Trip Point(2)
TOTP
140
Notes:
(1) Guaranteed by design.
(2) Not tested, by characterization.
Figure 2
Block Diagram
Figure 3
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SC1104A/B
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
Top View
(2)
P ackag e
Temp Range (TJ)
SOIC-8
-40° to 125°C
SC1104XISTR (1)
SC1104XISTRT (1)(3)
SC1104XEVB
Evaluation Board
Notes:
(1) In place of “X”: A = 300kHz, VCC = 5V to 12V.
B = 600kHz, VCC = 5V.
(2) Only available in tape and reel packaging. A reel
contains 2500 devices.
(3) Lead free product. This product is fully WEEE and
RoHS compliant.
(8-Pin SOIC)
Pin Descriptions
Pin
#
Pin Name
1
COMP/SS
2
GND
3
DL
Low side driver output
4
DH
High side driver output
5
BST
Bootstrap, high side driver.
6
PHASE
7
VC C
8
SENSE
Pin Function
Error amplifier output. Compensation, soft start/enable.
Ground.
Input from the phase node between the MOSFETs.
Chip bias supply voltage.
Output voltage sense input.
Marking Information
yyww = Date Code (Example: 0012)
xxxxxxxx = Semtech Lot No. (Example: E90101-1)
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2006 Semtech Corp.
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SC1104A/B
POWER MANAGEMENT
Theory of Operation
Synchronous Buck Converter
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier. The
inverting input of the error amplifier receives its voltage
from the SENSE pin. The non-inverting input of the error
amplifier is connected to an internal 1V reference.
The circuit will be in steady state when Vout =3.3V ,
Vsense = 1V, Icomp = 0 . The COMP voltage and duty
cycle depend on Vin.
The error amplifier output is connected to the
COMPensation pin. The error amplifier generates a current proportional to (Vsense – 1V), which is the COMP
pin output current (Transconductance ~ 12mS). The
voltage on the COMP pin is the integral of the error amplifier current. The COMP voltage is the non-inverting
input to the PWM comparator and controls the duty cycle
of the MOSFET drivers. The size of capacitor Ccomp controls the stability and transient response of the regulator. The larger the capacitor, the slower the COMP voltage changes, and the slower the duty cycle changes.
The under voltage lockout circuit of the SC1104A/B assures that both high-side and low-side MOSFET driver
outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if VCC
falls below 4.2V typ.
Under Voltage Lockout
RDS(ON) Current Limiting
In case of a short circuit or overload, the high-side (HS)
FET will conduct large currents. To prevent damage, in
this situation, large currents will generate a fault condition and begin a soft start cycle.
The inverting input voltage of the PWM comparator is
the triangular output of the oscillator.
While the HS driver is on, the phase voltage is compared
to the Vcc pin voltage. If the phase voltage is 200mV
lower than Vcc, a fault is latched and the soft start cycle
begins.
When the oscillator output voltage drops below the COMP
voltage, the comparator output goes high. This pulls DL
low, turning off the low-side FET. After a short delay (“dead
time”), DH is pulled high, turning on the high-side FET.
When the oscillator voltage rises back above the error
amplifier output voltage, the comparator output goes low.
This pulls DH low, turning off the high-side FET, and after
a dead time delay, DL is pulled high, turning on the lowside FET. The dead time delay is determined by a
monostable on the chip.
The voltages are compared during the middle of the HS
pulse, to prevent transients from affecting the accuracy.
The sampling of the voltage across the top FET occurs
after a time delay tDELAY = 100ns_typ from the time the
DH is pulled high. This delay prevents the measurement
to be effected by ringing on the leading edge of the phase
node pulse. The duration of the sampling is tSAMPLE =
100ns_typ. It is being disabled at very low duty cycle when
tON < 300ns_typ. This feature allows for the orderly startup during the inrush of the current charging output capacitor and the fault free operation with extremely high
input/output voltage ratio, e.g., VIN = 12V and VOUT = 1V.
The triangle wave minimum is about 1V, and the maximum is about 2V. Thus, if Vcomp = 0.9V, high side duty
cycle is the minimum (~0%) , but if Vcomp is 2.0V, duty
cycle is at maximum ( ~90%).The internal oscillator uses
an on-chip capacitor and trimmed precision current
sources to set the oscillation frequency to 300kHz
(SC1104A) or 600kHz (SC1104B).
The over-current comparator (OC) is only active if the
phase node is > 3.3V. This means that in the case of
power source being < 3V the OC will be disabled even
though the rest of the circuitry is completely functional.
SC1104 still can be used for stepping down, e.g. 2.8V to
2.5V, 2V, 1.8V, etc.
Figure 1 shows a 3.3V output converter. If the Vout <3.3V,
then the SENSE voltage < 1V. In this case the error
amplifier will be sourcing current into the COMP pin so
that COMP voltage and duty cycle will gradually increase.
If Vout > 3.3V, the error amplifier will sink current and
reduce the COMP voltage, so that duty cycle will decrease.
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POWER MANAGEMENT
Theory of Operation (Cont.)
When choosing OC trip point one should consider the
Tempco of the MOSFETs Rds_on and SC1104’s Vtrip.
Also, any ringing on the Vcc and Phase nodes due to
parasitic L and C will have some effect on the OC Vtrip.
Closing the Loop
In order to have a stable closed loop system with optimum
transient response one should make sure that open-loop
frequency response has an adequate Gain & Phase
margins. The Bode plot of log. Gain vs Freq. and Phase
vs Freq. provide the necessary means for the circuit
evaluation. Loop stability defined by compensation
networks around transconductance error amplifier (EA)
and output divider, see below and output capacitor Cout
and inductor Lout.
Example:
Iout_nom = 6A; assume I_max = 125% • Iout_nom =
7.5A
Rds_on = 0.014Ω; assume Rds_on_max ≈ 150% •
Rds_on = 0.02Ω
Vout
Voc = 7.5A • 0.02Ω = 150mV.
Cn
Ra
Rn
This proves that MOSFETs with RDS_ON = 0.014Ω @ 25°C
is the right choice.
EA
_
Soft Start
CC
The soft start (or hiccup) circuitry is activated when a
fault occurs. Faults occur for three reasons:
RC
1) Under voltage (VCC < 4.2V)
2) Over temperature (die temperature > 150°C)
3) Over current in high side FET.
Gm
+
Cp
Rb
Vref
Typical transconductance error amplifier
All faults are handled the same way. Both DH and DL are
forced low. The error amplifier is turned off, but a 2µA
current flows into the comp pin (soft start current). The
sink current reduces the Comp voltage down to 0.6V
over a period of a few milliseconds. When Vcomp ~ 0.6V,
the fault is cleared and the DL goes high. Also, the soft
start current changes polarity and begins to increase the
voltage on the Comp capacitor. The DH remains low, because Vcomp is less than the lowest excursion of the
oscillator ramp (1.0V). After a few ms, the Vcomp increases to about 1.0V and the DH will start to switch.
The duty cycle will gradually increase, and Vsns will increase. When Vsns ~ 1.00V, the error amplifier turns on
again. The circuit has now reached its operating point. If
a fault occurs during the soft start, the cycle will begin
again (drivers low, Vcomp decreasing down to 0.6V).
The inductor and output capacitor form a “double pole”
at the frequency:
fLC =
1
2 • ∏ • Lo • Co
The ESR of the output capacitor and the output capacitor
value create a “zero” at the frequency.
fESR =
1
2 • ∏ • ESR • Co
The “zero” and “pole” from the EA compensation network
are:
fZ =
1
2 • ∏ • Rc • Cc
fP =
1
2 • ∏ • Rc • Cp
The additional “lead” network RA, CN, RN can be used to
improve phase margin in case when output capacitors
with extra-low ESR are used and there is a need to
compensate for “high quality” output Lo, Co filter.
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2006 Semtech Corp.
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SC1104A/B
POWER MANAGEMENT
Theory of Operation (Cont.)
fNET =
attenuation due to the LO, CO filter and the output
resistor divider RA, RB is compensated by the gain of
the PWM modulator and the gain of the
transconductance error amplifier (GmEA • ZCOMP).
1
2 • ∏ • Ra • Cn
Value for the resistor RN should be 1/10 of the output
divider upper resistor RA.
Shown below is a typical Bode plot of the open-loop
frequency response of SC1104 based buck converter.
Example.
Switching frequency fSW = 300kHz
Output capacitance COUT = 3 x 330µF
Output capacitor ESR = 45mΩ/each
Plot1
vdberr in db(volts)
Let’s choose crossover frequency
fCO = 1/20 • fSW = 15kHz
The compensation values used in this example are based
on the following criteria:
80.0
-50.0
40.0
-150
0
-40.0
vpherr in degrees
Output inductance LOUT = 4.7µH
Input voltage VIN = 12V
Output voltage VOUT = 3.3V
-250
-350
2
1
fZ = fLC; fNET = 1/10 • fLC; fP = 10 • fCO = 150kHz
-80.0
Therefore,
fLC =
-450
1
1
= 2.33kHz
2 • ∏ • 4.7µH • 990µF
fESR =
10
1 vdberr
100
1k
frequency in hertz
10k
100k
1Meg
2 vpherr
1
= 10 .72kHz
2 • ∏ • 0.015 • 990µF
Since, the EA can sink/source about 1mA, let’s choose
Rc = 680Ω, then
C
C
=
CP =
1
= 0.1µF
2 • ∏ • Fz • Rc
1
= 1500pF
2 • ∏ • Fp • Rc
Assuming the output divider lower resistor RB = 1k, then
for VOUT = 3.3V the RA = 2.32k.
CN =
1
= 0.3µF
2 • ∏ • fNET • Ra
At the closed-loop crossover frequency fCO, the
© 2006 Semtech Corp.
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SC1104A/B
POWER MANAGEMENT
Typical Characteristics
Reference Voltage vs. Temp
Switching Frequency vs. Temp
25%
0.5%
0.4%
20%
0.3%
15%
0.2%
0.1%
10%
0.0%
5%
Freq, %
Vref, %
-0.1%
-0.2%
-0.3%
0%
-5%
-0.4%
-0.5%
-10%
-0.6%
-15%
-0.7%
-0.8%
-20%
-0.9%
-25%
-1.0%
-40
-20
0
20
40
60
80
100
-40
120
-20
0
20
25%
10%
20%
8%
15%
6%
10%
4%
5%
2%
0%
-5%
-4%
-6%
-20%
-8%
-25%
-10%
20
40
60
80
100
120
-40
Temp, °C
©
2006 Semtech Corp.
100
120
100
120
0%
-15%
0
80
-2%
-10%
-20
60
Under Voltage Lockout vs. Temp
UVLO, %
Vtrip, %
Trip Voltage vs. Temp
-40
40
Temp, °C
Temp, °C
-20
0
20
40
60
80
Temp, °C
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SC1104A/B
POWER MANAGEMENT
Evaluation Board Schematic - VIN = 5V
0
+
C3
1.0
C8
47/6.3V
C7
10.0
D1
MBRA130L
C1
1500p
C9
47/6.3V
C10
47/6.3V
Vin=5V
_
U1
C2
0.1
SC1104AISTR
R1
1k
1
COMP/SS
2
GND
SENSE
8
VCC
7
3
DL
PHASE
6
4
DH
BST
5
R8
1.50k
D2
MBRA130L(opt)
Q1
Si4410DY
R3
1
R7
1.0k
R5
0
C4
0.1
C11
0.47
L1
3.9uH
+
Q2
Si4410DY
R4
2.2
R9
150
C5
6800p
C15
330/4V
C16
330/4V
C17
330/4V
C18
10
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R6
2.2
_
Evaluation Board Schematic - VIN = 12V
0
+
C3
1.0
C8
33/16V
C7
10.0
C1
1500p
C9
33/16V
C10
33/16V
Vin=12V
D1
LL4148
_
U1
C2
0.1
SC1104AISTR
R1
680
1
COMP/SS
2
GND
SENSE
8
VCC
7
3
DL
PHASE
6
4
DH
BST
5
R3
2.2
R4
2.2
R8
2.32k
D2
MBRA130L(opt)
Q1
Si4410DY
R7
1.0k
R5
5.1opt
C4
0.1
R9
220
C11
0.33
L1
4.7uH
+
Q2
Si4410DY
C5
3300p
R6
3.3
C15
330/4V
C16
330/4V
C17
330/4V
C18
10
[email protected]
_
© 2006 Semtech Corp.
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SC1104A/B
POWER MANAGEMENT
Evaluation PC Board
Top View
Top Layer
Bottom Layer
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2006 Semtech Corp.
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SC1104A/B
POWER MANAGEMENT
Typical Characteristics
100%
95%
Efficiency
90%
85%
12V = Vin
80%
3.3V = Vout
75%
12A = Iout
70%
65%
60%
0
2
4
6
8
10
12
Regulation
Current, A
1.0%
0.8%
0.6%
0.4%
0.2%
0.0%
-0.2%
-0.4%
-0.6%
-0.8%
-1.0%
0
2
4
6
8
10
12
Current, A
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SC1104A/B
POWER MANAGEMENT
Typical Characteristics (Cont.)
100%
95%
Efficiency
90%
5V = Vin
85%
2V = Vout
80%
12A = Iout
75%
70%
65%
60%
0
2
4
6
8
10
12
Regulation
Current, A
1.0%
0.8%
0.6%
0.4%
0.2%
0.0%
-0.2%
-0.4%
-0.6%
-0.8%
-1.0%
0
2
4
6
8
10
12
Current, A
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2006 Semtech Corp.
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SC1104A/B
POWER MANAGEMENT
Outline Drawing - SOIC - 8
A
D
e
N
DIM
A
A1
A2
b
c
D
E1
E
e
h
L
L1
N
01
aaa
bbb
ccc
2X E/2
E1 E
1
2
ccc C
2X N/2 TIPS
e/2
B
D
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.069
.053
.010
.004
.065
.049
.020
.012
.010
.007
.189 .193 .197
.150 .154 .157
.236 BSC
.050 BSC
.010
.020
.016 .028 .041
(.041)
8
8°
0°
.004
.010
.008
aaa C
SEATING
PLANE
h
A2 A
C
A1
bxN
bbb
1.75
1.35
0.25
0.10
1.65
1.25
0.51
0.31
0.25
0.17
4.80 4.90 5.00
3.80 3.90 4.00
6.00 BSC
1.27 BSC
0.25
0.50
0.40 0.72 1.04
(1.04)
8
8°
0°
0.10
0.25
0.20
h
H
C A-B D
c
GAGE
PLANE
0.25
SEE DETAIL
L
(L1)
A
DETAIL
SIDE VIEW
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MS-012, VARIATION AA.
Minimum Land Pattern - SOIC - 8
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.205)
.118
.050
.024
.087
.291
(5.20)
3.00
1.27
0.60
2.20
7.40
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 300A.
Contact Information
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Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2006 Semtech Corp.
14
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