SC1480 DDR Memory Power Supply Controller POWER MANAGEMENT Description Features The SC1480 is a single output, constant on-time synchronous-buck, pseudo-fixed frequency, PWM controller intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and fast dynamic response with no minimum on time, a reference input and a buffered REFOUT pin capable of sourcing 3mA. The excellent transient response means that SC1480 based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. The SC1480 incorporates two power-reducing states, standby and shutdown. In standby mode, the switcher output is shutdown but the buffered reference output stays up, reducing quiescent current to a low 125µA. This is particularly useful for reducing battery draw in systems which implement a suspend-to-RAM (S3) state. The SC1480 can be completely shut down, drawing less than 10µA. Constant on-time for fast dynamic response Programmable VOUT based on external reference VIN range = 1.8V – 25V DC current sense using low-side RDS(ON) sensing or sense resistor 3mA reference output buffer Low power S3 state Resistor programmable frequency Cycle-by-cycle current limit Digital soft start Output current source-sink capability Overvoltage/under-voltage fault protection and PGOOD output Under 10uA typical shutdown current Low quiescent power dissipation 14-Pin TSSOP package. Also available in Lead-free package which is fully WEEE and RoHS compliant Industrial temperature range Integrated gate drivers with soft switching Efficiency >90% Applications The integrated gate drivers feature adaptive shootthrough protection and soft switching. Additional features Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies include cycle-by-cycle current limit, digital soft-start, overvoltage and under-voltage protection, and a PGOOD output. Typical Application Circuit 4.5V - 25V VDD = 2.5V +5VRUN R1 C1 C2 REFOUT D1 C3 +5VSB R2 R3 C4 +5V C5 R4 Q1 U1 1 2 3 4 5 6 7 R5 PGOOD BST REFIN DH TON REFOUT LX VCCA ILIM FBK VDDP PGOOD DL GND PGND 14 13 12 11 10 9 8 SC1480 R7 Revision: August 30, 2006 C8 L1 1.25VOUT R6 Q2 D2 + C6 C7 C10 C9 1 www.semtech.com SC1480 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Pin Combination Symbol Maximum Units TON to AGND -0.3 to +25.0 V DH, BST to AGND -0.3 to +30.0 V LX to AGND -2.0 to +25.0 V AGND to PGND -0.3 to +0.3 V BST to LX -0.3 to +6.0 V VCCA, VDDP to AGND -0.3 to +6.0 V FB, PGOOD, REFIN, ILIM, REFOUT, DL to PGND -0.3 to +6.0 V Thermal Resistance, Junction to Ambient(4) θJA 100 °C/W Operating Junction Temperature Range TJ -40 to +125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C Electrical Characteristics Test Conditions: VIN = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M (300kHz), 0.1% Resistor Dividers Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Max Units Input Supplies VCCA Input Voltage 5.0 4.5 5.5 V VDDP Input Voltage 5.0 4.5 5.5 V VIN Input Voltage 2.0 25 V VDDP Operating Current FB > regulation point, ILOAD = 0A 5 10 µA VCCA Operating Current FB > regulation point, ILOAD = 0A 700 1100 µA VCCA Standby Current VDDP < VDDP UV Threshold No Load On REFOUT 125 µA TON Operating Current RTON = 1M 15 µA (300kHz) Shutdown Current (REFIN = 0V) VC C A 5 10 µA VDDP + VIN 5 10 µA Controller Error Comparator Threshold (FBK Turn-on Threshold) (1) 2006 Semtech Corp. With Respect to REFOUT VCCA = 4.5V to 5.5V REFOUT 2 REFOUT REFOUT -10 +10 mV www.semtech.com SC1480 POWER MANAGEMENT Electrical Characteristics Cont. Test Conditions: VIN = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M (300kHz), 0.1% Resistor Dividers Parameter Conditions 25°C Min On-Time Typ -40°C to 125°C Max Min Max Units RTON = 1M (300kHz) VIN = 2.5V 1660 1411 1909 ns RTON = 500K (600kHz) VIN = 2.5V 913 776 1050 ns 550 ns Minimum Off Time 400 Line Regulation Error VCCA, VDDP = 4.5V to 5.5V Vin = 4.5V to 25V 0.04 %/V Load Regulation Error ILIM - PGND = 0V to 0°C Limit 0.3 % 500 kΩ FBK Input Resistance Over-Current Sensing ILIM Sink Current Current Comparator Offset 10 PGND - ILIM 9 11 µA -5 5 mV Reference Buffer REFOUT Source Current 3 REFIN Enable Threshold 0.8 REFIN Hysteresis 40 Offset Voltage 0.55 mA 1.0 V mV REFOUT current = 0mA -10 10 mV REFOUT current = 3mA -12.5 12.5 mV Fault Protection PGND-LX, RILIM = 5k 50 40 60 mV PGND-LX, RILIM = 10k 100 90 110 mV PGND-LX, RILIM = 20k 200 180 220 mV Current Limit (Negative) PGND-LX -140 -200 -100 mV Output Under-Voltage Fault With respect to REFOUT -20 -28 -15 % Output Over-Voltage Fault With respect to REFOUT +10 +8 +12 % Over-Voltage Fault Delay FBK forced above OV Vth 2.0 PGOOD Low Output Voltage Sink 1mA PGOOD Leakage Current FBK in regulation, PGOOD = 5V PGOOD UV Threshold With respect to REFOUT Current Limit (Positive) (2) 2006 Semtech Corp. -10 3 µs -12 0.4 V 1 µA -8 % www.semtech.com SC1480 POWER MANAGEMENT Electrical Characteristics Cont. Test Conditions: VIN = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M (300kHz), 0.1% Resistor Dividers Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Units Max PGOOD Fault Delay FB forced outside PGOOD window. 2.0 VCCA Under Voltage Threshold Rising Edge Hysteresis 100mv 4.0 3.7 4.3 V VDDP Under Voltage Threshold 3.3 3.0 3.75 V VDDP Under Voltage Hysteresis 250 mV 10°C Hysteresis 165 C Soft-Start Ramp Time REFIN high to full current limit. 1.6 ms Under-Voltage Blank Time SMPS Turn-On 2 ms Dead Time DH or DL rising 30 ns DL Pull-Down Resistance DL low 0.8 1.6 Ω DL Pull-Up Resistance DL high 2 4 Ω DH Pull-Down Resistance DH low, BST - LX = 5V 2 4 Ω DH Pull-Up Resistance DH high, BST - LX = 5V 2 4 Ω DL Sink Current DL - PGND = 2.5V 2 A DL Source Current VDDP - DL = 2.5V 1 A DH Sink Current DH - LX = 2.5V, BST - LX = 5V 1 A DH Source Current BST - DH = 2.5V, B S T - LX = 5V 1 A Over Temperature Lockout µs Soft Start Gate Drivers Notes: (1) When the inductor is in continuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. (3) This device is ESD sensitive. Use of ESD handling precautions is required. (4) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7. 2006 Semtech Corp. 4 www.semtech.com SC1480 POWER MANAGEMENT Pin Configuration Ordering Information Device TOP VIEW REFIN 1 14 BST TON 2 13 DH REFOUT 3 12 LX VCCA 4 11 ILIM FBK 5 10 VDDP PGOOD 6 9 DL AGND 7 8 PGND P ackag e (1) SC1480ITSTR TSSOP-14 SC1480ITSTRT(2) TSSOP-14 S C 1480E V B Evaluation Board Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (14 Pin TSSOP) Pin Descriptions Pin # Pin Name Pin Function 1 REFIN 2 TON 3 REFOUT 4 VC C A 5 FB K 6 PGOOD 7 AGND Analog ground. 8 PGND Power ground. 9 DL 10 VD D P 11 ILIM Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. 12 LX Switching node inductor connection. 13 DH Gate drive output for the high side MOSFET switch. 14 BST Boost capacitor connection for the high side gate drive. 2006 Semtech Corp. External Reference input. Tie to ground to disable SMPS and reference buffer. On-time set input. Sets on-time of upper MOSFET via series resistor to the input supply. Reference output pin. Can source 3mA. Supply voltage input for the analog supply. Connect through a RC filter to +5V. Feedback input. Connect from resistor divider at output of SMPS to select output voltage. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay following power up. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Tie to ground to disable SMPS. 5 www.semtech.com SC1480 POWER MANAGEMENT Block Diagram VDDQ = 2.5V VCCA VDDQ VDDP VDDP POR/SS 1 OT REFIN 14 BST HI 2 VIN +5V REFOUT VDDQ ON TON CONTROL LOGIC OFF 3 13 DH VOUT 12 LX PWM REFOUT 4 VCCA TOFF REF BUFFER OC ISENSE ZEROI VOUT 5 FBK + - 11 ILIM + - +5V PWM 10 VDDP 6 PGOOD 7 AGND FAULT MONITOR OV LO UV 9 DL REF+10% REF-10% REF-20% 8 PGND FIGURE 1 2006 Semtech Corp. 6 www.semtech.com SC1480 POWER MANAGEMENT Applications Information RTON is a resistor connected from the input supply to the TON pin. The graph on page 19 shows the relationship between RTON and switching frequency. +5V Bias Supply The SC1480 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator. There are two inputs for the external +5V bias supply, VCCA & VDDP. The VCCA input powers the analog section of the SC1480 while the VDDP input provides power to the upper and lower gate drivers. VCCA will need to be decoupled from the +5V supply through a 10 Ohm resistor and the addition of a filter capacitor from VCCA to ground. VCCA and VDDP must be separate in order to utilize the low power S3 state of the SC1480. The battery input VIN and the +5V input VCCA can be tied together if the input voltage is fixed from +4.5V to +5.5V; however, as before, VCCA will need to be decoupled from the +5V supply through a 10 Ohm resistor and the addition of a filter capacitor from VCCA to ground. Reference I/O The reference input can be generated off of a 2.5V or VDDQ supply by a simple resistive divider. Resistors less than 100k Ohms should be used and a small filter capacitor from the reference input to ground of 0.1uF will remove any ripple voltage present on the input. The input has a common mode range of the REFIN threshold to 2.5V. The voltage on the reference input passes through a unity gain buffer prior to being sent to REFOUT. This reference output has a class A output stage with 3mA of sourcing capacity. It has a pull-down impedance of 50k. The output will require a small RC filter of 10 Ohms and 1µF to maintain stability. Pseudo-Fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant-ontime, pseudo fixed frequency PWM controller, (Figure 1). The output ripple voltage developed across the output filter capacitors ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The highside switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time to 400ns typically. Shutdown, Suspend to RAM and Run Mode The SC1480 has three modes of operation: shutdown, suspend to RAM, and run mode. All three modes must have VCCA connected at all times. Shutdown mode is controlled by REFIN. When REFIN is below 0.8V, the reference buffer will be off and the SMPS is disabled. In this mode the bias current of the device will be less than 10µA. Suspend to RAM, or S3 State, is controlled by REFIN and VDDP. With REFIN is above 0.8V and VDDP is low (below 3V), the device will output the reference voltage onto REFOUT, but the SMPS is disabled. In this mode the bias current is approximately 125µA. Run mode is activated by maintaining REFIN above 0.8V and VDDP above 3V. In this mode the reference and SMPS are active. On-Time One-Shot (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input proportional current is used to charge an internal on-time capacitor. The TON time is the time required for the voltage on the capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator. V TON = 3.3x10 −12 •(RTON + 37x10 3 ) • OUT VIN 2006 Semtech Corp. Current Limit Circuit Current limiting of the SC1480 can be accomplished in two ways. First, the device can implement on-state resistance of the low-side MOSFET as the current sensing element (RDSON sensing). Second, the device can accept a resistive element in the low-side source (RSENSE, resistor sensing). The second method offers greater accuracy of the current limit threshold over RDSON sensing, at the added expense of a sense resistor and associated efficiency loss. Whether RDSON sensing or RSENSE resistor sensing is used, + 50ηS 7 www.semtech.com SC1480 POWER MANAGEMENT Applications Information (Cont.) a scaling resistor between LX and ILIM is required. This resistor, RILIM, is connected to a 10µA current source within the SC1480 through the ILIM pin. This sets a voltage drop equal to 10µA times RILIM. As the current increases through the lower MOSFET, the phase pin voltage will decrease until the offset voltage caused by RILIM is reached and ILIM < PGND. At this point an overcurrent trip signal is issued. Current limiting will prevent the firing of a DH on-pulse, thereby reducing the switching frequency. As the frequency decreases, the output voltage will drop until an under-voltage shutdown is reached. +5V +VIN + D1 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 C1 Q1 C2 L1 VOUT R1 D2 SC1480 + Q2 C3 FBK The current sensing circuit actually limits the inductor valley current (see Figure 2). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below: IL OC (Valley ) = 10µA • FIGURE 3 Schematic of RDSON sensing circuit is shown in Figure 3 with RDSON of Q2. Similarly, for resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an overcurrent will be issued. The overcurrent equation when using an external sense resistor is: RILIM RDS ON IL OC (Average) = IL OC (Valley ) + ∆IL 2 IL OC (Valley ) = 10µA • Schematic of resistor sensing circuit is shown in Figure 4 with RILIM = R1 and RSENSE = R2. IPEAK INDUCTOR CURRENT RILIM R SENSE ILOAD +5V +VIN ILIMIT + D1 BST DH LX ILIM VDDP DL PGND TIME Valley Current-Limit Threshold Point 14 13 12 11 10 9 8 C2 Q1 L1 VOUT Q2 + SC1480 D2 R1 FIGURE 2 C1 C3 R2 FBK FIGURE 4 2006 Semtech Corp. 8 www.semtech.com SC1480 POWER MANAGEMENT Applications Information (Cont.) Power Good Output Power good is an open-drain output and requires a pullup resistor. When the output voltage is 10% above or below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within 10% of the output set voltage. PGOOD is also held low during startup and will not be allowed to transition high until the output reaches 90% of its set voltage. There is a slight delay built into the PGOOD circuit to prevent false transitions. The high-side gate driver is equipped with turn-on soft switching to reduce gate drive power dissipation. When a DH turn-on is initiated the pull-up resistance is 10 Ohms. This limits the peak high-side gate current before the MOSFET is conducting current. The peak gate current plays a large role in gate driver switching losses. When the high-side MOSFET begins conducting, and LX starts to rise, the pull-up resistance on DH changes to 2 Ohms. Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the OV protection circuit to prevent false transitions. Design Procedure Prior to any design of a switch mode power supply (SMPS) for notebook computers, determination of input voltage, load current, switching frequency and inductor ripple current must be specified. Output Undervoltage Protection When the output is 20% below its set voltage the output is latched in a tristated condition, and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the UV protection circuit to prevent false transitions. Input Voltage Range The maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage. The minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high until VCCA rises above 4.1V. At this time the circuit will come out of UVLO and begin switching, and the softstart circuit being enabled, will progressively limit the output current over a predetermined time period. The ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. There is 100mV of hysteresis built into the UVLO circuit and when the VCCA falls to 4.0V the output drivers are shutdown and tristated. Maximum Load Current There are two values of load current to consider. Continuous load current and peak load current. Continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, MOSFETs and commutation diodes. Whereas, peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit. Switching Frequency Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on, until DL is fully off, and conversely, monitors the DH output and prevents the low-side MOSFET from turning on until DH is fully off. Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. 2006 Semtech Corp. Inductor Ripple Current Low inductor values create higher ripple current, resulting in smaller size, but are less efficient because of the high AC currents flowing through the inductor. Higher inductor values do reduce the ripple current and are more efficient, but are larger and more costly. 9 www.semtech.com SC1480 POWER MANAGEMENT Applications Information (Cont.) RDSON of the MOSFET is a nominal 0.013 Ohms, accounting for increased temperature effects use 0.015 Ohm. The selection of the ripple current is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. Again, cost, size and efficiency all play a part in the selection process. RILIM = Design Example The following design example is for the evaluation board schematic shown on page 16. While most DDR supplies have a maximum load of 3A, the following design was meant for applications beyond DDR memory. Therefore, this design will have an input voltage from 5V to 19V, with an output voltage of 1.25V at 5A of load current. The inductor chosen was a Panasonic 4µH, 11A inductor. Similarly, using a Sense resistor to obtain a more accurate current limit would make use of the valley current equation. Thus, for a 0.015 Ohm resistor the RILIM would calculate to the same 10k Ohm ILIM resistor will be 6 • 6 • 0.015 = 0.54 W effecting the efficiency budget. Inductor Selection The switching frequency is set to 300kHz which yields a good trade-off of size and efficiency. RTON is chosen to be 1M Ohm for a switching frequency of 300kHz. Because ripple voltage is used as the feedback mechanism of this device, this leads to the choice of the ripple current being 10% of load current. This will give a nice ripple voltage waveform for ensuring proper PWM triggering for this type of controller. Output Capacitor Selection The output filter capacitor must have low effective series resistance (ESR) to meet the output ripple and load transient requirements, at the same time have high enough ESR to satisfy stability requirements. In addition, the value of output capacitance must be high enough to absorb the inductor energy going from full-load to noload without tripping the overvoltage protection circuit. For CPU load transients, how much ESR is needed depends upon output voltage variation limits under a CPU load transient. The ESR for this condition is given: ∆IL = 0.1•5 = 0.5A L= VOUT • (VIN − VOUT ) • T VIN • ∆IL ESR = L = 4µH Setting the Current Limit The minimum current-limit threshold must be high enough to support the maximum load current. The valley of the inductor current occurs at: ILoad(Max) − ∆IL 2 ESR = ∆IL 2 Setting the over current to 6.5A is calculated as follows: CMIN = RDSON•ILOC 10µA 2006 Semtech Corp. ILOAD(MAX) ∆VOUT(p - p) ILOAD(MAX) However, for most CPU applications the minimum capacitance required is limited by the energy absorption of the output capacitor. The equation for determining the minimum capacitance can be found by the following equation: The inductor must not saturate under all conditions of operation. If the current limit is set to 6.5A the maximum current through the inductor will be: 6.5 + ∆IL = 7A RILIM = ∆VOUT In non CPU applications, the output capacitor size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. Under these conditions the ESR value is given: , (see Figure 2) therefore: ILIM(Low) > ILoad(Max) - 0.015 • 6.5 = 10k 10µA 10 LOUT •IOUT 2 VF 2 − VI2 www.semtech.com SC1480 POWER MANAGEMENT Applications Information (Cont.) empirically. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. Referring to Figure 3, the equation for the minimum ESR as a function of output capacitance and switching frequency and duty cycle is; Where VF is the final output voltage after release of the load and VI is the initial voltage prior to the release of load. If no more than 100mV of output voltage variation is required between VF and VI , plugging in the numbers for the application circuit yields minimum output capacitance of 1000µF. As shown, a large amount of capacitance is required to absorb the energy of the inductor during a load release of 5A. In typical DDR memory applications a load release of this magnitude is not an issue and therefore the application circuit can get by with 300µF of output capacitance. Fs - 200000 1+3 • Fs ESR > 2• π•Cout •Fs • 1 −D 2 ( ) Stability Considerations: Unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is too low, causing not enough voltage ramp in the output signal. This causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. However, in some cases double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. Where D = Vout/Vin. Plugging in the numbers for this design ESR > 0.004 Ohms. Input Capacitor Selection Input capacitors are selected based upon the input ripple current demand of the converter. First determine the input ripple current expected and then choose a capacitor to meet that demand. The input RMS ripple current can be calculated as follows: IRMS = IOUT VIN Therefore, for a maximum load current of 6.0A , the input capacitors should be able to safely handle 3A of ripple current. For the EVAL board, we chose two 10µF, 25V ceramic capacitors. Each capacitor has a ripple current capability of 2A. SC1480 ESR Requirements The constant on-time control used in the SC1480 regulates the ripple voltage at the output capacitor. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors the absolute minimum ESR must be considered. Existing literature describing the ESR requirements to prevent double pulsing does not accurately predict the performance of constant on-time controllers. A time domain model of the converter was developed to generate equations for the minimum ESR 2006 Semtech Corp. VOUT • (VIN − VOUT ) • MOSFET Switch Selection The current selection of MOSFETs are determined by the setting of the overcurrent limit circuit and the maximum input voltage. The next step is to determine their power handling capability. For the EVAL board the ISi4484 meet the voltage and current requirements. This is a 30V, 10A FET. Based on 85°C ambient temperature, 150°C junction temperature and thermal resistance, their power handling is calculated as follows: Power Limit for Upper & Lower FET: TJ = 150°C; TA = 85°C; θ = 50°C/W JA 11 www.semtech.com SC1480 POWER MANAGEMENT Applications Information (Cont.) PT = TJ − TA 150 − 85 = = 1.3W θ JA 50 performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by: Each FET must not exceed 1.3W of power dissipation. MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case conduction power dissipation occurs at minimum battery voltage: PDUC = DUTY = Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. VOUT •ILOAD2 •RDS(ON) VIN(MIN) Layout Guidelines As with any high frequency switching regulator, it is advisable to practice a careful layout strategy. This includes keeping loop area as small as possible. And properly decoupling lines that pull large currents in short periods of time. To keep loop area small always use a ground plane and if possible split the plane in two areas, signal GND and power GND, then tie the two together at one point. Be sure that high current paths have low inductance by making trace widths wide where possible. The SC1480 pin-outs contain digital signals on the right and analog signals on the left side of the device. This facilitates the isolation of digital and analog signals enabling effective layout of the device. In summary follow these guidelines for good PC board layout:: Typically, a small high-side MOSFET is selected to reduce switching losses at high input voltages. However, the RDS(ON) limits how small the MOSFET can be. Another element of loss in the upper MOSFET is the switching loss, especially at high input voltages, those seen when the AC adaptor is applied. The upper MOSFET switching losses can be estimated as follows: PDUS = CRSS• VIN(MAX )2 • f •ILOAD IGATE Where CRSS is the reverse transfer capacitance of the upper MOSFET and IGATE is the peak gate-drive source/ sink current which is approximately 1A for the SC1480. • Keep high-current paths short, especially at the ground terminals. • Tie AGND and PGND together close to the IC. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs 1oz) can enhance full-load efficiency by 1% or more. • Connect the ILIMIT resistor as close to the lower MOSFET drain as possible, and keep the resistance distance from the ILIM pin to the drain short. This will improve current limit accuracy. For the low-side MOSFET the there are only conduction loses to be concerned about since the commutation diode is active while the lower MOSFET switches. The worstcase power dissipation occurs at maximum battery voltage: VOUT PDLC = 1 •ILOAD2 •RDS( ON) V ( ) IN MAX Adding up the power dissipation for each MOSFET can now proceed and the total for each MOSFET should not exceed 1.3W which was calculated earlier to be the maximum power dissipation under worst-case conditions. 1480 System DC Accuracy Two IC parameters effect system DC accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. The 1480 regulates to the REFOUT voltage not the REFIN voltage. Since DDR specifications are written with respect to REFOUT, the offset of the reference buffer does not create a regulation error. Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 500nS (maximum) minimum off-time one-shot. For best dropout 2006 Semtech Corp. TON(MIN) TON(MIN) + TOFF(MAX) 12 www.semtech.com SC1480 POWER MANAGEMENT Applications Information (Cont.) The error comparator offset is trimmed so that it trips when VOUT is 1.25 volts +/-1% at room temperature. This offset does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. Thermal Considerations The on pulse in the SC1480 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if REFOUT=1.25 volts, then the valley of the output ripple will be 1.25 volts. If the ripple is 20mv with VIN=6, then the DC output voltage will be 1.26 volts. If the ripple is 40mv with VIN=25 volts, then the DC output voltage will be 1.27 volts. The best way to minimize this effect is to minimize the output ripple. Where: TA = ambient temperature (°C) PD = power dissipation in (W) θJA = thermal impedance junction to ambient from absolute maximum ratings (°C/W) The junction temperature of the device may be calculated as follows: TJ = TA + PD • θ JA °C The power dissipation may be calculated as follows: PD = VCCA • IVCCA + Vg • Q g • f W Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) To compensate for valley regulation it is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Passive droop also improves stability so it should be used when possible. Inserting the following values as an example: TA = 85°C θJA = 100°C/W VCCA = 5V IVCCA = 1100µA (data sheet maximum) Vg = 5V Qg = 60nC f = 300kHz gives us: ( ) TJ = 85 + 5 • 1100 • 10 −6 + 5 • 60 • 10 −9 • 300 • 10 3 • 100 = 95 °C As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout. 2006 Semtech Corp. 13 www.semtech.com SC1480 POWER MANAGEMENT Reference Design +5V_RUN C1 10uF/10V 4.5V - 25V 2.50V_SUS C2 10uF/25V R1 20K REFOUT D1 +5V R2 1M ZHCS400 R3 20K 8 +5V_SUS C4 1uF R4 10 1 2 3 4 5 6 7 R5 1M PGOOD R7 NO_POP C6 1uF C7 1000pF U1 REFIN BST TON DH REFOUT LX VCCA ILIM FBK VDDP PGOOD DL GND PGND C5 0.1uF 14 13 12 11 10 9 8 R6 10K SC1480 C8 0.01uF Q1 2 1 5 6 7 4 Si4818DY 3 C3 1uF L1 1.25VOUT 4.1uH + C9 150uF C10 10uF VIN = 4.5V - 25V VOUT = 1.25V; IOUT = 3A 2006 Semtech Corp. 14 www.semtech.com SC1480 POWER MANAGEMENT Reference Design - Bill of Material Item Quantity 1 1 C1 10uF/10V 2 1 C2 10uF/25V 3 3 C3,C4,C6 1uF 4 1 C5 0.1uF 5 1 C7 1000pF 6 1 C8 0.01uF 7 1 C9 150uF 8 1 C 10 10uF 9 1 D1 ZHCS400 10 1 L1 4.1uH 11 1 Q1 S i 4818D Y 12 2 R1, R3 20k 13 2 R2, R5 1m 14 1 R4 10 15 1 R6 10k 16 1 R7 No Pop 17 1 U1 S C 1480 2006 Semtech Corp. Reference Part 15 Vendor www.semtech.com SC1480 POWER MANAGEMENT Evaluation Board Schematic +5V 1.25V R1 TP1 750 +5V 2 C1 10uF/6.3V TP2 R2 100 J1 5VRUN U1 1 GND TP3 SC431L R3 12.4K 5VRUN C2 10uF/6.3V TP4 R4 10 C3 1uF GND J2 1 2 TP6 REFI RGND PGD U2 1 2 3 4 5 6 7 RGND R8 NO_POP C8 0.1uF REFIN BST TON DH REFOUT LX VCCA ILIM FBK VDDP PGOOD DL GND PGND 4 14 13 12 11 10 9 8 1 2 3 C9 1uF PHASE_TP 10K Q2 Si4884 4 C14 1000pF 1 2 4uH D2 MBRS140T3 SC1480 C13 1uF J3 L1 R7 + C10 150uF R9 C15 1uF C12 10uF/6.3V C16 NO_POP VOUT SP2 R10 NO_POP 0 2006 Semtech Corp. + C11 150uF 1 2 3 TP8 R6 1M SP1 Q1 Si4884 C7 1uF REFO C6 0.1uF ZHCS400 TP5 TP7 +5V C5 10uF/25V 5 6 7 8 1.25V 5 6 7 8 R5 1M TP9 C4 10uF/25V D1 VIN 16 R11 0 VOUT_TP www.semtech.com SC1480 POWER MANAGEMENT Evaluation Board - Bill of Materials Item Quantity 1 3 C1,C2,C12 10uF/6.3V 2 5 C3,C7,C9,C13,C15 1uF 3 2 C4,C5 10uF/25V 4 2 C6,C8 0.1uF 5 2 C10,C11 150uF 6 1 C 14 1000pF 7 3 R8,R10,C16 NO_POP 8 1 D1 ZHCS400 9 1 D2 MBRS140T3 10 1 J1 Header Post 11 2 J2,J3 Banana Jack 12 1 L1 4uH 13 2 Q1,Q2 S i 4884 14 1 R1 750 15 1 R2 100 16 1 R3 12.4K 17 1 R4 10 18 2 R5,R6 1M 19 1 R7 10K 20 2 R9,R11 0 21 2 SP1,SP2 Probe test point 22 9 TP1 thru TP9 23 1 U1 S C 431L 24 1 U2 S C 1480 2006 Semtech Corp. Reference Part 17 www.semtech.com SC1480 POWER MANAGEMENT Gerber Plots Silk Screen Layer Bottom Layer Power Ground Layer Analog Ground Layer Top Layer 2006 Semtech Corp. 18 www.semtech.com SC1480 POWER MANAGEMENT Typical Characteristic (Cont.) SC1480EVB Efficiency at VOUT = 1.25V SC1480EVB Line Regulation at VOUT = 1.25V 100 0.6 95 0.5 Line Regulation (%) Efficiency (%) 90 85 80 75 VIN=25V VIN=14V VIN=4.5V 70 60 0.5 1 1.5 2 2.5 3 3.5 4 0.3 IOUT=0A IOUT=1A IOUT=2A IOUT=3A IOUT=4A IOUT=5A 0.2 0.1 65 0.1 0.4 4.5 0 5 4.5 10 19 25 Frequency vs. Input Voltage (IOUT = 1A, VOUT = 1.25V, Rton = 1M) SC1480EVB Load Regulation at VOUT = 1.25V 280 0.6 270 0.5 260 Frequency (kHz) Load Regulation (%) 14 Input Voltage (Volts) Output Current (Amps) 0.4 0.3 0.2 VIN=4.5V VIN=10V VIN=14V VIN=19V VIN=25V 0.1 250 240 230 220 210 0 200 0 1 2 3 4 5 5 10 15 20 25 Load Current (Amps) Input Voltage (Volts) Frequency vs. Load Current (VIN = 15V, VOUT = 1.25V, Rton = 1M) Rton vs. Frequency (VIN = 15V, VOUT = 1.25V, IOUT = 1A) 290 600 280 500 Frequency (kHz) Frequency (kHz) 270 260 250 240 230 220 400 300 200 100 210 0 400 200 0 1 2 3 4 5 6 Load Current (Amps) 2006 Semtech Corp. 500 600 700 800 1000 1500 Rton (kohms) 19 www.semtech.com SC1480 POWER MANAGEMENT Typical Characteristic (Cont.) Upper Trace: 0A to +2A Transient Lower Trace: Output Ripple Voltage Upper Trace: Phase Lower Trace: Output Ripple Voltage Upper Trace: 0A to -2A Load Transient Lower Trace: Output Ripple Voltage 2006 Semtech Corp. Upper Trace: 0A to +2A and 0A to -2A Transient Lower Trace: Output Ripple Voltage 20 www.semtech.com SC1480 POWER MANAGEMENT Marking Diagram Top Mark Bottom Mark yy = two-digit year of manufacture ww = two-digit week of manufacture xxxxxx = Wafer Lot Number xx = Assembly Lot Number 2006 Semtech Corp. 21 www.semtech.com SC1480 POWER MANAGEMENT Outline Drawing - TSSOP-14 A D DIM A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc 2X E/2 E1 E PIN 1 INDICATOR ccc C 2X N/2 TIPS 1 2 3 e B aaa C SEATING PLANE DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .047 .006 .002 .042 .031 .012 .007 .003 .007 .193 .197 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 14 0° 8° .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.20 0.09 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 14 0° 8° 0.10 0.10 0.20 D A2 A A1 C bxN bbb H c GAGE PLANE C A-B D 0.25 L (L1) DETAIL SEE DETAIL SIDE VIEW 01 A A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB-1. Land Pattern - TSSOP-14 X DIM (C) G DIMENSIONS INCHES MILLIMETERS C G P X Y Z Z Y (.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805) 498-3804 Visit us at: www.semtech.com 2006 Semtech Corp. 22 www.semtech.com