STMICROELECTRONICS PSD835G2V

PSD835G2
Flash PSD, 5V Supply, for 8-bit MCUs
4 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
DUAL BANK FLASH MEMORIES
– 4 Mbits of Primary Flash Memory (8
uniform sectors, 64Kbyte)
– 256 Kbits of Secondary Flash Memory
with 4 sectors
– Concurrent operation: READ from one
memory while erasing and writing the
other
64 KBIT OF BATTERY-BACKED SRAM
52 RECONFIGURABLE I/O PORTS
ENHANCED JTAG SERIAL PORT
PLD WITH MACROCELLS
– Over 3000 Gates of PLD: CPLD and
DPLD
– CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
52 INDIVIDUALLY CONFIGURABLE I/O
PORT PINS
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open-drain
outputs.
IN-SYSTEM PROGRAMMING (ISP) WITH
JTAG
– Built-in JTAG compliant serial port allows
full-chip In-System Programmability
– Efficient manufacturing allow easy
product testing and programming
– Use low cost FlashLINK cable with PC
PAGE REGISTER
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
PROGRAMMABLE POWER MANAGEMENT
March 2004
Figure 1. Package
TQFP80 (U)
■
■
■
■
HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 1,000 Erase/WRITE Cycles of PLD
– 15 Year Data Retention
5V±10% SINGLE SUPPLY VOLTAGE
STANDBY CURRENT AS LOW AS 50µA
MEMORY SPEED
– 70ns Flash memory and SRAM access
time for VCC = 4.5V to 5.5V
– 90ns Flash memory and SRAM access
time for VCC = 4.5V to 5.5V
1/102
PSD835G2
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
First time programming.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Inventory build-up of pre-programmed devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Expensive sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Simultaneous READ and WRITE to Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Complex memory mapping.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Separate Program and Data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PSDsoft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. TQFP80 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. PSD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. JTAG SIgnals on Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
In-Application re-Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Methods of Programming Different Functional Blocks of the PSD . . . . . . . . . . . . . . . . . 17
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. PSDsoft Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Register Address Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Data-In Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Data-Out Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Direction Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Control Registers – Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Drive Registers – Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/102
PSD835G2
Table 11. Drive Registers – Ports C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Enable-Out Registers – Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. Input Macrocells – Ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 17. Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 18. Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 19. Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 20. JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 21. Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 22. PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 23. PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 24. VM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 25. Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 26. Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 27. Memory Block Size and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 25
Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Upper and Lower Block IN MAIN FLASH SECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5. Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Selecting the Upper or Lower Block in a Primary Flash Memory Sector . . . . . . . . . . . . . 26
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 28. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/102
PSD835G2
Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash Bulk Erase . . . . . . . . . . . . .
Flash Sector Erase . . . . . . . . . . .
Suspend Sector Erase . . . . . . . .
Resume Sector Erase . . . . . . . . .
.......
.......
.......
.......
......
......
......
......
.......
.......
.......
.......
......
......
......
......
.......
.......
.......
.......
......
......
......
......
......
......
......
......
. . . . 33
. . . . 33
. . . . 33
. . . . 33
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset (RESET) Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 35
Figure 9. Priority Level of Memory and I/O Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 36
Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10.8031 Memory Modules – Separate Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11.8031 Memory Modules – Combined Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12.Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 30. DPLD and CPLD Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13.PLD Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14.DPLD Logic Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 15.Macrocell and I/O Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 31. Output Macrocell Port and Data Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16.CPLD Output Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4/102
PSD835G2
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17.Input Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18.Handshaking Communication Using Input Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 19.External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 32. MCUs and their Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 20.An Example of a Typical 8-bit Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . 51
PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 21.An Example of a Typical 8-bit Non-Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . 52
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 22.Interfacing the PSD with an 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 33. 80C251 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 34. Interfacing the PSD with the 80C251, with One READ Input . . . . . . . . . . . . . . . . . . . . . 55
Figure 23.Interfacing the PSD with the 80C251, with RD and PSEN Inputs . . . . . . . . . . . . . . . . . . 56
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 24.Interfacing the PSD with the 80C51X, 8-bit Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 25.Interfacing the PSD with a 68HC11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 26.General I/O Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 35. Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 36. Port Operating Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 37. I/O Port Latched Address Output Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 27.Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 38. Port Configuration Registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 39. Port Pin Direction Control, Output Enable P.T. Not Defined . . . . . . . . . . . . . . . . . . . . . . 64
Table 40. Port Pin Direction Control, Output Enable P.T. Defined . . . . . . . . . . . . . . . . . . . . . . . . . 64
5/102
PSD835G2
Table 41. Port Direction Assignment Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 42. Drive Register Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 43. Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Ports A,B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 28.Port A, B and C Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 29.Port D Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Port G – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 30.Port E, F, G Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 44. Power-down Mode’s Effect on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 31.APD Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 45. PSD Timing and Stand-by Current during Power-down Mode . . . . . . . . . . . . . . . . . . . . 71
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SRAM Standby Mode (Battery Backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 32.Enable Power-down Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 46. APD Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 33.Power-Up and Warm Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 47. Status During Power-Up Reset, Warm Reset and Power-down Mode . . . . . . . . . . . . . . 75
PROGRAMMING IN-CIRCUIT USING THE JTAG/ISP INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6/102
PSD835G2
Table 48. JTAG Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 34.PLD ICC /Frequency Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 49. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode On) . . . . . 79
Table 50. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode Off) . . . . . 80
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 51. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 52. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 53. AC Signal Letters for PLD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 54. AC Signal Behavior Symbols for PLD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 55. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 56. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 35.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 36.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 37.Switching Waveforms – Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 57. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 38.Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 39.Combinatorial Timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 58. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 59. CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 60. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 40.Synchronous Clock Mode Timing – PLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 41.Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 42.Asynchronous Clock Mode Timing (Product Term Clock). . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 43.Input Macrocell Timing (Product Term Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 61. Input Macrocell Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 44.READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 62. READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 45.WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 63. WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 46.Peripheral I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 64. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 47.Peripheral I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 65. Port F Peripheral Data Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 66. Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 67. Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 48.Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 68. Reset (Reset) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 69. VSTBYON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 49.ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 70. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7/102
PSD835G2
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 50.TQFP80 - 80 lead Thin, Quad, Flat Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 71. TQFP80 - 80 lead Thin, Quad, Flat Package Mechanical Data. . . . . . . . . . . . . . . . . . . . 98
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 72. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
APPENDIX A.PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 73. PSD835G2 TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 74. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8/102
PSD835G2
SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for embedded designs. PSD devices combine many of
the peripheral functions found in MCU based applications.
The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique
requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to
simplify communication between the MCU and
other supporting devices.
The PSD family offers two methods to program the
PSD Flash memory while the PSD is soldered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Application Programming (IAP).
In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD
enabling the entire device (Flash memories, PLD,
configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU
participation, which means the PSD can be programmed anytime, even when completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
First time programming. How do I get firmware
into the Flash memory the very first time? JTAG is
the answer. Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devices. How do I maintain an accurate count of preprogrammed Flash memory and PLD devices
based on customer demand? How many and what
version? JTAG is the answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the customer. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets? JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
In-Application Programming (IAP)
Two independent Flash memory arrays are included so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the field are possible
over any communications channel (CAN, Ethernet, UART, J1850, etc.) using this unique architecture. Designers are relieved of these problems:
Simultaneous READ and WRITE to Flash memory. How can the MCU program the same memory from which it is executing code? It cannot. The
PSD allows the MCU to operate the two Flash
memory blocks concurrently, reading code from
one while erasing and programming the other during IAP.
Complex memory mapping. How can I map
these two memories efficiently? A programmable
Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extremely high address resolution.
As an option, the secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-in page register breaks the
MCU address limit.
Separate Program and Data space. How can I
write to Flash memory while it resides in Program
space during field firmware updates? My 80C51
will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP,
then back to Program space when complete.
PSDsoft
PSDsoft, a software development tool from ST,
guides you through the design process step-bystep making it possible to complete an embedded
MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft takes you through the
remainder of the design with point and click entry,
covering PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map
definition, ANSI-C code generation for your MCU,
and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft:
FlashLINK (JTAG) and PSDpro.
9/102
PSD835G2
61 PB0
62 PB1
63 PB2
64 PB3
65 PB4
66 PB5
67 PB6
69 VCC
68 PB7
70 GND
71 PE0
72 PE1
73 PE2
74 PE3
75 PE4
76 PE5
77 PE6
78 PE7
79 PD0
80 PD1
Figure 2. TQFP80 Connections
PD2 1
60 CNTL1
PD3 2
59 CNTL0
AD0 3
58 PA7
AD1 4
57 PA6
AD2 5
56 PA5
AD3 6
55 PA4
AD4 7
54 PA3
GND 8
53 PA2
VCC 9
AD5 10
52 PA1
AD6 11
50 GND
AD7 12
49 GND
AD8 13
48 PC7
AD9 14
47 PC6
AD10 15
46 PC5
AD11 16
45 PC4
AD12 17
44 PC3
AD13 18
43 PC2
AD14 19
42 PC1
AD15 20
41 PC0
CNTL2 40
RESET 39
PF7 38
PF6 37
PF5 36
PF4 35
PF3 34
PF2 33
PF1 32
PF0 31
GND 30
VCC 29
PG7 28
PG6 27
PG5 26
PG4 25
PG3 24
PG2 23
PG1 22
PG0 21
51 PA0
AI04943
10/102
PSD835G2
Table 1. Pin Description
Pin
Name
Pin
Type
Description
This is the lower Address/Data port. Connect your MCU address or address/data
bus according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with
the lower address bits, connect AD0-AD7 to this port.
ADIO0-7
3-710-12
I/O
If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks was selected. The addresses on this
port are passed to the PLDs.
This is the upper Address/Data port. Connect your MCU address or address/data
bus according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with
the lower address bits, connect A8-A15 to this port.
ADIO815
If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
13-20
I/O
If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
If you are using an 80C51XA in burst mode, connect A12-A19 to this port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks was selected. The addresses on this
port are passed to the PLDs.
The following control signals can be connected to this port, based on your MCU:
WR – active Low Write Strobe input.
CNTL0
59
I
R_W – active High READ/active Low WRITE input.
This port is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
The following control signals can be connected to this port, based on your MCU:
RD – active Low Read Strobe input.
E – E clock input.
DS – active Low Data Strobe input.
CNTL1
60
I
PSEN – connect PSEN to this port when it is being used as an active Low READ
signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is
actually the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
CNTL2
40
I
This port can be used to input the PSEN (Program Select Enable) signal from any
MCU that uses this signal for code exclusively. If your MCU does not output a
Program Select Enable signal, this port can be used as a generic input. This port is
connected to the PLDs as input.
11/102
PSD835G2
Pin
Name
Pin
Type
Reset
39
I
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
58
57
56
55
54
53
52
51
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
68
67
66
65
64
63
62
61
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
48
47
46
45
44
43
42
41
Description
Active Low input. Resets I/O Ports, PLD macrocells and some of the Configuration
Registers and JTAG registers. Must be Low at Power-up. Reset also aborts the
Flash programming/erase cycle that is in progress.
These pins make up Port A. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
I/O CMOS
or Open
Drain
CPLD macrocell (McellA0-7) outputs.
Inputs to the PLDs.
Latched, transparent or registered PLD input.
These pins make up Port B. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
I/O CMOS
or Open
Drain
CPLD macrocell (McellB0-7) output.
Inputs to the PLDs.
Latched, transparent or registered PLD input.
I/O CMOS
or Open
Drain
These pins make up Port C. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
External Chip Select (ECS0-7) output.
Latched, transparent or registered PLD input.
PD0 pin of Port D. This port pin can be configured to have the following functions:
ALE/AS input latches addresses on ADIO0-ADIO15 pins.
PD0
79
I/O CMOS
or Open
Drain
AS input latches addresses on ADIO0-ADIO15 pins on the rising edge.
Input to the PLDs.
Transparent PLD input.
PD1 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
PD1
80
I/O CMOS
or Open
Drain
Input to the PLDs.
CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter,
and the CPLD AND Array.
PD2 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
PD2
12/102
1
I/O CMOS
or Open
Drain
Input to the PLDs.
PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory
and I/O. When High, the PSD memory blocks are disabled to conserve power. The
trailing edge of CSI can be used to get the PSD out of power-down mode.
PSD835G2
Pin
Name
Pin
Type
PD3
2
I/O CMOS
or Open
Drain
PE0
71
I/O CMOS
or Open
Drain
Description
PD3 pin of Port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Input to the PLDs.
PE0 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TMS input for JTAG/ISP interface.
PE1
72
I/O CMOS
or Open
Drain
PE1 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TCK input for JTAG/ISP interface (Schmidt Trigger).
PE2
73
I/O CMOS
or Open
Drain
PE2 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TDI input for JTAG/ISP interface.
PE3
74
I/O CMOS
or Open
Drain
PE3 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TDO input for JTAG/ISP interface.
PE4 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
PE4
75
I/O CMOS
or Open
Drain
Latched address output.
TSTAT input for the ISP interface.
Ready/Busy for in-circuit Parallel Programming.
PE5
76
I/O CMOS
or Open
Drain
PE5 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
TERR active Low input for ISP interface.
PE6
77
I/O CMOS
or Open
Drain
PE6 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address output.
VSTBY SRAM standby voltage input for battery backup SRAM.
13/102
PSD835G2
Pin
Name
Pin
Type
Description
PE7 pin of Port E. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
PE7
78
I/O CMOS
or Open
Drain
Latched address output.
VBATON battery backup indicator output. Goes High when power is drawn from an
external battery.
PF0 through PF7 pins of Port F. This port pins can be configured to have the
following functions:
MCU I/O – write to or read from a standard output or input port.
PF0-PF7
31-38
I/O CMOS
or Open
Drain
Input to the PLDs.
Latched address outputs.
As address A0-A3 inputs in 80C51XA mode.
As data bus port (D07) in non-multiplexed bus configuration.
PG0PG7
8, 30,
49, 50,
70
I/O CMOS
or Open
Drain
PG0 through PG7 pins of Port G. This port pins can be configured to have the
following functions:
MCU I/O – write to or read from a standard output or input port.
Latched address outputs.
VCC
9, 29,
69
Supply Voltage
GND
8, 30,
49, 50,
70
Ground pins
14/102
PG0 – PG7
PF0 –PF7
AD0 – AD15
CNTL0,
CNTL1,
CNTL2
CLKIN
(PD1)
PORT G
PROG.
PORT
PORT F
PROG.
PORT
ADIO
PORT
PROG.
MCU BUS
INTRF.
PLD
INPUT
BUS
CLKIN
82
CSIOP
GLOBAL
CONFIG. &
SECURITY
CLKIN
64 KBIT BATTERY
BACKUP SRAM
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
8 SECTORS
4 MBIT PRIMARY
FLASH MEMORY
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
PORT F
JTAG
SERIAL
CHANNEL
PORT A ,B & C
24 INPUT MACROCELLS
PORT A & B
16 OUTPUT MACROCELLS
8 EXT CS TO PORT C OR F
RUNTIME CONTROL
AND I/O REGISTERS
PERIP I/O MODE SELECTS
SRAM SELECT
SECTOR
SELECTS
FLASH ISP CPLD
(CPLD)
FLASH DECODE
PLD (DPLD)
SECTOR
SELECTS
EMBEDDED
ALGORITHM
MACROCELL FEEDBACK OR PORT INPUT
82
PAGE
REGISTER
ADDRESS/DATA/CONTROL BUS
PORT
E
PROG.
PORT
PORT
D
PROG.
PORT
PORT
C
PROG.
PORT
PORT
B
PROG.
PORT
PORT
A
PROG.
PORT
POWER
MANGMT
UNIT
PE0 – PE7
PD0 – PD2
PC0 – PC7
PB0 – PB7
PA0 – PA7
VSTDBY
(PE6 )
PSD835G2
Figure 3. PSD Block Diagram
AI05793b
15/102
PSD835G2
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 3., page 15 shows the architecture
of the PSD device family. The functions of each
block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discussion can be found in the section entitled Memory
Blocks, page 24. The 4 Mbit (512K x 8) Flash
memory is the primary memory of the PSD. It is divided into 8 equally-sized sectors that are individually selectable.
The 256 Kbit (32K x 8) secondary Flash memory
is divided into 4 equally-sized sectors. Each sector
is individually selectable.
The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Standby (VSTBY, PC2), data is retained in
the event of power failure.
Each sector of memory can be located in a different address space as defined by the user. The access times for all memory types includes the
address latching and DPLD decoding time.
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or internal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different memory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 2, each optimized for a different function.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD internal memory and registers. The CPLD can implement user-defined logic functions. The DPLD has
combinatorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 8 combinatorial outputs.
The PSD also has 24 Input Macrocells (IMC) that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
16/102
and are differentiated by their output destinations,
number of product terms, and macrocells.
The PLDs consume minimal power by using Power-Management design techniques. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propagation time when invoking the power management
features.
I/O Ports
The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each I/O pin
can be individually configured for different functions. Ports can be configured as standard MCU I/
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data buses.
The JTAG pins can be enabled on Port E for InSystem Programming (ISP). Ports F and G can
also be configured as data ports for a non-multiplexed bus.
Ports A and B can also be configured as a data
port for a non-multiplexed bus.
MCU Bus Interface
PSD interfaces easily with most 8-bit MCUs that
have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU’s control signals, which are also
used as inputs to the PLDs. For examples, please
see MCU Bus Interface Examples, page 52.
Table 2. PLD I/O
Inputs
Outputs
Product
Terms
Decode PLD (DPLD)
82
17
43
Complex PLD (CPLD)
82
24
150
Name
Table 3. JTAG SIgnals on Port E
Port E Pins
JTAG Signal
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
PSD835G2
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial interface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port E. Table 3., page 16 indicates the JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be programmed or erased without the use of the MCU.
In-Application re-Programming (IAP)
The primary Flash memory can also be programmed in-system by the MCU executing the
programming algorithms out of the secondary
memory, or SRAM. Since this is a sizable separate
block, the application can also continue to operate.
The secondary memory can be programmed the
same way by executing out of the primary Flash
memory. The PLD or other PSD Configuration
blocks can be programmed through the JTAG port
or a device programmer. Table 4 indicates which
programming methods can program different functional blocks of the PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be
reset to ’0’ and the CPLD latches its outputs and
goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see POWER
MANAGEMENT, page 70 for more details.
Table 4. Methods of Programming Different Functional Blocks of the PSD
Functional Block
JTAG/ISP
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary Flash Memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
17/102
PSD835G2
DEVELOPMENT SYSTEM
The PSD family is supported by PSDsoft, a Windows-based (95, 98, NT) software development
tool. A PSD design is quickly and easily produced
in a point-and-click environment. The designer
does not need to enter Hardware Description Language (HDL) equations, unless desired, to define
PSD pin functions and memory map information.
The general design flow is shown in Figure 4. PSDsoft is available from our web site (the address is
given on the back page of this data sheet) or other
distribution channels.
PSDsoft directly supports two low cost device programmers form ST: PSDpro and FlashLINK
(JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit
card. The PSD is also supported by third party device programmers. See our web site for the current
list.
Figure 4. PSDsoft Development Tool
Choose MCU and PSD
Automatically Configures MCU
bus interface and other PSD
attributes.
Define PSD Pin and
Node Functions
Point-and-click definition of PSD
pin functions, internal nodes and
MCU system memory map
Define General Purpose
Logic in CPLD
C Code Generation
Point-and-click definition of
combinatorial and registered
logic in CPLD. Access to HDL is
available if needed.
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
Merge MCU Firmware
with PSD Configuration
A composite object file is created
containing MCU firmware and
PSD configuration
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
ST PSD Programmer
PSDPro, or
FlashLINK (JTAG)
*.OBJ
FILE AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG/ISP)
AI04918b
18/102
PSD835G2
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table 5 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 Bytes of address that is
allocated by the user to the internal PSD registers.
Table 5 provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 5. Register Address Offset
Other
Register Name
Port
A
Port
B
Port
C
Port
D
Port
E
Port
F
Port
G
Data In
00
01
10
11
30
40
41
Reads Port pin as input, MCU I/
O input mode
32
42
43
Selects mode between MCU I/O
or Address Out
Control
1
Description
Data Out
04
05
14
15
34
44
45
Stores data for output to Port
pins, MCU I/O output mode
Direction
06
07
14
15
36
46
47
Configures Port pin as input or
output
Drive Select
08
09
18
19
38
48
49
Configures Port pins as either
CMOS or Open Drain on some
pins, while selecting high slew
rate on other pins.
Input Macrocell
0A
0B
Enable Out
Output
Macrocells A
0C
Mask Macrocells
B
1C
Reads Input Macrocells
1B
Reads the status of the output
enable to the I/O Port driver
4C
READ – reads output of
macrocells A
WRITE – loads macrocell flipflops
20
Output
Macrocells B
Mask Macrocells
A
0D
1A
READ – reads output of
macrocells B
WRITE – loads macrocell flipflops
21
Blocks writing to the Output
Macrocells A
22
Blocks writing to the Output
Macrocells B
23
Primary Flash
Protection
C0
Read only – Primary Flash
Sector Protection
Secondary Flash
memory
Protection
C2
Read only – PSD Security and
Secondary Flash memory
Sector Protection
JTAG Enable
C7
Enables JTAG Port
PMMR0
B0
Power Management Register 0
PMMR2
B4
Power Management Register 2
Page
E0
Page Register
VM
E2
Places PSD memory areas in
Program and/or Data space on
an individual basis.
Memory_ID0
F0
Read only – Primary Flash
memory and SRAM size
Memory_ID1
F1
Read only – Secondary Flash
memory type and size
Note: 1. Other registers that are not part of the I/O ports.
19/102
PSD835G2
REGISTER BIT DEFINITION
All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can
be found in the following sections.
Table 6. Data-In Registers – Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions (Read only registers):
Read Port pin status when Port is in MCU I/O input mode.
Table 7. Data-Out Registers – Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 8. Direction Registers – Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured in Input mode (default).
Port pin 1 = Port pin is configured in Output mode.
Table 9. Control Registers – Ports E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured in MCU I/O mode (default).
Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 10. Drive Registers – Ports A, B, D, E, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured for Open Drain output driver.
Table 11. Drive Registers – Ports C, F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured in Slew Rate mode.
20/102
PSD835G2
Table 12. Enable-Out Registers – Ports A, B, C, F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions (Read only registers):
Port pin 0 = Port pin is in tri-state driver (default).
Port pin 1 = Port pin is enabled.
Table 13. Input Macrocells – Ports A, B, C
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
Note: Bit Definitions (Read only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 14. Output Macrocells A Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Note: Bit Definitions:
Write Register: Load MCellA7-MCellA0 with '0' or '1.'
Read Register: Read MCellA7-MCellA0 output status.
Table 15. Output Macrocells B Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Note: Bit Definitions:
Write Register: Load MCellB7-MCellB0 with '0' or '1.'
Read Register: Read MCellB7-MCellB0 output status.
Table 16. Mask Macrocells A Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Note: Bit Definitions:
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 17. Mask Macrocells B Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Note: Bit Definitions:
McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 18. Flash Memory Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Note: Bit Definitions (Read only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
21/102
PSD835G2
Table 19. Flash Boot Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
not used
not used
not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Note: Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 20. JTAG Enable Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
not used
not used
not used
not used
not used
JTAGEnable
Note: Bit Definitions:
JTAG_Enable 1 = JTAG Port is enabled.
JTAG_Enable 0 = JTAG Port is disabled.
Table 21. Page Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGR 7
PGR 6
PGR 5
PGR 4
PGR 3
PGR 2
PGR 1
PGR 0
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=00.
Table 22. PMMR0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
not used
(set to ’0’)
PLD
MCells CLK
PLD
Array CLK
PLD
Turbo
not used
(set to ’0’)
APD
Enable
not used
(set to ’0’)
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.
2. Bit Definitions:
APD Enable0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 23. PMMR2 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
PLD
Array WRH
PLD
Array ALE
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to ’0’)
PLD Array
Addr
Note: Bit Definitions:
PLD Array Addr
0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
22/102
PSD835G2
Table 24. VM Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Peripheral
mode
not used
(set to ’0’)
not used
(set to ’0’)
FL_data
Boot_data
FL_code
Boot_code
SR_code
Note: 1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset.
Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode.
2. Bit Definitions:
SR_code0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_code0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
Table 25. Memory_ID0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
Note: Bit Definitions:
F_size[3:0]
S_size[3:0]
4h = Primary Flash memory size is 4 Mbit
5h = Primary Flash memory size is 8Mbit
0h = There is no SRAM
1h = SRAM size is 16 Kbit
3h = SRAM size is 64 Kbit
Table 26. Memory_ID1 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
not used
(set to ’0’)
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
Note: Bit Definitions:
B_size[3:0]
B_type[1:0]
0h = There is no Secondary NVM
2h = Secondary NVM size is 256 Kbit
0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
23/102
PSD835G2
DETAILED OPERATION
As shown in Figure 3., page 15, the PSD consists
of six major types of functional blocks:
■
Memory Blocks
■
PLD Blocks
■
MCU Bus Interface
■
I/O Ports
■
Power Management Unit (PMU)
■
JTAG/ISP Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks:
– Primary Flash memory
– Secondary Flash memory
– SRAM
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft.
Table 27. Memory Block Size and Organization
Primary Flash Memory
Secondary Flash Memory
SRAM
Sector
Number
Sector Size
(Bytes)
Sector Select
Signal
Sector Size
(Bytes)
Sector Select
Signal
SRAM Size
(Bytes)
SRAM Select
Signal
0
64K
FS0
8K
CSBOOT0
16K
RS0
1
64K
FS1
8K
CSBOOT1
2
64K
FS2
8K
CSBOOT2
3
64K
FS3
8K
CSBOOT3
4
64K
FS4
5
64K
FS5
6
64K
FS6
7
64K
FS7
Total
512K
8 Sectors
32K
4 Sectors
24/102
16K
PSD835G2
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four equal sectors of eight KBytes
each. Each sector of either memory block can be
separately protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sector basis and programmed Word-by-Word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and then resumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PE4).
This pin is set up using PSDsoft.
Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see PLDs, page 38).
Each of the eight sectors of the primary Flash
memory has a Select signal (FS0-FS7) which can
contain up to three product terms. Each of the four
sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three
product terms for each Select signal allows a given
sector to be mapped in different areas of system
memory. When using an MCU with separate Program and Data space, these flexible Select signals
allow dynamic re-mapping of sectors from one
memory space to the other before and after IAP.
Upper and Lower Block IN MAIN FLASH
SECTOR
The PSD835G2’s main Flash memory has eight
64-KByte sectors. The 64-KByte sector size may
cause some difficulty in code mapping for an 8-bit
MCU with only 64-KByte address space. To resolve this mapping issue, the PSD835G2 provides
additional logic (see Figure 6., page 26) for the
user to split the 8 sectors such that each sector
has a lower and upper 32-KByte block, and the
two blocks can reside in different pages but in the
same address range.
If your design works with 64KB sectors, you don’t
need to configure this logic. If the design requires
32KB blocks in each sector, you need to define a
“FA15” PLD equation in PSDsoft as the A15 address input to the main Flash module. FA15 consists of 3 product terms and will control whether
the MCU is accessing the lower or upper 32KB in
the selected sector. Figure 4 shows an example
for Flash sector chip select FS0. A typical equation
is FA15 = pgr4 of the Page Register. When pgr4 is
0 (page 00), the lower 32KB is selected. When
pgr4 is switched to ’1’ by the user, the upper 32KB
is selected. PSDsoft will automatically generate
the PLD equations shown, based on your point
and click selections.
If no FA15 equation is defined in PSDsoft, the A15
that comes from the MCU address bus will be routed as input to the primary Flash memory instead of
FA15. The FA15 equation has no impact on the
Sector Erase operation.
Note: FA15 affects all eight sectors of the primary
Flash memory simultaneously. You cannot direct
FA15 to a particular Flash sector only.
Figure 5. Example for Flash Sector Chip Select FS0
page = [pgr7... pgr0]; “Page Register output
“Sector Chip Select Equation
FS0 = ((0000h <= address <= 7FFFh) & page = 00h) #
“select first 32KB block
((0000h <= address <= 7FFFh) & page = 10h);
“select second 32KB block
FA15 = pgr4;
“as address A15 input to the primary Flash memory
ai07652
25/102
PSD835G2
Figure 6. Selecting the Upper or Lower Block in a Primary Flash Memory Sector
FLASH MEMORY CHIP SELECT PINS FS0-FS7
DPLD
ARRAY
FA15
MUX
ADDR A15
PRIMARY
FLASH
MEMORY
SECTOR
A15
NVM CONTROL BIT(1)
A14-A0
ai07653
Ready/Busy (PE4)
This signal can be used to output the Ready/Busy
status of the PSD. The output on Ready/Busy
(PE4) is a ’0’ (Busy) when Flash memory blocks
are being written to, or when the Flash memory
block is being erased. The output is a '1' (Ready)
when no WRITE or Erase cycle is in progress.
Memory Operation
The primary Flash memory and secondary Flash
memory are addressed through the MCU Bus Interface. The MCU can access these memories in
one of two ways:
– The MCU can execute a typical bus WRITE or
READ operation just as it would if accessing a
RAM or ROM device using standard bus
cycles.
– The MCU can execute a specific instruction
that consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table
Table 28., page 27.
26/102
Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM device. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a READ operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device information (sector protect status and ID).
PSD835G2
Table 28. Instructions
Instruction
FS0-FS7 or
CSBOOT0CSBOOT3
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Read(5)
1
“Read” RA
@ RD
Read Primary
Flash ID(6,13)
1
AAh@ 555h
55h@
AAAh
90h@
555h
Read identifier
@X01h
Read Sector
Protection(6,8,13)
1
AAh@ 555h
55h@
AAAh
90h@
555h
Read identifier
00h or 01h
@X02h
Program a Flash
Byte(13)
1
AAh@ 555h
55h@
AAAh
A0h@
555h
PD@ PA
Flash Sector
Erase(7)
1
AAh@ 555h
55h@
AAAh
80h@
555h
AAh@ 555h
55h@
AAAh
30h@
SA
Flash Bulk Erase
1
AAh@ 555h
55h@
AAAh
80h@
555h
AAh@ 555h
55h@
AAAh
10h@
555h
Suspend Sector
Erase(11)
1
B0h@
XXXh
Resume Sector
Erase(12)
1
30h@ XXXh
Reset(6)
1
F0h@
any address
Unlock Bypass
1
AAh@ 555h
55h@
AAAh
20h@
555h
Unlock Bypass
Program(9)
1
A0h@
XXXh
PD@ PA
Unlock Bypass
Reset(10)
1
90h@ XXXh
00h@
XXXh
Cycle 7
30h(7)@
next SA
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal:
X = Don’t Care.
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select pins (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector or
whole memory to be erased, or verified, must be Active (High).
3. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft.
4. Only address Bits A11-A0 are used in instruction decoding. A15-A12 (or A16-A12) are don’t care.
5. No Unlock or instruction cycles are required when the device is in the READ mode
6. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High.
7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
27/102
PSD835G2
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received Byte is sequentially decoded by the PSD and not executed as a standard
WRITE operation. The instruction is executed
when the correct number of Bytes is properly received and the time between two consecutive
Bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations.
The instruction must be followed exactly. Any invalid combination of instruction Bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 28., page 27:
Flash memory:
■
Erase memory by chip or sector
■
Suspend or resume sector erase
■
Program a Byte
■
Reset to READ mode
■
Read primary Flash Identifier value
■
Read Sector Protection Status
■
Bypass
These instructions are detailed in Table 28. For efficient decoding of the instructions, the first two
Bytes of an instruction are the coded cycles and
are followed by an instruction Byte or a confirmation Byte. The coded cycles consist in writing the
data AAh to address X555h during the first cycle
and data 55h to address XAAAh during the second
cycle unless the Bypass Instruction feature is
used). Address signals A15-A12 are Don’t Care
during the instruction WRITE cycles. However, the
appropriate
Sector
Select
(FS0-FS7
or
CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is
selected if any one of Sector Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0CSBOOT3) is High.
28/102
Power-up Mode
The PSD internal logic is reset upon Power-up to
the READ mode. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must be held Low, and
Write Strobe (WR, CNTL0) High, during Power-up
for maximum security of the data contents and to
remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
WRITE cycle initiation is locked when VCC is below VLKO.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.
Read Memory Contents
Primary Flash memory and secondary Flash
memory are placed in the READ mode after Power-up, chip reset, or a Reset Flash instruction (see
Table 28). The MCU can read the memory contents of the primary Flash memory or the secondary Flash memory by using READ operations any
time the READ operation is not part of an instruction.
Read Primary Flash Identifier
The primary Flash memory identifier is read with
an instruction composed of 4 operations: 3 specific
WRITE operations and a READ operation (see Table 28., page 27). The identifier for the device is
E8h.
Read Memory Sector Protection Status
The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ
operation (see Table 28). The READ operation
produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash memory) can also be read by the MCU accessing the
Flash Protection and Flash Boot Protection registers in PSD I/O space. See Flash Memory Sector
Protect, page 34 for register definitions.
PSD835G2
Read the Erase/Program Status Bits
The PSD provides several status bits to be used
by the MCU to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the MCU spends performing these tasks and are defined in Table 29.
The status bits can be read as many times as
needed.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See PROGRAMMING
FLASH MEMORY, page 31 for details.
Table 29. Status Bit
Functional Block
Flash Memory
FS0-FS7/CSBOOT0CSBOOT3
VIH
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Data
Polling
Toggle
Flag
Error
Flag
X
Erase
Timeout
X
X
X
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'
2. DQ7-DQ0 represent the Data Bus Bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
29/102
PSD835G2
Data Polling Flag (DQ7)
When erasing or programming in Flash memory,
the Data Polling Flag Bit (DQ7) outputs the complement of the bit being entered for programming/
writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true
logic value is read on the Data Polling Flag Bit
(DQ7, in a READ operation).
– Data Polling is effective after the fourth WRITE
pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.
– During an Erase cycle, the Data Polling Flag
Bit (DQ7) outputs a '0.' After completion of the
cycle, the Data Polling Flag Bit (DQ7) outputs
the last bit programmed (it is a ’1’ after
erasing).
– If the Byte to be programmed is in a protected
Flash memory sector, the instruction is
ignored.
– If all the Flash memory sectors to be erased
are protected, the Data Polling Flag Bit (DQ7)
is reset to ’0’ for about 100µs, and then returns
to the previous addressed byte. No erasure is
performed.
Toggle Flag (DQ6)
The PSD offers another way for determining when
the Flash memory Program cycle is completed.
During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0-CSBOOT3 is true,
the Toggle Flag Bit (DQ6) toggles from '0' to '1' and
'1' to ’0’ on subsequent attempts to read any Byte
of the memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the addressed memory Byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is finished when two successive READs
yield the same output data.
30/102
–
The Toggle Flag Bit (DQ6) is effective after the
fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an Erase
instruction).
– If the Byte to be programmed belongs to a
protected Flash memory sector, the
instruction is ignored.
– If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag Bit
(DQ6) toggles to ’0’ for about 100µs and then
returns to the previous addressed Byte.
Error Flag (DQ5)
During a normal Program or Erase cycle, the Error
Flag Bit (DQ5) is set to '0.' This bit is set to ’1’ when
there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Error Flag Bit (DQ5) indicates the attempt to program
a Flash memory bit from the programmed state, 0,
to the erased state, 1, which is not valid. The Error
Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a Byte.
In case of an error in a Flash memory Sector Erase
or Byte Program cycle, the Flash memory sector in
which the error occurred or to which the programmed Byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag Bit (DQ5) is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3)
The Erase Time-out Flag Bit (DQ3) reflects the
time-out period allowed between two consecutive
Sector Erase instructions. The Erase Time-out
Flag Bit (DQ3) is reset to ’0’ after a Sector Erase
cycle for a time period of 100µs + 20% unless an
additional Sector Erase instruction is decoded. After this time period, or when the additional Sector
Erase instruction is decoded, the Erase Time-out
Flag Bit (DQ3) is set to '1.'
PSD835G2
PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all
at once or by-sector. A Flash memory sector is
erased to all 1s (FFh), and is programmed by setting selected bits to '0.' Although Flash memory is
erased by-sector, it is programmed Word-byWord.
The primary and secondary Flash memories require the MCU to send an instruction to program a
Word or to erase sectors (see Table 28., page 27).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check the status bits for
completion. The embedded algorithms that are invoked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or the Ready/Busy (PE4) output pin.
Data Polling
Polling on the Data Polling Flag Bit (DQ7) is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 7
shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the Word to be
programmed in Flash memory to check status.
The Data Polling Flag Bit (DQ7) of this location becomes the complement of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, comparing the Data Polling Flag
Bit (DQ7) and monitoring the Error Flag Bit (DQ5).
When the Data Polling Flag Bit (DQ7) matches b7
of the original data, and the Error Flag Bit (DQ5)
remains '0,' the embedded algorithm is complete.
If the Error Flag Bit (DQ5) is '1,' the MCU should
test the Data Polling Flag Bit (DQ7) again since
the Data Polling Flag Bit (DQ7) may have changed
simultaneously with the Error Flag Bit (DQ5, see
Figure 7).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the Byte or if the MCU attempted to program a ’1’ to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded programming algorithm has completed, to compare the
Byte that was written to the Flash memory with the
Byte that was intended to be written.
When using the Data Polling method after an
Erase cycle, Figure 7 still applies. However, the
Data Polling Flag Bit (DQ7) is '0' until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle; a
'0' indicates no error. The MCU can read any location within the sector being erased to get the Data
Polling Flag Bit (DQ7) and the Error Flag Bit
(DQ5).
PSDsoft generates ANSI C code functions which
implement these Data Polling algorithms.
Figure 7. Data Polling Flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
DQ7
=
DATA
YES
NO
FAIL
PASS
AI01369B
31/102
PSD835G2
Data Toggle
Checking the Toggle Flag Bit (DQ6) is a method of
determining whether a Program or Erase cycle is
in progress or has completed. Figure 8 shows the
Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be programmed in Flash memory to check status. The
Toggle Flag Bit (DQ6) of this location toggles each
time the MCU reads this location until the embedded algorithm is complete. The MCU continues to
read this location, checking the Toggle Flag Bit
(DQ6) and monitoring the Error Flag Bit (DQ5).
When the Toggle Flag Bit (DQ6) stops toggling
(two consecutive READs yield the same value),
and the Error Flag Bit (DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag Bit
(DQ5) is 1,' the MCU should test the Toggle Flag
Bit (DQ6) again, since the Toggle Flag Bit (DQ6)
may have changed simultaneously with the Error
Flag Bit (DQ5, see Figure 8).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU attempted to program a ’1’ to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded programming algorithm has completed, to compare the
Byte that was written to Flash memory with the
Byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 8 still applies. the Toggle Flag
Bit (DQ6) toggles until the Erase cycle is complete.
A 1 on the Error Flag Bit (DQ5) indicates a time-out
condition on the Erase cycle; a ’0’ indicates no error. The MCU can read any location within the sector being erased to get the Toggle Flag Bit (DQ6)
and the Error Flag Bit (DQ5).
PSDsoft generates ANSI C code functions which
implement these Data Toggling algorithms.
Unlock Bypass
The Unlock Bypass instructions allow the system
to program bytes to the Flash memories faster
than using the standard Program instruction. The
Unlock Bypass mode is entered by first initiating
two Unlock cycles. This is followed by a third
WRITE cycle containing the Unlock Bypass code,
20h (as shown in Table 28., page 27).
32/102
The Flash memory then enters the Unlock Bypass
mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The second cycle contains the program address and data.
Additional data is programmed in the same manner. These instructions dispense with the initial
two Unlock cycles required in the standard Program instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data
90h; the second cycle, the data 00h. Addresses
are Don’t Care for both cycles. The Flash memory
then returns to READ mode.
Figure 8. Data Toggle Flowchart
START
READ
DQ5 & DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI01370B
PSD835G2
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE
operations followed by a READ operation of the
status register, as described in Table
28., page 27. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and
the device is reset to the Read Flash memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in “PROGRAMMING
FLASH MEMORY, page 31. The Error Flag Bit
(DQ5) returns a ’1’ if there has been an Erase Failure (maximum number of Erase cycles has been
executed).
It is not necessary to program the memory with
00h because the PSD automatically does this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase
The Sector Erase instruction uses six WRITE operations, as described in Table 28., page 27. Additional Flash Sector Erase codes and Flash
memory sector addresses can be written subsequently to erase other Flash memory sectors in
parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than
the time-out period of about 100µs. The input of a
new Sector Erase code restarts the time-out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,'
the Sector Erase instruction has been received
and the time-out period is counting. If the Erase
Time-out Flag Bit (DQ3) is '1,' the time-out period
has expired and the PSD is busy erasing the Flash
memory sector(s). Before and during Erase timeout, any instruction other than Suspend Sector
Erase and Resume Sector Erase instructions
abort the cycle that is currently in progress, and reset the device to READ mode. It is not necessary
to program the Flash memory sector with 00h as
the PSD does this automatically before erasing
(Byte=FFh).
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in PROGRAMMING FLASH
MEMORY, page 31.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then resumed.
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even
address when an appropriate Sector Select (FS0FS7 or CSBOOT0-CSBOOT3) is High. (See Table
28., page 27). This allows reading of data from another Flash memory sector after the Erase cycle
has been suspended. Suspend Sector Erase is
accepted only during an Erase cycle and defaults
to READ mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in
addition to suspending the Erase cycle, terminates
the time out period.
The Toggle Flag Bit (DQ6) stops toggling when the
PSD internal logic is suspended. The status of this
bit must be monitored at an address within the
Flash memory sector being erased. The Toggle
Flag Bit (DQ6) stops toggling between 0.1µs and
15µs after the Suspend Sector Erase instruction
has been executed. The PSD is then automatically
set to READ mode.
If a Suspend Sector Erase instruction was executed, the following rules apply:
– Attempting to read from a Flash memory sector
that was being erased outputs invalid data.
– Reading from a Flash sector that was not being
erased is valid.
– The Flash memory cannot be programmed, and
only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation
and is allowed).
– If a Reset Flash instruction is received, data in
the Flash memory sector that was being erased
is invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed
with this instruction. The Resume Sector Erase instruction consists in writing 030h to any even address while an appropriate Sector Select (FS0FS7 or CSBOOT0-CSBOOT3) is High. (See Table
28., page 27.)
33/102
PSD835G2
SPECIFIC FEATURES
Flash Memory Sector Protect
Each primary and secondary Flash memory sector
can be separately protected against Program and
Erase cycles. Sector Protection provides additional data security because it disables all Program or
Erase cycles. This mode can be activated through
the JTAG/ISP Port or a Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft program. This automatically
protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be
unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
The retention of the Protection status is thus ensured.
The sector protection status can be read by the
MCU through the primary and secondary Flash
memory protection registers (in the CSIOP block).
See Table 18., page 21 and Table 19., page 22.
Reset Flash
The Reset Flash instruction consists of one
WRITE cycle (see Table 28., page 27). It can also
be optionally preceded by the standard two
WRITE decoding cycles (writing AAh to AAAh and
55h to 554h).
It must be executed after:
– Reading the Flash Protection Status or Flash ID
using the Flash instruction.
– An Error condition has occurred (and the device
has set the Error Flag Bit (DQ5) to ’1’) during a
Flash memory Program or Erase cycle.
The Reset Flash instruction puts the Flash memory back into normal READ mode immediately. If an
Error condition has occurred (and the device has
set the Error Flag Bit (DQ5) to ’1’) the Flash memory is put back into normal READ mode within
25 µs of the Reset Flash instruction having been
issued. The Reset Flash instruction is ignored
when it is issued during a Program or Bulk Erase
cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle,
and returns the Flash memory to the normal READ
mode within 25µs.
Reset (RESET) Signal
A pulse on Reset (RESET) aborts any cycle that is
in progress, and resets the Flash memory to the
READ mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up
to 25 µs to return to the READ mode. It is recommended that the Reset (RESET) pulse (except for
the one described in Power-Up Reset, page 74)
be at least 25 µs so that the Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage Stand-by (VSTBY, PE6). If you have an
external battery connected to the PSD, the contents of the SRAM are retained in the event of a
power loss. The contents of the SRAM are retained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
34/102
PE7 can be configured as an output that indicates
when power is being drawn from the external battery. Battery-on Indicator (VBATON, PE7) is High
when the supply voltage falls below the battery
voltage and the battery on Voltage Stand-by
(VSTBY, PE6) is supplying power to the internal
SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PC2) and Battery-on Indicator (VBATON, PC4) are
all configured using PSDsoft Express Configuration.
The SRAM Select (RS0), VBATON and VSTBY are
all configured using PSDsoft.
PSD835G2
SECTOR SELECT AND SRAM SELECT
Sector Select (FS0-FS7 for primary Flash memory, CSBOOT0-CSBOOT3 for secondary Flash
memory) and SRAM Select (RS0) are all outputs
of the DPLD. They are setup using PSDsoft. The
following rules apply to the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must not be
larger than the physical sector size.
2. Any primary Flash memory sector must not be
mapped in the same memory space as
another primary Flash memory sector.
3. A secondary Flash memory sector must not be
mapped in the same memory space as
another secondary Flash memory sector.
4. SRAM and I/O spaces must not overlap.
5. A secondary Flash memory sector may
overlap a primary Flash memory sector. In
case of overlap, priority is given to the
secondary Flash memory sector.
6. SRAM and I/O spaces may overlap any other
memory sector. Priority is given to the SRAM
and I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not
be valid.
Figure 9 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level one has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 80C51 and compatible family of MCUs have
separate address spaces for Program memory
(selected using Program Select Enable (PSEN,
CNTL2)) and Data memory (selected using Read
Strobe (RD, CNTL1)). Any of the memories within
the PSD can reside in either space or both spaces.
This is controlled through manipulation of the VM
register that resides in the CSIOP space.
The VM register is set using PSDsoft to have an
initial value. It can subsequently be changed by
the MCU so that memory mapping can be
changed on-the-fly.
For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft to configure
it for Boot-up and having the MCU change it when
desired.
Table 24., page 23 describes the VM Register.
Figure 9. Priority Level of Memory and I/O
Components
Highest Priority
Level 1
SRAM, I /O, or
Peripheral I /O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Memory
Lowest Priority
AI02867D
35/102
PSD835G2
Configuration Modes for MCUs with Separate
Program and Data Spaces
Separate Space Modes. Program space is separated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while Read Strobe (RD, CNTL1) is used to access
data from the secondary Flash memory, SRAM
and I/O Port blocks. This configuration requires
the VM register to be set to 0Ch (see Figure 10).
Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined
space, Bits b2 and b4 of the VM register are set to
’1’ (see Figure 11).
Figure 10. 8031 Memory Modules – Separate Space
DPLD
Primary
Flash
Memory
RS0
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
PSEN
RD
AI02869C
Figure 11. 8031 Memory Modules – Combined Space
DPLD
RD
RS0
Primary
Flash
Memory
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
AI02870C
36/102
PSD835G2
PAGE REGISTER
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Figure 12 shows the Page Register. The eight flipflops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
Figure 12. Page Register
RESET
D0
D0 - D7
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
PGR0
INTERNAL
SELECTS
AND LOGIC
PGR1
PGR2
PGR3
PGR4
DPLD
AND
CPLD
PGR5
PGR6
PGR7
R/W
PAGE
REGISTER
PLD
AI02871B
MEMORY ID REGISTERS
The 8-bit Read-only Memory Status Registers are
included in the CSIOP space. The user can determine the memory configuration of the PSD device
by reading the Memory ID0 and ID1 Registers.
The contents of the registers are defined in Table
25., page 23 and Table 26., page 23.
37/102
PSD835G2
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
in PSDsoft, the logic is programmed into the device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in Decode PLD
(DPLD), page 40
and
Complex
PLD
(CPLD), page 41. Figure 13 shows the configuration of the PLDs.
The DPLD performs address decoding for Select
signals for internal components, such as memory,
registers, and I/O ports.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state machines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
An Input Bus consisting of 82 signals is connected
to the PLDs. The signals are shown in Table 30.
The Turbo Bit in PSD
The PLDs in the PSD can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about
70ns. Resetting the Turbo Bit to ’0’ (Bit 3 of
PMMR0) automatically places the PLDs into
standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while
reducing power consumption. See POWER
MANAGEMENT, page 70, on how to set the Turbo Bit.
Additionally, five bits are available in PMMR2 to
block MCU control signals from entering the PLDs.
38/102
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Table 30. DPLD and CPLD Inputs
Input Name
Number
of
Signals
A15-A0
16
CNTL2-CNTL0
3
Reset
RST
1
Power-down
PDN
1
Port A Input
Macrocells
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC7-PC0
8
Port D Inputs
PD3-PD0
4
Port F Inputs
PF7-PF0
8
PGR7-PGR0
8
Macrocell A Feedback
MCELLA.FB7-FB0
8
Macrocell B Feedback
MCELLB.FB7-FB0
8
Ready/Busy
1
Input Source
MCU Address Bus1
MCU Control Signals
Page Register
Secondary Flash
memory Program
Status Bit
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
DATA
BUS
16
CPLD
PT
ALLOC.
OUTPUT MACROCELL FEEDBACK
1
2
1
1
4
8
24 INPUT MACROCELL
(PORT A,B,C)
INPUT MACROCELL & INPUT PORTS
PORT D AND F INPUTS
24
12
AI02872D
3
8
MCELLB
TO PORT B
EXTERNAL CHIP SELECTS
TO PORT C OR F
8
MCELLA
TO PORT A
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
JTAG SELECT
PERIPHERAL SELECTS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
PRIMARY FLASH MEMORY SELECTS
16 OUTPUT
MACROCELL
DIRECT MACROCELL INPUT TO MCU DATA BUS
82
73
DECODE PLD
PAGE
REGISTER
I/O PORTS
8
PSD835G2
Figure 13. PLD Diagram
39/102
PLD INPUT BUS
PSD835G2
Decode PLD (DPLD)
The DPLD, shown in Figure 14, is used for decoding the address for internal and external components. The DPLD can be used to generate the
following decode signals:
– 8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
– 4 Sector Select (CSBOOT0-CSBOOT3)
signals for the secondary Flash memory (three
product terms each)
–
–
–
–
1 internal SRAM Select (RS0) signal (three
product terms)
1 internal CSIOP Select (PSD Configuration
Register) signal
1 JTAG Select signal (enables JTAG/ISP on
Port E)
2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 14. DPLD Logic Array
(INPUTS)
I /O PORTS (PORT A,B,C,F)
3
CSBOOT 0
3
CSBOOT 1
3
CSBOOT 2
3
CSBOOT 3
3
(32)
3
MCELLA.FB7-FB0 (FEEDBACKS)
(8)
MCELLB.FB7-FB0 (FEEDBACKS)
(8)
PGR0 - PGR7
(8)
3
3
3
A15-A0(1,2)
(16)
3
PD3-PD0 (ALE,CLKIN,CSI)
(4)
PDN (APD OUTPUT)
(1)
3
3
FS0
FS1
FS2
FS3
FS4
8 PRIMARY FLASH
MEMORY SECTOR
SELECTS
FS5
FS6
FS7
CNTRL2-CNTRL0 (READ/WRITE CONTROL SIGNALS) (3)
RESET
(1)
RD_BSY
(1)
3
RS0
CSIOP
SRAM SELECT
I/O DECODER
SELECT
PSEL0
PSEL1
PERIPHERAL I/O
MODE SELECT
JTAGSEL
AI02873E
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
2. Additional address lines can be brought into PSD via Port A, B, C, D or F.
40/102
PSD835G2
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Select (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in Figure 13., page 39, the CPLD has
the following blocks:
■
24 Input Macrocells (IMC)
■
16 Output Macrocells (OMC)
■
Macrocell Allocator
Product Term Allocator
AND Array capable of generating up to 137
product terms
■
Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
■
■
41/102
PLD INPUT BUS
PLD INPUT BUS
CK
MACROCELL FEEDBACK
PT INPUT LATCH GATE/CLOCK
I/O PORT INPUT
Q
CL
D/T/JK FF
SELECT
D/T
PT OUTPUT ENABLE (OE)
PT CLEAR
CLOCK
SELECT
GLOBAL
CLOCK
PT
CLOCK
POLARITY
SELECT
MCU LOAD
MCU DATA IN
PR DI LD
PT PRESET
UP TO 10
PRODUCT TERMS
PRODUCT TERM
ALLOCATOR
COMB.
/REG
SELECT
MUX
CPLD MACROCELLS
MUX
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
MCU ADDRESS / DATA BUS
D
Q
Q
DIR
REG.
D
INPUT
SELECT
MUX
ALE/AS
G
Q D
Q D
INPUT MACROCELLS
WR
PDR
CPLD OUTPUT
WR
DATA
LATCHED
ADDRESS OUT
I/O PORTS
MUX
42/102
MUX
PRODUCT TERMS
FROM OTHER
MACROCELLS
AI02874b
I/O PIN
PSD835G2
Figure 15. Macrocell and I/O Port
AND ARRAY
PSD835G2
Output Macrocell (OMC)
Eight of the Output Macrocells (OMC) are connected to Port A pins and are named as McellA0McellA7. The other eight macrocells are connected to Port B pins and are named as McellB0McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 16., page 45. As shown in the figure, there are native product terms available from
the AND Array, and borrowed product terms available (if unused) from other Output Macrocells
(OMC). The polarity of the product term is controlled by the XOR gate. The Output Macrocell
(OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or
combinatorial logic outputs. The multiplexer output
can drive a port pin and has a feedback path to the
AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft program. The flip-flop’s clock, preset, and
clear inputs may be driven from a product term of
the AND Array. Alternatively, CLKIN (PD1) can be
used for the clock input to the flip-flop. The flip-flop
is clocked to the rising edge of CLKIN (PD1). The
preset and clear are active High inputs. Each clear
input can use up to two product terms.
Table 31. Output Macrocell Port and Data Bit Assignments
Output
Macrocell
Port
Assignment
Native Product Terms
Maximum Borrowed
Product Terms
Data Bit for Loading or
Reading
McellA0
Port A0
3
6
D0
McellA1
Port A1
3
6
D1
McellA2
Port A2
3
6
D2
McellA3
Port A3
3
6
D3
McellA4
Port A4
3
6
D4
McellA5
Port A5
3
6
D5
McellA6
Port A6
3
6
D6
McellA7
Port A7
3
6
D7
McellB0
Port B0
4
5
D0
McellB1
Port B1
4
5
D1
McellB2
Port B2
4
5
D2
McellB3
Port B3
4
5
D3
McellB4
Port B4
4
6
D4
McellB5
Port B5
4
6
D5
McellB6
Port B6
4
6
D6
McellB7
Port B7
4
6
D7
43/102
PSD835G2
Product Term Allocator
The CPLD has a Product Term Allocator. The PSD
uses the Product Term Allocator to borrow and
place product terms from one macrocell to another. The following list summarizes how product
terms are allocated:
– McellA0-McellA7 all have three native product
terms and may borrow up to six more
– McellB0-McellB3 all have four native product
terms and may borrow up to five more
– McellB4-McellB7 all have four native product
terms and may borrow up to six more.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms already in use by one macrocell are not available for
another macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required that consume other Output Macrocells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.
This is called product term expansion. PSDsoft
performs this expansion as needed.
Loading and Reading the Output Macrocells
(OMC)
The Output Macrocells (OMC) block occupies a
memory location in the MCU address space, as
defined by the CSIOP block (see I/O
PORTS, page 59). The flip-flops in each of the 16
Output Macrocells (OMC) can be loaded from the
data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority
over internal functions. As such, the preset, clear,
and clock inputs to the flip-flop can be overridden
by the MCU. The ability to load the flip-flops and
read them back is useful in such applications as
loadable counters and shift registers, mailboxes,
and handshaking protocols.
44/102
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of the Write Strobe
(WR, CNTL0) signal.
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight Output Macrocells (OMC). The
Mask Registers can be used to block the loading
of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
which allows loading of the Output Macrocells
(OMC). When a given bit in a Mask Register is set
to a '1,' the MCU is blocked from writing to the associated Output Macrocells (OMC). For example,
suppose McellA0-McellA3 are being used for a
state machine. You would not want a MCU WRITE
to McellA to overwrite the state machine registers.
Therefore, you would want to load the Mask Register for McellA (Mask Macrocell AB) with the value
0Fh.
The Output Enable of the OMC
The Output Macrocells (OMC) block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by
a single product term from the AND Array, ORed
with the Direction Register output. The pin is enabled upon Power-up if no output enable equation
is defined and if the pin is declared as a PLD output in PSDsoft.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, the port pin can be used for other
I/O functions. The internal node feedback can be
routed as an input to the AND Array.
AND ARRAY
PLD INPUT BUS
CLKIN
PT CLK
PT
PT
PT
PT
ALLOCATOR
PRESET(.PR)
ENABLE (.OE)
PORT INPUT
FEEDBACK (.FB)
MUX
CLEAR (.RE)
POLARITY
SELECT
WR
RD
MACROCELL CS
MASK
REG.
Q
MUX
PROGRAMMABLE
FF (D/T/JK /SR)
CLR
IN
LD
DIN PR
COMB/REG
SELECT
INTERNAL DATA BUS
DIRECTION
REGISTER
INPUT
MACROCELL
PORT
DRIVER
AI02875C
I/O PIN
PSD835G2
Figure 16. CPLD Output Macrocell
45/102
PSD835G2
Input Macrocells (IMC)
The CPLD has 24 Input Macrocells (IMC), one for
each pin on Ports A, B, and C. The architecture of
the Input Macrocells (IMC) is shown in Figure
17., page 47. The Input Macrocells (IMC) are individually configurable, and can be used as a latch,
register, or to pass incoming Port signals prior to
driving them onto the PLD input bus. The outputs
of the Input Macrocells (IMC) can be read by the
MCU through the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft. Outputs of the Input Macrocells (IMC) can be read by the MCU via the IMC
buffer. See I/O PORTS, page 59.
46/102
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18., page 48 shows a
typical configuration where the Master MCU writes
to the Port A Data Out Register. This, in turn, can
be read by the Slave MCU via the activation of the
“Slave-Read” output enable product term.
The Slave can also write to the Port A Input Macrocells (IMC) and the Master can then read the Input Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR, CNTL0), and Slave_CS.
AND ARRAY
PLD INPUT BUS
FEEDBACK
PT
PT
ENABLE ( .OE )
MUX
OUTPUT
MACROCELLS A
AND
MACROCELLS B
G
D
D
LATCH
Q
D FF
Q
INPUT MACROCELL _ RD
ALE/AS
PT
DIRECTION
REGISTER
INPUT MACROCELL
MUX
INTERNAL DATA BUS
PORT
DRIVER
AI02876C
I/O PIN
PSD835G2
Figure 17. Input Macrocell
47/102
MASTER
MCU
48/102
D [ 7:0]
MCU- WR
MCU- RD
PSD
MCU-RD
CPLD
D
Q
Q
D
PORT A
INPUT
MACROCELL
SLAVE–WR
MCU-WR
PORT A
DATA OUT
REGISTER
SLAVE–READ
WR
RD
SLAVE– CS
PORT A
D [ 7:0]
AI02877C
SLAVE
MCU
PSD835G2
Figure 18. Handshaking Communication Using Input Macrocells
PSD835G2
External Chip
The CPLD also provides eight Chip Select outputs
that can be used to select external devices. The
Chip Selects can be routed to either Port C or Port
F, depending on the pin declaration in the PSDsoft. Each Chip Select (ECS0-ECS7) consists of
one product term that can be configured active
High or Low.
The Output Enable of the pin is controlled by either
the Output Enable product term or the Direction
Register (See Figure 19).
Figure 19. External Chip Select
CPLD AND ARRAY
PLD INPUT BUS
ENABLE (.OE) PT
DIRECTION
REGISTER
ECS TO
PORT C OR F
ECS PT
PD0 PIN
POLARITY
BIT
PORT C OR PORT F
AI07654
49/102
PSD835G2
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 8-bit MCUs, with their
bus types and control signals, are shown in Table
32. The interface type is specified using the PSDsoft.
Table 32. MCUs and their Control Signals
MCU
Data Bus Width
CNTL0
CNTL1
CNTL2
PC7
PD02
ADIO0
PA3-PA0
PA7-PA4
8031/8051
8
WR
RD
PSEN
(Note 1)
ALE
A0
(Note 1)
(Note 1)
80C51XA
8
WR
RD
PSEN
(Note 1)
ALE
A4
A3-A0
(Note 1)
80C251
8
WR
PSEN
(Note 1) (Note 1)
ALE
A0
(Note 1)
(Note 1)
80C251
8
WR
RD
(Note 1)
ALE
A0
(Note 1)
(Note 1)
80198
8
WR
RD
(Note 1) (Note 1)
ALE
A0
(Note 1)
(Note 1)
68HC11
8
R/W
E
(Note 1) (Note 1)
AS
A0
(Note 1)
(Note 1)
68HC05C0
8
WR
RD
(Note 1) (Note 1)
AS
A0
(Note 1)
(Note 1)
68HC912
8
R/W
E
(Note 1)
AS
A0
(Note 1)
(Note 1)
Z80
8
WR
RD
(Note 1) (Note 1) (Note 1)
A0
D3-D0
D7-D4
Z8
8
R/W
DS
(Note 1) (Note 1)
AS
A0
(Note 1)
(Note 1)
68330
8
R/W
DS
(Note 1) (Note 1)
AS
A0
(Note 1)
(Note 1)
M37702M2
8
R/W
E
(Note 1) (Note 1)
ALE
A0
D3-D0
D7-D4
PSEN
DBE
Note: 1. Unused CNTL2 pin can be configured as PLD input. Other unused pins (PD3-PD0, PA3-PA0) can be configured for other I/O functions.
2. ALE/AS input is optional for MCUs with a non-multiplexed bus
50/102
PSD835G2
PSD Interface to a Multiplexed 8-Bit Bus
Figure 20 shows an example of a system using a
MCU with an 8-bit multiplexed bus and a PSD. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port E,
For G. The PSD drives the ADIO data bus only
when one of its internal resources is accessed and
Read Strobe (RD, CNTL1) is active. Should the
system address bus exceed sixteen bits, Ports A,
B, C, or F may be used as additional address inputs.
Figure 20. An Example of a Typical 8-bit Multiplexed Bus Interface
PSD
MCU
AD7-AD0
A15-A8
ADIO
PORT
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
A7-A0
PORT
F
(OPTIONAL)
PORT
G
(OPTIONAL)
PORT
A, B
or C
A15-A8
A23-A16
(OPTIONAL)
ALE (PD0)
PORT D
RESET
AI02878D
51/102
PSD835G2
PSD Interface to a Non-Multiplexed 8-Bit Bus
Figure 21 shows an example of a system using a
MCU with an 8-bit non-multiplexed bus and a
PSD. The address bus is connected to the ADIO
Port, and the data bus is connected to Port F. Port
F is in tri-state mode when the PSD is not accessed by the MCU. Should the system address bus
exceed sixteen bits, Ports A, B or C may be used
for additional address inputs.
MCU Bus Interface Examples
Figures 22 through 25 show examples of the basic
connections between the PSD and some popular
MCUs. The PSD Control input pins are labeled as
to the MCU function for which they are configured.
The MCU bus interface is specified using the PSDsoft.
Figure 21. An Example of a Typical 8-bit Non-Multiplexed Bus Interface
PSD
MCU
D7-D0
ADIO
PORT
PORT
F
D7-D0
A15-A0
PORT
G
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
PORT
A, B
or C
A23-A16
(OPTIONAL)
ALE (PD0)
PORT D
RESET
AI02879D
52/102
PSD835G2
80C31
Figure 22 shows the bus interface for the 80C31,
which has an 8-bit multiplexed address/data bus.
The lower address byte is multiplexed with the
data bus. The MCU control signals Program Select Enable (PSEN, CNTL2), Read Strobe (RD,
CNTL1), and Write Strobe (WR, CNTL0) may be
used for accessing the internal memory and I/O
Ports blocks. Address Strobe (ALE/AS, PD0)
latches the address.
Figure 22. Interfacing the PSD with an 80C31
A15-A8
AD[15:8]
AD7-AD0
AD[ 7:0 ]
VCC
PSD
80C31
19
CRYSTAL
18
9
RESET
12
13
14
15
X1
X2
RESET
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
RD
PSEN
10
RXD
11
TXD
ALE/P
VCC VCC VCC
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
16
WR
59
17
RD
60
29
30
31
PSEN
ALE
40
79
80
1
2
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0 (WR)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL1(RD)
CNTL2 (PSEN)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
EA/VP
39
RESET
RESET
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02880D
53/102
PSD835G2
80C251
The Intel 80C251 MCU features a user-configurable bus interface with four possible bus configurations, as shown in Table 33.
The first configuration is 80C31 compatible, and
the bus interface to the PSD is identical to that
shown in Figure 22., page 53. The second and
third configurations have the same bus connection
as shown in Table 34., page 55. There is only one
Read Strobe (PSEN) connected to CNTL1 on the
PSD. The A16 connection to PA0 allows for a larger address input to the PSD. The fourth configuration is shown in Figure 23., page 56. Read Strobe
(RD) is connected to CNTL1 and Program Select
Enable (PSEN) is connected to CNTL2.
The 80C251 has two major operating modes:
Page mode and Non-page mode. In Non-page
mode, the data is multiplexed with the lower address byte, and Address Strobe (ALE/AS, PD0) is
active in every bus cycle. In Page mode, data (D7D0) is multiplexed with address (A15-A8). In a bus
cycle where there is a Page hit, Address Strobe
(ALE/AS, PD0) is not active and only addresses
(A7-A0) are changing. The PSD supports both
modes. In Page Mode, the PSD bus timing is identical to Non-Page Mode except the address hold
time and setup time with respect to Address
Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0)
valid to data in valid.
Table 33. 80C251 Configurations
Configuration
80C251 READ/WRITE
Pins
Connecting to PSD Pins
Page Mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31
compatible A7-A0 multiplex with
D7-D0
2
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A7-A0 multiplex with D7-D0
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A15-A8 multiplex with D7-D0
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A15-A8 multiplex with D7-D0
54/102
PSD835G2
Table 34. Interfacing the PSD with the 80C251, with One READ Input
A17-A8
A17
AD[15:8]
AD7-AD0
AD[ 7:0 ]
VCC
U1
2
3
4
5
6
7
8
9
21
CRYSTAL
20
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
X1
X2
PSD
80C31
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
RD/A16
RESET
10
PSEN
43
42
41
40
39
38
37
36
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
VCC VCC VCC
ADIO0(2)
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
WR
59
CNTL0 (WR)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
18
19
32
A16
RD
ALE
RESET
ALE
33
35
60
40
CNTL1(RD)
CNTL2 (PSEN)
79
80
1
2
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
EA
39
RESET
RESET
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
A16(1)
A17
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02881D
Note: 1. The A16 and A17 connections are optional.
2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.
55/102
PSD835G2
Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
A15-A8
AD[15:8]
AD7-AD0
AD[ 7:0 ]
VCC
PSD
80C31
2
3
4
5
6
7
8
9
21
CRYSTAL
20
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
X1
X2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
RD/A16
RESET
10
PSEN
RESET
ALE
35
43
42
41
40
39
38
37
36
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
VCC VCC VCC
ADIO0(2)
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
18
WR
59
19
CNTL0 (WR)
RD
60
32
PSEN
40
CNTL1(RD)
CNTL2 (PSEN)
33
ALE
79
80
1
2
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
EA
39
RESET
RESET
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02882D
56/102
PSD835G2
80C51XA
The Philips 80C51XA MCU family supports an 8or 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multiplexed,
while (A19-A4) are multiplexed with data bits
(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4)
are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode (as shown in Figure 24).
The 80C51XA improves bus throughput and performance by executing burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 signals to fetch up to 16 bytes of code.
The PSD access time is then measured from address A3-A0 valid to data in valid. The PSD bus
timing requirement in Burst Mode is identical to the
normal bus cycle, except the address setup and
hold time with respect to Address Strobe (ALE/AS,
PD0) does not apply.
Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus
A[19:12] D[7:0]
A[3:0 ]
VCC
PSD
80C31
21
CRYSTAL
20
11
13
6
7
9
8
16
RESET
VCC
10
14
15
35
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RESET
INT0
INT1
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A3
A2
A1
A0/WRH
WRL
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
WR
59
CNTL0 (WR)
60
40
CNTL1(RD)
CNTL2 (PSEN)
79
80
1
2
PD0 (ALE)
PD1 (CLKIN)
PD2 (CS)
PD3
5
4
3
2
18
A3
A2
A1
A0
RD
19
RD
EA/WAIT
PSEN
ALE
32
33
PSEN
ALE
39
RESET
RESET
9
29 69
VCC VCC VCC
ADIO0(2)
PF0
ADIO1
PF1
ADIO2
PF2
ADIO3
PF3
PF4
ADIO4
PF5
ADIO5
PF6
ADIO6
PF7
ADIO7
43
42
41
40
39
38
37
36
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02883D
57/102
PSD835G2
68HC11
Figure 25 shows a bus interface to a 68HC11
where the PSD is configured in 8-bit multiplexed
mode with E and R/W settings. The DPLD can be
used to generate the READ and WR signals for
external devices.
Figure 25. Interfacing the PSD with a 68HC11
A15-A8
A[15:8]
AD7-AD0
A[3:0 ]
VCC
PSD
80C31
34
33
32
31
30
29
28
27
8
CRYSTAL
7
19
18
20
21
22
23
24
25
43
44
45
46
47
48
49
50
52
51
2
3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
XT
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
EX
IRQ
XIRQ
PD0
PD1
PD2
PD3
PD4
PD5
R/W
E
AS
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
42
41
40
39
38
37
36
35
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
6
R/W
E
59
CNTL0 (R/W)
60
CNTL1(RD)
40
CNTL2 (E)
79
80
1
2
PD0 (AS)
PD1 (CLKIN)
PD2 (CS)
PD3
5
4
AS
RESET
RESET
VRH
VRL
MODB
MODA
RESET
RESET
9
29 69
VCC VCC VCC
ADIO0(2)
PF0
ADIO1
PF1
ADIO2
PF2
ADIO3
PF3
PF4
ADIO4
PF5
ADIO5
PF6
ADIO6
PF7
ADIO7
9
10
11
12
13
14
15
16
39
71
72
73
74
75
76
77
78
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
GND GND GND GND GND
8
30 49 50 70
AI02884D
58/102
PSD835G2
I/O PORTS
There are seven programmable I/O ports: Ports A,
B, C, D, E and F. Each of the ports is eight bits except for Port D, which is 4 bits. Each port pin is individually user-configurable, thus allowing multiple
functions per port. The ports are configured using
PSDsoft or by the MCU writing to on-chip registers
in the CSIOP space.
The topics discussed in this section are:
■
General Port architecture
■
Port operating modes
■
Port Configuration Registers (PCR)
■
Port Data Registers
■
Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 26., page 60. Individual Port architectures are shown in Figure 28., page 66 to
Figure 30., page 69. In general, once the purpose
for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are
noted.
As shown in Figure 26., page 60, the ports contain
an output multiplexer whose select signals are
driven by the configuration bits in the Control Registers (Ports E, F and G only) and PSDsoft Configuration. Inputs to the multiplexer include the
following:
– Output data from the Data Out register
– Latched address outputs
– CPLD macrocell output
– External Chip Select (ECS0-ECS2) from the
CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direction and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs is not defined and
that port pin is not defined as a CPLD output in the
PSDabel file, then the Direction Register has sole
control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See Input Macrocells (IMC), page 46.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Registers in
CSIOP space, and some by both. The modes that
can only be defined using PSDsoft must be programmed into the device and cannot be changed
unless the device is reprogrammed. The modes
that can be changed by the MCU can be done so
dynamically at run-time. The PLD I/O, Data Port,
Address Input, Peripheral I/O and MCU Reset
modes are the only modes that must be defined
before programming the device. All other modes
can be changed by the MCU at run-time.
Table 35., page 61 summarizes which modes are
available on each port. Table 38., page 64 shows
how and where the different modes are configured. Each of the port operating modes are described in the following sections.
59/102
PSD835G2
Figure 26. General I/O Port Architecture
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
PORT PIN
OUTPUT
MUX
G
MACROCELL OUTPUTS
EXT CS
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
Q
ENABLE OUT
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD- INPUT
AI02885
60/102
PSD835G2
MCU I/O Mode
In the MCU I/O mode, the MCU uses the I/O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD are mapped
into the MCU address space. The addresses of
the ports are listed in Table 5., page 19.
A port pin can be put into MCU I/O mode by writing
a ’0’ to the corresponding bit in the Control Register (Ports E, F and G). The MCU I/O direction may
be changed by writing to the corresponding bit in
the Direction Register, or by the output enable
product term. See Direction Register, page 64.
When the pin is configured as an output, the content of the Data Out Register drives the pin. When
configured as an input, the MCU can read the port
input through the Data In buffer. See Figure
26., page 60.
Ports A, B and C do not have Control Registers,
and are in MCU I/O mode by default. They can be
used for PLD I/O if they are specified in PSDsoft.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells (IMC), and/or as an output from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product term from the PLD, or by resetting the
corresponding bit in the Direction Register to '0.'
The corresponding bit in the Direction Register
must not be set to ’1’ if the pin is defined as a PLD
input pin in PSDsoft. The PLD I/O mode is specified in PSDsoft by declaring the port pins, and then
specifying an equation in PSDsoft.
Address Out Mode
For MCUs with a multiplexed address/data bus,
Address Out Mode can be used to drive latched
addresses on to the port pins. These port pins can,
in turn, drive external devices. Either the output
enable or the corresponding bits of both the Direction Register and Control Register must be set to
a ’1’ for pins to use Address Out Mode. This must
be done by the MCU at run-time. See Table
37., page 62 for the address output pin assignments on Ports E, F and G for various MCUs.
Note: Do not drive address signals with Address
Out Mode to an external memory device if it is intended for the MCU to Boot from the external device. The MCU must first Boot from PSD memory
so the Direction and Control register bits can be
set.
Table 35. Port Operating Modes
Port Mode
Port A
Port B
Port C
Port D
Port E
Port F
Port G
MCU I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PLD I/O
McellA Outputs
McellB Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Address Out
No
No
No
No
Yes (A7-A0)
Yes (A7-A0)
Yes (A7-A0)
or (A15-A8)
Address In
Yes
Yes
Yes
Yes
No
Yes
No
Data Port
No
No
No
No
No
Yes
No
Peripheral I/O
No
No
No
No
No
Yes
No
JTAG ISP
No
No
No
No
Yes1
No
No
Note: 1. Can be multiplexed with other I/O functions.
61/102
PSD835G2
Table 36. Port Operating Mode Settings
Mode
Control
Register
Setting
Defined in PSDsoft
Direction
Register
Setting
VM Register
Setting
JTAG Enable
MCU I/O
Declare pins only
0 (Note 4)
1 = output,
0 = input
(Note 2)
N/A
N/A
PLD I/O
Declare pins and logic
equations
N/A
(Note 2)
N/A
N/A
Data Port (Port F)
Selected for MCU with
non-mux bus
N/A
N/A
N/A
N/A
Address Out
(Port E, F, G)
Declare pins only
1
1 (Note 2)
N/A
N/A
Address In
(Port A,B,C,D, F)
Declare pins or logic
equations for Input
Macrocells
N/A
N/A
N/A
N/A
Peripheral I/O
(Port F)
Logic equations
(PSEL0 & 1)
N/A
N/A
PIO Bit = 1
N/A
JTAG ISP (Note 3)
Declare pins only
N/A
N/A
N/A
JTAG_Enable
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port E.
4. Control Register setting is not applicable to Ports A, B and C.
Table 37. I/O Port Latched Address Output Assignments
Port E
(PE3-PE0)
Port E
(PE7-PE4)
Port F
(PF3-PF0)
Port F
(PF7-PF4)
Port G
(PG3-PG0)
Port G
(PG7-PG4)
8051XA
N/A1
Address
(A7-A4)
N/A1
Address
(A7-A4)
Address
(A11-A8)
Address
(A15-A12)
80C251
(Page Mode)
N/A
N/A
N/A
N/A
Address
(A11-A8)
Address
(A7-A4)
Address
(A3-A0)
Address
(A7-A4)
Address
(A3-A0)
Address
(A7-A4)
Address
(A3-A0)
Address
(A7-A4)
N/A
N/A
N/A
N/A
Address
(A3-A0)
Address
(A7-A4)
MCU
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed Bus
Note: 1. N/A = Not Applicable.
62/102
PSD835G2
Address In Mode
For MCUs that have more than 16 address signals, the higher addresses can be connected to
Port A, B, C, D or F and are routed as inputs to the
PLDs. The address input can be latched in the Input Macrocell (IMC) by Address Strobe (ALE/AS,
PD0). Any input that is included in the DPLD equations for the SRAM, or primary or secondary Flash
memory is considered to be an address input.
Data Port Mode
Port F can be used as a data bus port for an MCU
with a non-multiplexed address/data bus. The
Data Port is connected to the data bus of the MCU.
The general I/O functions are disabled in Port F if
the port is configured as a Data Port. Data Port
Mode is automatically configured in PSDsoft when
a non-multiplexed bus MCU is selected.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external 8-bit peripherals. In this mode, all of Port
F serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by setting Bit 7 of the VM Register to a '1.' Figure 27
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is enabled. An equation for PSEL0 and/or PSEL1 must
be written in PSDsoft. The buffer is tri-stated when
PSEL0 or PSEL1 is not active.
Figure 27. Peripheral I/O Mode
RD
PSEL0
PSEL
PSEL1
VM REGISTER BIT 7
D0 - D7
DATA BUS
PF0 - PF7
WR
AI02886b
63/102
PSD835G2
JTAG In-System Programming (ISP)
Port E is JTAG compliant, and can be used for InSystem Programming (ISP). You can multiplex
JTAG operations with other functions on Port E
because In-System Programming (ISP) is not performed in normal Operating mode. For more information on the JTAG Port, see PROGRAMMING
IN-CIRCUIT
USING
THE
JTAG/ISP
INTERFACE, page 76.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 5., page 19. The addresses in Table 5 are the offsets in hexadecimal from the base
of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 38, are used for setting the
Port configurations. The default Power-up state for
each register in Table 38 is 00h.
Control Register
Any bit reset to ’0’ in the Control Register sets the
corresponding port pin to MCU I/O Mode, and a ’1’
sets it to Address Out Mode. The default mode is
MCU I/O. Only Ports E, F and G have an associated Control Register.
Direction Register
The Direction Register, in conjunction with the output enable (except for Port D), controls the direction of data flow in the I/O Ports. Any bit set to ’1’
in the Direction Register causes the corresponding pin to be an output, and any bit set to ’0’ causes
it to be an input. The default mode for all port pins
is input.
Figure 28., page 66 and Figure 29., page 67 show
the Port Architecture diagrams for Ports A/B/C and
E/F/G, respectively. The direction of data flow for
Ports A, B, C and F are controlled not only by the
direction register, but also by the output enable
product term from the PLD AND Array. If the output enable product term is not active, the Direction
Register has sole control of a given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the remainder set to input is shown in Table 41. Since
Port D only contains four pins (shown in Figure
29., page 67), the Direction Register for Port D
has only the four least significant bits active.
64/102
Drive Select Register
The Drive Select Register configures the pin driver
as Open Drain or CMOS for some port pins, and
controls the slew rate for the other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a
'1.' The default pin drive is CMOS.
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates at a high slew
rate when the corresponding bit in the Drive Register is set to '1.' The default rate is slow slew.
Table 42., page 65 shows the Drive Register for
Ports A, B, C, D, E and F. It summarizes which
pins can be configured as Open Drain outputs and
which pins the slew rate can be set for.
Table 38. Port Configuration Registers (PCR)
Register Name
Port
MCU Access
Control
E, F, G
WRITE/READ
Direction
A,B,C,D, E, F, G
WRITE/READ
Drive Select1
A,B,C,D, E, F, G
WRITE/READ
Note: 1. See Table 42., page 65 for Drive Register bit definition.
Table 39. Port Pin Direction Control, Output
Enable P.T. Not Defined
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Table 40. Port Pin Direction Control, Output
Enable P.T. Defined
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Table 41. Port Direction Assignment Example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
PSD835G2
Table 42. Drive Register Pin Assignment
Drive Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port C
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port D
NA1
NA1
NA1
NA1
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port E
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port F
Slew Rate
Slew Rate
Slew Rate
Slew Rate
Slew Rate
Slew Rate
Slew Rate
Slew Rate
Port G
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Note: 1. NA = Not Applicable.
Port Data Registers
The Port Data Registers, shown in Table 43, are
used by the MCU to write data to or read data from
the ports. Table 43 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is read
through the Data In buffer.
Data Out Register
Stores output data written by the MCU in the MCU
I/O output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to '1.' The
contents of the register can also be read back by
the MCU.
Output Macrocells (OMC)
The CPLD Output Macrocells (OMC) occupy a location in the MCU’s address space. The MCU can
read the output of the Output Macrocells (OMC). If
the OMC Mask Register bits are not set, writing to
the macrocell loads data to the macrocell flip-flops.
See PLDs, page 38.
OMC Mask Register
Each OMC Mask Register bit corresponds to an
Output Macrocell (OMC) flip-flop. When the OMC
Mask Register bit is set to a '1,' loading data into
the Output Macrocell (OMC) flip-flop is blocked.
The default value is 0 or unblocked.
Table 43. Port Data Registers
Register Name
Port
MCU Access
Data In
A, B, C, D, E, F, G
READ – input on pin
Data Out
A, B, C, D, E, F, G
WRITE/READ
Output Macrocell
A, B
READ – outputs of macrocells
WRITE – loading macrocell flip-flops
Mask Macrocell
A, B
WRITE/READ – prevents loading into a given
macrocell
Input Macrocell
A, B, C
READ – outputs of the Input Macrocells
Enable Out
A, B, C, F
READ – the output enable control of the port driver
65/102
PSD835G2
Input Macrocells (IMC)
The Input Macrocells (IMC) can be used to latch or
store external inputs. The outputs of the Input
Macrocells (IMC) are routed to the PLD input bus,
and can be read by the MCU. See PLDs, page 38.
Enable Out
The Enable Out register can be read by the MCU.
It contains the output enable values for a given
port. A ‘1’ indicates the driver is in output mode. A
‘0’ indicates the driver is in tri-state and the pin is
in input mode.
Ports A,B and C – Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 28.
The two ports can be configured to perform one or
more of the following functions:
–
–
–
–
–
MCU I/O Mode
CPLD Output – Macrocells McellA7-McellA0
can be connected to Port A, McellB7-McellB0
can be connected to Port B, External Chip
Select ECS7-ECS0 can be connected to Port
C.
CPLD Input – Via the Input Macrocells (IMC).
Address In – Additional high address inputs
using the Input Macrocells (IMC).
Open Drain/Slew Rate – pins PC7-PC0 can be
configured to fast slew rate, pins PA7-PA0 and
PB7-PB0 can be configured to Open Drain
Mode.
Figure 28. Port A, B and C Structure
DATA OUT
REG.
D
DATA OUT
Q
WR
PORT PIN
OUTPUT
MUX
MCELLA7-MCELLA0 (PORT A)
MCELLB7-MCELLB0 (PORT B)
EXT.CS (PORT C)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
ENABLE OUT
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD- INPUT
AI02887b
66/102
PSD835G2
Port D – Functionality and Structure
Port D has four I/O pins. It can be configured to
program one or more of the following functions
(see Figure 29):
– MCU I/O Mode
– CPLD Input – direct input to CPLD, no Input
Macrocell (IMC).
Port D pins can be configured in PSDsoft as input
pins for other dedicated functions:
– PD0 – ALE, as Address Strobe input.
– PD1 – CLKIN, as Clock input to the Macrocell
flip-flops and APD counter.
– PD2 – CSI, as active Low Chip Select input. A
High input will disable the Flash/SRAM
memories and the CSIOP.
– PD3 – as DBE input from 68HC912.
Figure 29. Port D Structure
DATA OUT
REG.
D
Q
DATA OUT
WR
PORT D PIN
OUTPUT
MUX
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
DIR REG.
D
WR
Q
CPLD-INPUT
AI02888C
67/102
PSD835G2
Port E – Functionality and Structure
Port E can be configured to perform one or more
of the following functions:
– MCU I/O Mode
– In-System Programming – JTAG port can be
enabled for programming/erase of the PSD
device. Refer to PROGRAMMING IN-CIRCUIT USING THE JTAG/ISP
INTERFACE, page 76 for more information.
– Open Drain – Port E pins can be configured in
Open Drain Mode.
– Battery Backup features – PE6 can be
configured as a Battery Input (VSTBY) pin. PE7
can be configured as a Battery On Indicator
output pin, indicating when VCC is less than
VBAT.
– Latched Address Output – Provided latched
address (A7-A0) output.
Port F – Functionality and Structure
Port F can be configured to perform one or more
of the following functions:
– MCU I/O Mode
– CPLD Output – External Chip Select ECS7ECS0 can be connected to Port F (or Port C).
68/102
–
CPLD Input – as direct input of the CPLD
array.
– Address In – addition high address inputs.
Direct input to the CPLD array, no Input
Macrocell (IMC) latching is available.
– Latched Address Out – Provide latched
address out per Table 47., page 75.
– Slew Rate – pins can be set up for fast slew
rate.
– Data Port – connected to D7-D0 when Port F
is configured as Data Port for a nonmultiplexed bus.
– Peripheral I/O Mode.
Port G – Functionality and Structure
Port G can be configured to perform one or more
of the following functions:
– MCU I/O Mode
– Latched Address Out – Provide latched
address out per Table 47., page 75.
– Open Drain – pins can be configured in Open
Drain Mode.
PSD835G2
Figure 30. Port E, F, G Structure
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
PORT
E, F OR G PIN
ADDRESS
A7-A0 OR A15-A8
G
OUTPUT
MUX
EXT.CS (PORT F)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
ENABLE OUT
Q
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
CPLD-INPUT
ISP OR BATTERY BACK-UP (PORT E)
CONFIGURATION
BIT
AI02889b
69/102
PSD835G2
POWER MANAGEMENT
The PSD835G2 offers configurable power saving
options. These options may be used individually or
in combinations, as follows:
– All memory blocks in a PSD (primary and
secondary Flash memory, and SRAM) are
built with Power Management technology. In
addition to using special silicon design
methodology, power management technology
puts the memories into standby mode when
address/data inputs are not changing (zero
DC current). As soon as a transition occurs on
an input, the affected memory “wakes up”,
changes and latches its outputs, then goes
back to standby. The designer does not have
to do anything special to achieve memory
standby mode when no inputs are changing—
it happens automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as
described in the sections on the Power
Management Mode Registers (PMMR).
– As with the Power Management mode, the
Automatic Power Down (APD) unit allows the
PSD to reduce to standby current
automatically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs. This feature is available
on all the devices of the PSD family. The APD
Unit is described in more detail in Automatic
Power-down (APD) Unit and Power-down
Mode, page 71.
Built-in logic monitors the Address Strobe of
the MCU for activity. If there is no activity for a
certain time period (MCU is asleep), the APD
Unit initiates Power-down mode (if enabled).
Once in Power-down mode, all address/data
signals are blocked from reaching PSD
memory and PLDs, and the memories are
deselected internally. This allows the memory
and PLDs to remain in standby mode even if
the address/data signals are changing state
70/102
–
–
externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked
PLD input signals that are changing states
keep the PLD out of Stand-by mode, but not
the memories.
PSD Chip Select Input (CSI, PD2) can be
used to disable the internal memories, placing
them in standby mode even if inputs are
changing. This feature does not block any
internal signals or disable the PLDs. This is a
good alternative to using the APD Unit. There
is a slight penalty in memory access time
when PSD Chip Select Input (CSI, PD2)
makes its initial transition from deselected to
selected.
The PMMRs can be written by the MCU at runtime to manage power. All PSD devices
support “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 34., page 78). Significant power
savings can be achieved by blocking signals
that are not used in PLD logic equations at
run-time. PSDsoft creates a fuse map that
automatically blocks the low address Byte
(A7-A0) or the Control signals (CNTL0CNTL2, ALE and WRH/DBE) if none of these
signals are used in PLD logic equations.
PSD devices have a Turbo Bit in PMMR0. This
bit can be set to turn the Turbo mode off (the
default is with Turbo mode turned on). While
Turbo mode is off, the PLDs can achieve
standby current when no PLD inputs are
changing (zero DC current). Even when inputs
do change, significant power can be saved at
lower frequencies (AC current), compared to
when Turbo mode is on. When the Turbo
mode is on, there is a significant DC current
component and the AC component is higher.
PSD835G2
Automatic Power-down (APD) Unit and Power-down Mode
The APD Unit, shown in Figure 31, puts the PSD
registers. The blocked signals include MCU
into Power-down mode by monitoring the activity
control signals and the common CLKIN (PD1).
of Address Strobe (ALE/AS, PD0). If the APD Unit
Note that blocking CLKIN (PD1) from the
is enabled, as soon as activity on Address Strobe
PLDs does not block CLKIN (PD1) from the
(ALE/AS, PD0) stops, a four-bit counter starts
APD Unit.
counting. If Address Strobe (ALE/AS, PD0) re– All PSD memories enter Standby mode and
mains inactive for fifteen clock periods of CLKIN
are drawing standby current. However, the
(PD1), Power-down (PDN) goes High, and the
PLD and I/O ports blocks do not go into
PSD enters Power-down mode, as discussed
Standby Mode because you don’t want to
next.
have to wait for the logic and I/O to “wake-up”
Power-down Mode. By default, if you enable the
before their outputs can change. See Table 44
APD Unit, Power-down mode is automatically enfor Power-down mode effects on PSD ports.
abled. The device enters Power-down mode if Ad– Typical standby current is of the order of
dress Strobe (ALE/AS, PD0) remains inactive for
microamperes. These standby current values
fifteen periods of CLKIN (PD1).
assume that there are no transitions on any
PLD input.
The following should be kept in mind when the
PSD is in Power-down mode:
– If Address Strobe (ALE/AS, PD0) starts
Table 44. Power-down Mode’s Effect on Ports
pulsing again, the PSD returns to normal
Port Function
Pin Level
Operating mode. The PSD also returns to
normal Operating mode if either PSD Chip
MCU I/O
No Change
Select Input (CSI, PD2) is Low or the Reset
PLD Out
No Change
(RESET) input is High.
– The MCU address/data bus is blocked from all
Address Out
Undefined
memories and PLDs.
Data Port
Tri-State
– Various signals can be blocked (prior to
Power-down mode) from entering the PLDs by
Peripheral I/O
Tri-State
setting the appropriate bits in the PMMR
Figure 31. APD Unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
CLR
RESET
CSI
PD
SECONDARY FLASH SELECT
APD
COUNTER
PRIMARY FLASH SELECT
EDGE
DETECT
PD
PLD
CLKIN
SRAM SELECT
POWER DOWN
(PDN) SELECT
DISABLE PRIMARY AND
SECONDARY FLASH/SRAM MEMORIES
AI02891b
Table 45. PSD Timing and Stand-by Current during Power-down Mode
Mode
PLD Propagation
Delay
Memory
Access Time
Access Recovery Time to
Normal Access
5V VCC
Typical Standby Current
Power-down
Normal tPD (Note 1)
No Access
tLVDV
50µA (Note 2)
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is '0.'
71/102
PSD835G2
Other Power Saving Options
The PSD offers other reduced power saving options that are independent of the Power-down
mode. Except for the SRAM Standby and Chip Select Input (CSI, PD2) features, they are enabled by
setting bits in the PMMR0 and PMMR2 registers
(see Table 22., page 22 and Table 23., page 22
for a bit definition of the two registers).
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo Bit (Bit 3) in PMMR0. By setting the
bit to '1,' the Turbo mode is off and the PLDs consume the specified standby current when the inputs are not switching for an extended time of
70ns. The propagation delay time is increased after the Turbo Bit is set to ’1’ (turned off) when the
inputs change at a composite frequency of less
than 15 MHz. When the Turbo Bit is reset to ’0’
(turned on), the PLDs run at full power and speed.
The Turbo Bit affects the PLD’s DC power, AC
power, and propagation delay. Refer to MAXIMUM RATING, page 81 for PLD timings.
Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power consumption.
SRAM Standby Mode (Battery Backup). The
PSD supports a battery backup mode in which the
contents of the SRAM are retained in the event of
a power loss. The SRAM has a Voltage Standby
pin (VSTBY, PC2) that can be connected to an external battery. When VCC becomes lower than
VSTBY then the PSD automatically connects to
Voltage Stand-by (VSTBY, PC2) as a power source
to the SRAM. The SRAM Standby Current (ISTBY)
is typically 0.5µA. The SRAM data retention voltage is 2 V minimum. The Battery-on Indicator
(VBATON) can be routed to PE7. This signal indicates when the VCC has dropped below VSTBY and
the SRAM is running on battery power.
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft as the
PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal (primary)
Flash memory, secondary Flash memory, SRAM,
and I/O blocks for READ or WRITE operations involving the PSD. A High on PSD Chip Select Input
(CSI, PD2) disables the primary Flash memory,
72/102
secondary Flash memory, and SRAM, and reduces the PSD power consumption. However, the
PLD and I/O signals remain operational when PSD
Chip Select Input (CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See
the timing parameter tSLQV in Table 64., page 93.
Input Clock
The PSD provides the option to turn off CLKIN
(PD1) to the PLD to save AC power consumption.
CLKIN (PD1) is an input to the PLD AND Array and
the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting Bits 4 or 5
to a ’1’ in PMMR0.
Figure 32. Enable Power-down Flow Chart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bit 0.
No
ALE/AS idle
for 15 CLKIN
clocks?
Yes
PSD in Power
Down Mode
AI02892B
PSD835G2
Input Control Signals
The PSD provides the option to turn off the address input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/
AS, PD0) and DBE) to the PLD to save AC power
consumption. These signals are inputs to the PLD
AND Array. During Power-down mode, or, if any of
them are not being used as part of the PLD logic
equation, these signals should be disabled to save
AC power. They are disconnected from the PLD
AND Array by setting Bits 0, 2, 3, 4, 5, and 6 to a
‘1’ in PMMR2.
Table 46. APD Counter Operation
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
73/102
PSD835G2
RESET TIMING AND DEVICE STATUS AT RESET
Power-Up Reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO (1ms minimum)
after VCC is steady. During this period, the device
loads internal configurations, clears some of the
registers and sets the Flash memory into Operating mode. After the rising edge of Reset (RESET),
the PSD remains in the Reset mode for an additional period, tOPR (120ns maximum), before the
first memory access is allowed.
The Flash memory is reset to the READ mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR, CNTL0) High, during Power-Up Reset for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Flash memory WRITE cycle initiation is prevented
automatically when VCC is below VLKO.
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
tNLNH (150ns minimum). The same tOPR period is
needed before the device is operational after
warm reset. Figure 33 shows the timing of the
Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset
Table 47., page 75 shows the I/O pin, register and
PLD status during Power-Up Reset, warm reset
and Power-down mode. PLD outputs are always
valid during warm reset, and they are valid in Power-Up Reset once the internal PSD Configuration
bits are loaded. This loading of PSD is completed
typically long before VCC ramps up to operating
level. Once the PLD is active, the state of the outputs are determined by the equations specified in
PSDsoft.
Reset of Flash Memory Erase and Program
Cycles
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to
the READ mode within a period of tNLNH-A (25µs
minimum).
Figure 33. Power-Up and Warm Reset (RESET) Timing
VCC
VCC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
tNLNH-A
Warm Reset
tOPR
RESET
AI02866b
74/102
PSD835G2
Table 47. Status During Power-Up Reset, Warm Reset and Power-down Mode
Port Configuration
Power-Up Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-Un Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to ’0’
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to ’0’ by internal
Power-Up Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register1
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to ’0’
Cleared to ’0’
Unchanged
Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to ’0’ on Power-Up Reset or Warm Reset.
75/102
PSD835G2
PROGRAMMING IN-CIRCUIT USING THE JTAG/ISP INTERFACE
The JTAG/ISP Interface block can be enabled on
Port E (see Table 48., page 77). All memory
blocks (primary and secondary Flash memory),
PLD logic, and PSD Configuration Register bits
may be programmed through the JTAG/ISP Interface block. A blank device can be mounted on a
printed circuit board and programmed using
JTAG/ISP.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank PSD (as shipped from the
factory or after erasure), four pins on Port E are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO.
See Application Note AN1153 for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different conditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
JTAG serial command from an external JTAG controller device (such as FlashLINK or Automated
Test Equipment). When the enabling command is
received, TDO becomes an output and the JTAG
channel is fully functional inside the PSD. The
same command that enables the JTAG channel
may optionally enable the two additional JTAG signals, TSTAT and TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG signals
(TMS, TCK, TDI, and TDO) on their respective
Port E pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
76/102
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside
the PSD is set by the designer in
the
PSDsoft
Configuration
utility. This dedicates the pins
for JTAG at all times (compliant
with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a
bit at run-time by writing to the
PSD register, JTAG Enable. This
register is located at address
CSIOP + offset C7h. Setting the
JTAG_ENABLE bit in this register
will enable the pins for JTAG use.
This bit is cleared by a PSD reset
or the microcontroller. See Table
20., page 22 for bit definition.
*/
PSD_product_term_enabled;
/* A dedicated product term (PT)
inside the PSD can be used to
enable the JTAG pins. This PT has
the reserved name JTAGSEL. Once
defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when
the Port E JTAG pins are
multiplexed with other I/O
signals. It is recommended to
logically tie the node JTAGSEL to
the JEN\ signal on the Flashlink
cable when multiplexing JTAG
signals. See Application Note 1153
for details. */
The PSD supports JTAG/ISP commands, but not
Boundary Scan. The PSDsoft software tool and
FlashLINK JTAG programming cable implement
the JTAG/ISP commands.
PSD835G2
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an JTAG command received over the
four standard JTAG signals (TMS, TCK, TDI, and
TDO). They are used to speed Program and Erase
cycles by indicating status on PSD signals instead
of having to scan the status out serially using the
standard JTAG channel. See Application Note
AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming a Byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until a special JTAG command is executed or a chip Reset
pulse
is
received
after
an
(RESET)
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy described in the section entitled Ready/Busy
(PE4), page 26. TSTAT is High when the PSD device is in READ mode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory Program or Erase cycles
are in progress, and also when data is being written to the secondary Flash memory.
TSTAT and TERR can be configured as opendrain type signals during a JTAG command.
Security and Flash memory Protection
When the Security Bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the part to a
non-secured blank state. The Security Bit can be
set in PSDsoft.
All primary and secondary Flash memory sectors
can individually be sector protected against erasures. The Sector Protect Bits can be set in PSDsoft.
Table 48. JTAG Port Signals
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
PE4
TSTAT
Status
PE5
TERR
Error Flag
77/102
PSD835G2
AC/DC PARAMETERS
The tables provided below describe the AD and
DC parameters of the PSD:
❏ DC Electrical Specification
❏ AC Timing Specification
■
PLD Timing
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Macrocell Timing
■
MCU Timing
– READ Timing
– WRITE Timing
– Peripheral Mode Timing
– Power-down and Reset Timing
The following are issues concerning the parameters presented:
– In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo Bit is '0.'
– The AC power component gives the PLD,
Flash memory, and SRAM mA/MHz
specification. Figure 34 show the PLD mA/
MHz as a function of the number of Product
Terms (PT) used.
– In the PLD timing parameters, add the
required delay when Turbo Bit is '0.'
Figure 34. PLD ICC /Frequency Consumption
110
VCC = 5V
100
)
00%
N (1
O
BO
TUR
90
FF
70
O
60
O
T
RB
50
O
URB
ON
(25%
)
TU
ICC – (mA)
80
40
30
20
O
RB
TU
10
F
OF
PT 100%
PT 25%
0
0
5
10
15
20
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
78/102
25
AI02894
PSD835G2
Table 49. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
= 8 MHz
= 4 MHz
% Flash memory Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down Mode
= 90%
Number of product terms used
(from fitter report)
= 45 PT
% of total product terms
= 45/193 = 23.3%
Turbo Mode
= ON
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE
+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x 2mA/MHz x Freq PLD
+ #PT x 400µA/PT)
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz
+ 0.15 x 1.5mA/MHz x 4 MHz
+ 2mA/MHz x 8 MHz
+ 45 x 0.4mA/PT)
= 45µA + 0.1 x (8 + 0.9 + 16 + 18mA)
= 45µA + 0.1 x 42.9
= 45µA + 4.29mA
= 4.34mA
This is the operating power with no Flash memory WRITE or Erase cycles in progress.
Calculation is based on IOUT = 0mA.
79/102
PSD835G2
Table 50. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
= 8 MHz
= 4 MHz
% Flash memory Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down Mode
= 90%
Number of product terms used
(from fitter report)
= 45 PT
% of total product terms
= 45/193 = 23.3%
Turbo Mode
= Off
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE
+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz
+ 0.15 x 1.5mA/MHz x 4 MHz
+ 24mA)
= 45µA + 0.1 x (8 + 0.9 + 24)
= 45µA + 0.1 x 32.9
= 45µA + 3.29mA
= 3.34mA
This is the operating power with no Flash memory WRITE or Erase cycles in progress.
Calculation is based on IOUT = 0mA.
80/102
PSD835G2
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 51. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering (20 seconds max.)1
Min.
Max.
Unit
–65
125
°C
235
°C
VIO
Input and Output Voltage (Q = VOH or Hi-Z)
–0.6
7.0
V
VCC
Supply Voltage
–0.6
7.0
V
VPP
Device Programmer Supply Voltage
–0.6
14.0
V
–2000
2000
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
81/102
PSD835G2
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 52. Operating Conditions
Symbol
VCC
Parameter
Min.
Max.
Unit
Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (industrial)
–40
85
°C
0
70
°C
TA
Ambient Operating Temperature (commercial)
Table 54. AC Signal Behavior Symbols for PLD
Timing
Table 53. AC Signal Letters for PLD Timing
A
Address Input
C
CEout Output
D
Input Data
E
E Input
I
Interrupt Input
L
ALE Input
N
RESET Input or Output
P
Port Signal Output
t
Time
L
Logic Level Low or ALE
H
Logic Level High
V
Valid
X
No Longer a Valid Logic Level
Z
Float
PW
Pulse Width
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.
Q
Output Data
R
UDS, LDS, DS, RD, PSEN Inputs
S
Chip Select Input
T
R/W Input
W
WR Input
B
VSTBY Output
M
Output Macrocell
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.
Table 55. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Load Capacitance
Max.
30
Unit
pF
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 56. Capacitance
Symbol
Parameter
Test Condition
Typ.2
Max.
Unit
CIN
Input Capacitance (for input pins)
VIN = 0V
4
6
pF
COUT
Output Capacitance (for input/
output pins)
VOUT = 0V
8
12
CVPP
Capacitance (for CNTL2/VPP)
VPP = 0V
18
25
Note: 1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
82/102
pF
pF
PSD835G2
Figure 35. AC Measurement I/O Waveform
Figure 36. AC Measurement Load Circuit
2.01 V
195 Ω
3.0V
Test Point
1.5V
Device
Under Test
0V
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI03103b
AI03104b
Figure 37. Switching Waveforms – Key
WAVEFORMS
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
83/102
PSD835G2
Table 57. DC Characteristics
Symbol
Parameter
Test Condition
(in addition to those in
Table 52., page 82)
Min.
Typ.
Max.
Unit
VIH
Input High Voltage
4.5V < VCC < 5.5V
2
VCC +0.5
V
VIL
Input Low Voltage
4.5V < VCC < 5.5V
–0.5
0.8
V
VIH1
Reset High Level Input Voltage
(Note 1)
0.8VCC
VCC + 0.5
V
VIL1
Reset Low Level Input Voltage
(Note 1)
–0.5
0.2VCC –0.1
V
VHYS
Reset Pin Hysteresis
0.3
VLKO
VCC (min) for Flash Erase and
Program
2.5
VOL
Output Low Voltage
0.1
V
IOL = 8mA, VCC = 4.5V
0.25
0.45
V
IOH = –20µA, VCC = 4.5V
4.4
4.49
V
IOH = –2mA, VCC = 4.5V
2.4
3.9
V
IOH1 = –1µA
VSTBY – 0.8
VOH1
Output High Voltage VSTBY On
VSTBY
SRAM Stand-by Voltage
ISTBY
SRAM Stand-by Current
IIDLE
Idle Current (VSTBY input)
VDF
SRAM Data Retention Voltage
ISB
Stand-by Supply Current
for Power-down Mode
CSI > VCC – 0.3V
ILI
Input Leakage Current
VSS < VIN < VCC
ILO
Output Leakage Current
0.45 < VIN < VCC
VCC = 0V
0.5
VCC > VSTBY
–0.1
Only on VSTBY
2
VCC
V
1
µA
0.1
µA
V
100
200
µA
–1
±0.1
1
µA
–10
±5
10
µA
(Notes 2,3,5)
PLD_TURBO = On,
f = 0 MHz
400
700
µA/PT
During Flash memory
WRITE/Erase Only
15
30
mA
Read only, f = 0 MHz
0
0
mA
f = 0 MHz
0
0
mA
Flash memory AC Adder
2.5
3.5
mA/
MHz
SRAM AC Adder
1.5
3.0
mA/
MHz
Operating
Supply
Current
SRAM
PLD AC Base
84/102
2.0
0
Flash memory
Note: 1.
2.
3.
4.
5.
V
PLD_TURBO = Off,
f = 0 MHz (Note 3)
PLD Only
ICC (AC)
(Note5)
V
0.01
Output High Voltage Except
VSTBY On
(Note5)
4.2
IOL = 20µA, VCC = 4.5V
VOH
ICC (DC)
V
µA/PT
Figure 34
(note4)
Reset (Reset) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
CSI deselected or internal Power-down mode is active.
PLD is in non-Turbo mode, and none of the inputs are switching.
Please see Figure 34 for the PLD current calculation.
IOUT = 0mA
PSD835G2
Figure 38. Input to Output Disable / Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Figure 39. Combinatorial Timing – PLD
CPLD INPUT
tPD
CPLD OUTPUT
AI07655
Table 58. CPLD Combinatorial Timing
Symbol
Parameter
Conditions
-70
Min
-90
Max
Min
Max
PT
Aloc
Turbo
Off
Slew
rate1
Unit
+2
+ 12
–2
ns
tPD
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
20
25
tEA
CPLD Input to CPLD Output
Enable
21
26
+ 12
–2
ns
tER
CPLD Input to CPLD Output
Disable
21
26
+ 12
–2
ns
tARP
CPLD Register Clear or
Preset Delay
21
26
+ 12
–2
ns
tARPW
CPLD Register Clear or
Preset Pulse Width
tARD
CPLD Array Delay
10
Any macrocell
20
11
+ 12
16
+2
ns
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
85/102
PSD835G2
Table 59. CPLD Macrocell Synchronous Clock Mode Timing
-70
Symbol
Parameter
Min
Maximum Frequency
External Feedback
fMAX
Maximum Frequency
Internal Feedback (fCNT)
Maximum Frequency
Pipelined Data
-90
Conditions
Max
Min
Max
PT
Aloc
Turbo
Off
Slew
rate1
Unit
1/(tS+tCO)
34.4
30.30
MHz
1/(tS+tCO–10)
52.6
43.48
MHz
1/(tCH+tCL)
83.3
50.00
MHz
tS
Input Setup Time
14
15
tH
Input Hold Time
0
0
ns
tCH
Clock High Time
Clock Input
6
10
ns
tCL
Clock Low Time
Clock Input
6
10
ns
tCO
Clock to Output Delay
Clock Input
15
18
tARD
CPLD Array Delay
Any macrocell
11
16
tMIN
Minimum Clock Period 2
tCH+tCL
12
+2
+ 12
ns
–2
+2
ns
ns
20
ns
Note: 1. Fast Slew Rate output available on Ports C and F.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Table 60. CPLD Macrocell Asynchronous Clock Mode Timing
-70
Symbol
Parameter
Min
fMAXA
-90
Conditions
Max
Min
Max
PT
Aloc
Turbo
Off
Slew
Rate
Unit
Maximum
Frequency
External Feedback
1/(tSA+tCOA)
38.4
26.32
MHz
Maximum
Frequency
Internal Feedback
(fCNTA)
1/(tSA+tCOA–10)
62.5
35.71
MHz
1/(tCHA+tCLA)
47.6
37.3
MHz
Maximum
Frequency
Pipelined Data
tSA
Input Setup Time
6
8
tHA
Input Hold Time
7
12
tCHA
Clock Input High
Time
9
12
+ 12
ns
tCLA
Clock Input Low
Time
12
15
+ 12
ns
tCOA
Clock to Output
Delay
tARDA
CPLD Array Delay
tMINA
Minimum Clock
Period
86/102
Any macrocell
1/fCNTA
16
+2
ns
ns
21
30
11
16
28
+ 12
+ 12
+2
–2
ns
ns
ns
PSD835G2
Figure 40. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
tS
tH
INPUT
tCO
REGISTERED
OUTPUT
AI02860
Figure 41. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 42. Asynchronous Clock Mode Timing (Product Term Clock)
tCHA
tCLA
CLOCK
tSA
tHA
INPUT
tCOA
REGISTERED
OUTPUT
AI02859
87/102
PSD835G2
Figure 43. Input Macrocell Timing (Product Term Clock)
t INH
t INL
PT CLOCK
t IS
t IH
INPUT
OUTPUT
t INO
AI03101
Table 61. Input Macrocell Timing
-70
Symbol
Parameter
-90
Conditions
Min
Max
Min
Max
PT
Aloc
Turbo
Off
Unit
tIS
Input Setup Time
(Note 1)
0
0
tIH
Input Hold Time
(Note 1)
15
20
tINH
NIB Input High Time
(Note 1)
9
12
ns
tINL
NIB Input Low Time
(Note 1)
9
12
ns
tINO
NIB Input to Combinatorial
Delay
(Note 1)
34
ns
+ 12
46
+2
+ 12
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
88/102
ns
ns
PSD835G2
Figure 44. READ Timing
tAVLX
1
tLXAX
ALE /AS
tLVLX
A /D
MULTIPLEXED
BUS
DATA
VALID
ADDRESS
VALID
tAVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLQV
CSI
tRLQV
tRHQX
tRLRH
RD
(PSEN, DS)
tRHQZ
tEHEL
E
tTHEH
tELTL
R/W
tAVPV
ADDRESS OUT
AI02895
Note: 1. tAVLX and tLXAX are not required for 80C51XA in Burst Mode.
89/102
PSD835G2
Table 62. READ Timing
-70
Symbol
Parameter
Min
tLVLX
ALE or AS Pulse Width
tAVLX
Address Setup Time
tLXAX
-90
Conditions
Max
Min
Max
Turbo
Off
Unit
15
20
ns
(Note 3)
4
6
ns
Address Hold Time
(Note 3)
7
8
ns
tAVQV
Address Valid to Data Valid
(Note 3)
tSLQV
CS Valid to Data Valid
70
90
+ 12
ns
75
100
ns
RD to Data Valid 8-Bit Bus
(Note 5)
24
32
ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note 2)
31
38
ns
tRHQX
RD Data Hold Time
(Note 1)
0
0
ns
tRLRH
RD Pulse Width
(Note 1)
27
32
ns
tRHQZ
RD to Data High-Z
(Note 1)
tEHEL
E Pulse Width
27
32
ns
tTHEH
R/W Setup Time to Enable
6
10
ns
tELTL
R/W Hold Time After Enable
0
0
ns
tAVPV
Address Input Valid to
Address Output Delay
tRLQV
Note: 1.
2.
3.
4.
5.
90/102
(Note 4)
20
25
20
RD timing has the same timing as DS and PSEN signals.
RD and PSEN have the same timing.
Any input used to select an internal PSD function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
RD timing has the same timing as DS signal.
25
ns
ns
PSD835G2
Figure 45. WRITE Timing
tAVLX
t LXAX
ALE/AS
t LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLWL
CSI
tDVWH
t WLWH
WR
(DS)
t WHDX
t WHAX
t EHEL
E
t THEH
t ELTL
R/ W
t WLMV
tAVPV
t WHPV
ADDRESS OUT
STANDARD
MCU I/O OUT
AI02896
91/102
PSD835G2
Table 63. WRITE Timing
-70
Symbol
Parameter
Unit
Min
tLVLX
ALE or AS Pulse Width
tAVLX
Address Setup Time
tLXAX
Address Hold Time
tAVWL
Address Valid to Leading
Edge of WR
tSLWL
-90
Conditions
Max
Min
Max
15
20
ns
(Note 1)
4
6
ns
(Note 1)
7
8
ns
(Notes 1,3)
8
15
ns
CS Valid to Leading Edge of WR
(Note 3)
12
15
ns
tDVWH
WR Data Setup Time
(Note 3)
25
35
ns
tWHDX
WR Data Hold Time
(Note 3,7)
4
5
ns
tWLWH
WR Pulse Width
(Note 3)
28
35
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
6
8
ns
tWHAX2
Trailing Edge of WR to DPLD Address
Invalid
(Note 3,6)
0
0
ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
tDVMV
(Note 3)
27
30
ns
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
(Notes 3,5)
42
55
ns
tAVPV
Address Input Valid to Address
Output Delay
(Note 2)
20
25
ns
tWLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes 3,4)
48
55
ns
Note: 1.
2.
3.
4.
5.
6.
7.
92/102
Any input used to select an internal PSD function.
In multiplexed mode, latched address generated from ADIO delay to address output on any port.
WR has the same timing as E and DS signals.
Assuming data is stable before active WRITE signal.
Assuming WRITE is active before data becomes valid.
tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
tWHDX is 6ns when writing to Output Macrocell Registers AB and BC.
PSD835G2
Figure 46. Peripheral I/O Read Timing
ALE/AS
ADDRESS
A/D BUS
DATA VALID
tAVQV (PF)
tSLQV (PF)
CSI
tRLQV (PF)
tQXRH (PF)
tRHQZ (PF)
tRLRH (PF)
RD
tDVQV (PF)
DATA ON PORT F
AI02897b
Table 64. Port F Peripheral Data Mode Read Timing
-70
-90
Turbo
Off
Unit
Max
30
35
+ 12
ns
25
35
+ 12
ns
21
32
ns
RD to Data Valid 8031 Mode
31
38
ns
tDVQV–PF
Data In to Data Out Valid
22
30
ns
tQXRH–PF
RD Data Hold Time
tRLRH–PF
RD Pulse Width
(Note 1)
tRHQZ–PF
RD to Data High-Z
(Note 1)
Symbol
Parameter
Conditions
Min
tAVQV–PF
Address Valid to Data
Valid
tSLQV–PF
CSI Valid to Data Valid
RD to Data Valid
tRLQV–PF
(Note 3)
(Notes 1,4)
Max
Min
0
0
ns
27
32
ns
23
25
ns
93/102
PSD835G2
Figure 47. Peripheral I/O Write Timing
ALE/AS
ADDRESS
A / D BUS
DATA OUT
tWLQV
tWHQZ (PF)
(PF)
WR
tDVQV (PF)
PORT F
DATA OUT
AI02898B
Table 65. Port F Peripheral Data Mode Write Timing
-70
Symbol
Parameter
-90
Conditions
Unit
Min
Max
Min
Max
tWLQV–PF
WR to Data Propagation Delay
(Note 2)
25
35
ns
tDVQV–PF
Data to Port A Data Propagation Delay
(Note 5)
22
30
ns
tWHQZ–PF
WR Invalid to Port A Tri-state
(Note 2)
20
25
ns
Note: 1.
2.
3.
4.
5.
RD has the same timing as DS and PSEN.
WR has the same timing as the E and DS signals.
Any input used to select Port F Data Peripheral mode.
Data is already stable on Port F.
Data stable on ADIO pins to data on Port F.
Table 66. Program, Write and Erase Times
Symbol
Parameter
Min.
Flash Program
Typ.
8.5
1
Flash Bulk Erase (pre-programmed to “00”)
3
Flash Bulk Erase (not pre-programmed)
10
tWHQV3
Sector Erase (pre-programmed)
1
tWHQV2
Sector Erase (not pre-programmed to “00”)
2.2
tWHQV1
Byte Program
14
Program / Erase Cycles (per Sector)
tWHWLO
Sector Erase Time-Out
tQ7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2
Unit
s
30
s
s
30
s
s
1200
100,000
µs
cycles
100
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
94/102
Max.
µs
30
ns
PSD835G2
Table 67. Power-down Timing
-70
Symbol
Parameter
-90
Conditions
Unit
Min
tLVDV
ALE Access Time from Power-down
tCLWH
Maximum Delay from
APD Enable to Internal PDN Valid Signal
Max
Min
Max
80
90
ns
15 * tCLCL1
Using CLKIN (PD1)
µs
Note: 1. tCLCL is the period of CLKIN (PD1).
Figure 48. Reset (RESET) Timing
VCC
VCC(min)
tNLNH-PO
tNLNH
tNLNH-A
Warm Reset
tOPR
Power-On Reset
tOPR
RESET
AI02866b
Table 68. Reset (Reset) Timing
Symbol
Parameter
tNLNH
RESET Active Low Time 1
tNLNH–PO
Conditions
Min
Max
Unit
150
ns
Power On Reset Active Low Time
1
ms
tNLNH–A
Warm Reset 2
25
µs
tOPR
RESET High to Operational Device
120
ns
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ mode.
Table 69. VSTBYON Timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBYON Output High
(Note 1)
20
µs
tBXBL
VSTBY Off Detection to VSTBYON Output Low
(Note 1)
20
µs
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
95/102
PSD835G2
Figure 49. ISC Timing
t ISCCH
TCK
t ISCCL
t ISCPSU
t ISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 70. ISC Timing
-70
Symbol
Parameter
-90
Conditions
Unit
Min
Max
Min
Max
tISCCF
Clock (TCK, PC1) Frequency (except for PLD)
(Note 1)
tISCCH
Clock (TCK, PC1) High Time (except for PLD)
(Note 1)
23
26
ns
tISCCL
Clock (TCK, PC1) Low Time (except for PLD)
(Note 1)
23
26
ns
tISCCFP
Clock (TCK, PC1) Frequency (PLD only)
(Note 2)
tISCCHP
Clock (TCK, PC1) High Time (PLD only)
(Note 2)
240
240
ns
tISCCLP
Clock (TCK, PC1) Low Time (PLD only)
(Note 2)
240
240
ns
tISCPSU
ISC Port Set Up Time
6
8
ns
tISCPH
ISC Port Hold Up Time
5
5
ns
tISCPCO
ISC Port Clock to Output
21
23
ns
tISCPZV
ISC Port High-Impedance to Valid Output
21
23
ns
tISCPVZ
ISC Port Valid Output to
High-Impedance
21
23
ns
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
96/102
20
18
2
2
MHz
MHz
PSD835G2
PACKAGE MECHANICAL
Figure 50. TQFP80 - 80 lead Thin, Quad, Flat Package Outline
D
D1
D2
A2
e
E2 E1 E
Ne
b
N
1
A
Nd
CP
L1
c
QFP-A
A1
α
L
Note: Drawing is not to scale.
97/102
PSD835G2
Table 71. TQFP80 - 80 lead Thin, Quad, Flat Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
A
Typ.
Min.
1.20
Max.
0.047
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
0.17
0.27
0.007
0.011
0.09
0.20
0.004
0.008
—
—
b
0.22
c
98/102
Max.
0.009
D
14.00
0.551
D1
12.00
0.472
D2
9.50
E
14.00
0.551
E1
12.00
0.472
E2
9.50
—
—
0.374
—
—
e
0.50
—
—
0.020
—
—
L
0.60
0.45
0.75
0.024
0.018
0.030
L1
1.00
0.039
CP
0.08
0.003
α
3.5°
0.0°
7.0°
—
0.0°
—
7.0°
0.374
3.5°
N
80
80
Nd
20
20
Ne
20
20
PSD835G2
PART NUMBERING
Table 72. Ordering Information Scheme
Example:
PSD8
3
5
G
2
–
90
U
I
T
Device Type
PSD8 = 8-bit PSD with Register Logic
SRAM Size
3 = 64 Kbit
Flash Memory Size
5 = 4 Mbit (512 Kb x8)
I/O Count
G = 52 I/O
2nd Flash Memory
2 = 256 Kbit (32 Kb x8) Flash Memory
Operating Voltage
blank = VCC = 4.5 to 5.5V
V(1) = VCC = 3.0 to 3.6V
Speed
70 = 70ns
90 = 90ns
Package
U = TQFP80
Temperature Range
blank = 0 to 70°C (Commercial)
I = –40 to 85°C (Industrial)
Shipping Option
T = Tape & Reel Packing
Note: 1. The 3.3V ±10% devices are not covered by this datasheet, but by the PSD835G2V datasheet.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
99/102
PSD835G2
APPENDIX A. PIN ASSIGNMENTS
Table 73. PSD835G2 TQFP80
Pin
Pin No. Assignments
Pin
Pin No. Assignments
Pin No.
Pin
Assignments
Pin
Pin No. Assignments
1
PD2
21
PG0
41
PC0
61
PB0
2
PD3
22
PG1
42
PC1
62
PB1
3
AD0
23
PG2
43
PC2
63
PB2
4
AD1
24
PG3
44
PC3
64
PB3
5
AD2
25
PG4
45
PC4
65
PB4
6
AD3
26
PG5
46
PC5
66
PB5
7
AD4
27
PG6
47
PC6
67
PB6
8
GND
28
PG7
48
PC7
68
PB7
9
VCC
29
VCC
49
GND
69
VCC
10
AD5
30
GND
50
GND
70
GND
11
AD6
31
PF0
51
PA0
71
PE0
12
AD7
32
PF1
52
PA1
72
PE1
13
AD8
33
PF2
53
PA2
73
PE2
14
AD9
34
PF3
54
PA3
74
PE3
15
AD10
35
PF4
55
PA4
75
PE4
16
AD11
36
PF5
56
PA5
76
PE5
17
AD12
37
PF6
57
PA6
77
PE6
18
AD13
38
PF7
58
PA7
78
PE7
19
AD14
39
RESET
59
CNTL0
79
PD0
20
AD15
40
CNTL2
60
CNTL1
80
PD1
100/102
PSD835G2
REVISION HISTORY
Table 74. Document Revision History
Date
Version
01-Mar-2000
1.0
PSD835G2: Document written in the WSI format. Initial release.
1.1
Turbo Off changed from +10 to +12 in Table 58, CPLD Combinatorial Timing, Table 59,
CPLD Macrocell Synchronous Clock Mode Timing, Table 60, CPLD Macrocell
Asynchronous Clock Mode Timing, Table 61, Input Macrocell Timing, Table 62, Read
Timing, Table 64, Port F Peripheral Data Mode Read Timing.
tCO max for 70ns speed class changed from 13 to 15 in Table 59.
tHA min and tCLA min for 70ns speed class changed from 5 to 7 and 9 to 12, respectively
and tCLA min for 90ns speed class changed from 12 to 15 in Table 60.
tLXAX min changed for 70ns speed class changed from 5 to 7 in Table 62.
tLXAX min changed for 70ns speed class changed from 5 to 7, tDVWH min for 70ns speed
class changed from 12 to 25, tWLWH min for 70ns speed class changed from 25 to 28 in
Table 63.
31-Jan-2002
1.2
PSD835G2: Configurable Memory System on a Chip for 8-bit Microcontrollers.
Front page and back two pages in ST format added to the PDF file.
Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST,
Flash+PSD and PSDsoft.
11-Sep-2002
2.0
Document reformatted. No parameters changed.
03-Mar-04
3.0
Document reformatted; mechanical dimensions corrected (Table 71)
30-Nov-2000
Description of Revision
101/102
PSD835G2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequ
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is g
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products a
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
102/102

Open as PDF

Similar pages: STMICROELECTRONICS PSD913F2; STMICROELECTRONICS PSD854F2V; STMICROELECTRONICS PSD953F2V-15MT; STMICROELECTRONICS PSD833F3A; ETC PSD813F3V; STMICROELECTRONICS DSM2180F3V-15; STMICROELECTRONICS DSM2180F3V-15K6; STMICROELECTRONICS DSM2190F4V; STMICROELECTRONICS PSD813F1-A-90MI; STMICROELECTRONICS PSD4235F1V-B-12U; ETC UPSD3333D; STMICROELECTRONICS PSD835G2V-90UI; STMICROELECTRONICS PSD4256G6; STMICROELECTRONICS PSD835F1-A-20U; STMICROELECTRONICS PSD4235G2V; STMICROELECTRONICS PSD4235F1V-B-12MI; STMICROELECTRONICS DSM2150F5V-12T6; STMICROELECTRONICS PSD935F1V; STMICROELECTRONICS PSD954F2-70M; STMICROELECTRONICS PSD813F1A-12JI; STMICROELECTRONICS PSD813F1A; STMICROELECTRONICS PSD9342V20JT