STMICROELECTRONICS PSD833F3A

PSD8XXFX
Flash in-system programmable (ISP)
peripherals for 8-bit MCUs, 5 V
Features
■
Flash in-system programmable (ISP)
peripheral for 8-bit MCUs
■
Dual bank Flash memories
– Up to 2 Mbit of primary Flash memory (8
uniform sectors, 32K x8)
– Up to 256 Kbit secondary Flash memory (4
uniform sectors)
– Concurrent operation: read from one
memory while erasing and writing the other
■
Up to 256 Kbit SRAM
■
27 reconfigurable I/Oports
■
Enhanced JTAG serial port
■
PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
and 24 input macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
■
■
■
PQFP52 (M)
PLCC52 (J)
27 individually configurable I/O port pins
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
open-drain outputs.
TQFP64 (U)
■
Programmable power management
■
Packages are ECOPACK®
Table 1.
In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
full-chip in-system programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
Page register
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
May 2009
Doc ID 7833 Rev 7
Device summary
Reference
Part number
PSD813F2
PSD813F4
PSD813F5
PSD8XXFX
PSD833F2
PSD834F2
PSD853F2
PSD854F2
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www.st.com
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Contents
PSD8XXFX
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6
JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.7
In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8
Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 24
6
Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
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6.1
Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2
Description of primary Flash memory and secondary Flash memory . . . 27
6.3
Memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.1
Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.2
Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3
Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4
Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.5
Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6
Reading the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.7
Data Polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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7.8
Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.9
Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.10
Erase timeout flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3
Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) . . 36
Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.1
Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.3
Reset (RESET) signal (on the PSD83xF2 and PSD85xF2) . . . . . . . . . . . 41
11
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12
Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.2
Memory select configuration for MCUs with separate program and data
spaces 43
12.3
Configuration modes for MCUs with separate program and data spaces 44
12.3.1
Separate Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.3.2
Combined Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
14
PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1
The Turbo Bit in PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.2
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
14.3
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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PSD8XXFX
14.4
Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.5
Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.6
Loading and reading the Output macrocells (OMC) . . . . . . . . . . . . . . . . . 54
14.7
The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.8
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.9
Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.1
PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.2
PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 60
15.3
Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.4
MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
15.5
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
15.6
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
15.7
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
15.8
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
16.1
General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
16.2
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
16.3
MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16.4
PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16.5
Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16.6
Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.7
Data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.8
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.9
JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.10 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.11 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.12 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.13 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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16.17 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.18 Input macro (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
16.19 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.20 Ports A and B – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . 75
16.21 Port C – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.23 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17
18
19
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.1
Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 80
17.2
For users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
17.3
Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
17.4
PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.5
PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
17.6
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
17.7
Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 85
18.1
Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
18.2
Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
18.3
I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 85
18.4
Reset of Flash memory erase and program cycles (on the PSD834Fx) . 85
Programming in-circuit using the JTAG serial interface . . . . . . . . . . . 87
19.1
Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
19.2
JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
19.3
Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
20
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
21
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
22
AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
23
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Appendix A PQFP52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Appendix B PLCC52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Appendix C TQFP64 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PLCC52 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
JTAG SIgnals on port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Methods for programming different functional blocks of the PSD. . . . . . . . . . . . . . . . . . . . 22
I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Sector Protection/Security Bit definition – Flash Protection register. . . . . . . . . . . . . . . . . . 41
Sector Protection/Security Bit definition – PSD/EE Protection register . . . . . . . . . . . . . . . 41
VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MCUs and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
80C251 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O port Latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Port configuration registers (PCR)t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port Pin Direction Control, Output Enable P.T. not defined . . . . . . . . . . . . . . . . . . . . . . . . 73
Port Pin Direction Control, Output Enable P.T. defined . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port Direction assignment example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Power-down mode’s effect on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PSD timing and standby current during Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 81
Power Management mode registers PMMR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Power Management mode registers PMMR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Status during Power-on reset, Warm reset and Power-down mode. . . . . . . . . . . . . . . . . . 86
JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Example of PSD typical power calculation at VCC=5.0 V (Turbo mode on) . . . . . . . . . . . . 93
Example of PSD typical power calculation at VCC = 5.0 V (Turbo mode off) . . . . . . . . . . . 94
Operating conditions (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Operating conditions (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AC signal letters for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
AC signal behavior symbols for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
DC characteristics (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DC Characteristics (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
CPLD combinatorial timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
8/128
PSD8XXFX
CPLD combinatorial timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
CPLD macrocell Synchronous clock mode timing (5 V devices) . . . . . . . . . . . . . . . . . . . 101
CPLD macrocell synchronous clock mode timing (3 V devices). . . . . . . . . . . . . . . . . . . . 102
CPLD macrocell asynchronous clock mode timing (5 V devices). . . . . . . . . . . . . . . . . . . 103
CPLD macrocell Asynchronous clock mode timing (3 V devices) . . . . . . . . . . . . . . . . . . 104
Input macrocell timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
input macrocell timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
READ timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
READ timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
WRITE timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
WRITE timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Program, WRITE and Erase times (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Program, WRITE and Erase times (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Port A Peripheral Data mode READ timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . 111
Port A Peripheral Data mode READ timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . 112
Port A Peripheral Data mode WRITE timing (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . 112
Port A Peripheral Data mode WRITE timing (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . 113
Reset (RESET) timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset (RESET) timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ISC timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ISC timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Power-down timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Power-down timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PQFP52 - 52-pin plastic quad flat package mechanical dimensions . . . . . . . . . . . . . . . . 117
PLCC52-52-lead plastic lead chip carrier mechanical dimensions . . . . . . . . . . . . . . . . . . 118
TQFP64 - 64-lead thin quad flatpack, package mechanical data . . . . . . . . . . . . . . . . . . . 119
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PQFP52 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PLCC52 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
TQFP64 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Doc ID 7833 Rev 7
PSD8XXFX
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
PQFP52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PLCC52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TQFP64 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PSDsoft Express development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8031 memory modules – separate space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8031 memory modules – combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Macrocell and I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CPLD Output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
An example of a typical 8-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
An example of a typical 8-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . . 61
Interfacing the PSD with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interfacing the PSD with the 80C251, with One READ input . . . . . . . . . . . . . . . . . . . . . . . 63
Interfacing the PSD with the 80C251, with RD and PSEN inputs. . . . . . . . . . . . . . . . . . . . 64
Interfacing the PSD with the 80C51X, 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interfacing the PSD with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Port A and port B structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Port C structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Port D external Chip Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Enable Power-down flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PLD ICC /frequency consumption (5 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PLD ICC /frequency consumption (3 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Switching waveforms – key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Input to output disable / enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Synchronous clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Asynchronous Clock mode Timing (product term clock). . . . . . . . . . . . . . . . . . . . . . . . . . 103
Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Peripheral I/O READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Peripheral I/O WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Doc ID 7833 Rev 7
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List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
10/128
PSD8XXFX
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
PQFP52 - 52-pin plastic quad flat package mechanical drawing . . . . . . . . . . . . . . . . . . . 117
PLCC52 - 52-lead plastic lead chip carrier package mechanical drawing . . . . . . . . . . . . 118
TQFP64 - 64-lead thin quad flatpack, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Doc ID 7833 Rev 7
PSD8XXFX
1
Summary description
Summary description
The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings in-systemprogrammability (ISP) to Flash memory and programmable logic. The result is a simple and
flexible solution for embedded designs. PSD devices combine many of the peripheral
functions found in MCU based applications.
Table 2 summarizes all the devices.
The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD
macrocell was created to address the unique requirements of embedded system designs. It
allows direct connection between the system address/data bus, and the internal PSD
registers, to simplify communication between the MCU and other supporting devices.
The PSD device includes a JTAG serial programming interface, to allow in-system
programming (ISP) of the entire device. This feature reduces development time, simplifies
the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s
special Fast-JTAG programming, a design can be rapidly programmed into the PSD in as
little as seven seconds.
The innovative PSD8XXFX family solves key problems faced by designers when managing
discrete Flash memory devices, such as:
●
First-time in-system programming (ISP)
●
Complex address decoding
●
Simultaneous read and write to the device.
The JTAG Serial Interface block allows in-system programming (ISP), and eliminates the
need for an external Boot EPROM, or an external programmer. To simplify Flash memory
updates, program execution is performed from a secondary Flash memory while the primary
Flash memory is being updated. This solution avoids the complicated hardware and
software overhead necessary to implement IAP.
ST makes available a software development tool, PSDsoft™ Express, that generates ANSIC compliant code for use with your target MCU. This code allows you to manipulate the nonvolatile memory (NVM) within the PSD. Code examples are also provided for:
Table 2.
●
Flash memory IAP via the UART of the host MCU
●
Memory paging to execute code across several PSD memory pages
●
Loading, reading, and manipulation of PSD macrocells by the MCU.
Product range
Primary Flash
memory
Secondary
Flash memory
(8 sectors)
(4 sectors)
PSD813F2
1 Mbit
256 Kbit
16 Kbit
PSD813F4
1 Mbit
256 Kbit
PSD813F5
1 Mbit
PSD833F2
PSD834F2
Part
number(1)
SRAM
I/O
ports
Number of
macrocells
Serial ISP
JTAG/ISC
port
Turbo
mode
Input
Output
27
24
16
yes
yes
none
27
24
16
yes
yes
none
none
27
24
16
yes
yes
1 Mbit
256 Kbit
64 Kbit
27
24
16
yes
yes
2 Mbit
256 Kbit
64 Kbit
27
24
16
yes
yes
Doc ID 7833 Rev 7
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Summary description
Table 2.
PSD8XXFX
Product range (continued)
Primary Flash
memory
Secondary
Flash memory
(8 sectors)
(4 sectors)
PSD853F2
1 Mbit
256 Kbit
256 Kbit
PSD854F2
2 Mbit
256 Kbit
256 Kbit
(1)
Part number
SRAM
Number of
macrocells
I/O
ports
Serial ISP
JTAG/ISC
port
Turbo
mode
Input
Output
27
24
16
yes
yes
27
24
16
yes
yes
1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power
Management Unit (PMU), Automatic Power-down (APD)
40 CNTLO
41 RESET
42 CNTL2
43 CNTL1
44 PB7
45 PB6
46 GND
47 PB5
48 PB4
49 PB3
50 PB2
51 PB1
52 PB0
PQFP52 connections
29 AD6
PC1 12
28 AD5
PC0 13
27 AD4
AD3 26
PC2 11
AD2 25
30 AD7
AD1 24
31 VCC
PC3 10
AD0 23
32 AD8
GND 9
PA0 22
33 AD9
VCC 8
PA1 21
34 AD10
PC4 7
PA2 20
35 AD11
PC5 6
GND 19
36 AD12
PC6 5
PA3 18
37 AD13
PC7 4
PA4 17
38 AD14
PD0 3
PA5 16
39 AD15
PD1 2
PA7 14
PD2 1
PA6 15
Figure 1.
AI02858
12/128
Doc ID 7833 Rev 7
PSD8XXFX
Summary description
PB7
CNTL1
CNTL2
RESET
CNTL0
PB5
PB6
PB4
GND
PB3
47
PB2
48
PB1
49
2
50
3
51
4
52
5
1
PD1
6
8
7
PD2
PB0
PLCC52 connections
37
AD7
PC2
18
36
AD6
PC1
19
35
AD5
PC0
20
34
AD4
33
17
AD2
PC3
AD3
VCC
32
38
31
AD8
16
AD1
39
GND
30
AD9
AD0
40
15
29
PC4
VCC
PA0
AD10
28
41
14
PA1
13
27
PC5
PA2
AD11
GND
42
26
AD12
12
25
43
PC6
PA3
AD13
11
24
44
PC7
PA4
PD0
23
AD14
PA5
45
10
PA6
9
22
AD15
21
46
PA7
Figure 2.
Doc ID 7833 Rev 7
AI02857
13/128
Summary description
49 NC
50 RESET
51 CNTL2
52 CNTL1
53 PB7
54 PB6
55 GND
56 GND
57 PB5
58 PB4
59 PB3
60 PB2
61 PB1
62 PB0
63 NC
64 NC
TQFP64 connections
35 AD5
PC0 15
34 AD4
16
33 AD3
NC 17
NC
AD2 32
36 AD6
PC1 14
ND 31
37 AD7
PC2 13
AD1 30
38 VCC
PC3 12
AD0 29
39 VCC
GND 11
PA0 28
40 AD8
GND 10
PA1 27
41 AD9
VCC 9
PA2 26
42 AD10
VCC 8
GND 25
43 AD11
PC4 7
GND 24
44 AD12
PC5 6
PA3 23
45 AD13
PC6 5
PA4 22
46 AD14
PC7 4
PA5 21
47 AD15
PD0 3
PA6 20
48 CNTL0
PD1 2
PA7 19
PD2 1
NC 18
Figure 3.
PSD8XXFX
AI09645b
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Doc ID 7833 Rev 7
PSD8XXFX
Pin description
2
Pin description
Table 3.
PLCC52 pin description (1)
Pin name
ADIO0-7
ADIO8-15
CNTL0
CNTL1
Pin
30-37
39-46
47
50
Type
Description
I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.
If your MCU does not have a multiplexed address/data bus, or you are using an 80C251
in page mode, connect A0-A7 to this port.
If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks was selected. The addresses on this port
are passed to the PLDs.
I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.
If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port.
If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks was selected. The addresses on this port
are passed to the PLDs.
I
The following control signals can be connected to this port, based on your MCU:
WR – active low Write Strobe input.
R_W – active high READ/active low write input.
This port is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
I
The following control signals can be connected to this port, based on your MCU:
RD – active low Read Strobe input.
E – E clock input.
DS – active low Data Strobe input.
PSEN – connect PSEN to this port when it is being used as an active low READ signal.
For example, when the 80C251 outputs more than 16 address bits, PSEN is actually
the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode
and other logic equations.
CNTL2
49
I
This port can be used to input the PSEN (Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.
Reset
48
I
Resets I/O ports, PLD macrocells and some of the Configuration registers. Must be low
at Power-up.
Doc ID 7833 Rev 7
15/128
Pin description
Table 3.
Pin name
PLCC52 pin description (1) (continued)
Pin
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
PC0
PC1
PC2
16/128
PSD8XXFX
20
19
18
Type
Description
I/O
These pins make up port A. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see Table 7).
Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
D0/A16-D3/A19 in M37702M2 mode.
Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate.
However, PA4-PA7 can be configured as CMOS or Open Drain outputs.
I/O
These pins make up port B. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see Table 7).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.
However, PB4-PB7 can be configured as CMOS or Open Drain outputs.
I/O
PC0 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC0) output.
Input to the PLDs.
TMS input(2) for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
I/O
PC1 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC1) output.
Input to the PLDs.
TCK input(2) for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
I/O
PC2 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC2) output.
Input to the PLDs.
This pin can be configured as a CMOS or Open Drain output.
Doc ID 7833 Rev 7
PSD8XXFX
Table 3.
Pin name
PC3
PC4
PC5
PC6
PC7
PD0
PD1
Pin description
PLCC52 pin description (1) (continued)
Pin
17
14
13
12
11
10
9
Type
Description
I/O
PC3 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC3) output.
Input to the PLDs.
TSTAT output(2) for the JTAG Serial Interface.
Ready/Busy output for parallel in-system programming (ISP).
This pin can be configured as a CMOS or Open Drain output.
I/O
PC4 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC4) output.
Input to the PLDs.
TERR output(2) for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
I/O
PC5 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC5) output.
Input to the PLDs.
TDI input(2) for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
I/O
PC6 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC6) output.
Input to the PLDs.
TDO output(2) for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
I/O
PC7 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC7) output.
Input to the PLDs.
DBE – active low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.
I/O
PD0 pin of port D. This port pin can be configured to have the following functions:
ALE/AS input latches address output from the MCU.
MCU I/O – write or read from a standard output or input port.
Input to the PLDs.
CPLD output (External Chip Select).
I/O
PD1 pin of port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Input to the PLDs.
CPLD output (External Chip Select).
CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and
the CPLD AND Array.
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Pin description
Table 3.
Pin name
PSD8XXFX
PLCC52 pin description (1) (continued)
Pin
Type
I/O
Description
PD2 pin of port D. This port pin can be configured to have the following functions:
MCU I/O - write to or read from a standard output or input port.
Input to the PLDs.
CPLD output (External Chip Select).
PSD Chip Select input (CSI). When low, the MCU can access the PSD memory and
I/O. When high, the PSD memory blocks are disabled to conserve power.
PD2
8
VCC
15, 38
Supply voltage
GND
1, 16,
26
Ground pins
1. The pin numbers in this table are for the PLCC package only. See the package information from Table 73 onwards, for pin
numbers on other package types.
2. These functions can be multiplexed with other functions.
18/128
Doc ID 7833 Rev 7
AD0 – AD15
CNTL0,
CNTL1,
CNTL2
Doc ID 7833 Rev 7
CLKIN
(PD1)
GLOBAL
CONFIG. &
SECURITY
ADIO
PORT
PROG.
MCU BUS
INTRF.
CLKIN
73
8
CSIOP
CLKIN
256 KBIT SRAM
256 KBIT SECONDARY
NON-VOLATILE MEMORY
(BOOT OR DATA)
4 SECTORS
3 EXT CS TO PORT D
JTAG
SERIAL
CHANNEL
PORT A ,B & C
24 INPUT MACROCELLS
PORT A ,B & C
16 OUTPUT MACROCELLS
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
8 SECTORS
1 OR 2 MBIT PRIMARY
FLASH MEMORY
RUNTIME CONTROL
AND I/O REGISTERS
PERIP I/O MODE SELECTS
SRAM SELECT
SECTOR
SELECTS
FLASH ISP CPLD
(CPLD)
FLASH DECODE
PLD (DPLD)
SECTOR
SELECTS
EMBEDDED
ALGORITHM
MACROCELL FEEDBACK OR PORT INPUT
73
PAGE
REGISTER
PORT
D
PROG.
PORT
PORT
C
PROG.
PORT
PORT
B
PROG.
PORT
PORT
A
PROG.
PORT
PD0 – PD2
PC0 – PC7
PB0 – PB7
PA0 – PA7
Figure 4.
PLD
INPUT
BUS
ADDRESS/DATA/CONTROL BUS
PSD8XXFX
Pin description
PSD block diagram
AI02861f
19/128
PSD architectural overview
3
PSD8XXFX
PSD architectural overview
PSD devices contain several major functional blocks. Figure 4 shows the architecture of the
PSD device family. The functions of each block are described briefly in the following
sections. Many of the blocks perform multiple functions and are user configurable.
3.1
Memory
Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed
discussion can be found in Section 6.1: Memory blocks.
The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash memory is the primary memory of the
PSD. It is divided into 8 equally-sized sectors that are individually selectable.
The optional 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized
sectors. Each sector is individually selectable.
The optional SRAM is intended for use as a scratch-pad memory or as an extension to the
MCU SRAM.
Each sector of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
3.2
Page register
The 8-bit Page register expands the address range of the MCU by up to 256 times. The
paged address can be used as part of the address space to access external memory and
peripherals, or internal memory and I/O. The Page register can also be used to change the
address mapping of sectors of the Flash memories into different memory spaces for IAP.
3.3
PLDs
The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 4, each optimized for a different function. The functional partitioning of the
PLDs reduces power consumption, optimizes cost/performance, and eases design entry.
The DPLD is used to decode addresses and to generate Sector Select signals for the PSD
internal memory and registers. The DPLD has combinatorial outputs. The CPLD has 16
Output macrocells (OMC) and 3 combinatorial outputs. The PSD also has 24 input
macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their
inputs from the PLD input bus and are differentiated by their output destinations, number of
product terms, and macrocells.
The PLDs consume minimal power. The speed and power consumption of the PLD is
controlled by the Turbo Bit in PMMR0 and other bits in the PMMR2. These registers are set
by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the
power management features.
20/128
Doc ID 7833 Rev 7
PSD8XXFX
3.4
PSD architectural overview
I/O ports
The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B,
C, and D). Each I/O pin can be individually configured for different functions. ports can be
configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using
multiplexed address/data buses.
The JTAG pins can be enabled on port C for in-system programming (ISP).
Ports A and B can also be configured as a data port for a non-multiplexed bus.
3.5
MCU bus interface
PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed
address/data buses. The device is configured to respond to the MCU control signals, which
are also used as inputs to the PLDs. For examples, please see Section 15.4: MCU bus
interface examples.
Table 4.
PLD I/O
Name
3.6
Inputs
Outputs
Product terms
Decode PLD (DPLD)
73
17
42
Complex PLD (CPLD)
73
19
140
JTAG port
In-system programming (ISP) can be performed through the JTAG signals on port C. This
serial interface allows complete programming of the entire PSD device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on port C. Table 5 indicates the JTAG pin assignments.
3.7
In-system programming (ISP)
Using the JTAG signals on port C, the entire PSD device can be programmed or erased
without the use of the MCU. The primary Flash memory can also be programmed in-system
by the MCU executing the programming algorithms out of the secondary memory, or SRAM.
The secondary memory can be programmed the same way by executing out of the primary
Flash memory. The PLD or other PSD configuration blocks can be programmed through the
JTAG port or a device programmer. Table 6 indicates which programming methods can
program different functional blocks of the PSD.
3.8
Power management unit (PMU)
The power management unit (PMU) gives the user control of the power consumption on
selected functional blocks based on system requirements. The PMU includes an Automatic
Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD unit
has a Power-down mode that helps reduce power consumption.
Doc ID 7833 Rev 7
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PSD architectural overview
PSD8XXFX
The PSD also has some bits that are configured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches
its outputs and goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD
to reduce power consumption. Please see Section 17: Power management for more details.
Table 5.
JTAG SIgnals on port C
Port C pins
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Table 6.
Methods for programming different functional blocks of the PSD
Functional block
22/128
JTAG signal
JTAG
programming
Device
programmer
IAP
Primary Flash memory
Yes
Yes
Yes
Secondary Flash memory
Yes
Yes
Yes
PLD array (DPLD and CPLD)
Yes
Yes
No
PSD configuration
Yes
Yes
No
Doc ID 7833 Rev 7
PSD8XXFX
4
Development system
Development system
The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software
development tool. A PSD design is quickly and easily produced in a point and click
environment. The designer does not need to enter Hardware Description Language (HDL)
equations, unless desired, to define PSD pin functions and memory map information. The
general design flow is shown in Figure 5. PSDsoft Express is available from our web site
(the address is given on the back page of this data sheet) or other distribution channels.
PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers may be purchased through your local
distributor/representative, or directly from our web site using a credit card. The PSD is also
supported by third party device programmers. See our web site for the current list.
Figure 5.
PSDsoft Express development tool
PSDabel
PLD DESCRIPTION
MODIFY ABEL TEMPLATE FILE
OR GENERATE NEW FILE
PSD Configuration
PSD TOOLS
CONFIGURE MCU BUS
INTERFACE AND OTHER
PSD ATTRIBUTES
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
PSD Fitter
LOGIC SYNTHESIS
AND FITTING
FIRMWARE
ADDRESS TRANSLATION
AND MEMORY MAPPING
HEX OR S-RECORD
FORMAT
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
PSD Simulator
PSD Programmer
PSDsilos III
DEVICE SIMULATION
(OPTIONAL)
PSDPro, or
FlashLINK (JTAG)
*.OBJ AND *.SVF
FILES AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
AI04918
Doc ID 7833 Rev 7
23/128
PSD register description and address offset
5
PSD8XXFX
PSD register description and address offset
Table 7 shows the offset addresses to the PSD registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD registers. Table 8 provides brief descriptions of the registers in CSIOP space.
The following section gives a more detailed description.
I/O port latched address output assignments(1)(2)
Table 7.
Port A
Port B
MCU
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
N/A
Address a7-a4
Address a11-a8
N/A
80C251 (page mode)
N/A
N/A
Address a11-a8
Address a15a12
All other 8-bit multiplexed
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
8-bit non-multiplexed bus
N/A
N/A
Address a3-a0
Address a7-a4
1. See Section 16: I/O ports, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 8.
Register
name
Port A Port B Port C Port D
(1)
11
Description
Reads port pin as input, MCU I/O input
mode
00
01
Control
02
03
Data Out
04
05
12
13
Stores data for output to port pins, MCU
I/O output mode
Direction
06
07
14
15
Configures port pin as input or output
Drive Select
08
09
16
17
Configures port pins as either CMOS or
Open Drain on some pins, while selecting
high slew rate on other pins.
Input
macrocell
0A
0B
18
Enable Out
0C
0D
1A
Output
macrocells
AB
20
20
21
10
Other
Data In
Output
macrocells
BC
24/128
Register address offset
Selects mode between MCU I/O or
Address Out
Reads input macrocells
1B
Reads the status of the output enable to
the I/O port driver
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
21
Doc ID 7833 Rev 7
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
PSD8XXFX
PSD register description and address offset
Table 8.
Register address offset (continued)
Register
name
Mask
macrocells
AB
Mask
macrocells
BC
Port A Port B Port C Port D
22
Other
Blocks writing to the Output macrocells
AB
22
23
Description
(1)
Blocks writing to the Output macrocells
BC
23
Primary Flash
Protection
C0
Read only – Primary Flash Sector
Protection
Secondary
Flash memory
Protection
C2
Read only – PSD Security and Secondary
Flash memory Sector Protection
JTAG Enable
C7
Enables JTAG port
PMMR0
B0
Power Management register 0
PMMR2
B4
Power Management register 2
Page
E0
Page register
VM
E2
Places PSD memory areas in program
and/or data space on an individual basis.
1. Other registers that are not part of the I/O ports.
Doc ID 7833 Rev 7
25/128
Detailed operation
6
PSD8XXFX
Detailed operation
As shown in Figure 4, the PSD consists of six major types of functional blocks:
●
Memory blocks
●
PLD blocks
●
MCU bus interface
●
I/O ports
●
Power management unit (PMU)
●
JTAG interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
6.1
Memory blocks
The PSD has the following memory blocks:
●
Primary Flash memory
●
Optional Secondary Flash memory
●
Optional SRAM
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are
user-defined in PSDsoft Express.
Table 9.
Memory block size and organization
Primary Flash memory
Sector
number
26/128
Secondary Flash
memory
SRAM
Sector size
(Kbytes)
Sector
select
signal
Sector size
(Kbytes)
Sector
select
signal
SRAM size
(Kbytes)
SRAM
select
signal
0
32
FS0
16
CSBOOT0
256
RS0
1
32
FS1
16
CSBOOT1
2
32
FS2
16
CSBOOT2
3
32
FS3
16
CSBOOT3
4
32
FS4
5
32
FS5
6
32
FS6
7
32
FS7
Total
512
8 sectors
64
4 sectors
Doc ID 7833 Rev 7
256
PSD8XXFX
6.2
Detailed operation
Description of primary Flash memory and secondary Flash
memory
The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash
memory is divided into four equal sectors. Each sector of either memory block can be
separately protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be
suspended while data is read from other sectors of the block and then resumed after
reading.
During a program or erase cycle in Flash memory, the status can be output on Ready/Busy
(PC3). This pin is set up using PSDsoft Express Configuration.
6.3
Memory block select signals
The DPLD generates the Select signals for all the internal memory blocks (see Section 14:
PLDS). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three
product terms. Having three product terms for each Select signal allows a given sector to be
mapped in different areas of system memory. When using a MCU with separate program
and data space, these flexible Select signals allow dynamic re-mapping of sectors from one
memory space to the other.
6.3.1
Ready/Busy (PC3)
This signal can be used to output the Ready/Busy status of the PSD. The output on
Ready/Busy (PC3) is a 0 (Busy) when Flash memory is being written to, or when Flash
memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in
progress.
6.3.2
Memory operation
The primary Flash memory and secondary Flash memory are addressed through the MCU
bus interface. The MCU can access these memories in one of two ways:
●
The MCU can execute a typical bus WRITE or READ operation just as it would if
accessing a RAM or ROM device using standard bus cycles.
●
The MCU can execute a specific instruction that consists of several WRITE and READ
operations. This involves writing specific data patterns to special addresses within the
Flash memory to invoke an embedded algorithm. These instructions are summarized in
Table 10.
Typically, the MCU can read Flash memory using READ operations, just as it would read a
ROM device. However, Flash memory can only be altered using specific Erase and Program
instructions. For example, the MCU cannot write a single byte directly to Flash memory as it
would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a
Program instruction, then test the status of the Program cycle. This status test is achieved
by a READ operation or polling Ready/Busy (PC3).
Flash memory can also be read by using special instructions to retrieve particular Flash
device information (sector protect status and ID).
Doc ID 7833 Rev 7
27/128
Detailed operation
Table 10.
PSD8XXFX
Instructions (1)(2)(3)
Instruction
FS0-FS7 or
CSBOOT0CSBOOT3
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
[email protected]
next SA
(4)
READ(5)
1
“READ”
RD @ RA
Read Main
Flash ID(6)
1
[email protected]
X555h
[email protected]
XAAAh
[email protected]
X555h
Read identifier
(A6,A1,A0 = 0,0,1)
1
[email protected]
X555h
[email protected]
XAAAh
[email protected]
X555h
Read identifier
(A6,A1,A0 = 0,1,0)
Program a
Flash Byte(8)
1
[email protected]
X555h
[email protected]
XAAAh
[email protected]
X555h
[email protected] PA
Flash Sector
Erase(9)(8)
1
[email protected]
X555h
[email protected]
XAAAh
[email protected]
X555h
[email protected] X555h
[email protected]
XAAAh
[email protected]
SA
Flash Bulk
Erase(8)
1
[email protected]
X555h
[email protected]
XAAAh
[email protected]
X555h
[email protected] X555h
[email protected]
XAAAh
[email protected]
X555h
Suspend
Sector
Erase(10)
1
[email protected]
XXXXh
Resume
Sector
Erase(11)
1
[email protected]
XXXXh
Reset(6)
1
[email protected]
XXXXh
Unlock Bypass
1
[email protected]
X555h
[email protected]
XAAAh
[email protected]
X555h
Unlock Bypass
Program(12)
1
[email protected]
XXXXh
[email protected] PA
Unlock Bypass
Reset(13)
1
[email protected]
XXXXh
[email protected]
XXXXh
Read Sector
Protection(6)(7)
(8)
1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label
2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR,
CNTL0). PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to
be erased, or verified, must be Active (high).
3. Only address bits A11-A0 are used in instruction decoding.
4. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active high, and are defined in PSDsoft Express.
5. No Unlock or instruction cycles are required when the device is in the READ mode
6. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector
Protection Status, or if the Error flag bit (DQ5/DQ13) goes high.
7. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active,
and (A1,A0)=(1,0)
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Detailed operation
8. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the
instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the
Sector Protection Status of the primary Flash memory.
9. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs.
10. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection
Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase
cycle.
11. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
12. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
13. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock
Bypass mode.
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Instructions
7
PSD8XXFX
Instructions
An instruction consists of a sequence of specific operations. Each received byte is
sequentially decoded by the PSD and not executed as a standard WRITE operation. The
instruction is executed when the correct number of bytes are properly received and the time
between two consecutive bytes is shorter than the timeout period. Some instructions are
structured to include READ operations after the initial WRITE operations.
The instruction must be followed exactly. Any invalid combination of instruction bytes or
timeout between two consecutive bytes while addressing Flash memory resets the device
logic into READ mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in Table 10:
Flash memory:
●
Erase memory by chip or sector
●
Suspend or resume sector erase
●
Program a Byte
●
Reset to READ mode
●
Read primary Flash Identifier value
●
Read Sector Protection Status
●
Bypass (on the PSD833F2, PSD834F2, PSD853F2 and PSD854F2)
These instructions are detailed in Table 10. For efficient decoding of the instructions, the first
two bytes of an instruction are the coded cycles and are followed by an instruction byte or
confirmation byte. The coded cycles consist of writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle. Address
signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the
appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have the same instruction set (except for Read
Primary Flash Identifier). The Sector Select signals determine which Flash memory is to
receive and execute the instruction. The primary Flash memory is selected if any one of
Sector Select (FS0-FS7) is high, and the secondary Flash memory is selected if any one of
Sector Select (CSBOOT0-CSBOOT3) is high.
7.1
Power-up mode
The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7
and CSBOOT0-CSBOOT3) must be held low, and Write Strobe (WR, CNTL0) high, during
Power-up for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of Write Strobe (WR, CNTL0). Any WRITE cycle initiation is
locked when VCC is below VLKO.
7.2
READ
Under typical conditions, the MCU may read the primary Flash memory or the secondary
Flash memory using READ operations just as it would a ROM or RAM device. Alternately,
the MCU may use READ operations to obtain status information about a program or erase
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Instructions
cycle that is currently in progress. Lastly, the MCU may use instructions to read special data
from these memory blocks. The following sections describe these READ functions.
7.3
Read memory contents
Primary Flash memory and secondary Flash memory are placed in the READ mode after
Power-up, chip reset, or a Reset Flash instruction (see Table 10). The MCU can read the
memory contents of the primary Flash memory or the secondary Flash memory by using
READ operations any time the READ operation is not part of an instruction.
7.4
Read Primary Flash Identifier
The primary Flash memory identifier is read with an instruction composed of 4 operations: 3
specific WRITE operations and a READ operation (see Table 10). During the READ
operation, address bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate
Sector Select (FS0-FS7) must be high. The identifier for the PSD813F2/3/4/5 is E4h, and for
the PSD83xF2 or PSD85xF2 it is E7h.
7.5
Read Memory Sector Protection status
The primary Flash memory Sector Protection Status is read with an instruction composed of
4 operations: 3 specific WRITE operations and a READ operation (see Table 10). During the
READ operation, address Bits A6, A1, and A0 must be '0,1,0,' respectively, while Sector
Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose
protection has to be verified. The READ operation produces 01h if the Flash memory sector
is protected, or 00h if the sector is not protected.
The sector protection status for all NVM blocks (primary Flash memory or secondary Flash
memory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O
space. See Section 10.1: Flash Memory Sector Protect for register definitions.
7.6
Reading the Erase/Program Status bits
The PSD provides several status bits to be used by the MCU to confirm the completion of an
Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU
spends performing these tasks and are defined in Table 11. The status bits can be read as
many times as needed.
For Flash memory, the MCU can perform a READ operation to obtain these status bits while
an Erase or Program instruction is being executed by the embedded algorithm. See
Section 8: Programming Flash memory for details.
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Instructions
Table 11.
PSD8XXFX
Status bits(1)(2)(3)
Functional
block
Flash memory
FS0FS7/CSBOOT0CSBOOT3
VIH
DQ7
DQ6
Data
Polling
Toggle
flag
DQ5
Error
flag
DQ4
X
DQ3
Erase
X
timeout
DQ2
DQ1
X
DQ0
X
1. X = Not guaranteed value, can be read either '1' or ’0.’
2. DQ7-DQ0 represent the data bus bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3 are active high.
7.7
Data Polling flag (DQ7)
When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the
complement of the bit being entered for programming/writing on the DQ7 Bit. Once the
Program instruction or the WRITE operation is completed, the true logic value is read on the
Data Polling flag bit (DQ7, in a READ operation).
7.8
●
Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after
the sixth WRITE pulse (for an Erase instruction). It must be performed at the address
being programmed or at an address within the Flash memory sector being erased.
●
During an Erase cycle, the Data Polling flag bit (DQ7) outputs a ’0.’ After completion of
the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a '1' after
erasing).
●
If the byte to be programmed is in a protected Flash memory sector, the instruction is
ignored.
●
If all the Flash memory sectors to be erased are protected, the Data Polling flag bit
(DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte.
No erasure is performed.
Toggle flag (DQ6)
The PSD offers another way for determining when the Flash memory Program cycle is
completed. During the internal WRITE operation and when either the FS0-FS7 or
CSBOOT0-CSBOOT3 is true, the Toggle flag bit (DQ6) toggles from '0' to '1' and '1' to '0' on
subsequent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling stops and the data read on the data bus
D0-D7 is the addressed memory byte. The device is now accessible for a new READ or
WRITE operation. The cycle is finished when two successive READs yield the same output
data.
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●
The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for an Erase instruction).
●
If the byte to be programmed belongs to a protected Flash memory sector, the
instruction is ignored.
●
If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit
(DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte.
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7.9
Instructions
Error flag (DQ5)
During a normal program or erase cycle, the Error flag bit (DQ5) is to ’0.’ This bit is set to '1'
when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase
cycle.
In the case of Flash memory programming, the Error flag bit (DQ5) indicates the attempt to
program a Flash memory bit from the programmed state, ’0,’ to the erased state, '1,' which is
not valid. The Error flag bit (DQ5) may also indicate a timeout condition while attempting to
program a byte.
In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash
memory sector in which the error occurred or to which the programmed byte belongs must
no longer be used. Other Flash memory sectors may still be used. The Error flag bit (DQ5)
is reset after a Reset Flash instruction.
7.10
Erase timeout flag (DQ3)
The Erase timeout flag bit (DQ3) reflects the timeout period allowed between two
consecutive Sector Erase instructions. The Erase timeout flag bit (DQ3) is reset to '0' after a
Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase
instruction is decoded. After this time period, or when the additional Sector Erase instruction
is decoded, the Erase timeout flag bit (DQ3) is set to '1.'
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Programming Flash memory
8
PSD8XXFX
Programming Flash memory
Flash memory must be erased prior to being programmed. A byte of Flash memory is
erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may
erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may
program Flash memory byte-by-byte.
The primary and secondary Flash memories require the MCU to send an instruction to
program a byte or to erase sectors (see Table 10).
Once the MCU issues a Flash memory Program or Erase instruction, it must check for the
status bits for completion. The embedded algorithms that are invoked inside the PSD
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or Ready/Busy (PC3).
8.1
Data Polling
Polling on the Data Polling flag bit (DQ7) is a method of checking whether a program or
erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the byte to be programmed in Flash memory to
check status. The Data Polling flag bit (DQ7) of this location becomes the complement of b7
of the original data byte to be programmed. The MCU continues to poll this location,
comparing the Data Polling flag bit (DQ7) and monitoring the Error flag bit (DQ5). When the
Data Polling flag bit (DQ7) matches b7 of the original data, and the Error flag bit (DQ5)
remains ’0,’ the embedded algorithm is complete. If the Error flag bit (DQ5) is '1,' the MCU
should test the Data Polling flag bit (DQ7) again since the Data Polling flag bit (DQ7) may
have changed simultaneously with the Error flag bit (DQ5, see Figure 6).
The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to the Flash
memory with the byte that was intended to be written.
When using the Data Polling method during an Erase cycle, Figure 6 still applies. However,
the Data Polling flag bit (DQ7) is '0' until the Erase cycle is complete. A 1 on the Error flag bit
(DQ5) indicates a timeout condition on the Erase cycle; a 0 indicates no error. The MCU can
read any location within the sector being erased to get the Data Polling flag bit (DQ7) and
the Error flag bit (DQ5).
PSDsoft Express generates ANSI C code functions which implement these Data Polling
algorithms.
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Programming Flash memory
Figure 6.
Data Polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
DQ7
=
DATA
YES
NO
FAIL
PASS
AI01369B
8.2
Data Toggle
Checking the Toggle flag bit (DQ6) is a method of determining whether a program or erase
cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the byte to be programmed in Flash memory to
check status. The Toggle flag bit (DQ6) of this location toggles each time the MCU reads
this location until the embedded algorithm is complete. The MCU continues to read this
location, checking the Toggle flag bit (DQ6) and monitoring the Error flag bit (DQ5). When
the Toggle flag bit (DQ6) stops toggling (two consecutive reads yield the same value), and
the Error flag bit (DQ5) remains ’0,’ the embedded algorithm is complete. If the Error flag bit
(DQ5) is '1,' the MCU should test the Toggle flag bit (DQ6) again, since the Toggle flag bit
(DQ6) may have changed simultaneously with the Error flag bit (DQ5, see Figure 7).
The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to Flash
memory with the byte that was intended to be written.
When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle
flag bit (DQ6) toggles until the Erase cycle is complete. A '1' on the Error flag bit (DQ5)
indicates a timeout condition on the Erase cycle; a '0' indicates no error. The MCU can read
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Programming Flash memory
PSD8XXFX
any location within the sector being erased to get the Toggle flag bit (DQ6) and the Error flag
bit (DQ5).
PSDsoft Express generates ANSI C code functions which implement these Data Toggling
algorithms.
8.3
Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x,
PSD854F2x)
The Unlock Bypass instructions allow the system to program bytes to the Flash memories
faster than using the standard Program instruction. The Unlock Bypass mode is entered by
first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the
Unlock Bypass code, 20h (as shown in Table 10).
The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass
Program instruction is all that is required to program in this mode. The first cycle in this
instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the
program address and data. Additional data is programmed in the same manner. These
instructions dispense with the initial two Unlock cycles required in the standard Program
instruction, resulting in faster total Flash memory programming.
During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass
Reset Flash instructions are valid.
To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset
Flash instruction. The first cycle must contain the data 90h; the second cycle the data 00h.
Addresses are Don’t Care for both cycles. The Flash memory then returns to READ mode.
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Figure 7.
Data Toggle flowchart
START
READ
DQ5 & DQ6
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI01370B
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Erasing Flash memory
PSD8XXFX
9
Erasing Flash memory
9.1
Flash Bulk Erase
The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation
of the status register, as described in Table 10. If any byte of the Bulk Erase instruction is
wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory
status.
During a Bulk Erase, the memory status may be checked by reading the Error flag bit (DQ5),
the Toggle flag bit (DQ6), and the Data Polling flag bit (DQ7), as detailed in Section 8:
Programming Flash memory. The Error flag bit (DQ5) returns a '1' if there has been an
Erase Failure (maximum number of Erase cycles have been executed).
It is not necessary to program the memory with 00h because the PSD automatically does
this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the Flash memory does not accept any
instructions.
9.2
Flash Sector Erase
The Sector Erase instruction uses six WRITE operations, as described in Table 10.
Additional Flash Sector Erase codes and Flash memory sector addresses can be written
subsequently to erase other Flash memory sectors in parallel, without further coded cycles,
if the additional bytes are transmitted in a shorter time than the timeout period of about
100µs. The input of a new Sector Erase code restarts the timeout period.
The status of the internal timer can be monitored through the level of the Erase timeout flag
bit (DQ3). If the Erase timeout flag bit (DQ3) is ’0,’ the Sector Erase instruction has been
received and the timeout period is counting. If the Erase timeout flag bit (DQ3) is '1,' the
timeout period has expired and the PSD is busy erasing the Flash memory sector(s). Before
and during Erase timeout, any instruction other than Suspend Sector Erase and Resume
Sector Erase instructions abort the cycle that is currently in progress, and reset the device
to READ mode. It is not necessary to program the Flash memory sector with 00h as the
PSD does this automatically before erasing (byte = FFh).
During a Sector Erase, the memory status may be checked by reading the Error flag bit
(DQ5), the Toggle flag bit (DQ6), and the Data Polling flag bit (DQ7), as detailed in
Section 8: Programming Flash memory.
During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend
Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order
to read data from another Flash memory sector, and then resumed.
9.3
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be
used to suspend the cycle by writing 0B0h to any address when an appropriate Sector
Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 10). This allows reading of
data from another Flash memory sector after the Erase cycle has been suspended.
Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ mode.
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Erasing Flash memory
A Suspend Sector Erase instruction executed during an Erase timeout period, in addition to
suspending the Erase cycle, terminates the time out period.
The Toggle flag bit (DQ6) stops toggling when the PSD internal logic is suspended. The
status of this bit must be monitored at an address within the Flash memory sector being
erased. The Toggle flag bit (DQ6) stops toggling between 0.1µs and 15µs after the Suspend
Sector Erase instruction has been executed. The PSD is then automatically set to READ
mode.
If an Suspend Sector Erase instruction was executed, the following rules apply:
9.4
●
Attempting to read from a Flash memory sector that was being erased outputs invalid
data.
●
Reading from a Flash sector that was not being erased is valid.
●
The Flash memory cannot be programmed, and only responds to Resume Sector
Erase and Reset Flash instructions (READ is an operation and is allowed).
●
If a Reset Flash instruction is received, data in the Flash memory sector that was being
erased is invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previously executed, the erase cycle may be
resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h
to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is
high. (See Table 10.)
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Specific features
PSD8XXFX
10
Specific features
10.1
Flash Memory Sector Protect
Each primary and secondary Flash memory sector can be separately protected against
Program and Erase cycles. Sector Protection provides additional data security because it
disables all program or erase cycles. This mode can be activated through the JTAG port or a
device programmer.
Sector protection can be selected for each sector using the PSDsoft Express Configuration
program. This automatically protects selected sectors when the device is programmed
through the JTAG port or a device programmer. Flash memory sectors can be unprotected
to allow updating of their contents using the JTAG port or a device programmer. The MCU
can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash memory sector is ignored by the device.
The Verify operation results in a READ of the protected data. This allows a guarantee of the
retention of the Protection status.
The sector protection status can be read by the MCU through the Flash memory protection
and PSD/EE protection registers (in the CSIOP block). See Table 12 and Table 13.
10.2
Reset Flash
The Reset Flash instruction consists of one WRITE cycle (see Table 10). It can also be
optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
●
Reading the Flash Protection Status or Flash ID
●
An Error condition has occurred (and the device has set the Error flag bit (DQ5) to '1')
during a Flash memory program or erase cycle.
On the PSD813F2/3/4/5, the Reset Flash instruction puts the Flash memory back into
normal READ mode. It may take the Flash memory up to a few milliseconds to complete the
Reset cycle. The Reset Flash instruction is ignored when it is issued during a Program or
Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going
Sector Erase cycle, and returns the Flash memory to the normal READ mode within a few
milliseconds.
On the PSD83xF2 or PSD85xF2, the Reset Flash instruction puts the Flash memory back
into normal READ mode. If an Error condition has occurred (and the device has set the
Error flag bit (DQ5) to '1') the Flash memory is put back into normal READ mode within 25μs
of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored
when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset
Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to
the normal READ mode within 25μs.
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10.3
Specific features
Reset (RESET) signal (on the PSD83xF2 and PSD85xF2)
A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash
memory to the READ mode. When the reset occurs during a program or erase cycle, the
Flash memory takes up to 25μs to return to the READ mode. It is recommended that the
Reset (RESET) pulse (except for Power On Reset, as described in Section 18: Reset timing
and device status at reset) be at least 25 µs so that the Flash memory is always ready for
the MCU to fetch the bootstrap instructions after the Reset cycle is complete.
Table 12.
Bit 7
Sector Protection/Security Bit definition – Flash Protection register(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
1. Bit Definitions:
Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected.
Table 13.
Bit 7
Sector Protection/Security Bit definition – PSD/EE Protection register(1)
Bit 6
Bit 5
Bit 4
Security_B
not used
it
not used
not used
Bit 3
Bit 2
Bit 1
Bit 0
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
1. Bit Definitions:
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
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SRAM
11
PSD8XXFX
SRAM
The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select
(RS0) can contain up to two product terms, allowing flexible memory mapping.
SRAM Select (RS0) is configured using PSDsoft Express Configuration.
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12
Sector Select and SRAM Select
Sector Select and SRAM Select
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of
the DPLD. They are setup by writing equations for them in PSDabel. The following rules
apply to the equations for these signals:
12.1
1.
Primary Flash memory and secondary Flash memory Sector Select signals must not
be larger than the physical sector size.
2.
Any primary Flash memory sector must not be mapped in the same memory space as
another Flash memory sector.
3.
A secondary Flash memory sector must not be mapped in the same memory space as
another secondary Flash memory sector.
4.
SRAM, I/O, and Peripheral I/O spaces must not overlap.
5.
A secondary Flash memory sector may overlap a primary Flash memory sector. In
case of overlap, priority is given to the secondary Flash memory sector.
6.
SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any
address greater than 9FFFh accesses the primary Flash memory segment 0. You can see
that half of the primary Flash memory segment 0 and one-fourth of secondary Flash
memory segment 0 cannot be accessed in this example. Also note that an equation that
defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid.
Figure 8 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on the
same level must not overlap. Level one has the highest priority and level 3 has the lowest.
12.2
Memory select configuration for MCUs with separate
program and data spaces
The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and
80C51XA, have separate address spaces for program memory (selected using Program
Select Enable (PSEN, CNTL2)) and data memory (selected using Read Strobe (RD,
CNTL1)). Any of the memories within the PSD can reside in either space or both spaces.
This is controlled through manipulation of the VM register that resides in the CSIOP space.
The VM register is set using PSDsoft Express to have an initial value. It can subsequently
be changed by the MCU so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and primary Flash memory in the data space at
Boot-up, and secondary Flash memory in the program space at Boot-up, and later swap the
primary and secondary Flash memories. This is easily done with the VM register by using
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Sector Select and SRAM Select
PSD8XXFX
PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it
when desired. Table 14 describes the VM register.
Figure 8.
Priority level of memory and I/O components
Highest Priority
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Memory
Lowest Priority
AI02867D
12.3
Configuration modes for MCUs with separate program and
data spaces
12.3.1
Separate Space modes
Program space is separated from data space. For example, Program Select Enable (PSEN,
CNTL2) is used to access the program code from the primary Flash memory, while Read
Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and
I/O port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9).
12.3.2
Combined Space modes
The program and data spaces are combined into one memory space that allows the primary
Flash memory, secondary Flash memory, and SRAM to be accessed by either Program
Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the
primary Flash memory in Combined space, Bits b2 and b4 of the VM register are set to '1'
(see Figure 10).
Figure 9.
8031 memory modules – separate space
DPLD
RS0
Primary
Flash
Memory
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
PSEN
RD
AI02869C
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PSD8XXFX
Sector Select and SRAM Select
Figure 10. 8031 memory modules – combined space
DPLD
RD
SRAM
Secondary
Flash
Memory
Primary
Flash
Memory
RS0
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
RD
VM REG BIT 2
VM REG BIT 0
AI02870C
Table 14.
Bit 7
PIO_EN
VM register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Primary
FL_Data
econdary
EE_Data
Primary
FL_Code
Secondary
EE_Code
SRAM_Code
0 = RD can’t
access
secondary Flash
memory
0 = PSEN
cannot
access
Flash
memory
0 = PSEN can’t
access
secondary Flash
memory
0 = PSEN
cannot
access
SRAM
1 = RD access
secondary Flash
memory
1 = PSEN
access
Flash
memory
1 = PSEN access
secondary Flash
memory
1 = PSEN
access
SRAM
0 = disable
PIO mode
not
used
not
used
0 = RD
cannot access
Flash memory
1= enable
PIO mode
not
used
not
used
1 = RD
access Flash
memory
Doc ID 7833 Rev 7
Bit 0
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Page register
13
PSD8XXFX
Page register
The 8-bit Page register increases the addressing capability of the MCU by a factor of up to
256. The contents of the register can also be read by the MCU. The outputs of the Page
register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector
Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application Note
AN1154.
Figure 11 shows the Page register. The eight flip-flops in the register are connected to the
internal data bus D0-D7. The MCU can write to or read from the Page register. The Page
register can be accessed at address location CSIOP + E0h.
Figure 11. Page register
RESET
D0
D0 - D7
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
PGR0
INTERNAL
SELECTS
AND LOGIC
PGR1
PGR2
PGR3
PGR4
DPLD
AND
CPLD
PGR5
PGR6
PGR7
R/ W
PAGE
REGISTER
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PLD
AI02871B
PSD8XXFX
14
PLDS
PLDS
The PLDs bring programmable logic functionality to the PSD. After specifying the logic for
the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the
device and available upon Power-up.
The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The
PLDs are briefly discussed in the next few paragraphs, and in more detail in Section 14.2:
Decode PLD (DPLD), and Section 14.3: Complex PLD (CPLD). Figure 12 shows the
configuration of the PLDs.
The DPLD performs address decoding for Select signals for internal components, such as
memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the 16 Output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The
CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDabel. An input bus consisting of 73 signals is connected to the PLDs. The signals are
shown in Table 15.
14.1
The Turbo Bit in PSD
The PLDs in the PSD can minimize power consumption by switching off when inputs remain
unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of
PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the
Turbo mode off increases propagation delays while reducing power consumption. See
Section 17: Power management on how to set the Turbo Bit.
Additionally, five bits are available in PMMR2 to block MCU control signals from entering the
PLDs. This reduces power consumption and can be used only when these MCU control
signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Table 15.
DPLD and CPLD inputs
Input name
Number of
signals
MCU address bus(1)
A15-A0
16
MCU control signals
CNTL2-CNTL0
3
Reset
RST
1
Power-down
PDN
1
Port A input macrocells
PA7-PA0
8
Port B input macrocells
PB7-PB0
8
Port C input macrocells
PC7-PC0
8
Port D inputs
PD2-PD0
3
Input source
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PLDS
PSD8XXFX
Table 15.
DPLD and CPLD inputs (continued)
Input name
Number of
signals
PGR7-PGR0
8
Macrocell AB feedback
MCELLAB.FB7-FB0
8
Macrocell BC feedback
MCELLBC.FB7-FB0
8
Ready/Busy
1
Input source
Page register
Secondary Flash memory Program Status
Bit
1. The address inputs are A19-A4 in 80C51XA mode.
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DATA
BUS
Doc ID 7833 Rev 7
16
1
2
1
1
4
8
CPLD
PT
ALLOC.
OUTPUT MACROCELL FEEDBACK
DECODE PLD
24 INPUT MACROCELL
(PORT A,B,C)
INPUT MACROCELL & INPUT PORTS
PORT D INPUTS
24
3
MACROCELL
ALLOC.
AI02872C
3
8
MCELLBC
TO PORT B OR C
EXTERNAL CHIP SELECTS
TO PORT D
8
MCELLAB
TO PORT A OR B
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
JTAG SELECT
PERIPHERAL SELECTS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
PRIMARY FLASH MEMORY SELECTS
16 OUTPUT
MACROCELL
DIRECT MACROCELL INPUT TO MCU DATA BUS
73
73
PAGE
REGISTER
I/O PORTS
8
PSD8XXFX
PLDS
Figure 12. PLD diagram
49/128
PLD INPUT BUS
PLDS
14.2
PSD8XXFX
Decode PLD (DPLD)
The DPLD, shown in Figure 13, is used for decoding the address for internal and external
components. The DPLD can be used to generate the following decode signals:
●
8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms
each)
●
4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three
product terms each)
●
1 internal SRAM Select (RS0) signal (two product terms)
●
1 internal CSIOP Select (PSD Configuration register) signal
●
1 JTAG Select signal (enables JTAG on port C)
●
2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 13. DPLD logic array
(INPUTS)
I /O PORTS (PORT A,B,C)
3
CSBOOT 0
3
CSBOOT 1
3
CSBOOT 2
3
CSBOOT 3
3
FS0
(24)
3
MCELLAB.FB [7:0] (FEEDBACKS)
FS1
(8)
3
MCELLBC.FB [7:0] (FEEDBACKS)
FS2
(8)
3
PGR0 - PGR7
FS3
(8)
3
A[15:0] *
(16)
3
PD[2:0] (ALE,CLKIN,CSI)
(3)
PDN (APD OUTPUT)
(1)
FS5
3
FS6
3
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(3)
RESET
(1)
RD_BSY
(1)
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
FS4
FS7
2
RS0
1
CSIOP
1
PSEL0
1
PSEL1
1
JTAGSEL
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O MODE
SELECT
AI02873D
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PSD8XXFX
14.3
PLDS
Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters and
shift registers, system mailboxes, handshaking protocols, state machines, and random logic.
The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to
port D.
Although External Chip Select (ECS0-ECS2) can be produced by any Output macrocell
(OMC), these three External Chip Select (ECS0-ECS2) on port D do not consume any
Output macrocells (OMC).
As shown in Figure 12, the CPLD has the following blocks:
●
24 input macrocells (IMC)
●
16 Output macrocells (OMC)
●
Macrocell Allocator
●
Product Term Allocator
●
AND Array capable of generating up to 137 product terms
●
Four I/O ports.
Each of the blocks are described in the sections that follow.
The input macrocells (IMC) and Output macrocells (OMC) are connected to the PSD
internal data bus and can be directly accessed by the MCU. This enables the MCU software
to load data into the Output macrocells (OMC) or read data from both the input and Output
macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND Array as required in most standard PLD macrocell
architectures.
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PLD INPUT BUS
PLD INPUT BUS
CK
MACROCELL FEEDBACK
PT INPUT LATCH GATE/CLOCK
I/O PORT INPUT
Q
CL
D/T/JK FF
SELECT
D/T
PT OUTPUT ENABLE (OE)
PT CLEAR
CLOCK
SELECT
GLOBAL
CLOCK
PT
CLOCK
POLARITY
SELECT
MCU LOAD
MCU DATA IN
PR DI LD
PT PRESET
UP TO 10
PRODUCT TERMS
PRODUCT TERM
ALLOCATOR
COMB.
/REG
SELECT
MUX
CPLD MACROCELLS
MUX
MACROCELL
TO
I/O PORT
ALLOC.
CPLD
OUTPUT
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
MCU ADDRESS / DATA BUS
D
Q
Q
DIR
REG.
D
INPUT
SELECT
MUX
ALE/AS
G
Q D
Q D
INPUT MACROCELLS
WR
PDR
CPLD OUTPUT
WR
DATA
LATCHED
ADDRESS OUT
I/O PORTS
TO OTHER I/O PORTS
MUX
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MUX
PRODUCT TERMS
FROM OTHER
MACROCELLS
AI02874
I/O PIN
PLDS
PSD8XXFX
Figure 14. Macrocell and I/O port
AND ARRAY
PSD8XXFX
14.4
PLDS
Output macrocell (OMC)
Eight of the Output macrocells (OMC) are connected to ports A and B pins and are named
as McellAB0-McellAB7. The other eight macrocells are connected to ports B and C pins and
are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in
PSDabel, the macrocell Allocator block assigns it to either port A or B. The same is true for
a McellBC output on port B or C. Table 16 shows the macrocells and port assignment.
The Output macrocell (OMC) architecture is shown in Figure 15. As shown in the figure,
there are native product terms available from the AND Array, and borrowed product terms
available (if unused) from other Output macrocells (OMC). The polarity of the product term
is controlled by the XOR gate. The Output macrocell (OMC) can implement either sequential
logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the
sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and
has a feedback path to the AND Array inputs.
The flip-flop in the Output macrocell (OMC) block can be configured as a D, T, JK, or SR
type in the PSDabel program. The flip-flop’s clock, preset, and clear inputs may be driven
from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock
input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset
and clear are active high inputs. Each clear input can use up to two product terms.
Table 16.
Output macrocell port and data bit assignments
assignment
Native product
terms
Maximum
borrowed product
terms
Data bit for loading
or reading
McellAB0
Port A0, B0
3
6
D0
McellAB1
Port A1, B1
3
6
D1
McellAB2
Port A2, B2
3
6
D2
McellAB3
Port A3, B3
3
6
D3
McellAB4
Port A4, B4
3
6
D4
McellAB5
Port A5, B5
3
6
D5
McellAB6
Port A6, B6
3
6
D6
McellAB7
Port A7, B7
3
6
D7
McellBC0
Port B0, C0
4
5
D0
McellBC1
Port B1, C1
4
5
D1
McellBC2
Port B2, C2
4
5
D2
McellBC3
Port B3, C3
4
5
D3
McellBC4
Port B4, C4
4
6
D4
McellBC5
Port B5, C5
4
6
D5
McellBC6
Port B6, C6
4
6
D6
McellBC7
Port B7, C7
4
6
D7
Output
Port
macrocell
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PLDS
14.5
PSD8XXFX
Product Term Allocator
The CPLD has a Product Term Allocator. The PSDabel compiler uses the Product Term
Allocator to borrow and place product terms from one macrocell to another. The following list
summarizes how product terms are allocated:
●
McellAB0-McellAB7 all have three native product terms and may borrow up to six more
●
McellBC0-McellBC3 all have four native product terms and may borrow up to five more
●
McellBC4-McellBC7 all have four native product terms and may borrow up to six more.
Each macrocell may only borrow product terms from certain other macrocells. Product
terms already in use by one macrocell are not available for another macrocell.
If an equation requires more product terms than are available to it, then “external” product
terms are required, which consume other Output macrocells (OMC). If external product
terms are used, extra delay is added for the equation that required the extra product terms.
This is called product term expansion. PSDsoft Express performs this expansion as needed.
14.6
Loading and reading the Output macrocells (OMC)
The Output macrocells (OMC) block occupies a memory location in the MCU address
space, as defined by the CSIOP block (see Section 16: I/O ports). The flip-flops in each of
the 16 Output macrocells (OMC) can be loaded from the data bus by a MCU. Loading the
Output macrocells (OMC) with data from the MCU takes priority over internal functions. As
such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The
ability to load the flip-flops and read them back is useful in such applications as loadable
counters and shift registers, mailboxes, and handshaking protocols.
Data can be loaded to the Output macrocells (OMC) on the trailing edge of Write Strobe
(WR, CNTL0) (edge loading) or during the time that Write Strobe (WR, CNTL0) is active
(level loading). The method of loading is specified in PSDsoft Express Configuration.
14.7
The OMC Mask register
There is one Mask register for each of the two groups of eight Output macrocells (OMC).
The Mask registers can be used to block the loading of data to individual Output macrocells
(OMC). The default value for the Mask registers is 00h, which allows loading of the Output
macrocells (OMC). When a given bit in a Mask register is set to a 1, the MCU is blocked
from writing to the associated Output macrocells (OMC). For example, suppose McellAB0McellAB3 are being used for a state machine. You would not want a MCU write to McellAB
to overwrite the state machine registers. Therefore, you would want to load the Mask
register for McellAB (Mask macrocell AB) with the value 0Fh.
14.8
The Output Enable of the OMC
The Output macrocells (OMC) block can be connected to an I/O port pin as a PLD output.
The output enable of each port pin driver is controlled by a single product term from the
AND Array, ORed with the Direction register output. The pin is enabled upon Power-up if no
output enable equation is defined and if the pin is declared as a PLD output in PSDsoft
Express.
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PSD8XXFX
PLDS
If the Output macrocell (OMC) output is declared as an internal node and not as a port pin
output in the PSDabel file, the port pin can be used for other I/O functions. The internal node
feedback can be routed as an input to the AND Array.
PORT INPUT
FEEDBACK (.FB)
CLKIN
PT CLK
MUX
CLEAR (.RE)
CLR
IN
POLARITY
SELECT
PROGRAMMABLE
FF (D/T/JK /SR)
MACROCELL
ALLOCATOR
Q
LD
PT
RD
PRESET(.PR)
PT
PT
ALLOCATOR
PT
PLD INPUT BUS
MACROCELL CS
WR
AND ARRAY
MASK
REG.
ENABLE (.OE)
DIN PR
MUX
COMB/REG
SELECT
INTERNAL DATA BUS
D [ 7:0]
DIRECTION
REGISTER
PORT
DRIVER
INPUT
MACROCELL
AI02875B
I/O PIN
Figure 15. CPLD Output macrocell
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PLDS
14.9
PSD8XXFX
Input macrocells (IMC)
The CPLD has 24 input macrocells (IMC), one for each pin on ports A, B, and C. The
architecture of the input macrocells (IMC) is shown in Figure 16. The input macrocells (IMC)
are individually configurable, and can be used as a latch, register, or to pass incoming port
signals prior to driving them onto the PLD input bus. The outputs of the input macrocells
(IMC) can be read by the MCU through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each
product term output is used to latch or clock four input macrocells (IMC). port inputs 3-0 can
be controlled by one product term and 7-4 by another.
Configurations for the input macrocells (IMC) are specified by equations written in PSDabel
(see Application Note AN1171). outputs of the input macrocells (IMC) can be read by the
MCU via the IMC buffer (see Section 16: I/O ports).
Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher
than A15. Any latched addresses are routed to the PLDs as inputs.
Input macrocells (IMC) are particularly useful with handshaking communication applications
where two processors pass data back and forth through a common mailbox. Figure 17
shows a typical configuration where the Master MCU writes to the port A Data Out register.
This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output
enable product term.
The Slave can also write to the port A input macrocells (IMC) and the Master can then read
the input macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from
the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and
Slave_CS.
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AND ARRAY
PLD INPUT BUS
Doc ID 7833 Rev 7
FEEDBACK
PT
PT
ENABLE ( .OE )
MUX
OUTPUT
MACROCELLS BC
AND
MACROCELL AB
G
D
D
LATCH
Q
D FF
Q
INPUT MACROCELL _ RD
ALE/AS
DIRECTION
REGISTER
D [ 7:0]
INPUT MACROCELL
MUX
PT
INTERNAL DATA BUS
PORT
DRIVER
AI02876B
I/O PIN
PSD8XXFX
PLDS
Figure 16. Input macrocell
57/128
MASTER
MCU
58/128
D [ 7:0]
MCU-WR
MCU-RD
PSD
MCU-RD
CPLD
D
Q
Doc ID 7833 Rev 7
Q
D
PORT A
INPUT
MACROCELL
SLAVE – WR
MCU-WR
PORT A
DATA OUT
REGISTER
SLAVE – READ
WR
RD
SLAVE– CS
PORT A
D [ 7:0]
AI02877C
SLAVE
MCU
PLDS
PSD8XXFX
Figure 17. Handshaking communication using input macrocells
PSD8XXFX
15
MCU bus interface
MCU bus interface
The “no-glue logic” MCU bus interface block can be directly connected to most popular
MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are
shown in Table 17. The interface type is specified using the PSDsoft Express Configuration.
Table 17.
MCUs and their control signals
MCU
Data bus
width
CNTL0
CNTL1
CNTL2
PC7
PD0(1)
ADIO0
PA3-PA0
PA7-PA3
8031
8
WR
RD
PSEN
(2)
ALE
A0
(2)
(2)
80C51XA
8
WR
RD
PSEN
(2)
ALE
A4
A3-A0
(2)
80C251
8
WR
PSEN
(2)
(2)
ALE
A0
(2)
(2)
80C251
8
WR
RD
PSEN
(2)
ALE
A0
(2)
(2)
80198
8
WR
RD
(2)
(2)
ALE
A0
(2)
(2)
68HC11
8
R/W
E
(2)
(2)
AS
A0
(2)
(2)
68HC912
8
R/W
E
(2)
DBE
AS
A0
(2)
(2)
Z80
8
WR
RD
(2)
(2)
(2)
A0
D3-D0
D7-D4
(2)
AS
A0
(2)
(2)
Z8
8
R/W
DS
(2)
68330
8
R/W
DS
(2)
(2)
AS
A0
(2)
(2)
M37702M2
8
R/W
E
(2)
(2)
ALE
A0
D3-D0
D7-D4
1. ALE/AS input is optional for MCUs with a non-multiplexed bus
2. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other
I/O functions.
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MCU bus interface
15.1
PSD8XXFX
PSD interface to a multiplexed 8-bit bus
Figure 18 shows an example of a system using a MCU with an 8-bit multiplexed bus and a
PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus.
Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses
can be brought out to port A or B. The PSD drives the ADIO data bus only when one of its
internal resources is accessed and Read Strobe (RD, CNTL1) is active. Should the system
address bus exceed sixteen bits, ports A, B, C, or D may be used as additional address
inputs.
Figure 18. An example of a typical 8-bit multiplexed bus interface
PSD
MCU
AD [ 7:0]
ADIO
PORT
A[ 15:8]
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
A [ 7: 0]
PORT
A
(OPTIONAL)
PORT
B
(OPTIONAL)
A [ 15: 8]
PORT
C
ALE (PD0)
PORT D
RESET
15.2
AI02878C
PSD interface to a non-multiplexed 8-bit bus
Figure 19 shows an example of a system using a MCU with an 8-bit non-multiplexed bus
and a PSD. The address bus is connected to the ADIO port, and the data bus is connected
to port A. port A is in tri-state mode when the PSD is not accessed by the MCU. Should the
system address bus exceed sixteen bits, ports B, C, or D may be used for additional address
inputs.
15.3
Data Byte Enable reference
MCUs have different data byte orientations. Table 18 shows how the PSD interprets
byte/word operations in different bus WRITE configurations. Even-byte refers to locations
with address A0 equal to '0' and odd byte as locations with A0 equal to ’1.’
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PSD8XXFX
15.4
MCU bus interface
MCU bus interface examples
Figure 20, Figure 21, Figure 22, Figure 23, and Figure 24 show examples of the basic
connections between the PSD and some popular MCUs. The PSD Control input pins are
labeled as to the MCU function for which they are configured. The MCU bus interface is
specified using the PSDsoft Express Configuration.
Table 18.
8-bit data bus
BHE
A0
D7-D0
X
0
Even byte
X
1
Odd byte
Figure 19. An example of a typical 8-bit non-multiplexed bus interface
PSD
MCU
D [ 7:0]
ADIO
PORT
PORT
A
D [ 7:0]
A [ 15:0]
PORT
B
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
A[ 23:16]
(OPTIONAL)
PORT
C
ALE (PD0)
PORT D
RESET
AI02879C
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MCU bus interface
15.5
PSD8XXFX
80C31
Figure 20 shows the bus interface for the 80C31, which has an 8-bit multiplexed
address/data bus. The lower address byte is multiplexed with the data bus. The MCU control
signals Program Select Enable (PSEN, CNTL2), Read Strobe (RD, CNTL1), and Write
Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O ports blocks.
Address Strobe (ALE/AS, PD0) latches the address.
Figure 20. Interfacing the PSD with an 80C31
AD7-AD0
AD[ 7:0]
PSD
80C31
31
19
18
9
RESET
12
13
14
15
EA/VP
X1
X2
RESET
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE/P
TXD
RXD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
30
31
32
33
34
35
36
37
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
A15
39
40
41
42
43
44
45
46
17
RD
WR
47
16
29
30
PSEN
ALE
50
49
11
10
10
9
8
RESET
48
RESET
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CNTL0 (WR)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
CNTL1(RD)
CNTL2 (PSEN)
PD0-ALE
PD1
PD2
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
AI02880C
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Doc ID 7833 Rev 7
PSD8XXFX
15.6
MCU bus interface
80C251
The Intel 80C251 MCU features a user-configurable bus interface with four possible bus
configurations, as shown in Table 19.
The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to
that shown in Figure 20. The second and third configurations have the same bus connection
as shown in Figure 21. There is only one Read Strobe (PSEN) connected to CNTL1 on the
PSD. The A16 connection to PA0 allows for a larger address input to the PSD. The fourth
configuration is shown in Figure 22. Read Strobe (RD) is connected to CNTL1 and Program
Select Enable (PSEN) is connected to CNTL2.
The 80C251 has two major operating modes: Page mode and Non-page mode. In Nonpage mode, the data is multiplexed with the lower address byte, and Address Strobe
(ALE/AS, PD0) is active in every bus cycle. In Page mode, data (D7-D0) is multiplexed with
address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0)
is not active and only addresses (A7-A0) are changing. The PSD supports both modes. In
Page mode, the PSD bus timing is identical to Non-Page mode except the address hold time
and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0) valid to data in valid.
Figure 21. Interfacing the PSD with the 80C251, with One READ input
PSD
80C251SB
2
3
4
5
6
7
8
9
21
20
11
13
14
15
16
17
RESET
10
35
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
X2
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
RST
EA
ALE
PSEN
WR
RD/A16
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
39
40
41
42
43
44
45
46
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
24
25
26
27
28
29
30
31
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
33
ALE
47
32
RD
50
18
WR
19
A16
49
10
9
8
RESET
RESET
48
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 ( WR)
CNTL1( RD)
CNTL 2(PSEN)
PD0-ALE
PD1
PD2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
29
28
27
25
24
23
22
21
A161
A171
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
AI02881C
1. The A16 and A17 connections are optional.
2. In non-Page-mode, AD7-AD0 connects to ADIO7-ADIO0.
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MCU bus interface
PSD8XXFX
Figure 22. Interfacing the PSD with the 80C251, with RD and PSEN inputs
80C251SB
2
3
4
5
6
7
8
9
21
20
10
35
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
X1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
X2
11
13
14
15
16
17
RESET
PSD
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
RST
ALE
PSEN
WR
RD/A16
EA
43
42
41
40
39
38
37
36
A0
A1
A2
A3
A4
A5
A6
A7
24
25
26
27
28
29
30
31
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A0
A1
A2
A3
A4
A5
A6
A7
30
31
32
33
34
35
36
37
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
39
40
41
42
43
44
45
46
33
ALE
47
32
RD
50
18
WR
19
PSEN
49
10
9
8
RESET
RESET
48
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CNTL0 ( WR)
CNTL1( RD)
CNTL 2(PSEN)
PD0-ALE
PD1
PD2
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
AI02882C
Table 19.
80C251 configurations
Configuration
80C251 READ/WRITE
pins
Connecting to PSD pins
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page mode, 80C31 compatible
A7-A0 multiplex with D7-D0
2
WR
PSEN only
CNTL0
CNTL1
Non-Page mode
A7-A0 multiplex with D7-D0
3
WR
PSEN only
CNTL0
CNTL1
Page mode
A15-A8 multiplex with D7-D0
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page mode
A15-A8 multiplex with D7-D0
64/128
Doc ID 7833 Rev 7
Page mode
PSD8XXFX
15.7
MCU bus interface
80C51XA
The Philips 80C51XA MCU family supports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with
data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits
(D7-D0).
The 80C51XA can be configured to operate in eight-bit data mode (as shown in Figure 23).
The 80C51XA improves bus throughput and performance by executing burst cycles for code
fetches. In Burst mode, address A19-A4 are latched internally by the PSD, while the
80C51XA changes the A3-A0 signals to fetch up to 16 bytes of code. The PSD access time
is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst mode is identical to the normal bus cycle, except the address setup
and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply.
Figure 23. Interfacing the PSD with the 80C51X, 8-bit data bus
PSD
80C51XA
21
20
11
13
6
7
9
8
16
RESET
10
14
15
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RST
INT0
INT1
A0/WRH
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
2
3
4
5
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A15
A16
A17
A18
A19
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
30
31
32
33
34
35
36
37
A12
A13
A14
A15
A16
A17
A18
A19
39
ADIO8
40
ADIO9
41
ADIO10
42
ADIO11
43
AD1012
44
AD1013
45
ADIO14
46
ADIO15
47
50
35
17
EA/WAIT
BUSW
PSEN
RD
WRL
ALE
32
PSEN
49
19
RD
WR
ALE
10
8
9
18
33
48
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
CNTL0 (WR)
CNTL1(RD)
CNTL 2 (PSEN)
PD0-ALE
PD1
PD2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
29
28
27
25
24
23
22
21
A0
A1
A2
A3
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
RESET
AI02883C
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MCU bus interface
15.8
PSD8XXFX
68HC11
Figure 24 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit
multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ
and WR signals for external devices.
Figure 24. Interfacing the PSD with a 68HC11
AD7-AD0
AD7-AD0
PSD
31
30
29
28
27
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
30
31
32
33
34
35
36
37
42
41
40
39
38
37
36
35
A8
A9
A10
A11
A12
A13
A14
A15
39
40
41
42
43
44
45
46
68HC11
8
7
RESET
17
19
18
2
34
33
32
43
44
45
46
47
48
49
50
52
51
XT
EX
RESET
IRQ
XIRQ
MODB
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/W
9
10
11
12
13
14
15
16
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
20
21
22
23
24
25
47
50
49
10
9
8
48
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CNTL0 (R _W)
CNTL1(E)
CNTL 2
PD0 – AS
PD1
PD2
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
29
28
27
25
24
23
22
21
7
6
5
4
3
2
52
51
20
19
18
17
14
13
12
11
RESET
3
5
E
4
AS
6
R/ W
RESET
AI02884C
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Doc ID 7833 Rev 7
PSD8XXFX
16
I/O ports
I/O ports
There are four programmable I/O ports: ports A, B, C, and D. Each of the ports is eight bits
except port D, which is 3 bits. Each port pin is individually user configurable, thus allowing
multiple functions per port. The ports are configured using PSDsoft Express Configuration
or by the MCU writing to on-chip registers in the CSIOP space.
The topics discussed in this section are:
16.1
●
General port architecture
●
Port operating modes
●
Port configuration registers (PCR)
●
Port Data registers
●
Individual port functionality.
General port architecture
The general architecture of the I/O port block is shown in Figure 25. Individual port
architectures are shown in Figure 27, Figure 28, Figure 29, and Figure 30. In general, once
the purpose for a port pin has been defined, that pin is no longer available for other
purposes. Exceptions are noted.
As shown in Figure 25, the ports contain an output multiplexer whose select signals are
driven by the configuration bits in the Control registers (Ports A and B only) and PSDsoft
Express Configuration.Inputs to the multiplexer include the following:
●
Output data from the Data Out register
●
Latched address outputs
●
CPLD macrocell output
●
External Chip Select (ECS0-ECS2) from the CPLD.
The port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The port Data Buffer (PDB) is connected to the Internal data bus for feedback and can
be read by the MCU. The Data Out and macrocell outputs, Direction and Control registers,
and port pin input are all connected to the port data buffer (PDB).
The port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND Array enable product term and the Direction register. If the
enable product term of any of the Array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDabel file, then the Direction register has sole control of
the buffer that drives the port pin.
The contents of these registers can be altered by the MCU. The port Data Buffer (PDB)
feedback path allows the MCU to check the contents of the registers.
Ports A, B, and C have embedded input macrocells (IMC). The input macrocells (IMC) can
be configured as latches, registers, or direct inputs to the PLDs. The latches and registers
are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array.
The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the
MCU (see Figure 16: Input macrocell).
Doc ID 7833 Rev 7
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I/O ports
16.2
PSD8XXFX
Port operating modes
The I/O ports have several modes of operation. Some modes can be defined using
PSDabel, some by the MCU writing to the Control registers in CSIOP space, and some by
both. The modes that can only be defined using PSDsoft Express must be programmed into
the device and cannot be changed unless the device is reprogrammed. The modes that can
be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data port,
Address input, and Peripheral I/O modes are the only modes that must be defined before
programming the device. All other modes can be changed by the MCU at run-time. See
Application Note AN1171 for more detail.
Table 20 summarizes which modes are available on each port. Table 23 shows how and
where the different modes are configured. Each of the port operating modes are described
in the following sections.
Figure 25. General I/O port architecture
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
PORT PIN
OUTPUT
MUX
G
MACROCELL OUTPUTS
EXT CS
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
ENABLE OUT
Q
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD-INPUT
AI02885
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Doc ID 7833 Rev 7
PSD8XXFX
16.3
I/O ports
MCU I/O mode
In the MCU I/O mode, the MCU uses the I/O ports block to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD are mapped into the MCU address
space. The addresses of the ports are listed in Table 8.
A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the
Control register. The MCU I/O direction may be changed by writing to the corresponding bit
in the Direction register, or by the output enable product term (see Section 16.8: Peripheral
I/O mode). When the pin is configured as an output, the content of the Data Out register
drives the pin. When configured as an input, the MCU can read the port input through the
Data In buffer (see Figure 25).
Ports C and D do not have Control registers, and are in MCU I/O mode by default. They can
be used for PLD I/O if equations are written for them in PSDabel.
16.4
PLD I/O mode
The PLD I/O mode uses a port as an input to the CPLD’s input macrocells (IMC), and/or as
an output from the CPLD’s Output macrocells (OMC). The output can be tri-stated with a
control signal. This output enable control signal can be defined by a product term from the
PLD, or by resetting the corresponding bit in the Direction register to ’0.’ The corresponding
bit in the Direction register must not be set to '1' if the pin is defined for a PLD input signal in
PSDabel. The PLD I/O mode is specified in PSDabel by declaring the port pins, and then
writing an equation assigning the PLD I/O to a port.
16.5
Address Out mode
For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive
latched addresses on to the port pins. These port pins can, in turn, drive external devices.
Either the output enable or the corresponding bits of both the Direction register and Control
register must be set to a 1 for pins to use Address Out mode. This must be done by the
MCU at run-time. See Table 22 for the address output pin assignments on ports A and B for
various MCUs.
For non-multiplexed 8-bit bus mode, address signals (A7-A0) are available to port B in
Address Out mode.
Note:
Do not drive address signals with Address Out mode to an external memory device if it is
intended for the MCU to Boot from the external device. The MCU must first Boot from PSD
memory so the Direction and Control register bits can be set.
Table 20.
Port operating modes
Port mode
Port A
Port B
Port C
Port D
MCU I/O
Yes
Yes
Yes
Yes
PLD I/O
McellAB outputs
McellBC outputs
Additional Ext. CS outputs
PLD inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Doc ID 7833 Rev 7
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I/O ports
PSD8XXFX
Table 20.
Port operating modes (continued)
Port mode
Port A
Port B
Port C
Port D
Yes (A7 – 0)
Yes (A7 – 0)
or (A15 – 8)
No
No
Yes
Yes
Yes
Yes
Yes (D7 – 0)
No
No
No
Peripheral I/O
Yes
No
No
No
JTAG ISP
No
No
Yes(1)
No
Address Out
Address In
Data port
1. Can be multiplexed with other I/O functions.
Table 21.
Port operating mode settings
Defined in
PSDabel
Defined in PSD
configuration
Control
register
setting
Direction
register
setting
VM
register
setting
JTAG Enable
MCU I/O
Declare pins only
N/A(1)
0
1 = output,
0 = input(2)
N/A
N/A
PLD I/O
Logic equations
N/A
N/A
(2)
N/A
N/A
N/A
Specify bus type
N/A
N/A
N/A
N/A
Address Out
(Port A,B)
Declare pins only
N/A
1
1(2)
N/A
N/A
Address In
(Port A,B,C,D)
Logic for equation
input macrocells
N/A
N/A
N/A
N/A
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
N/A
PIO bit = 1
N/A
JTAGSEL
JTAG
Configuration
N/A
N/A
N/A
JTAG_Enable
Mode
Data port (Port A)
JTAG ISP(3)
1. N/A = Not Applicable
2. The direction of the port A,B,C, and D pins are controlled by the Direction register ORed with the individual output enable
product term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on port C.
Table 22.
I/O port Latched address output assignments
MCU
8051XA (8-Bit)
80C251
(Page mode)
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed bus
Port A (PA3-PA0)
Port A (PA7-PA4)
Port B (PB3-PB0)
Port B (PB7-PB4)
N/A(1)
Address a7-a4
Address a11-a8
N/A
N/A
N/A
Address a11-a8
Address a15-a12
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
N/A
N/A
Address a3-a0
Address a7-a4
1. N/A = Not Applicable
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PSD8XXFX
16.6
I/O ports
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to port A, B, C, and D. The address input can be latched in the input macrocell (IMC) by
Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the
SRAM, or primary or secondary Flash memory is considered to be an address input.
16.7
Data port mode
Port A can be used as a data bus port for a MCU with a non-multiplexed address/data bus.
The Data port is connected to the data bus of the MCU. The general I/O functions are
disabled in port A if the port is configured as a Data port.
16.8
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of
port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting Bit 7 of the VM register to a ’1.’ Figure 26 shows how port A acts as a bidirectional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is tri-stated when PSEL0 or
PSEL1 is not active.
Figure 26. Peripheral I/O mode
RD
PSEL0
PSEL
PSEL1
VM REGISTER BIT 7
D0 - D7
DATA BUS
PA0 - PA7
WR
AI02886
16.9
JTAG in-system programming (ISP)
Port C is JTAG compliant, and can be used for in-system programming (ISP). You can
multiplex JTAG operations with other functions on port C because in-system programming
(ISP) is not performed in normal operating mode. For more information on the JTAG port,
see Section 19: Programming in-circuit using the JTAG serial interface.
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I/O ports
16.10
PSD8XXFX
Port configuration registers (PCR)
Each port has a set of port configuration registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal READ/WRITE bus
cycles at the addresses given in Table 8. The addresses in Table 8 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three port
configuration registers (PCR), shown in Table 23, are used for setting the port
configurations. The default Power-up state for each register in Table 23 is 00h.
16.11
Control register
Any bit reset to '0' in the Control register sets the corresponding port pin to MCU I/O mode,
and a '1' sets it to Address Out mode. The default mode is MCU I/O. Only ports A and B
have an associated Control register.
16.12
Direction register
The Direction register, in conjunction with the output enable (except for port D), controls the
direction of data flow in the I/O ports. Any bit set to '1' in the Direction register causes the
corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default
mode for all port pins is input.
Figure 27 and Figure 28 show the port architecture diagrams for ports A/B and C,
respectively. The direction of data flow for ports A, B, and C are controlled not only by the
direction register, but also by the output enable product term from the PLD AND Array. If the
output enable product term is not active, the Direction register has sole control of a given
pin’s direction.
An example of a configuration for a port with the three least significant bits set to output and
the remainder set to input is shown in Table 26. Since port D only contains three pins
(shown in Figure 30), the Direction register for port D has only the three least significant bits
active.
16.13
Drive Select register
The Drive Select register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is
set to a ’1.’ The default pin drive is CMOS.
Note that the slew rate is a measurement of the rise and fall times of an output. A higher
slew rate means a faster output response and may create more electrical noise. A pin
operates in a high slew rate when the corresponding bit in the Drive register is set to ’1.’ The
default rate is slow slew.
Table 27 shows the Drive register for ports A, B, C, and D. It summarizes which pins can be
configured as Open Drain outputs and which pins the slew rate can be set for.
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PSD8XXFX
I/O ports
Table 23.
Port configuration registers (PCR)t
Register name
Port
Control
Direction
Drive Select
(1)
MCU access
A,B
WRITE/READ
A,B,C,D
WRITE/READ
A,B,C,D
WRITE/READ
1. See Table 27 for Drive register bit definition.
Table 24.
Table 25.
Port Pin Direction Control, Output Enable P.T. not defined
Direction register bit
Port Pin mode
0
Input
1
Output
Port Pin Direction Control, Output Enable P.T. defined
Direction register Bit
Output Enable P.T.
Port Pin mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Table 26.
Port Direction assignment example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
Table 27.
Drive register pin assignment
Drive
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D
NA(1)
NA(1)
NA(1)
NA(1)
NA(1)
Slew
Rate
Slew
Rate
Slew
Rate
1. NA = Not Applicable.
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I/O ports
16.14
PSD8XXFX
Port Data registers
The port Data registers, shown in Table 28, are used by the MCU to write data to or read
data from the ports. Table 28 shows the register name, the ports having each register type,
and MCU access for each register type. The registers are described below.
16.15
Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is
read through the Data In buffer.
16.16
Data Out register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
register are driven out to the pins if the Direction register or the output enable product term
is set to ’1.’ The contents of the register can also be read back by the MCU.
Output macrocells (OMC)
The CPLD Output macrocells (OMC) occupy a location in the MCU’s address space. The
MCU can read the output of the Output macrocells (OMC). If the OMC Mask register bits are
not set, writing to the macrocell loads data to the macrocell flip-flops (see Section 14:
PLDS).
16.17
OMC Mask register
Each OMC Mask register bit corresponds to an Output macrocell (OMC) flip-flop. When the
OMC Mask register bit is set to a 1, loading data into the Output macrocell (OMC) flip-flop is
blocked. The default value is 0 or unblocked.
Table 28.
Port Data registers
Register name
16.18
Port
MCU access
Data In
A,B,C,D
READ – input on pin
Data Out
A,B,C,D
WRITE/READ
Output macrocell
A,B,C
READ – outputs of macrocells
WRITE – loading macrocells flip-flop
Mask macrocell
A,B,C
WRITE/READ – prevents loading into a given
macrocell
Input macrocell
A,B,C
READ – outputs of the input macrocells
Enable Out
A,B,C
READ – the output enable control of the port driver
Input macro (IMC)
The input macrocells (IMC) can be used to latch or store external inputs. The outputs of the
input macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU (see
Section 14: PLDS).
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PSD8XXFX
16.19
I/O ports
Enable Out
The Enable Out register can be read by the MCU. It contains the output enable values for a
given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state
and the pin is in input mode.
Ports A and B – functionality and structure
Ports A and B have similar functionality and structure, as shown in Figure 27. The two ports
can be configured to perform one or more of the following functions:
●
MCU I/O mode
●
CPLD Output – macrocells McellAB7-McellAB0 can be connected to port A or port B.
McellBC7-McellBC0 can be connected to port B or port C.
●
CPLD input – Via the input macrocells (IMC).
●
Latched Address output – Provide latched address output as per Table 22.
●
Address In – Additional high address inputs using the input macrocells (IMC).
●
Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew
rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode.
●
Data port – port A to D7-D0 for 8 bit non-multiplexed bus
●
Multiplexed Address/Data port for certain types of MCU bus interfaces.
●
Peripheral mode – port A only
Figure 27. Port A and port B structure
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
PORT
A OR B PIN
ADDRESS
A[ 7:0] OR A[15:8]
G
OUTPUT
MUX
MACROCELL OUTPUTS
READ MUX
INTERNAL DATA BUS
16.20
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
Q
ENABLE OUT
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD - INPUT
AI02887
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I/O ports
16.21
PSD8XXFX
Port C – functionality and structure
Port C can be configured to perform one or more of the following functions (see Figure 28):
●
MCU I/O mode
●
CPLD Output – McellBC7-McellBC0 outputs can be connected to port B or port C.
●
CPLD input – via the input macrocells (IMC)
●
Address In – Additional high address inputs using the input macrocells (IMC).
●
In-system programming (ISP) – JTAG port can be enabled for programming/erase of
the PSD device (see Section 19: Programming in-circuit using the JTAG serial interface
for more information on JTAG programming).
●
Open Drain – port C pins can be configured in Open Drain mode
Port C does not support Address Out mode, and therefore no Control register is required.
Pin PC7 may be configured as the DBE input in certain MCU bus interfaces.
Figure 28. Port C structure
DATA OUT
REG.
D
DATA OUT
Q
WR
1
SPECIAL FUNCTION
PORT C PIN
OUTPUT
MUX
MCELLBC[ 7:0]
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
ENABLE OUT
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
SPECIAL FUNCTION
CPLD-INPUT
16.22
CONFIGURATION
AI02888B
BIT
Port D – functionality and structure
Port D has three I/O pins. See Figure 29 and Figure 30. This port does not support Address
Out mode, and therefore no Control register is required. port D can be configured to perform
one or more of the following functions:
76/128
●
MCU I/O mode
●
CPLD Output – External Chip Select (ECS0-ECS2)
●
CPLD input – direct input to the CPLD, no input macrocells (IMC)
●
Slew rate – pins can be set up for fast slew rate
Doc ID 7833 Rev 7
PSD8XXFX
I/O ports
Port D pins can be configured in PSDsoft Express as input pins for other dedicated
functions:
●
Address Strobe (ALE/AS, PD0)
●
CLKIN (PD1) as input to the macrocells flip-flops and APD counter
●
PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory,
SRAM and CSIOP.
Figure 29. Port D structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT D PIN
OUTPUT
MUX
ECS[ 2:0]
INTERNAL DATA BUS
READ MUX
OUTPUT
SELECT
P
D
DATA IN
B
ENABLE PRODUCT
TERM (.OE)
DIR REG.
D
Q
WR
16.23
CPLD - INPUT
AI02889
External Chip Select
The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on port D pins
that can be used to select external devices. Each External Chip Select (ECS0-ECS2)
consists of one product term that can be configured active high or low. The output enable of
the pin is controlled by either the output enable product term or the Direction register (see
Figure 30).
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I/O ports
PSD8XXFX
Figure 30. Port D external Chip Select signals
ENABLE (.OE)
CPLD AND ARRAY
PLD INPUT BUS
PT0
DIRECTION
REGISTER
PD0 PIN
ECS0
POLARITY
BIT
ENABLE (.OE)
PT1
DIRECTION
REGISTER
PD1 PIN
ECS1
POLARITY
BIT
ENABLE (.OE)
PT2
ECS2
POLARITY
BIT
78/128
DIRECTION
REGISTER
Doc ID 7833 Rev 7
PD2 PIN
AI02890
PSD8XXFX
17
Power management
Power management
All PSD devices offer configurable power saving options. These options may be used
individually or in combinations, as follows:
●
All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are
built with power management technology. In addition to using special silicon design
methodology, power management technology puts the memories into standby mode
when address/data inputs are not changing (zero DC current). As soon as a transition
occurs on an input, the affected memory “wakes up”, changes and latches its outputs,
then goes back to Standby. The designer does not have to do anything special to
achieve memory Standby mode when no inputs are changing—it happens
automatically.
The PLD sections can also achieve Standby mode when its inputs are not changing, as
described in the sections on the Power Management mode registers (PMMR).
●
As with the Power Management mode, the Automatic Power Down (APD) block allows
the PSD to reduce to standby current automatically. The APD Unit can also block MCU
address/data signals from reaching the memories and PLDs. This feature is available
on all the devices of the PSD family. The APD Unit is described in more detail in
Section 17.1: Automatic Power-down (APD) Unit and Power-down mode.
Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity
for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if
enabled). Once in Power-down mode, all address/data signals are blocked from
reaching PSD memory and PLDs, and the memories are deselected internally. This
allows the memory and PLDs to remain in Standby mode even if the address/data
signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep
in mind that any unblocked PLD input signals that are changing states keeps the PLD
out of Standby mode, but not the memories.
●
PSD Chip Select input (CSI, PD2) can be used to disable the internal memories,
placing them in Standby mode even if inputs are changing. This feature does not block
any internal signals or disable the PLDs. This is a good alternative to using the APD
Unit. There is a slight penalty in memory access time when PSD Chip Select input
(CSI, PD2) makes its initial transition from deselected to selected.
●
The PMMRs can be written by the MCU at run-time to manage power. All PSD
supports “blocking bits” in these registers that are set to block designated signals from
reaching both PLDs. Current consumption of the PLDs is directly related to the
composite frequency of the changes on their inputs (see Figure 34 and Figure 35).
Significant power savings can be achieved by blocking signals that are not used in
DPLD or CPLD logic equations.
PSD devices have a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off
(the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can
achieve standby current when no PLD inputs are changing (zero DC current). Even
when inputs do change, significant power can be saved at lower frequencies (AC
current), compared to when Turbo mode is on. When the Turbo mode is on, there is a
significant DC current component and the AC component is higher.
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Power management
17.1
PSD8XXFX
Automatic Power-down (APD) Unit and Power-down mode
The APD Unit, shown in Figure 31, puts the PSD into Power-down mode by monitoring the
activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes high, and the PSD enters Power-down mode, as discussed next.
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the PSD is in Power-down mode:
●
If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal
operating mode. The PSD also returns to normal operating mode if either PSD Chip
Select input (CSI, PD2) is low or the Reset (RESET) input is high.
●
The MCU address/data bus is blocked from all memory and PLDs.
●
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the PMMR registers. The blocked signals include MCU
control signals and the common CLKIN (PD1). Note that blocking CLKIN (PD1) from
the PLDs does not block CLKIN (PD1) from the APD Unit.
●
All PSD memories enter Standby mode and are drawing standby current. However, the
PLD and I/O ports blocks do not go into Standby mode because you don’t want to have
to wait for the logic and I/O to “wake up” before their outputs can change. See Table 29
for Power-down mode effects on PSD ports.
●
Typical standby current is of the order of microamperes. These standby current values
assume that there are no transitions on any PLD input.
Table 29.
Power-down mode’s effect on ports
Port function
80/128
Pin level
MCU I/O
No change
PLD Out
No change
Address Out
Undefined
Data port
Tri-state
Peripheral I/O
Tri-state
Doc ID 7833 Rev 7
PSD8XXFX
Power management
Figure 31. APD unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
CLR
RESET
EEPROM SELECT
FLASH SELECT
EDGE
DETECT
CSI
PD
APD
COUNTER
PD
PLD
CLKIN
SRAM SELECT
POWER DOWN
(PDN) SELECT
DISABLE
FLASH/EEPROM/SRAM
Table 30.
Mode
Power-down
AI02891
PSD timing and standby current during Power-down mode
PLD propagation delay
Normal tPD(1)
Memory
access time
Access recovery time
to normal access
No access
tLVDV
Typical standby current
5 V VCC
3 V VCC
75 µA(2)
25 µA(2)
1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’
17.2
For users of the HC11 (or compatible)
The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or
compatible) in your design, and you wish to use the Power-down mode, you must not
connect the E clock to CLKIN (PD1). You should instead connect a crystal oscillator to
CLKIN (PD1). The crystal oscillator frequency must be less than 15 times the frequency of
AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS,
the PSD keeps going into Power-down mode.
17.3
Other power saving options
The PSD offers other reduced power saving options that are independent of the Powerdown mode. Except for PSD Chip Select input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2.
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Power management
PSD8XXFX
Figure 32. Enable Power-down flowchart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
No
ALE/AS idle
for 15 CLKIN
clocks?
Yes
PSD in Power
Down Mode
17.4
AI02892
PLD power management
The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70ns. The propagation
delay time is increased by 10ns after the Turbo Bit is set to '1' (turned off) when the inputs
change at a composite frequency of less than 15 MHz. When the Turbo Bit is reset to '0'
(turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC
power, AC power, and propagation delay.
Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power
consumption.
Table 31.
Bit
Bit 0
Bit 1
Bit 2
Bit 3
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Power Management mode registers PMMR0(1)
Name
X
Description
0
Not used, and should be set to zero.
0=
off
Automatic Power-down (APD) is disabled.
1=
on
Automatic Power-down (APD) is enabled.
0
Not used, and should be set to zero.
0=
on
PLD Turbo mode is on
1=
off
PLD Turbo mode is off, saving power.
APD Enable
X
PLD Turbo
Doc ID 7833 Rev 7
PSD8XXFX
Table 31.
Bit
Bit 4
Bit 5
Power management
Power Management mode registers PMMR0(1) (continued)
Name
Description
0=
on
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo Bit is ’0.’
1=
off
CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
0=
on
CLKIN (PD1) input to the PLD macrocells is connected.
1=
off
CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
PLD Array clk
PLD MCell clk
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the
registers.
Table 32.
Bit
Power Management mode registers PMMR2(1)
Name
Description
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
PLD Array
CNTL0
0 = on Cntl0 input to the PLD AND Array is connected.
Bit 2
PLD Array
CNTL1
0 = on Cntl1 input to the PLD AND Array is connected.
PLD Array
CNTL2
0 = on Cntl2 input to the PLD AND Array is connected.
PLD Array
ALE
0 = on ALE input to the PLD AND Array is connected.
PLD Array
DBE
0 = on DBE input to the PLD AND Array is connected.
X
0
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
1 = off ALE input to PLD AND Array is disconnected, saving power.
1 = off DBE input to PLD AND Array is disconnected, saving power.
Not used, and should be set to zero.
1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the
registers.
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Power management
17.5
PSD8XXFX
PSD Chip Select input (CSI, PD2)
PD2 of port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When
low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O
blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select input
(CSI, PD2) disables the Flash memory, EEPROM, and SRAM, and reduces the PSD power
consumption. However, the PLD and I/O signals remain operational when PSD Chip Select
input (CSI, PD2) is high.
There may be a timing penalty when using PSD Chip Select input (CSI, PD2) depending on
the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 62
or Table 63.
17.6
Input clock
The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power
consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output macrocells
(OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the macrocells block by setting Bits 4 or 5 to a 1 in PMMR0.
17.7
Input control signals
The PSD provides the option to turn off the input control signals (CNTL0, CNTL1, CNTL2,
Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC power consumption. These
control signals are inputs to the PLD AND Array. During Power-down mode, or, if any of
them are not being used as part of the PLD logic equation, these control signals should be
disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits
2, 3, 4, 5, and 6 to a 1 in PMMR2.
Table 33.
84/128
APD counter operation
APD Enable
bit
ALE PD
polarity
ALE level
0
X
X
Not counting
1
X
Pulsing
Not counting
1
1
1
Counting (generates PDN after 15 clocks)
1
0
0
Counting (generates PDN after 15 clocks)
APD counter
Doc ID 7833 Rev 7
PSD8XXFX
Reset timing and device status at reset
18
Reset timing and device status at reset
18.1
Power-up reset
Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO after VCC is
steady. During this period, the device loads internal configurations, clears some of the
registers and sets the Flash memory into operating mode. After the rising edge of Reset
(RESET), the PSD remains in the Reset mode for an additional period, tOPR, before the first
memory access is allowed.
The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR, CNTL0) high, during Power On
Reset for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of Write Strobe (WR, CNTL0). Any Flash memory WRITE
cycle initiation is prevented automatically when VCC is below VLKO.
18.2
Warm reset
Once the device is up and running, the device can be reset with a pulse of a much shorter
duration, tNLNH.
The same tOPR period is needed before the device is operational after warm reset.
Figure 33 shows the timing of the Power-up and warm reset.
18.3
I/O pin, register and PLD status at Reset
Table 34 shows the I/O pin, register and PLD status during Power On Reset, warm reset and
Power-down mode. PLD outputs are always valid during warm reset, and they are valid in
Power On Reset once the internal PSD Configuration bits are loaded. This loading of PSD is
completed typically long before the VCC ramps up to operating level. Once the PLD is active,
the state of the outputs are determined by the PSDabel equations.
18.4
Reset of Flash memory erase and program cycles (on the
PSD834Fx)
A Reset (RESET) also resets the internal Flash memory state machine. During a Flash
memory program or erase cycle, Reset (RESET) terminates the cycle and returns the Flash
memory to the Read mode within a period of tNLNH-A.
Doc ID 7833 Rev 7
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Reset timing and device status at reset
PSD8XXFX
Figure 33. Reset (RESET) timing
VCC(min)
VCC
tNLNH-PO
tNLNH
tNLNH-A
tOPR
Power-On Reset
tOPR
Warm Reset
RESET
AI02866b
Table 34.
Status during Power-on reset, Warm reset and Power-down mode
Port configuration
Power-on reset
Warm reset
Power-down mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-on reset
Warm reset
Power-down mode
PMMR0 and PMMR2
Cleared to '0'
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to '0' by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM register(1)
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to '0'
Cleared to '0'
Unchanged
1. The SR_cod and Periphmode bits in the VM register are always cleared to '0' on Power-on reset or Warm reset.
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Doc ID 7833 Rev 7
PSD8XXFX
19
Programming in-circuit using the JTAG serial interface
Programming in-circuit using the JTAG serial
interface
The JTAG Serial Interface block can be enabled on port C (see Table 35). All memory blocks
(primary and secondary Flash memory), PLD logic, and PSD Configuration register bits may
be programmed through the JTAG Serial Interface block. A blank device can be mounted on
a printed circuit board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and
Erase cycles.
Note:
By default, on a blank PSD (as shipped from the factory or after erasure), four pins on port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note AN1153 for more details on JTAG in-system programming (ISP).
19.1
Standard JTAG signals
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a JTAG serial command from an external JTAG controller device (such as
FlashLINK or Automated Test Equipment). When the enabling command is received, TDO
becomes an output and the JTAG channel is fully functional inside the PSD. The same
command that enables the JTAG channel may optionally enable the two additional JTAG
signals, TSTAT and TERR.
The following symbolic logic equation specifies the conditions enabling the four basic JTAG
signals (TMS, TCK, TDI, and TDO) on their respective port C pins. For purposes of
discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are
enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside the PSD is set by the designer
in the PSDsoft Express Configuration utility. This dedicates the
pins for JTAG at all times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-time by writing to the
PSD register, JTAG Enable. This register is located at address CSIOP
+ offset C7h. Setting the JTAG_ENABLE bit in this register will
enable the pins for JTAG use. This bit is cleared by a PSD reset or
the microcontroller. See Table 36 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the PSD can be used to
enable the JTAG pins. This PT has the reserved name JTAGSEL. Once
defined as a node in PSDabel, the designer can write an equation for
JTAGSEL. This method is used when the port C JTAG pins are
multiplexed with other I/O signals. It is recommended to logically
tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when
multiplexing JTAG signals. See Application Note 1153 for details. */
The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations
if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However,
Doc ID 7833 Rev 7
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Programming in-circuit using the JTAG serial interface
PSD8XXFX
Reset (RESET) will prevent or interrupt JTAG operations if the JTAG enable register is used
to enable the JTAG pins.
The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary
Scan. The PSDsoft Express software tool and FlashLINK JTAG programming cable
implement the JTAG In-System-Configuration (ISC) commands. A definition of these JTAG
In-System-Configuration (ISC) commands and sequences is defined in a supplemental
document available from ST. This document is needed only as a reference for designers
who use a FlashLINK to program their PSD.
19.2
JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command
received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to
speed Program and Erase cycles by indicating status on PSD signals instead of having to
scan the status out serially using the standard JTAG channel. See Application Note
AN1153.
TERR indicates if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal goes low (active) when an Error condition occurs, and stays low
until an “ISC_CLEAR” command is executed or a chip Reset (RESET) pulse is received
after an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy described in Section 6.3.1: Ready/Busy (PC3).
TSTAT is high when the PSD device is in READ mode (primary and secondary Flash
memory contents can be read). TSTAT is low when Flash memory program or erase cycles
are in progress, and also when data is being written to the secondary Flash memory.
TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”
command. This facilitates a wired-OR connection of TSTAT signals from multiple PSD
devices and a wired-OR connection of TERR signals from those same devices. This is
useful when several PSD devices are “chained” together in a JTAG environment.
19.3
Security and Flash memory protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG port. When using the JTAG port, only a Full Chip Erase command is allowed.
All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part
to a non-secured blank state. The Security bit can be set in PSDsoft Express configuration.
All primary and secondary Flash memory sectors can individually be sector protected
against erasures. The sector protect bits can be set in PSDsoft Express configuration.
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Doc ID 7833 Rev 7
PSD8XXFX
Programming in-circuit using the JTAG serial interface
Table 35.
JTAG port signals
Port C pin
JTAG signals
Description
PC0
TMS
mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
Doc ID 7833 Rev 7
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Initial delivery state
20
PSD8XXFX
Initial delivery state
When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The
PSD Configuration register bits are set to ’0.’ The code, configuration, and PLD logic are
loaded using the programming procedure. Information for programming the device is
available directly from ST. Please contact your local sales representative.
Table 36.
Bit
Bit 0
JTAG Enable register(1)
Name
Description
0=
off
JTAG port is disabled.
1=
on
JTAG port is enabled.
JTAG_Enable
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
X
0
Not used, and should be set to zero.
Bit 3
X
0
Not used, and should be set to zero.
Bit 4
X
0
Not used, and should be set to zero.
Bit 5
X
0
Not used, and should be set to zero.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are
dedicated by an NVM Configuration bit (via PSDsoft Express). However, Reset (RESET) prevents or
interrupts JTAG operations if the JTAG enable register is used to enable the JTAG signals.
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PSD8XXFX
21
Maximum rating
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 37.
Absolute maximum ratings
Symbol
Parameter
TSTG
Storage temperature
TLEAD
Lead temperature during soldering (20 seconds
max.)(1)
Min.
Max.
Unit
–65
125
°C
235
°C
VIO
Input and output voltage (Q = VOH or Hi-Z)
–0.6
7.0
V
VCC
Supply voltage
–0.6
7.0
V
VPP
Device programmer supply voltage
–0.6
14.0
V
–2000
2000
V
VESD
Electrostatic discharge voltage (human body model)
(2)
1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
Doc ID 7833 Rev 7
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AC/DC parameters
22
PSD8XXFX
AC/DC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device:
●
DC electrical specifications
●
AC timing specifications
–
PLD timings
Combinatorial timings
Synchronous clock mode
Asynchronous clock mode
Input macrocell timings
–
MCU timings
READ timings
WRITE timings
Peripheral mode timings
Power-down and Reset timings
The parameters in the DC and AC Characteristic tables that follow are derived from tests
performed under the Measurement Conditions summarized in the relevant tables. Designers
should check that the operating conditions in their circuit match the measurement conditions
when relying on the quoted parameters.
The following are issues concerning the parameters presented:
92/128
●
In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD is in each mode. Also, the supply power is considerably different if the Turbo
Bit is ’0.’
●
The AC power component gives the PLD, Flash memory, and SRAM mA/MHz
specification. Figure 34 and Figure 35 show the PLD mA/MHz as a function of the
number of Product Terms (PT) used.
●
In the PLD timing parameters, add the required delay when Turbo Bit is ’0.’
Doc ID 7833 Rev 7
PSD8XXFX
AC/DC parameters
Figure 34. PLD ICC /frequency consumption (5 V range)
110
VCC = 5V
100
90
80
(100
70
FF
)
ON
RBO
O
60
O
TU
RB
50
(25%
TU
ICC – (mA)
%)
ON
BO
TUR
40
30
F
20
O
RB
OF
PT 100%
PT 25%
TU
10
0
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI02894
Figure 35. PLD ICC /frequency consumption (3 V range)
60
VCC = 3V
O
URB
)
100%
ON (
T
40
FF
30
O
5%)
(2
O ON
O
ICC – (mA)
50
RB
TURB
TU
20
10
PT 100%
PT 25%
F
O
RB
TU
OF
0
0
5
10
15
20
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Table 38.
25
AI03100
Example of PSD typical power calculation at VCC=5.0 V (Turbo mode on) (1)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
= 8 MHz
= 4 MHz
% Flash memory access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational modes
% Normal
= 10%
% Power-down mode
= 90%
Doc ID 7833 Rev 7
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AC/DC parameters
Table 38.
PSD8XXFX
Example of PSD typical power calculation at VCC=5.0 V (Turbo mode on) (1)
Conditions
Number of product terms used
(from fitter report)
= 45 PT
% of total product terms
= 45/182 = 24.7%
Turbo mode
= ON
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT)
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA
1. This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on
IOUT = 0 mA.
Table 39.
Example of PSD typical power calculation at VCC = 5.0 V (Turbo mode off) (1)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
= 8 MHz
= 4 MHz
% Flash memory access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational modes
% Normal
= 10%
% Power-down mode
= 90%
Number of product terms used
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Doc ID 7833 Rev 7
PSD8XXFX
Table 39.
AC/DC parameters
Example of PSD typical power calculation at VCC = 5.0 V (Turbo mode off)
Conditions
(from fitter report)
= 45 PT
% of total product terms
= 45/182 = 24.7%
Turbo mode
= Off
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE
+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz
+ 0.15 x 1.5mA/MHz x 4 MHz
+ 24mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29mA
= 3.34mA
1. This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on
IOUT = 0 mA.
Table 40.
Operating conditions (5 V devices)
Symbol
VCC
TA
Table 41.
Parameter
Min.
Max.
Unit
Supply voltage
4.5
5.5
V
Ambient operating temperature (industrial)
–40
85
°C
0
70
°C
Min.
Max.
Unit
Supply voltage
3.0
3.6
V
Ambient operating temperature (industrial)
–40
85
°C
0
70
°C
Ambient operating temperature (commercial)
Operating conditions (3 V devices)
Symbol
VCC
TA
Parameter
Ambient operating temperature (commercial)
Doc ID 7833 Rev 7
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AC/DC parameters
PSD8XXFX
AC signal letters for PLD timing(1)
Table 42.
Letter
Signal description
A
Address input
C
CEout output
D
Input data
E
E output
G
Internal WDOG_ON signal
I
Interrupt input
L
ALE input
N
RESET input or output
P
Port signal output
Q
Output data
R
WR, UDS, LDS, DS, IORD, PSEN inputs
S
Chip Select input
T
R/W input
W
Internal PDN signal
M
Output macrocell
1. Example: tAVLX = time from address valid to ALE invalid.
AC signal behavior symbols for PLD timing(1)
Table 43.
Letter
AC signal description
t
Time
L
Logic level low or ALE
H
Logic level high
V
Valid
X
No longer a valid logic level(2)
Z
Float
PW
Pulse width
1. Example: tAVLX = time from address valid to ALE invalid.
2. Output Hi-Z is defined as the point where data out is no longer driven.
Table 44.
AC measurement conditions
Symbol
CL
96/128
Parameter
Load capacitance
Min.
Max.
30
Doc ID 7833 Rev 7
Unit
pF
PSD8XXFX
AC/DC parameters
Table 45.
Symbol
CIN
Capacitance(1)
Parameter
Test condition
Typ.(2)
Max.
Unit
VIN = 0V
4
6
pF
Input capacitance (for input
pins)
COUT
Output capacitance (for
input/output pins)
VOUT = 0V
8
12
pF
CVPP
Capacitance (for
CNTL2/VPP)
VPP = 0V
18
25
pF
1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
Figure 36. AC measurement I/O waveform
3.0V
Test Point
1.5V
0V
AI03103b
Figure 37. AC measurement load circuit
2.01 V
195 Ω
Device
Under Test
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI03104b
Figure 38. Switching waveforms – key
2.01 V
195 Ω
Device
Under Test
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI03104b
Doc ID 7833 Rev 7
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AC/DC parameters
Table 46.
PSD8XXFX
DC characteristics (5 V devices)
Test condition
Symbol
Parameter
(in addition to those in
Table 40)
Min.
Typ.
Max.
Unit
VIH
Input high voltage
4.5 V < VCC < 5.5 V
2
VCC +0.5
V
VIL
Input low voltage
4.5 V < VCC < 5.5 V
–0.5
0.8
V
VIH1
Reset high level input voltage
(1)
0.8VCC
VCC +0.5
V
VIL1
Reset low level input voltage
(1)
–0.5
0.2VCC –
0.1
V
VHYS
Reset pin hysteresis
0.3
VLKO
VCC (min) for Flash Erase and
Program
2.5
VOL
Output low voltage
VOH
Output high voltage
ISB
Standby supply current
for Power-down mode
CSI >VCC –0.3 V(2)(3)
ILI
input leakage current
VSS < VIN < VCC
ILO
Output leakage current
0.45 < VOUT < VCC
V
4.2
V
IOL = 20 µA, VCC = 4.5 V
0.01
0.1
V
IOL = 8 mA, VCC = 4.5 V
0.25
0.45
V
IOH = –20 µA, VCC = 4.5 V
4.4
4.49
V
IOH = –2 mA, VCC = 4.5 V
2.4
3.9
V
50
200
µA
–1
±0.1
1
µA
–10
±5
10
µA
PLD_TURBO = off,
f = 0 MHz(4)
0
PLD_TURBO = on,
f = 0 MHz
400
700
µA/PT
During Flash memory
WRITE/Erase only
15
30
mA
Read only, f = 0 MHz
0
0
mA
f = 0 MHz
0
0
mA
µA/PT
PLD only
ICC
(DC)(4)
Operating
supply current
Flash memory
SRAM
(5)
PLD AC adder
ICC
(AC)(4)
Flash memory AC adder
2.5
3.5
mA/MHz
SRAM AC adder
1.5
3.0
mA/MHz
1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. IOUT = 0 mA
5. Please see Figure 34 for the PLD current calculation.
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PSD8XXFX
Table 47.
AC/DC parameters
DC Characteristics (3 V devices)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIH
High level input voltage
3.0 V < VCC < 3.6 V
0.7VCC
VCC +0.5
V
VIL
Low level input voltage
3.0 V < VCC < 3.6 V
–0.5
0.8
V
0.8VCC
VCC +0.5
V
–0.5
0.2VCC –
0.1
V
VIH1
Reset high level input voltage
(1)
VIL1
Reset low level input voltage
(1)
VHYS
Reset pin hysteresis
0.3
VLKO
VCC (min) for Flash Erase and
Program
1.5
VOL
Output low voltage
VOH
Output high voltage
ISB
Standby supply current
for Power-down mode
ILI
Input leakage current
VSS < VIN < VCC
ILO
Output leakage current
0.45 < VIN < VCC
V
2.2
V
IOL = 20 µA, VCC = 3.0 V
0.01
0.1
V
IOL = 4 mA, VCC = 3.0 V
0.15
0.45
V
IOH = –20 µA, VCC = 3.0 V
2.9
2.99
V
IOH = –1 mA, VCC = 3.0 V
2.7
2.8
V
CSI >VCC –0.3 V(2)(3)
25
100
µA
–1
±0.1
1
µA
–10
±5
10
µA
PLD_TURBO = off,
f = 0 MHz(3)
0
PLD_TURBO = on,
f = 0 MHz
200
400
µA/PT
During Flash memory
WRITE/Erase only
10
25
mA
Read only, f = 0 MHz
0
0
mA
0
0
mA
µA/PT
PLD only
ICC
(DC)(4)
Operating
supply current
Flash memory
SRAM
ICC
(AC)(4)
f = 0 MHz
PLD AC adder
(5)
Flash memory AC adder
1.5
2.0
mA/MHz
SRAM AC adder
0.8
1.5
mA/MHz
1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.
2. CSI deselected or internal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. IOUT = 0 mA
5. Please see Figure 35 for the PLD current calculation.
Doc ID 7833 Rev 7
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AC/DC parameters
PSD8XXFX
Figure 39. Input to output disable / enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 48.
CPLD combinatorial timing (5 V devices)
-70
Symbol
Parameter
-90
-15
Conditions
Min Max Min Max Min Max
Fast
PT
Aloc
Turbo
off
+2
+ 10
–2
ns
Slew
rate
Unit
(1)
tPD
CPLD input
pin/feedback to
CPLD combinatorial
output
20
25
32
tEA
CPLD input to CPLD
output enable
21
26
32
+ 10
–2
ns
tER
CPLD input to CPLD
output disable
21
26
32
+ 10
–2
ns
tARP
CPLD register clear
or preset delay
21
26
33
+ 10
–2
ns
tARPW
CPLD register clear
or preset pulse width
tARD
CPLD array delay
10
Any
macrocell
20
11
29
16
+ 10
22
ns
+2
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Table 49.
CPLD combinatorial timing (3 V devices)
-12
Symbol
Parameter
-15
-20
Conditions
Min Max Min Max Min Max
tPD
CPLD input
pin/feedback to
CPLD combinatorial
output
40
45
50
tEA
CPLD input to CPLD
output enable
43
45
tER
CPLD input to CPLD
output disable
43
tARP
CPLD register clear
or preset delay
40
100/128
Doc ID 7833 Rev 7
PT Turbo
Aloc
off
+4
Slew
rate
Unit
(1)
+ 20
–6
ns
50
+ 20
–6
ns
45
50
+ 20
–6
ns
43
48
+ 20
–6
ns
PSD8XXFX
Table 49.
AC/DC parameters
CPLD combinatorial timing (3 V devices) (continued)
-12
Symbol
Parameter
-15
-20
Conditions
Min Max Min Max Min Max
tARPW
CPLD register clear
or preset pulse width
tARD
CPLD array delay
25
Any
macrocell
30
PT Turbo
Aloc
off
35
25
Slew
rate
+ 20
29
33
Unit
(1)
ns
+4
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Figure 40. Synchronous clock mode timing – PLD
tCH
tCL
CLKIN
tS
tH
INPUT
tCO
REGISTERED
OUTPUT
AI02860
Table 50.
CPLD macrocell Synchronous clock mode timing (5 V devices)
-70
Symbol
Parameter
Min
Maximum
frequency
External
feedback
fMAX
-90
-15
Conditions
Max
Min
Max
Min
Max
Fast
Turbo Slew
PT
rate
off
(1)
Aloc
Unit
1/(tS+tCO)
40.0
30.30
25.00
MHz
Maximum
frequency
Internal
feedback (fCNT)
1/(tS+tCO–10)
66.6
43.48
31.25
MHz
Maximum
frequency
Pipelined data
1/(tCH+tCL)
83.3
50.00
35.71
MHz
tS
Input setup time
12
15
20
tH
Input hold time
0
0
0
ns
tCH
Clock high time
Clock input
6
10
15
ns
tCL
Clock low time
Clock input
6
10
15
ns
tCO
Clock to output
delay
Clock input
13
18
Doc ID 7833 Rev 7
+2
22
+ 10
ns
–2
ns
101/128
AC/DC parameters
Table 50.
PSD8XXFX
CPLD macrocell Synchronous clock mode timing (5 V devices) (continued)
-70
Symbol
Parameter
Min
tARD
CPLD array
delay
tMIN
Minimum clock
period(2)
-90
-15
Conditions
Max
Any macrocell
tCH+tCL
Min
Max
11
Min
16
12
20
Max
22
Fast
Turbo Slew
PT
rate
off
(1)
Aloc
+2
Unit
ns
30
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Table 51.
CPLD macrocell synchronous clock mode timing (3 V devices)
-12
Symbol
Parameter
-15
-20
Conditions
Min Max Min Max Min Max
fMAX
PT
Aloc
Turbo Slew
rate
off
(1)
Unit
Maximum
frequency
External feedback
1/(tS+tCO)
22.2
18.8
15.8
MHz
Maximum
frequency
Internal feedback
(fCNT)
1/(tS+tCO–10)
28.5
23.2
18.8
MHz
1/(tCH+tCL)
40.0
33.3
31.2
MHz
Maximum
frequency
Pipelined data
tS
Input setup time
20
25
30
tH
Input hold time
0
0
0
ns
tCH
Clock high time
Clock input
15
15
16
ns
tCL
Clock low time
Clock input
10
15
16
ns
tCO
Clock to output
delay
Clock input
25
28
33
tARD
CPLD array delay
Any macrocell
25
29
33
tMIN
Minimum clock
period(2)
tCH+tCL
25
29
+4
+ 20
–6
+4
32
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
102/128
Doc ID 7833 Rev 7
ns
ns
ns
ns
PSD8XXFX
AC/DC parameters
Figure 41. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 42. Asynchronous Clock mode Timing (product term clock)
tCHA
tCLA
CLOCK
tSA
tHA
INPUT
tCOA
REGISTERED
OUTPUT
AI02859
Table 52.
CPLD macrocell asynchronous clock mode timing (5 V devices)
-70
Symbol
Parameter
Min
fMAXA
-90
-15
Conditions
Max
Min
Max
Min
Max
PT Turbo Slew
Aloc
off
rate
Unit
Maximum
frequency
External
feedback
1/(tSA+tCOA)
38.4
26.32
21.27
MHz
Maximum
frequency
Internal
feedback
(fCNTA)
1/(tSA+tCOA–10)
62.5
35.71
27.78
MHz
1/(tCHA+tCLA)
71.4
41.67
35.71
MHz
Maximum
frequency
Pipelined data
tSA
Input setup
time
7
8
12
tHA
Input hold
time
8
12
14
tCHA
Clock input
high time
9
12
15
+ 10
ns
tCLA
Clock input
low time
9
12
15
+ 10
ns
Doc ID 7833 Rev 7
+2
+ 10
ns
ns
103/128
AC/DC parameters
Table 52.
PSD8XXFX
CPLD macrocell asynchronous clock mode timing (5 V devices) (continued)
-70
Symbol
Parameter
Min
tCOA
Clock to
output delay
tARDA
CPLD array
delay
Any macrocell
tMINA
Minimum
clock period
1/fCNTA
Table 53.
-90
Max
Min
Max
Min
+ 10
ns
30
37
11
16
22
16
28
–2
+2
ns
39
ns
CPLD macrocell Asynchronous clock mode timing (3 V devices)
Parameter
-15
-20
Conditions
Min
fMAXA
Unit
Max
PT Turbo Slew
Aloc
off
rate
21
-12
Symbol
-15
Conditions
Max
Min
Max
Min
Max
PT Turbo Slew
rate
Aloc
off
Unit
Maximum
frequency
External
feedback
1/(tSA+tCOA)
21.7
19.2
16.9
MHz
Maximum
frequency
Internal
feedback
(fCNTA)
1/(tSA+tCOA–10)
27.8
23.8
20.4
MHz
1/(tCHA+tCLA)
33.3
27
24.4
MHz
Maximum
frequency
Pipelined data
tSA
Input setup time
10
12
13
tHA
Input hold time
12
15
17
tCHA
Clock high time
17
22
25
+ 20
ns
tCLA
Clock low time
13
15
16
+ 20
ns
tCOA
Clock to output
delay
tARD
CPLD array
delay
tMINA
Minimum clock
period
104/128
Any macrocell
1/fCNTA
36
+4
40
46
25
29
33
Doc ID 7833 Rev 7
49
ns
ns
36
42
+ 20
+ 20
+4
–6
ns
ns
ns
PSD8XXFX
AC/DC parameters
Figure 43. Input macrocell timing (product term clock)
t INH
t INL
PT CLOCK
t IS
t IH
INPUT
OUTPUT
t INO
AI03101
Table 54.
Input macrocell timing (5 V devices)
-70
Symbol
Parameter
-90
-15
Conditions
Min Max Min Max Min Max
PT
Aloc
Turbo
off
Unit
tIS
Input setup time
(1)
0
0
0
tIH
Input hold time
(1)
15
20
26
NIB input high time
(1)
9
12
18
ns
tINL
NIB input low time
(1)
9
12
18
ns
tINO
NIB input to combinatorial
delay
(1)
tINH
34
ns
+ 10
46
59
+2
ns
+ 10
ns
1. Inputs from port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
Table 55.
input macrocell timing (3 V devices)
-12
Symbol
Parameter
-15
-20
Conditions
Min Max Min Max Min Max
PT
Aloc
Turbo
off
Unit
Input setup time
(1)
0
0
0
Input hold time
(1)
25
25
30
NIB input high time
(1)
12
13
15
ns
tINL
NIB input low time
(1)
12
13
15
ns
tINO
NIB input to combinatorial
delay
(1)
tIS
tIH
tINH
46
62
ns
+ 20
70
+4
+ 20
ns
ns
1. Inputs from port A, B, and C relative to register/ latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
Doc ID 7833 Rev 7
105/128
AC/DC parameters
PSD8XXFX
Figure 44. READ timing
tAVLX
1
tLXAX
ALE/AS
tLVLX
A /D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLQV
CSI
tRLQV
tRHQX
tRLRH
RD
(PSEN, DS)
tRHQZ
tEHEL
E
tTHEH
tELTL
R /W
tAVPV
ADDRESS OUT
AI02895
1. tAVLX and tLXAX are not required for 80C251 in Page mode or 80C51XA in Burst mode.
Table 56.
READ timing (5 V devices)
Symbol
Parameter
-70
-90
-15
Conditions
Min Max Min Max Min Max
tLVLX
ALE or AS pulse width
tAVLX
Address setup time
Turbo
off
Unit
15
20
28
ns
(1)
4
6
10
ns
Address hold time
(1)
7
8
11
ns
tAVQV
Address valid to data valid
(1)
tSLQV
CS valid to data valid
tLXAX
70
90
150
+ 10
ns
75
100
150
ns
RD to data valid 8-bit bus
(2)
24
32
40
ns
tRLQV
RD or PSEN to data valid
8-bit bus, 8031, 80251
(3)
31
38
45
ns
tRHQX
RD data hold time
(4)
0
0
0
ns
tRLRH
RD pulse width
(4)
27
32
38
ns
tRHQZ
RD to data high-Z
(4)
tEHEL
E pulse width
106/128
20
27
Doc ID 7833 Rev 7
25
32
30
38
ns
ns
PSD8XXFX
Table 56.
AC/DC parameters
READ timing (5 V devices) (continued)
-70
Symbol
Parameter
-90
-15
Conditions
Min Max Min Max Min Max
Turbo
off
Unit
tTHEH
R/W setup time to Enable
6
10
18
ns
tELTL
R/W hold time After Enable
0
0
0
ns
tAVPV
Address input valid to
Address output delay
(5)
20
25
30
ns
1. Any input used to select an internal PSD function.
2. RD timing has the same timing as DS, LDS, and UDS signals.
3. RD and PSEN have the same timing.
4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
5. In multiplexed mode, latched addresses generated from ADIO delay to address output on any port.
Table 57.
READ timing (3 V devices)
Symbol
Parameter
-12
-15
-20
Conditions
Min Max Min Max Min Max
tLVLX
ALE or AS pulse width
tAVLX
Address setup time
Turbo
off
Unit
26
26
30
ns
(1)
9
10
12
ns
Address hold time
(1)
9
12
14
ns
tAVQV
Address valid to data valid
(1)
tSLQV
CS valid to data valid
tLXAX
120
150
200
+ 20
ns
120
150
200
ns
RD to data valid 8-bit bus
(2)
35
35
40
ns
tRLQV
RD or PSEN to data valid 8-bit bus,
8031, 80251
(3)
45
50
55
ns
tRHQX
RD data hold time
(4)
tRLRH
RD pulse width
0
0
0
ns
38
40
45
ns
(4)
tRHQZ
RD to data high-Z
38
tEHEL
E pulse width
40
45
52
ns
tTHEH
R/W setup time to enable
15
18
20
ns
tELTL
R/W hold time after enable
0
0
0
ns
tAVPV
Address input valid to
address output delay
(5)
33
40
35
45
40
ns
ns
1. Any input used to select an internal PSD function.
2. RD timing has the same timing as DS, LDS, and UDS signals.
3. RD and PSEN have the same timing for 8031.
4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
5. In multiplexed mode latched address generated from ADIO delay to address output on any port.
Doc ID 7833 Rev 7
107/128
AC/DC parameters
PSD8XXFX
Figure 45. WRITE timing
tAVLX
t LXAX
ALE/AS
t LVLX
A /D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLWL
CSI
tDVWH
t WHDX
t WLWH
WR
(DS)
t WHAX
t EHEL
E
t THEH
t ELTL
R/ W
t WLMV
tAVPV
t WHPV
STANDARD
MCU I/O OUT
ADDRESS OUT
AI02896
Table 58.
WRITE timing (5 V devices)
-70
Symbol
Parameter
-90
-15
Conditions
Unit
Min Max Min Max Min Max
tLVLX
ALE or AS pulse width
15
20
28
ns
tAVLX
Address setup time
(1)
4
6
10
ns
(1)
tLXAX
Address hold time
7
8
11
ns
tAVWL
Address valid to leading
edge of WR
(1)(2)
8
15
20
ns
tSLWL
CS valid to leading edge of WR
(2)
12
15
20
ns
WR data setup time
(2)
25
35
45
ns
WR data hold time
(2)
4
5
5
ns
tWLWH
WR pulse widthpulse width
(2)
31
35
45
ns
tWHAX1
Trailing edge of WR to address invalid
(2)
6
8
10
ns
tWHAX2
Trailing edge of WR to DPLD address
invalid
(2)(3)
0
0
0
ns
tDVWH
tWHDX
108/128
Doc ID 7833 Rev 7
PSD8XXFX
Table 58.
AC/DC parameters
WRITE timing (5 V devices) (continued)
-70
Symbol
Parameter
-90
-15
Conditions
Unit
Min Max Min Max Min Max
tWHPV
Trailing edge of WR to port output
valid using I/O port data register
tDVMV
(2)
27
30
38
ns
Data valid to port output valid
using macrocell register
Preset/Clear
(2)(4)
42
55
65
ns
tAVPV
Address input valid to address
output delay
(5)
20
25
30
ns
tWLMV
WR valid to port output valid using
macrocell register Preset/Clear
(2)(6)
48
55
65
ns
1. Any input used to select an internal PSD function.
2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
3. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
4. Assuming WRITE is active before data becomes valid.
5. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
6. Assuming data is stable before active WRITE signal.
Table 59.
WRITE timing (3 V devices)
-12
Symbol
Parameter
-15
-20
Conditions
Unit
Min Max Min Max Min Max
tLVLX
ALE or AS pulse width
26
26
30
9
10
12
ns
tAVLX
Address setup time
(1)
tLXAX
Address hold time
(1)
9
12
14
ns
tAVWL
Address valid to Leading
Edge of WR
(1)(2)
17
20
25
ns
tSLWL
CS valid to Leading Edge of WR
(2)
17
20
25
ns
tDVWH
WR data setup time
(2)
45
45
50
ns
WR data hold time
(2)
7
8
10
ns
WR pulse width
(2)
46
48
53
ns
tWHAX1
Trailing edge of WR to address invalid
(2)
10
12
17
ns
tWHAX2
Trailing edge of WR to DPLD address
invalid
(2)(3)
0
0
0
ns
tWHPV
Trailing edge of WR to port output
valid using I/O port data register
tDVMV
Data valid to port output valid
using macrocell register Preset/Clear
tWHDX
tWLWH
(2)
33
35
40
ns
(2)(4)
70
70
80
ns
Doc ID 7833 Rev 7
109/128
AC/DC parameters
Table 59.
PSD8XXFX
WRITE timing (3 V devices) (continued)
-12
Symbol
Parameter
-15
-20
Conditions
Unit
Min Max Min Max Min Max
tAVPV
Address input valid to address output delay
tWLMV
WR valid to port output valid using
macrocell register Preset/Clear
(5)
33
35
40
ns
(2)(6)
70
70
80
ns
1. Any input used to select an internal PSD function.
2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
3. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
4. Assuming WRITE is active before data becomes valid.
5. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
6. Assuming data is stable before active WRITE signal.
Table 60.
Program, WRITE and Erase times (5 V devices)
Symbol
Parameter
Min.
Flash Program
Flash Bulk
Typ.
8.5
Erase (pre-programmed)(1)
3
Flash Bulk Erase (not pre-programmed)
5
tWHQV3
Sector Erase (pre-programmed)
1
tWHQV2
Sector Erase (not pre-programmed)
2.2
tWHQV1
Byte Program
14
Program/Erase cycles (per sector)
tWHWLO
tQ7VQV
Max.
s
30
30
s
s
1200
µs
cycles
100
DQ7 valid to output (DQ7-DQ0) valid (data
s
s
100,000
Sector Erase timeout
Unit
polling)(2)
µs
30
ns
Max.
Unit
1. The whole memory is programmed to 00h before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Table 61.
Program, WRITE and Erase times (3 V devices)
Symbol
Parameter
Min.
Flash Program
Typ.
8.5
Flash Bulk Erase (pre-programmed)(1)
3
Flash Bulk Erase (not pre-programmed)
5
tWHQV3
Sector Erase (pre-programmed)
1
tWHQV2
Sector Erase (not pre-programmed)
2.2
tWHQV1
Byte Program
14
Program / Erase Cycles (per sector)
tWHWLO
Sector Erase timeout
tQ7VQV
DQ7 valid to Output (DQ7-DQ0) valid (data polling)(2)
110/128
Doc ID 7833 Rev 7
s
30
s
s
30
s
s
1200
100,000
µs
cycles
100
µs
30
ns
PSD8XXFX
AC/DC parameters
1. The whole memory is programmed to 00h before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Figure 46. Peripheral I/O READ timing
ALE/AS
ADDRESS
A /D BUS
DATA VALID
tAVQV (PA)
tSLQV (PA)
CSI
tRLQV (PA)
tQXRH (PA)
tRHQZ (PA)
tRLRH (PA)
RD
tDVQV (PA)
DATA ON PORT A
AI02897
Table 62.
Port A Peripheral Data mode READ timing (5 V devices)
-70
Symbol
Parameter
-90
-15
Turbo
Conditions
Min Max Min Max Min Max
tAVQV–PA
Address valid to data valid
tSLQV–PA
CSI valid to data valid
(1)
off
Unit
37
39
45
+ 10
ns
27
35
45
+ 10
ns
21
32
40
ns
RD to data valid 8031 mode
32
38
45
ns
tDVQV–PA
Data In to data out valid
22
30
38
ns
tQXRH–PA
RD data hold time
(2)(3)
RD to data valid
tRLQV–PA
tRLRH–PA
RD pulse width
(2)
tRHQZ–PA
RD to data high-Z
(2)
0
0
0
ns
27
32
38
ns
23
25
30
ns
1. Any input used to select port A Data Peripheral mode.
2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
3. Data is already stable on port A.
Doc ID 7833 Rev 7
111/128
AC/DC parameters
Table 63.
PSD8XXFX
Port A Peripheral Data mode READ timing (3V devices)
-12
Symbol
Parameter
-15
-20
Turbo
Conditions
Min Max Min Max Min Max
tAVQV–PA
Address valid to data valid
tSLQV–PA
CSI valid to data valid
(1)
off
Unit
50
50
50
+ 20
ns
37
45
50
+ 20
ns
37
40
45
ns
RD to data valid 8031 mode
45
45
50
ns
tDVQV–PA
Data In to data Out valid
38
40
45
ns
tQXRH–PA
RD data hold time
tRLRH–PA
RD pulse width
(2)
RD to data high-Z
(2)
(2)(3)
RD to data valid
tRLQV–PA
tRHQZ–PA
0
0
0
ns
36
36
46
ns
36
40
45
ns
1. Any input used to select port A Data Peripheral mode.
2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
3. Data is already stable on port A.
Figure 47. Peripheral I/O WRITE timing
ALE/AS
A / D BUS
ADDRESS
DATA OUT
tWLQV
tWHQZ (PA)
(PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI02898
Table 64.
Port A Peripheral Data mode WRITE timing (5 V devices)
-70
Symbol
Parameter
-90
-15
Conditions
Unit
Min Max Min Max Min Max
tWLQV–PA
WR to data propagation delay
(1)
25
35
40
ns
tDVQV–PA
Data to port A data propagation delay
(2)
22
30
38
ns
tWHQZ–PA
WR invalid to port A tri-state
(1)
20
25
33
ns
1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2. Data stable on ADIO pins to data on port A.
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PSD8XXFX
Table 65.
AC/DC parameters
Port A Peripheral Data mode WRITE timing (3 V devices)
-12
Symbol
Parameter
-15
-20
Conditions
Unit
Min Max Min Max Min Max
WR to data propagation delay
(1)
42
45
55
ns
tDVQV–PA
Data to port A data propagation delay
(2)
38
40
45
ns
tWHQZ–PA
WR invalid to port A tri-state
(1)
33
33
35
ns
tWLQV–PA
1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2. Data stable on ADIO pins to data on port A.
Figure 48. Reset (RESET) timing
VCC
VCC(min)
tNLNH-PO
tNLNH
tNLNH-A
tOPR
Power-On Reset
tOPR
Warm Reset
RESET
AI02866b
Table 66.
Symbol
Reset (RESET) timing (5 V devices)
Parameter
tNLNH
RESET active low time(1)
tNLNH–PO
Power-on Reset active low time
Conditions
PSD834Fx)(2)
tNLNH–A
Warm Reset (on the
tOPR
RESET high to operational device
Min
Max
Unit
150
ns
1
ms
25
µs
120
ns
Max
Unit
1. Reset (RESET) does not reset Flash memory program or erase cycles.
2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode.
Table 67.
Symbol
Reset (RESET) timing (3 V devices)
Parameter
tNLNH
RESET active low time(1)
tNLNH–PO
Conditions
Min
300
ns
Power-on Reset active low time
1
ms
tNLNH–A
Warm Reset (on the PSD834Fx)(2)
25
µs
tOPR
RESET high to operational device
300
ns
1. Reset (RESET) does not reset Flash memory program or erase cycles.
2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode.
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AC/DC parameters
PSD8XXFX
Figure 49. ISC timing
t ISCCH
TCK
t ISCCL
t ISCPSU
t ISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 68.
ISC timing (5 V devices)
-70
Symbol
Parameter
-90
-15
Conditions
Unit
Min Max Min Max Min Max
tISCCF
Clock (TCK, PC1) frequency (except for
PLD)
(1)
tISCCH
Clock (TCK, PC1) high time (except for
PLD)
(1)
23
26
31
ns
tISCCL
Clock (TCK, PC1) low time (except for
PLD)
(1)
23
26
31
ns
tISCCFP
Clock (TCK, PC1) frequency (PLD only)
(2)
Clock (TCK, PC1) high time (PLD only)
(2)
240
240
240
ns
tISCCLP
Clock (TCK, PC1) low time (PLD only)
(2)
240
240
240
ns
tISCPSU
ISC port setup time
7
8
10
ns
tISCPH
ISC port hold up time
5
5
5
ns
tISCPCO
ISC port clock to output
21
23
25
ns
tISCPZV
ISC port high-impedance to valid output
21
23
25
ns
tISCPVZ
ISC port valid output to
high-Impedance
21
23
25
ns
tISCCHP
1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For program or erase PLD only.
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20
18
2
14
2
2
MHz
MHz
PSD8XXFX
Table 69.
AC/DC parameters
ISC timing (3 V devices)
-12
Symbol
Parameter
-15
-20
Conditions
Unit
Min Max Min Max Min Max
tISCCF
Clock (TCK, PC1) frequency (except for
PLD)
(1)
tISCCH
Clock (TCK, PC1) high time (except for
PLD)
(1)
40
45
51
ns
tISCCL
Clock (TCK, PC1) low time (except for
PLD)
(1)
40
45
51
ns
tISCCFP
Clock (TCK, PC1) frequency (PLD only)
(2)
tISCCHP
Clock (TCK, PC1) high time (PLD only)
(2)
240
240
240
ns
tISCCLP
Clock (TCK, PC1) low time (PLD only)
(2)
240
240
240
ns
tISCPSU
ISC port setup time
12
13
15
ns
tISCPH
ISC port hold up time
5
5
5
ns
tISCPCO
ISC port clock to output
30
36
40
ns
tISCPZV
ISC port high-Impedance to valid Output
30
36
40
ns
tISCPVZ
ISC port valid Output to high-Impedance
30
36
40
ns
12
10
2
9
2
MHz
2
MHz
1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For program or erase PLD only.
Table 70.
Power-down timing (5 V devices)
-70
Symbol
Parameter
-90
-15
Conditions
Unit
Min Max Min Max Min Max
tLVDV
ALE access time from Power-down
tCLWH
Maximum delay from APD Enable to
Internal PDN valid signal
80
Using CLKIN
(PD1)
90
150
ns
15 * tCLCL(1)
µs
1. tCLCL is the period of CLKIN (PD1).
Table 71.
Power-down timing (3 V devices)
-12
Symbol
Parameter
-15
-20
Conditions
Unit
Min Max Min Max Min Max
tLVDV
ALE access time from Power-down
tCLWH
Maximum Delay from APD Enable to
Internal PDN valid Signal
145
Using CLKIN
(PD1)
150
15 * tCLCL(1)
200
ns
µs
1. tCLCL is the period of CLKIN (PD1).
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Package mechanical
23
PSD8XXFX
Package mechanical
In order to meet environmental requirements, ST offers this device in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
116/128
Doc ID 7833 Rev 7
PSD8XXFX
Package mechanical
Figure 50. PQFP52 - 52-pin plastic quad flat package mechanical drawing
D
D1
D2
A2
e
E2 E1 E
Ne
b
N
1
A
Nd
CP
L1
c
A1
QFP-A
α
L
1. Drawing is not to scale.
Table 72.
PQFP52 - 52-pin plastic quad flat package mechanical dimensions
mm
inches
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
2.350
0.0930
A1
0.250
0.0100
A2
2.000
1.800
2.100
b
0.220
c
0.0790
0.0770
0.0830
0.380
0.0090
0.0150
0.110
0.230
0.0040
0.0090
D
13.200
13.150
13.250
0.5200
0.5180
0.5220
D1
10.000
9.950
10.050
0.3940
0.3920
0.3960
D2
7.800
–
–
0.3070
–
–
E
13.200
13.150
13.250
0.5200
0.5180
0.5220
E1
10.000
9.950
10.050
0.3940
0.3920
0.3960
E2
7.800
–
–
0.3070
–
–
e
0.650
–
–
0.0260
L
0.880
0.730
1.030
0.0350
0.0290
0.0410
L1
1.600
–
–
0.0630
α
0°
7°
0°
7°
N
52
52
Nd
13
13
Ne
13
13
CP
0.100
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0.0040
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Package mechanical
PSD8XXFX
Figure 51. PLCC52 - 52-lead plastic lead chip carrier package mechanical drawing
D
D1
A1
A2
M
M1
1 N
b1
e
D2/E2 D3/E3
E1 E
b
L1
L
C
A
CP
PLCC-B
1. Drawing is not to scale.
Table 73.
PLCC52-52-lead plastic lead chip carrier mechanical dimensions
mm
inches
Symbol
Typ.
118/128
Min.
Max.
A
4.190
A1
Typ.
Min.
Max.
4.570
0.1650
0.1800
2.540
2.790
0.1000
0.1100
A2
–
0.910
–
0.0360
B
0.330
0.530
0.0130
0.0210
B1
0.660
0.810
0.0260
0.0320
C
0.2460
0.2610
0.0097
0.0103
D
19.940
20.190
0.7850
0.7950
D1
19.050
19.150
0.7500
0.7540
D2
17.530
18.540
0.6900
0.7300
E
19.940
20.190
0.7850
0.7950
E1
19.050
19.150
0.7500
0.7540
E2
17.530
18.540
0.6900
0.7300
e
1.270
–
–
0.050
–
–
R
0.890
–
–
0.035
–
–
N
52
52
Nd
13
13
Ne
13
13
Doc ID 7833 Rev 7
PSD8XXFX
Package mechanical
Figure 52. TQFP64 - 64-lead thin quad flatpack, package outline
D
D1
D2
A2
e
E2 E1 E
Ne
b
N
1
A
Nd
CP
L1
c
A1
QFP-A
α
L
1. Drawing is not to scale.
Table 74.
TQFP64 - 64-lead thin quad flatpack, package mechanical data
mm
inches
Symb.
Typ.
A
Min.
Max.
1.420
1.540
Typ.
Min.
Max.
0.0560
0.0610
A1
0.100
0.070
0.140
0.0040
0.0030
0.0050
A2
1.400
1.360
1.440
0.0550
0.0540
0.0570
a
3.5°
0.0°
7.0°
3.5°
0.0°
7.0°
b
0.350
0.330
0.380
0.0140
0.0130
0.0150
c
0.170
0.006
D
16.000
15.900
16.100
0.6300
0.6260
0.6340
D1
14.000
13.980
14.030
0.5510
0.5500
0.5520
D2
12.000
11.950
12.050
0.4720
0.4700
0.4740
E
16.000
15.900
16.100
0.6300
0.6260
0.6340
E1
14.000
13.980
14.030
0.5510
0.5500
0.5520
E2
12.000
11.950
12.050
0.4720
0.4700
0.4740
e
0.800
0.750
0.850
0.0310
0.0300
0.0330
L
0.600
0.450
0.750
0.0240
0.0180
0.0300
L1
1.000
0.940
1.060
0.0390
0.0370
0.0420
CP
0.100
0.0040
N
64
64
Nd
16
16
Ne
16
16
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Part numbering
PSD8XXFX
24
Part numbering
Table 75.
Ordering information scheme
Example:
PSD8
1
3
F
2
V
A
– 15
J
1
T
Device Type
PSD8 = 8-bit PSD with register Logic
SRAM Capacity
1 = 16 Kbit
3 = 64 Kbit
5 = 256 Kbit
Flash Memory Capacity
3 = 1 Mbit (128K x 8)
4 = 2 Mbit (256K x 8)
2nd Flash Memory
2 = 256 Kbit Flash memory + SRAM
3 = SRAM but no Flash memory
4 = 256 Kbit Flash memory but no SRAM
5 = no Flash memory + no SRAM
Operating voltage
blank = VCC = 4.5 to 5.5V
V = VCC = 3.0 to 3.6V
Silicon Revision
A = Revision A
Speed
70 = 70ns
90 = 90ns
12 = 120ns
15 = 150ns
20 = 200ns
Package
J = ECOPACK-compliant PLCC52
M = ECOPACK-compliant PQFP52
U =ECOPACK-compliant TQFP64
Temperature Range
blank = 0 to 70°C (commercial)
I = –40 to 85°C (industrial)
Option
T = Tape & Reel Packing
For a list of available options (e.g., speed, package) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
120/128
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PSD8XXFX
PQFP52 pin assignments
Appendix A
Table 76.
PQFP52 pin assignments
PQFP52 connections (see Features)
Pin number
Pin assignments
1
PD2
2
PD1
3
PD0
4
PC7
5
PC6
6
PC5
7
PC4
8
VCC
9
GND
10
PC3
11
PC2
12
PC1
13
PC0
14
PA7
15
PA6
16
PA5
17
PA4
18
PA3
19
GND
20
PA2
21
PA1
22
PA0
23
AD0
24
AD1
25
AD2
26
AD3
27
AD4
28
AD5
29
AD6
30
AD7
31
VCC
32
AD8
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PQFP52 pin assignments
Table 76.
122/128
PSD8XXFX
PQFP52 connections (see Features) (continued)
Pin number
Pin assignments
33
AD9
34
AD10
35
AD11
36
AD12
37
AD13
38
AD14
39
AD15
40
CNTL0
41
RESET
42
CNTL2
43
CNTL1
44
PB7
45
PB6
46
GND
47
PB5
48
PB4
49
PB3
50
PB2
51
PB1
52
PB0
Doc ID 7833 Rev 7
PSD8XXFX
PLCC52 pin assignments
Appendix B
Table 77.
PLCC52 pin assignments
PLCC52 connections (see Features)
Pin number
Pin assignments
1
GND
2
PB5
3
PB4
4
PB3
5
PB2
6
PB1
7
PB0
8
PD2
9
PD1
10
PD0
11
PC7
12
PC6
13
PC5
14
PC4
15
VCC
16
GND
17
PC3
18
PC2
19
PC1
20
PC0
21
PA7
22
PA6
23
PA5
24
PA4
25
PA3
26
GND
27
PA2
28
PA1
29
PA0
30
AD0
31
AD1
32
AD2
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PLCC52 pin assignments
Table 77.
124/128
PSD8XXFX
PLCC52 connections (see Features) (continued)
Pin number
Pin assignments
33
AD3
34
AD4
35
AD5
36
AD6
37
AD7
38
VCC
39
AD8
40
AD9
41
AD10
42
AD11
43
AD12
44
AD13
45
AD14
46
AD15
47
CNTL0
48
RESET
49
CNTL2
50
CNTL1
51
PB7
52
PB6
Doc ID 7833 Rev 7
PSD8XXFX
TQFP64 pin assignments
Appendix C
Table 78.
TQFP64 pin assignments
TQFP64 connections (see Features)
Pin number
Pin assignments
1
PD2
2
PD1
3
PD0
4
PC7
5
PC6
6
PC5
7
VCC
8
VCC
9
VCC
10
GND
11
GND
12
PC3
13
PC2
14
PC1
15
PC0
16
NC
17
NC
18
NC
19
PA7
20
PA6
21
PA5
22
PA4
23
PA3
24
GND
25
GND
26
PA2
27
PA1
28
PA0
29
AD0
30
AD1
31
N/D
32
AD2
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TQFP64 pin assignments
Table 78.
126/128
PSD8XXFX
TQFP64 connections (see Features) (continued)
Pin number
Pin assignments
33
AD3
34
AD4
35
AD5
36
AD6
37
AD7
38
VCC
39
VCC
40
AD8
41
AD9
42
AD10
43
AD11
44
AD12
45
AD13
46
AD14
47
AD15
48
CNTL0
49
NC
50
RESET
51
CNTL2
52
CNTL1
53
PB7
54
PB6
55
GND
56
GND
57
PB5
58
PB4
59
PB3
60
PB2
61
PB1
62
PB0
63
NC
64
NC
Doc ID 7833 Rev 7
PSD8XXFX
Revision history
Revision history
Table 79.
Document revision history
Date
Revision
Changes
15-Oct-99
1.0
Initial release as a WSI document
27-Oct-00
1.1
Port A Peripheral Data mode Read Timing, changed to 50
30-Nov-00
1.2
PSD85xF2 added
23-Oct-01
2.0
Document rewritten using the ST template
07-Apr-03
3.0
v2.2 Template applied; voltage correction (Table 75)
12-Jun-03
3.1
Fix errors in PQFQ52 Connections
02-Oct-03
3.2
Correct Instructions (Table 10); update disclaimer, Title for EDOCS
application
17-Nov-03
3.3
Correct package references (Features)
04-Jun-04
4.0
Reformatted (adjust RPN list); added Table 9; added ‘U’ package
(64-pin) (Features, Figure 3, Figure 52; Table 74, Table 75,
Table 78); 5V split from original
05-Jan-06
5.0
Added Silicon Revision A into part numbering scheme. See Table 75
13-Feb-2009
6
Document reformatted.
Removed root part number PSD813F3.
SRAM standby mode removed. Backup battery feature removed.
All products are delivered in ECOPACK-compliant packages.
Section 23: Package mechanical updated.
Minor text modifications.
05-May-2009
7
Corrected pin 7 of TQFP64 package in Figure 3: TQFP64
connections.
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PSD8XXFX
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