ST6G3240 Dual supply level translator for dual memory cards (mini SD/micro SD + managed NAND) Features ■ High speed: tPD (A to B) = 5 ns at TA = 85 °C with VCCA = 1.8 V, VCCBn = 3.0 V ■ Low power dissipation: ICCA = ICCBn = 5 µA (max.) at TA = 85 °C ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: – VCCA (opr) = 1.4 to 3.6 V – VCCBn (opr) = 1.4 to 3.6 V ■ B-side power supplies (VCCB1 and VCCB2) can be different and separately controlled ■ Interchangeable voltage levels: VCCA can either be greater than or less than VCCBn ■ Low power mode: when VCCBn is grounded or floating, there is very low quiescent current on VCCA μTFBGA 36 Description ■ Power down detection: when either one of the B-side power supplies (VCCB1 and VCCB2) is grounded or floating, the corresponding port-n goes into high-Z state automatically ■ Latch-up performance exceeds 500 mA (JESD17) ■ ESD protection: 2 kV HBM ■ Integrated pull-up resistor and level translator on the MS_Insert pin ■ Integrated pull-up resistor for card-detect pin The ST6G3240 is a dual supply low voltage CMOS level translator supporting the dual function of mini SD/micro SD card and managed NAND memories. It is designed for use as an interface between three systems using 3.3, 2.5 and 1.8 V respectively. The ST6G3240 is capable of achieving high speed operation and at the same time maintaining low power dissipation. While the A port is designed to track VCCA, the Bn port (nCMD, nDAT, nCLK) is designed to track VCCBn. The device is intended for a two-way asynchronous communication between data buses. Table 1. April 2008 Device summary Order code Package Packing ST6G3240TBR μTFBGA36 (3.6 x 3.6 mm) Tape and reel Rev 2 1/29 www.st.com 29 Contents ST6G3240 Contents 1 ST6G3240 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/29 ST6G3240 1 ST6G3240 general description ST6G3240 general description The ST6G3240 is a dual supply low voltage CMOS level translator supporting the dual function of mini SD/micro SD card and managed NAND memories. It is designed for use as an interface between three systems using 3.3, 2.5 and 1.8 V respectively. The ST6G3240 is capable of achieving high speed operation and at the same time maintaining low power dissipation. While the A port is designed to track VCCA, the Bn port (nCMD, nDAT, nCLK) is designed to track VCCBn. The device is intended for a two-way asynchronous communication between data buses. The direction of data transmission is determined by CMD-dir/DATA0-dir/DAT123-dir inputs. In the typical application the Bn-port interfaces with the 3 V bus and the A-port with the 1.8V bus. With interchangeable voltage levels, there is no restriction on the voltage settings for each supply. VCCA can be less than or greater than VCCB1 or VCCB2. For example, VCCA = 2.5 V, VCCB1 = 3.6 V, VCCB2 = 1.8 V. Full low power mode This device can be entered into 'full lower power mode' by setting all the INn pins to low or high, which will disable the device completely. Partial low power mode Alternatively, the device can be set into 'partial low power mode' by grounding or floating one of the VCCBn power supplies. This will set all the corresponding output Port-n to High-Z. However, it is important to note that VCCA power supply must not be grounded or floating whenever VCCBn is connected to a power supply as this will lead to significant current consumption increase. 3/29 Pin settings ST6G3240 2 Pin settings 2.1 Pin connection Figure 1. Pin connection (top through view) 1 2 3 4 5 6 A B C D E F μTFBGA36 Table 2. Pin mapping 1 Note: 4/29 2 3 4 5 6 A VCCA GND IN1 CD GND VCCB1 B CMD.h CMD-dir IN2 1CMD 1DAT0 2DAT0 C DAT0.h DAT0-dir GND 2CMD 1DAT1 2DAT1 D DAT1.h DAT123-dir GND GND 1DAT2 2DAT2 E DAT2.h CLK-f 2CLK 1CLK 1DAT3 2DAT3 F DAT3.h CLK-h MS_Insert MS_InsertB 1 GND VCCB2 It is required that VCC supply and ground pins are in close proximity, so as to allow for easy capacitive coupling in application. ST6G3240 2.2 Pin settings Pin description Table 3. Pin description Pin Type Side Symbol Name and function A1 - A VCCA A-side power supply A2 - - GND Ground (0 V) A3 I A IN1 Output enable pin. Functions together with IN2 pin. Refer to truth table for more information on the settings A4 - A CD Card detect pin with 100 kΩ internal pullup resistor on the A-side A5 - - GND Ground (0 V) A6 - B1 VCCB1 B1-side power supply B1 I/O A CMD.h Command pin for A-side B2 I A CMD-dir B3 I A IN2 B4 I/O B1 1CMD Command pin for B1-side B5 I/O B1 1DAT0 Data0 pin for B1-side B6 I/O B2 2DAT0 Data0 pin for B2-side C1 I/O A DAT0.h Data0 pin for A-side C2 I A DAT0-dir C3 - - GND C4 I/O B2 2CMD Command pin for B2-side C5 I/O B1 1DAT1 Data1 pin for B1-side C6 I/O B2 2DAT1 Data1 pin for B2-side D1 I/O A DAT1.h Data1 pin for A-side Command direction pin HIGH => CMD.h input, nCMD output LOW => CMD.h output, nCMD input Output enable pin. Functions together with IN1 pin. Refer to truth table for more information on the settings Data direction pin for DAT0 HIGH => DAT0.h input, nDAT0 output LOW => DAT0.h output, nDAT0 input Ground (0 V) Data direction pin for DAT1-DAT3 HIGH => DAT123.h input, nDAT123 output LOW => DAT123.h output, nDAT123 input D2 I A DAT123-dir D3 - - GND Ground (0 V) D4 - GND Ground (0 V) D5 I/O B1 1DAT2 Data2 pin for B1-side 5/29 Pin settings ST6G3240 Table 3. Pin description (continued) Pin Type Side Symbol Name and function D6 I/O B2 2DAT2 Data2 pin for B2-side E1 I/O A DAT2.h Data2 pin for A-side E2 O A CLK-f Feedback clock pin on A-side E3 O B2 2CLK Clock Output pin for B2-side E4 O B1 1CLK Clock Output pin for B1-side E5 I/O B1 1DAT3 Data3 pin for B1-side E6 I/O B2 2DAT3 Data3 pin for B2-side F1 I/O A DAT3.h Data3 pin for A-side F2 I A CLK.h Clock input pin for A-side F3 - A MS_Insert F4 O B1 F5 - - GND Ground (0V) F6 - B2 VCCB2 B2-side power supply MS_Insert pin with 100 kΩ internal pullup resistor on A-side MS_InsertB1 MS_Insert pin on B1-side CMD Command pin is a bidirectional line. The host and card drivers are operating in push-pull configuration. DAT0-3 All data lines are bi-directional lines. Host and card drivers operate in push-pull mode. CLK Clock is a host to card signal. CLK operates in push-pull mode. Feedback (return) clock is a feedback clock signal from level shifter to the host for controlling delays. CD Card detect with internal pull up resistor. Pin will be pulled to VCCA when it is in high state. IN1, IN2 Selection pins. When IN1 and IN2 are set to disabled state, all the data bus will be in highimpedance. When enabled, all the data bus will be working as a level translator between port A and port Bn (refer to the truth table for possible pin configuration). 6/29 ST6G3240 3 Logic diagram Logic diagram Figure 2. ST6G3240 logic block diagram V CCB1 VCCA CMD-dir 1CMD CMD.h 1DAT0 1DAT1 1DAT2 1DAT3 DATA0-dir DAT0.h 1CLK DAT123-dir DAT1.h V CCB2 DAT2.h DAT3.h 2CMD 2DAT0 2DAT1 2DAT2 2DAT3 2CLK CLK.h CLK - f IN1 VCCA IN2 100kΩ V CCB1 100kΩ CD MS_ InsertB1 MS_ Insert GND CS00091 7/29 Logic diagram ST6G3240 Figure 3. Input and output equivalent circuit Table 4. Truth table DAT123dir IN1 IN2 CMD-dir DAT0-dir CMD.h DAT0.h DAT1.h DAT2.h 1CMD 2CMD 1DAT0 2DAT0 CLK.h 1DAT1 2DAT1 CLK-f.h 1DAT2 2DAT2 1DAT3 2DAT3 1CLK 2CLK DAT3.h H H H-Z H-Z H-Z H-Z H-Z H-Z L H Active Active Active Active Active H-Z H L Active Active Active Active H-Z Active L L H-Z H-Z H-Z H-Z H-Z H-Z H - Z: high impedance Table 5. 8/29 MS_Insert truth table MS_Insert (referenced to VCCA) MS_InsertB1 (referenced to VCCB1) H H L L ST6G3240 4 Maximum rating Maximum rating Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute maximum ratings Symbol Value Unit VCCA Supply voltage -0.5 to 4.6 V VCCB1 Supply voltage -0.5 to 4.6 V VCCB2 Supply voltage -0.5 to 4.6 V DC input voltage -0.5 to 4.6 V VI/OA DC I/O voltage (output disabled) -0.5 to 4.6 V VI/OBn DC I/O voltage (output disabled) -0.5 to 4.6 V VI VOA DC output voltage -0.5 to VCCA +0.5 V VOBn DC output voltage -0.5 to VCCBn +0.5 V IIK DC input diode current - 20 mA IOK DC output diode current - 50 mA IOA DC output current ± 50 mA IOBn DC output current ± 50 mA ICCA DC VCCA or ground current ± 100 mA ICCBn DC VCCBn or ground current ± 100 mA 400 mW -65 to 150 °C 260 °C PD Power dissipation at TA = 70 ºC Tstg Storage temperature TL 1. Parameter (1) Lead temperature (10 sec) Derate above 70ºC by 18.5 mW/C Table 7. Recommended operating conditions Symbol Parameter Value Unit VCCA Supply voltage 1.4 to 3.6 V VCCB1 Supply voltage 1.4 to 3.6 V VCCB2 Supply voltage 1.4 to 3.6 V Input voltage (/IN1, /IN2, CMD-dir, DAT0-dir, DAT123-dir) 0 to VCCA V VI/OA I/O voltage 0 to VCCA V VI/OBn I/O voltage 0 to VCCBn V VI 9/29 Maximum rating ST6G3240 Table 7. Recommended operating conditions (continued) Symbol 10/29 Parameter Value Unit Top Operating temperature -40 to 85 °C dt/dv Input rise and fall time 0 to 10 ns/V ST6G3240 Electrical characteristics 5 Electrical characteristics Table 8. DC specifications for VCCA Test conditions Symbol Parameter VCCA (V) TA = 25 °C VCCB (V) Min 1.4 − 1.95 VIH High level input voltage 1.95 − 2.7 Value 1.4 − 3.6 2.7 − 3.6 Low level input voltage 1.95 − 2.7 0.65 VCCA 1.7 1.7 2.0 2.0 1.4 − 3.6 2.7 − 3.6 1.4 − 3.6 IOH = -100 µA VOH VOL Low level output voltage V 0.35 VCCA 0.35 VCCA 0.7 0.7 0.8 0.8 VCCA-0.1 IOH = -1 mA 1.20 1.20 IOH = -2 mA 1.40 1.40 IOH = -4 mA 2.30 2.30 3 IOH = -8 mA 2.45 2.45 3.6 IOH = -8 mA 3.05 3.05 1.4 − 3.6 IOL = 100µA 0.10 0.10 1.4 IOL = 1 mA 0.20 0.20 IOL = 2 mA 0.25 0.25 IOL = 4 mA 0.40 0.40 3 IOL = 8 mA 0.55 0.55 3.6 IOL = 8 mA 0.55 0.55 1.65 2.7 1.65 2.7 1.4 − 3.6 1.4 − 3.6 Unit Max VCCA-0.1 1.4 High level output voltage Min 0.65 VCCA 1.4 − 1.95 VIL Max -40 to 85 °C V V V IIA Input leakage current per input channel 1.4 − 3.6 1.4 − 3.6 VIA = VCCA or GND ±0.5 ±5 µA IDIR Input leakage current per control input (DIR) 1.4 − 3.6 1.4 − 3.6 VDIR = VCCA or GND ±0.1 ±2 µA 11/29 Electrical characteristics Table 8. ST6G3240 DC specifications for VCCA (continued) Test conditions Symbol Parameter VCCA (V) Value TA = 25 °C VCCB (V) Min Max -40 to 85 °C Min Unit Max VIA = GND to 3.6 V VIBn = GND 3.6 to 3.6 V IN1, IN2 = VCCA or IN1, IN2 = GND ±1.0 ±10 µA VIA= 0 to 3.6 V INn = 0, DIR=0 ±1.0 ±10 µA IOZA High impedance output leakage current IOFF Power off A-side I/O leakage current ICD CD pin input leakage current 3.6 1.4 − 3.6 VCD = 0 50 500 µA IMS MS pin input leakage current 3.6 1.4 − 3.6 VMS = 0 50 500 µA 12/29 1.4-3.6 0 1.4 − 0 1 All A-ports I/Os and control inputs are powered by VCCA. 2 All Bn-ports I/Os are powered by VCCBn. 3 There is no restriction on VCCA or VCCBn, either one can be greater than the other. ST6G3240 Table 9. Electrical characteristics DC specification for VCCBn Test conditions Symbol VIH VIL Parameter High level input voltage Low level input voltage TA = 25 °C High level output voltage VCCBn (V) (V) Min 1.4 – 1.95 0.65 VCCBn 0.65 VCCBn 1.95 – 2.7 1.7 1.7 2.7 – 3.6 2.0 2.0 1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 IIBn Low level output voltage Input leakage current per input channel Min Unit Max V 0.35 VCCBn 0.35 VCCBn 1.95 – 2.7 0.7 0.7 2.7 – 3.6 0.8 0.8 V VCCBn0.1 VCCBn0.1 1.4 IOH = -1 mA 1.10 1.10 1.65 IOH = -2 mA 1.20 1.20 2.7 IOH = -4 mA 2.20 2.20 3.0 IOH = -8 mA 2.30 2.30 3.6 IOH = -8 mA 3.00 3.00 V 0.20 0.20 1.4 IOL = 1 mA 0.35 0.35 1.65 IOL = 2 mA 0.45 0.45 2.7 IOL = 4 mA 0.55 0.55 3.0 IOL = 8 mA 0.70 0.70 3.6 IOL = 8 mA 0.70 0.70 1.4 – 3.6 VIBn = VCCBn or GND ±0.5 ±5 µA ±1.0 ±10 µA ±1.0 ±10 µA 1.4 – 3.6 1.4 – 3.6 Max 1.4 – 1.95 1.4 – 3.6 IOL = 100 µA VOL -40 to 85 °C VCCA 1.4 – 3.6 IOH = -100 µA VOH Value IOZBn High impedance output leakage current 3.6 3.6 VIA = GND to 3.6 V VIBn = GND to 3.6 IN1,IN2 = VCCA or IN1,IN2 = GND IOFF Power off Bside I/O leakage current 0 0 VIBn= 0 to 3.6 V INn= 0, DIR =0 V 13/29 Electrical characteristics Table 10. ST6G3240 DC quiescent current Test conditions Symbol ICCA ICCBn ICCAZ 14/29 Parameter Quiescent supply current for A-side Quiescent supply current for Bn-side High impedence quiescent supply current for Aside VCCA VCCB1 VCCB2 (V) (V) (V) 1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 0 1.4 – 3.6 1.4-3.6 1.4 – 3.6 0 1.4 – 3.6 VIA = VCCA or 1.4 – 3.6 GND VIBn = VCCBn or 0 GND VCD = VMS = VCCA 0 Value Unit TA = 25 °C -40 to 85 °C Min Min Max Max 1 5 1 5 1 5 1 5 1 5 1.4 – 3.6 1.4 – 3.6 VIA =VCCA or GND or V =V 1.4 – 3.6 IBn CCBn GND VCD = VMS = VCCA 1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 IN1 = GND/VCCA IN2 = GND/VCCA 0.2 1 1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 IN1 = VCCA and IN2 = GND 0.5 2 1.4 – 3.6 1.4 – 3.6 1.4 – 3.6 IN1 = GND and IN2 = VCCA 0.5 2 μA μA μA ST6G3240 Table 11. Electrical characteristics AC electrical characteristics (f = 10 MHz, 50% duty cycle(1)) VCCA = 1.5 V ±0.1 V Paramete r From To (input) (output) VCCBn=1.8 V ± 0.15 V Min tPLHAB, tPHLAB tPLHBA, tPHLBA Propagation delay time from A to B (CL= 15 pF, RL= 2 kΩ) Propagation delay time from B to A (CL = 7 pF, RL = 2 kΩ) Max VCCBn= 2.5 V ± 0.2 V VCCBn = 3.0 ± 0.3 V Min Min Max Max VCCBn=3.3 V ± 0.3 V Min Unit Max CMD.h nCMD 9 6 5.5 5.5 CLK.h nCLK 9 6 5.5 5.5 CLK.h CLK-f 18 12 11 11 DATx.h nDATx 9 6 5.5 5.5 nCMD CMD.h 9 9 9 9 nDATx DATx.h 9 9 9 9 22 22 22 22 ns ns Output enable time (CL =7 pF, RL = 2 kΩ) INn Output enable time (CL = 15 pF, RL = 2 kΩ) INn Bn 22 22 22 22 Output disable time (CL=7 pF, RL= 2 kΩ ) INn A 33 33 33 33 Output disable time (CL= 15 pF, RL= 2 kΩ) INn Bn 33 33 33 33 DIR A 8 8 8 8 DIR B 9 9 9 9 tDIR, DIR A 7 7 7 7 disable DIR B 8 8 8 8 tOSLH,tOS Output to output skew time(2) HL 1 1 1 1 ns tCDLH,tCD Clock and data skew time HL 1 1 1 1 ns tPZL, tPZH tPLZ, tPHZ tDIR, enable A ns ns ns ns A Bn 52 52 52 52 Bn A 52 52 52 52 A Bn 104 104 104 104 Bn A 104 104 104 104 Clock fmax MHz Data Mbps 1. Refer to figure 4. 2. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either High or Low ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | ) 15/29 Electrical characteristics Table 12. ST6G3240 VCCA = 1.8 V ± 0.15 V Parameter From To (input) (output) VCCBn = 1.8 V ± 0.15 V Min tPLHAB, tPHLAB tPLHBA, tPHLBA Propagation delay time from A to B (CL= 15 pF, RL= 2 kΩ) Propagation delay time from B to A (CL=7 pF, RL= 2 kΩ ) Max VCCBn= 2.5V ± 0.2V Min Max VCCBn= 3.0 ± 0.3 V VCCBn = 3.3 V ± 0.3V Min Min Max Unit Max CMD.h nCMD 8.5 5.5 5 5 CLK.h nCLK 8.5 5.5 5 5 CLK.h CLK-f 17 11 10 10 DATx.h nDATx 8.5 5.5 5 5 CMD.h 7 7 7 7 nDATx DATx.h 7 7 7 7 15 15 15 15 ns nCMD ns Output enable time (CL=7pF, RL=2 kΩ ) INn Output enable time (CL= 15 pF, RL=2 kΩ ) INn Bn 15 15 15 15 Output disable time (CL= 7 pF, RL= 2 kΩ ) INn A 22 22 22 22 Output disable time (CL= 15 pF, RL= 2 kΩ ) INn Bn 22 22 22 22 DIR A 7 7 7 7 DIR B 8 8 8 8 DIR A 5 5 5 5 DIR B 6 6 6 6 tOSLH,tOSH Output to output skew time(1) L 1 1 1 1 ns tCDLH,tCDH Clock and data skew time L 1 1 1 1 ns tPZL, tPZH tPLZ, tPHZ tDIR, enable A ns ns ns tDIR, disable ns A Bn 52 52 52 52 Bn A 52 52 52 52 A Bn 104 104 104 104 Bn A 104 104 104 104 Clock fmax MHz Data 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | ) 16/29 Mbp s ST6G3240 Table 13. Electrical characteristics VCCA = 2.5 ± 0.2 V From To (input) (output) Parameter tPLHAB, tPHLAB tPLHBA, tPHLBA tPZL, tPZH tPLZ, tPHZ VCCBn=2.5V ± 0.2V Min Min Max Max VCCBn=3.0 ± 0.3V Min Max VCCBn=3.3V ± 0.3V Min Unit Max CMD.h nCMD 7.5 5 4.5 4.5 CLK.h nCLK 7.5 5 4.5 4.5 CLK.h CLK-f 15 10 9 9 DATx.h nDATx 7.5 5 4.5 4.5 Propagation nCMD delay time from B to A nDATx (CL= 7 pF, RL= 2 kΩ) CMD.h 5 5 5 5 DATx.h 5 5 5 5 A 11 11 11 11 Propagation delay time from A to B ( CL= 15 pF, RL= 2 kΩ) ns ns Output enable time (CL= 7 pF, RL= 2 kΩ ) INn Output enable time (CL=15 pF, RL= 2 kΩ) INn Bn 11 11 11 11 Output disable time (CL=7 pF, RL=2 kΩ ) INn A 21 21 21 21 ns Output disable time (CL= 15 pF, RL=2 kΩ) INn Bn 21 21 21 21 ns DIR A 5 5 5 5 DIR B 6 6 6 6 DIR A 5 5 5 5 DIR B 6 6 6 6 1 1 1 1 ns 1 1 1 1 ns ns ns tDIR, enable tDIR, disable ns Output to tOSLH,tOSHL output skew time(1) tCDLH,tCDHL Clock and data skew time fmax VCCBn=1.8V ± 0.15V A Bn 52 52 52 52 Bn A 52 52 52 52 A Bn 104 104 104 104 Bn A 104 104 104 104 Clock MHz Data Mbps 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | ) 17/29 Electrical characteristics Table 14. ST6G3240 VCCA = 3.3 V ± 0.3 V Parameter From To VCCBn = 1.8 V ± 0.15 V Min tPLHAB, tPHLAB tPLHBA, tPHLBA CMD.h nCMD Propagation delay time from CLK.h nCLK A to B CLK.h CLK-f (CL = 15 pF, RL= 2 kΩ) DATx.h nDATx Propagation delay time from B to A (CL= 7 pF, RL= 2 kΩ ) Output enable time (CL= 7 pF, RL= 2 kΩ ) tPZL, tPZH tPLZ, tPHZ Max Min Max VCCBn = Unit 3.3 V ± 0.3 V Min Max 7 4.5 4.3 4.3 7 4.5 4.3 4.3 14 9 8.6 8.6 7 4.5 4.3 4.3 CMD.h 4 4 4 4 nDATx DATx.h 4 4 4 4 9 9 9 9 nCMD ns ns INn A ns INn Bn 9 9 9 9 Output disable time (CL = 7 pF, RL= 2 kΩ) INn A 20 20 20 20 Output disable time (CL= 15 pF, RL=2 kΩ) ns INn Bn 20 20 20 20 DIR A 4 4 4 4 DIR B 5 5 5 5 DIR A 4 4 4 4 DIR B 5 5 5 5 1 1 1 1 ns 1 1 1 1 ns ns tDIR, disable L Min VCCBn = 3.0 ± 0.3 V Output enable time (CL = 15 pF, RL = 2 kΩ) tDIR, enable tOSLH,tOSH Max VCCBn = 2.5 V ± 0.2 V ns Output to output skew time(1) tCDLH,tCDH Clock and data skew time L A Bn 52 52 52 52 Bn A 52 52 52 52 A Bn 104 104 104 104 Bn A 104 104 104 104 Clock fmax MHz Data 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW ( tOSLH = | tPLHm - tPLHn |, tOSHL = | tPHLm – tPHLn | ) 18/29 Mbp s ST6G3240 Table 15. Electrical characteristics Output slew rate (f = 1 MHz, 50% duty cycle, CL=15 pF on Bn-side; CL=7 pF on A-side) Test condition TA = -40 to 85 °C Symbol Parameter From VCCA = 1.8 V ± 0.15V To Unit VCCBn = 3.0 V ± 0.3V Min Max tr Rise time 10% 90% 3.5 ns tf Fall time 10% 90% 3.5 ns Table 16. Capacitance characteristics Test condition Symbol Parameter VCCA (V) VCCBn (V) Open Open CINBn Input capacitance CI/OA Input/output capacitance for A-side 1.8 3.0 CI/OBn Input/output capacitance for Bn-side 1.8 3.0 Power dissipation capacitance 2.5 3.3 CPD Value TA = 25 °C Min Typ 3.3 Max Min Unit Max 9 pF f = 1 MHz VBIAS = 250 mV VPP = 500 mV 5 pF f = 1 MHz VBIAS = 250 mV VPP = 500 mV 11 pF 29 f = 10 MHz 1.8 -40 to 85 °C pF 29 19/29 Test circuit 6 ST6G3240 Test circuit Figure 4. Test circuit Table 17. Test circuit switches RL/R1 (kΩ) CL (pF) Test Switch A-side B-side tPLH, tPHL 7 15 2 Open tPZL, tPLZ 7 15 2 2 VCC tPZH, tPHZ 7 15 2 GND RT is the Zout of the pulse generator, typically 50Ω. Table 18. Waveform symbol value VCC Symbol 20/29 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V VIH VCC VCC VCC VM 1.5 V VCC/2 VCC/2 VX VOL + 0.3 V VOL + 0.15 V VOL + 0.15 V VY VOH - 0.3 V VOH - 0.15 V VOH - 0.15 V ST6G3240 Test circuit Figure 5. Waveform - propagation delay (f = 1 MHz, 50% duty cycle) Figure 6. Waveform - output enable/disable (f = 1 MHz, 50% duty cycle) IN 1, IN2 21/29 Base Band 22/29 100kΩ 100kΩ VCCA 01 10 VCCB1 2DAT0 2DAT1 2DAT2 2DAT3 2CMD 2CLK MS_InsertB1 6 6 VCCB2 Auto short to ground via the M2 card internal circuitry when card is inserted. (1) MS_Insert CD IN1 IN2 10 ST6G3240 ... R R R Card Detection external switch Combocard holder (MicroSD + M2) MS_Insert (1) CD 1DAT0 1DAT1 1DAT2 1DAT3 1CMD 1CLK Figure 7. GPIO option DAT0 DAT1 DAT2 DAT3 DAT0 DIR DAT123 DIR CMD CMD DIR CLK CLK-f VCCA Test circuit ST6G3240 Application block diagram ST6G3240 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 8. μTFBGA package outline 23/29 Package mechanical data Table 19. ST6G3240 μTFBGA 36 mechanical data Millimeters Symbol A Min Typ Max 1 1.1 1.16 A1 0.25 A2 0.78 b 0.25 0.30 0.35 D 3.50 3.60 3.70 D1 E Figure 9. 24/29 0.86 2.50 3.50 3.60 E1 2.50 e 0.50 F 0.55 Recommended footprint 3.70 ST6G3240 Package mechanical data Figure 10. Carrier tape information 25/29 Package mechanical data ST6G3240 Figure 11. Reel dimensions Table 20. 26/29 Reel dimensions Tape width N W1 W2 max C 12 178 ± 5 mm 12.4 (+2,-0) 18.4 13 ± 0.25 ST6G3240 Package mechanical data Figure 12. Reel information 27/29 Revision history 8 ST6G3240 Revision history Table 21. 28/29 Document revision history Date Revision Changes 27-Mar-2008 1 Initial release. 18-Apr-2008 2 Minor text changes. Modified fmax values in Table 11, Table 12, Table 13 and Table 14. ST6G3240 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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