STMICROELECTRONICS STVM100DC6E

STVM100
I2C LCD VCOM calibrator
Features
■
I2C interface, slave address: 1001111
■
7-bit adjustable sink current output
■
2.25V to 3.6V logic supply voltage VDD
■
AVDD operating voltages
– 4.5V to 20V for VDD from 2.6V to 3.6V
– 4.5V to 13V for VDD from 2.25V to 3.6V
■
EEPROM for storing the optimum VCOM setting
■
Guaranteed monotonic output over operating
range
■
400kHz maximum interface bus speed
■
Operating temperature: –40°C to 85°C
■
Available in an 8-pin 3mm x 3mm TDFN8 or
3mm x 3mm TSSOP8 Package
TDFN8 (3mm x 3mm) (DC)
TSSOP8 (3mm x 3mm) (DS)
Description
The STVM100 is a programmable VCOM adjustment solution for thin-film transistor (TFT) liquidcrystal displays (LCDs) to remove “flickers”. It can
replace a mechanical potentiometer, so that the
factory operator can physically view the front
screen when performing the VCOM adjustment.
This significantly reduces labor costs, increases
reliability, and enables automation.
STVM100 provides a digital I2C interface to control the sink current output (IOUT). This output
drives an external resistive voltage divider, which
can then be applied to an external VCOM buffer.
Three external resistors R1, R2, and RSET determine the highest and lowest value of the VCOM.
An increase in the output sink current will lower
the voltage on the external divider so that the
VCOM can be adjusted by 128 steps within this
range. Once the desired VCOM setting is
achieved, it can be stored in the internal
EEPROM that will be automatically recalled during each power-up.
STVM100 is available in an 8-pin, 3mm x 3mm
TDFN8 or 3mm x 3mm TSSOP8 package.
Applications
■
TFT-LCD panels
Table 1.
Device summary
Order code
Optimum temperature range
Package
Packing
STVM100DC6E
-40°C to 85°C
TDFN
ECOPACK package, tubes
STVM100DS6F
-40°C to 85°C
TSSOP
ECOPACK package, tape and reel
July 2007
Rev 6
1/27
www.st.com
1
Contents
STVM100
Contents
1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2-wire bus characteristics and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
VDD power supply ramp-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
STVM100
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Bit P read and write mode values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MLPD-DFN 3 x 3 x .75mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . 23
TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data. . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
List of figures
STVM100
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
4/27
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connections diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read/write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R1, R2, and RSET connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VDD supply current v’s VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AVDD supply current v’s AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VDD supply current v’s temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AVDD supply current v’s temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IOUT error v’s temperature (STVM100 at middle scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Total unadjusted error v’s DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Differential non-linearity v’s DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Integral non-linearity v’s DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AVDD power-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Full scale-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Full scale-down response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MLPD-DFN 3 x 3 x.75mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . 23
TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data. . . . . . . . . . . . . . . . 24
STVM100
1
Device overview
Device overview
Figure 1.
Logic diagram
VDD
AVDD
SDA
SCL
OUT
STVM100
SET
WP
GND
AI12272
Table 2.
Pin names and functions
Name
Type
OUT
Analog
Adjustable sink current output pin. (1)
See Section 3: Application information on page 11.
AVDD
Supply
High-voltage analog supply.
Bypass to GND with a 0.1µF capacitor.
WP
Input
GND
Function
WRITE protectection.
Active-low. To enable write operations to the DAC or to the EEPROM
writing, connect to 0.7VDD or greater. Internally pulled down by a 130kΩ
resistor.
Supply ground.
VDD
Supply
System power supply input.
Bypass to GND with a 0.1µF capacitor.
SDA
In/Out
I2C serial data input/output.
SCL
Input
I2C serial clock input.
SET
Analog
Maximum sink current adjustment point.
Connect a resistor from SET to GND to set the maximum adjustable sink
current of the OUT pin. The maximum adjustable sink current is equal to
AVDD /20 divided by RSET (see Figure 4 on page 6).
1. See SET pin function in this table for the maximum adjustable sink current setting.
5/27
Device overview
Figure 2.
STVM100
Connections diagram
OUT
AVDD
WP
GND
SET
SCL
SDA
VDD
8
7
6
5
1
2
3
4
AI12273
Figure 3.
Block diagram
VDD
AVDD
19R
SDA
7
I2C
Interface
SCL
DAC
R
OUT
+
–
7
SET
EEPROM
Block
WP
GND
Figure 4.
AI12274
Hardware hookup
VDD
3.3V
MCU
I2C Interface
0.1µF
AVDD
VDD
SDA
0.1µF
AVDD
STVM100
+
OUT
SCL
WP
R1
GND
SET
R2
VCOM
–
RSET
AI12275
6/27
STVM100
2
Device operation
Device operation
The STVM100 operates as a slave device on the serial bus. Access is obtained by
implementing a Start condition, followed by the 7-bit slave address (1001111), and the
eighth bit for READ/WRITE identification. The volatile DAC register and non-volatile
EEPROM values can be read out or written in.
2.1
2-wire bus characteristics and conditions
This bus is intended for communication between different ICs. It consists of two lines:
●
a bi-directional data signal (SDA).
●
a clock signal (SCL).
The SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor. The following protocols have been defined:
2.1.1
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is high.
●
Changes in the data line while the clock line is high will be interpreted as control
signals.
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the data line state from high-to-low while the clock is high indicate the Start
condition.
2.1.3
Stop data transfer
A change in the data line state from low-to-high while the clock is high indicates the Stop
condition.
7/27
Device operation
2.1.4
STVM100
Data valid
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or
LOW state of the data line can only change when the clock signal on the SCL line is low
(see Figure 5). The data on the line may be changed during the clock signal low period.
There is one clock pulse per bit of data.
Each data transfer is initiated with a Start condition and terminated with a Stop condition.
The number of data bytes transferred between the Start and Stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges transmission with
a ninth bit.
By definition, the device that gives out a message is called “transmitter”, the device that gets
the message is called “receiver”. The device that controls the message is called the
“master”. The devices controlled by the master are called “slave” devices.
Figure 5.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
8/27
STVM100
2.1.5
Device operation
Acknowledge
Each byte of eight bits is followed by one Acknowledge bit. This Acknowledge bit is a low
level signal put on the bus by the receiver, whereas the master generates an extra
acknowledge-related clock pulse (see Figure 6). A slave receiver which is addressed is
obliged to generate an acknowledge signal after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges transmissions has to pull down the SDA line during the
acknowledge clock pulse in such a way, that the SDA line is a stable low during the high
period of the acknowledge-related clock pulse. The setup and hold times must be taken into
account. A master receiver must signal an end of transmitted data to the slave transmitter
by not generating an acknowledge on the last byte that has been clocked out of the slave. In
this case, the transmitter must leave the data line high to enable the master to generate the
Stop condition.
Figure 6.
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
9/27
Device operation
2.2
STVM100
Read mode
In READ mode, after the Start condition, the master sets the slave address (see Figure 7).
Followed by the READ/WRITE Mode Control bit (R/W=1) and the Acknowledge bit, the
value in DAC register will be transmitted and the master receiver will send an Acknowledge
bit to the slave transmitter. Finally the Stop condition will terminate the READ operation. In
READ mode, the valid data is the first 7 bits and the P bit (the eight bit) is don’t care.
2.3
Write mode
In WRITE mode the master transmits to the STVM100 slave receiver. The bus protocol is
shown in Figure 7. Following the Start condition and slave address, a logic '0' (R/W = 0) is
placed on the bus to identify a WRITE operation. After the acknowledgement by the slave,
the data will be transmitted to the slave with the 7-bit which indicates the data is valid as well
as the eighth bit “P” for the register’s identification. When P = 1, the DAC register is written
to, and when P = 0, the EEPROM is written to (Programming). After receiving the data, the
slave will generate an acknowledge signal, then a Stop condition will terminate the WRITE
operation. STVM100 is pre-programmed with 80H in the EEPROM after manufacturing.
A period of tW (see Table 8) is needed for EEPROM programming. During this period, the
slave will not acknowledge any WRITE operation.
The bit P values in both READ and WRITE modes are shown in Table 3.
Figure 7.
Read/write mode sequence
START
SLAVE ADDRESS
R/W A
1
0
0
1
1
1
1
1
0
0
1
1
1
1
A
6
5
4
3
2
1
0
STOP
P
SCL
SDA
R/W
A
6
5
START
4
3
2
1
0
P
A
STOP
AI12276_b
Table 3.
Bit P read and write mode values
Operation
P-bit value
Description
READ
X
Don’t care
1
DAC register WRITE
0
EEPROM WRITE
(programming)
WRITE
2.4
VDD power supply ramp-up
The ramp-up from 10% VDD to 90%VDD level should be achieved in less than or equal to
10ms to ensure that the EEPROM and power-on reset circuits are synchronized, and the
correct value is read from the EEPROM.
10/27
STVM100
3
Application information
Application information
The STVM100 is a programmable VCOM calibrator for the TFT-LCD to remove flickers. It
provides a digital I2C interface to control the sink current output. This output drives an
external resistive voltage divider, which can then be applied to an external VCOM buffer.
The highest and lowest VCOM value is determined by three resistors, R1, R2, and RSET. The
connection is shown in Figure 8.
The sink current from the STVM100 OUT pin is given in Equation 1. This current then flows
through RSET. This current must be less than 120µA (see ISET value in Table 7 on page 15).
Figure 8.
R1, R2, and RSET connection
AVDD
AVDD
AVDD
R1
STVM100
+
OUT
SET
VCOM
IOUT
RSET
R2
–
AI12933
Equation 1
AV DD
D+1
I OUT = -------------- ⋅ -------------------------128 20 ( R SET )
Note:
“D” is a user-selected value, an integer ranging from 0 to 127.
The VCOM value can be obtained in Equation 2.
Equation 2
R2
R1
D+1
V COM = -------------------- ⋅ AV DD ⎛ 1 – -------------- ⋅ --------------------------⎞
⎝
R1 + R2
128 20 ( R SET )⎠
11/27
Application information
STVM100
If the user-selected value is 0 (zero scale), the minimum current is sunk. The maximum
VCOM value is obtained in Equation 3.
Equation 3
R2
R1
1
V COM ( max ) = -------------------- ⋅ AV DD ⎛ 1 – ---------- ⋅ --------------------------⎞
⎝
128 20 ( R SET )⎠
R1 + R2
If the user-selected value is 127 (full scale), the maximum current is sunk and the minimum
VCOM value is obtained in Equation 4.
Equation 4
R2
R1
V COM ( min ) = -------------------- ⋅ AV DD ⎛ 1 – -------------------------⎞
⎝
R1 + R2
20 ( R SET )⎠
During operation, the VCOM(max) and VCOM(min) range is set, based on different TFT-LCD
processes.The R1 value is given based on the acceptable power loss from the AVDD supply
rail. Using Equation 3 and Equation 4, the R2 and RSET values can be calculated. If RSET is
put into Equation 1 on page 11 and maximum IOUT ≥ 120µA, then R1 should be increased.
12/27
STVM100
4
Maximum rating
Maximum rating
Stressing the device above the ratings listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
TSTG
TSLD
(1)
TJ
Parameter
Value
Unit
Storage temperature (VDD Off, AVDD Off)
–55 to 150
°C
Lead solder temperature for 10 seconds
260
°C
Maximum junction temperature (plastic package)
150
°C
–0.3 to 20
V
+5.5
V
VOUT
Output voltage (OUT pin to GND)
VDD
VDD to GND
AVDD
AVDD input voltage to GND
–0.3 to 20
V
VSET
Output voltage (SET pin to GND)
–0.3 to 5.5
V
TDFN8
2.66
W
PDIS
Power dissipation
TSSOP8
0.53
W
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
13/27
DC and AC parameters
5
STVM100
DC and AC parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 5, Operating and ac Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
Conditions
Unit
VDD supply voltage
2.25 to 3.6
V
VDD EEPROM programming supply voltage
2.25 to 3.6
V
AVDD reference voltage
4.5 to 20
V
Ambient operating temperature (TA)
–40 to 85
°C
Table 6.
Capacitances
Parameter(1)(2)
Symbol
Max
Unit
Bus capacitive load
400
pF
CSDA
Capacitance on SDA
10
pF
WP = 0
10
pF
CS
Capacitance on SCL
WP = 1
22
pF
Cb
Min
1. Effective capacitance measured with power supply at 3V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
14/27
STVM100
DC and AC parameters
Table 7.
Sym
DC and AC characteristics
Description
Test Condition(1)
Min
Typ
Max
Unit
Supply voltage
2.25
3.6
V
VDD
EEPROM
programming supply
voltage
2.25
3.6
V
IDD(2)
VDD supply current
50
µA
AVDD
Analog supply voltage
VDD = 2.6V to 3.6V
4.5
20
V
VDD = 2.25V to 3.6V
4.5
13
V
25
µA
IAVDD(3) AVDD supply current
SETVR
SET voltage resolution
SETDN
SET differential
nonlinearity
7
Monotonic over
temperature
Bits
±1
LSB
SETZSE SET zero scale error
±2
LSB
SETFSE SET full scale error
±8
LSB
120
µA
ISET(4)
SET current
Through RSET
SETER
SET external
resistance
To GND, AVDD = 20V
10
200
kΩ
To GND, AVDD = 4.5V
2.25
45
kΩ
AVDD to AVDD to SET voltage
SET
attenuation(5)
OUTST
VOUT
SETVD
OUT settling time
VIH
SDA, SCL, WP input
logic high
VIL
SDA, SCL, WP input
logic low
T = 25°C to 55°C
VOL(s)
µs
13
V
0.3VDD
0.22VDD
15
At 3mA
V
mV
0.7VDD
WPN input current
SDA, SCL output logic
low
8
<10
SDA, SCL hysteresis(5)
IIL(WPN)
V/V
VSET +
0.5V
OUT voltage
SET voltage drift(5)
20
25
V
V
35
µA
0.4
V
1. Valid for ambient operating temperature: TA = –40 to 85°C; VDD = 3V; AVDD = 10V; typical TA = 25°C;
OUT = 1/2AVDD; RSET = 24.9kΩ (except where noted).
2. Simulated maximum current draw when Programming EEPROM is 23mA; should be considered when
designing a power supply.
3. Tested at AVDD = 20V.
4. A typical Current of 20µA is calculated using AVDD = 10V and RSET = 24.9kΩ. The maximum suggested
SET current should be 120µA.
5. Simulated and determined via design and NOT directly tested.
15/27
DC and AC parameters
Figure 9.
STVM100
Bus timing requirements sequence
SDA
tBUF
tHD:STA
tHD:STA
tR
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
tSU:ST
SR
P
AI00589
Table 8.
Sym
AC characteristics
Description
Test Condition(1)
Min
Typ
400
kHz
SCL clock frequency
tLOW
Clock low period
1.3
µs
tHIGH
Clock high period
0.6
µs
tSU:DAT
Data setup time
100
ns
tHD:DAT
Data hold time
0
SDA and SCL rise time
tF
SDA and SCL fall time
tBUF
Bus free time before
new transmission can
start
tDSP
I2C spike rejection filter
pulse width
Dependent on load (see
Table 6 on page 14)
20 +
0.1Cb
900
ns
300
ns
300
ns
1.3
0
µs
50
ns
tSU:STA
Repeated start
condition setup time
0.6
µs
tHD:STA
Repeated start
condition hold time
0.6
µs
tSU:STO
Stop condition setup
time
0.6
µs
tW
WRITE cycle time
1. Valid for ambient operating temperature: TA = –40 to 85°C; VDD = 3.0V to 3.6V; AVDD = 10V;
OUT = 1/2AVDD; RSET = 24.9kΩ (except where noted, see Figure 9).
16/27
Unit
fSCL
tR
0
Max
100
ms
STVM100
Typical operating characteristics
Typical operating characteristics for the STVM100 are TA = 25°C, VDD = 3V, AVDD = 10V,
OUT = 1/2AVDD, and RSET = 24.9kΩ except where noted.
Figure 10. VDD supply current v’s VDD
27.5
27
IDD (µA)
26.5
26
25.5
25
24.5
24
.2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDD (V)
AI13362
Figure 11. AVDD supply current v’s AVDD
10
9
8
7
IAVDD (µA)
6
Typical operating characteristics
6
5
4
3
2
1
0
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
19.5
AVDD (V)
AI13363
17/27
Typical operating characteristics
STVM100
Figure 12. VDD supply current v’s temperature
35
IDD (µA)
30
25
20
15
-40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
Temperature˚C
AI13364
Figure 13. AVDD supply current v’s temperature
4.95
4.9
IAVDD (µA)
4.85
4.8
4.75
4.7
4.65
4.6
4.55
4.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature˚C
AI13365
18/27
STVM100
Typical operating characteristics
Figure 14. IOUT error v’s temperature (STVM100 at middle scale)
0.06
0.05
IOUT error (LSB)
0.04
0.03
0.02
0.01
0
-40
-20
0
20
40
60
80
Temperature˚C
AI13366
Figure 15. Total unadjusted error v’s DAC setting
Total unadjusted error (LSB)
0.022474
0.020395
0.018316
0.016237
0.014158
0.012079
0.01
1
17
33
49
65
81
97
113
DAC settling (decimal)
AI13367
19/27
Typical operating characteristics
STVM100
Figure 16. Differential non-linearity v’s DAC setting
0.2
Differential non-linearity (LSB)
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
1
17
33
49
65
81
97
113
DAC setting (decimal)
AI13368
Figure 17. Integral non-linearity v’s DAC setting
Integrate non-linearity (LSB)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
1
17
33
49
65
81
97
113
DAC setting (decimal)
AI13369
20/27
STVM100
Typical operating characteristics
Figure 18. AVDD power-up response
AVDD
VDD
VOUT
VSET
ai13370
5ms/DIV
AVDD: 5V/DIV, VDD: 5V/DIV, VOUT: 1V/DIV, VSET: 1V/DIV
Figure 19. Full scale-up response
SCL
SDA
VOUT
VSET
ai13371
20µs/DIV
SCL: 5V/DIV, SDA: 5V/DIV, VOUT: 1V/DIV, VSET: 1V/DIV
21/27
Typical operating characteristics
STVM100
Figure 20. Full scale-down response
SCL
SDA
VOUT
VSET
ai13372
20µs/DIV
SCL: 5V/DIV, SDA: 5V/DIV, VOUT: 1V/DIV, VSET: 1V/DIV
22/27
STVM100
7
Package mechanical
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 21. MLPD-DFN 3 x 3 x.75mm, pitch 0.65, package mechanical data
D
D2
1
L
E E2
8
A
e
b
A3 A1
0.08
EZ_ME
1. Drawing is not to scale.
Table 9.
MLPD-DFN 3 x 3 x .75mm, pitch 0.65, package mechanical data
mm
inches
Sym
Typ
Min
Max
Typ
Min
Max
A
0.75
0.70
0.80
0.0295
0.0276
0.0315
A1
0.02
0.00
0.05
0.0008
0.0000
0.0020
A3
0.20
b
0.30
0.0098
0.0138
D
3.00
D2
2.38
0.0878
0.0976
E
3.00
E2
1.64
1.49
1.74
0.0646
0.0587
0.0685
e
0.65
–
–
0.0256
–
–
L
0.40
0.30
0.50
0.0157
0.0118
0.0197
0.0079
0.25
0.35
0.0118
0.1181
2.23
2.48
0.0937
0.1181
23/27
Package mechanical
STVM100
Figure 22. TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8BM
Note:
Drawing is not to scale.
Table 10.
TSSOP8 – 8-lead, thin shrink small outline, 3mm x 3mm, mech. data
mm
inches
Sym
Typ
Min
A
0.050
0.150
0.750
0.950
b
0.250
c
0.130
A2
Typ
Min
1.100
A1
0.850
CP
24/27
Max
Max
0.0433
0.0020
0.0059
0.0295
0.0374
0.400
0.0098
0.0157
0.230
0.0051
0.0091
0.0335
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
4.900
4.6500
5.150
0.1929
0.1831
0.2028
E1
3.000
2.900
3.100
0.1181
0.1142
0.1220
L
0.550
0.400
0.700
0.0217
0.0157
0.0276
L1
0.950
0°
6°
0.0374
α
0°
N
8
6°
8
STVM100
8
Part numbering
Part numbering
Table 11.
Ordering information scheme
Example:
STVM100
DC
6
F
Device type
STVM100, VCOM calibrator with 7-bit DAC and I2C interface
Package
DC = TDFN8
DS = TSSOP8
Temperature range
6 = –40 to 85°C
Shipping method
E = ECOPACK package, tubes
F = ECOPACK package, tape & reel
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
25/27
Revision history
9
STVM100
Revision history
Table 12.
Revision history
Date
Revision
09-May-2006
1
Initial release.
14-Jul-2006
2
Graphical and textual updates
3
Document status upgraded to Preliminary Data; changed the
wording of Input function to include ‘WRITE operations’ instead of
‘programming’ in Table 2: Pin names and functions; deleted some
bracketed text and modified the P bit function in Section 2.2: Read
mode; ensured that all of Equation 2 and Equation 3 were visible;
amalgamated 2 cells containing the same information (VDD) in
Table 7: DC and AC characteristics; deleted footnotes 2 and 3 of
Table 8: AC characteristics; updated package mechanical
information in Figure 21, Table 9, and Table 10.
12-Feb-2007
4
Reformatted Inside Cover Page according to new template; renamed
section 1 Device overview and section 2 Device operation; deleted
Signal names table; moved and renamed Table 2: Pin names and
functions, addedSection 6: Typical operating characteristics and
Figure 10 to Figure 20.
20-Apr-2007
5
Value added in Section 2.3: Write mode.
24-Jul-2007
6
Document status upgraded to full datasheet.
08-Nov-2006
26/27
Changes
STVM100
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