INTERSIL ISL45042IR-T

ISL45042
®
Data Sheet
November 14, 2006
FN6072.6
LCD Module Calibrator
Features
The VCOM voltage of an LCD panel needs to be adjusted to
remove flicker. The ISL45042 can be used to digitally adjust
a panel’s VCOM voltage by controlling its output sinkcurrent. The output of the ISL45042 is connected to an
external voltage divider and an external VCOM buffer
amplifier. In this application, the user can control the VCOM
voltage with 7 Bit accuracy (128 steps). Once the desired
VCOM setting is obtained, the settings can be stored in the
non-volatile EEPROM memory, which would then be
automatically recalled during every power-up.
• 128-Step Adjustable Sink Current Output
The VCOM adjustment and non-volatile memory
programming is through a single interface pin (CTL). Once
the desired programmed value is obtained the Counter
Enable pin (CE) can be used to prevent further adjustment
or programming.
The full-scale sink current of the ISL45042 is set using an
external resister connected to the SET pin. The full-scale
sink current determines the lowest voltage of the external
voltage divider.
The ISL45042 is available in an 8 Ld 3mmx3mm Thin DFN
package with a maximum thickness of 0.8mm for ultra thin
LCD panel design.
• 2.6V to 3.6V Logic Supply Voltage Operating Range
• 4.5V to 20V Analog Supply Voltage Range
• Rewritable EEPROM for storing the optimum VCOM value
• Output Adjustment Enable/Disable Control
• Output Guaranteed Monotonic Over Temperature
• Two Pin Adjustment, Programming and Enable
• Ultra Thin 8 Ld 3mmx3mm DFN (0.8mm max)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LCD Panels
Ordering Information
TEMP.
RANGE
PART
(°C)
PART NUMBER MARKING
OUT 1
8
SET
AVDD 2
7
CE
N/C 3
6
CTL
GND 4
5
VDD
PKG.
DWG. #
ISL45042IR
042I
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
ISL45042IR-T
042I
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
Tape and Reel
ISL45042IRZ
(Note)
042Z
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
(Pb-free)
ISL45042IRZ-T
(Note)
042Z
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
Tape and Reel
(6k pcs) (Pb-free)
ISL45042IRZ-TK 042Z
(Note)
-40 to +85 8 Ld 3x3 Thin DFN L8.3x3A
Tape and Reel
(1k pcs) (Pb-free)
Pinout
ISL45042
(8 LD THIN DFN)
TOP VIEW
PACKAGE
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL45042
Pin Descriptions
PIN
FUNCTION
OUT
Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink
current divided by 128. See SET pin function description for the maxim adjustable sink current setting.
AVDD
High-Voltage Analog Supply. Connects to top of external resistor divider to determine the VCOM voltage. Typically 10V to 20V. Bypass
to GND with 0.1µF de-coupling capacitor.
N/C
No Connect. Not internally connected.
GND
Ground connection.
VDD
ISL45042 power supply input. Bypass to GND with 0.1µF de-coupling capacitor.
CTL
Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments
the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high
transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage
at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter.
See EEPROM Programming section for details.
CE
Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent
further adjustment or programming (note: the CE pin has an internal pull down resistor).
SET
Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of
the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. The maximum set current has to be less
than 120μA.
Block Diagram
ISL45042
CE
AVDD
400kΩ
to
500kΩ
IBIAS
IOUT
UP
CTL
DWN
DIGITAL INTERFACE
WITH THRESHOLD
SENSORS
PWRUP
POR
PRGM
UP/DOWN COUNTER
WITH PRESET
LATCHES
READ
ANALOG DCP AND
CURRENT OUTPUT
BLOCK
SET
PRGM MEMORY
POR
PRGM
EEPROM
OR
NVL MEMORY
VDD
GND
2
FN6072.6
November 14, 2006
ISL45042
Absolute Maximum Ratings
Thermal Information
VDD to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V
Input Voltages to GND
SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
Output Voltages to GND
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V
ESD Rating
HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75kV
HBM for CTL to GND (no EEPROM Content Disruption). . . . .8kV
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
8 Ld Thin DFN Package. . . . . . . . . . . . . . . . . . . . . .
90
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(Lead Tips Only)
Erase/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years @ +85°C
Operating Conditions
Temperature Range
ISL45042IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified.
Typicals are at TA = +25°C
PARAMETER
TEMP
(°C)
MIN
TYP
MAX
UNITS
0 to 85
3
-
3.6
V
For Operation
Full
2.6
-
3.6
V
CE = VDD (Note 6)
Full
-
-
50
μA
CE = GND
Full
-
-
20
μA
Full
4.5
-
20
V
SYMBOL
TEST CONDITIONS
DC CHARACTERISTICS
VDD Supply Range
VDD
VDD Supply Current
IDD
For Programming
AVDD Supply Range
AVDD
AVDD Supply Current
IAVDD
(Note 3)
Full
-
-
20
μA
CTL High Voltage
CTLIH
2.6V < VDD < 3.6V
Full
0.7*VDD
-
0.8*VDD
V
CTL Low Voltage
CTLIL
2.6V < VDD < 3.6V
Full
0.2*VDD
-
0.3*VDD
V
CTL High Rejected Pulse Width
CTLIHRPW
Full
20
-
-
μs
CTL Low Rejected Pulse Width
CTLILRPW
Full
20
-
-
μs
CTL High Minimum Pulse Width
CTLIHMPW
Full
-
-
200
μs
CTL Low Minimum Pulse Width
CTLILMPW
Full
-
-
200
μs
CTLMTC
Full
-
-
10
μs
CTL = GND
Full
-
-
10
μA
CTL = VDD
Full
-
-
10
μA
(Note 5)
Full
-
10
-
pF
CTL Minimum Time Between
Counts
CTL Input Current
ICTL
CTL Input Capacitance
CTLCAP
CE Input Low Voltage
CEIL
2.6V < VDD < 3.6V
Full
-
-
0.4
V
CE Input High Voltage
CEIH
2.6V < VDD < 3.6V
Full
0.64*VDD
-
-
V
CE Minimum Start Up Time
CEST
(Note 5)
Full
-
1
-
ms
2.6V < VDD < 3.6V, (Note 2)
Full
4.9
-
15.75
V
>4.9V
Full
200
-
-
μs
CTL EEPROM Program Voltage
CTLPROM
CTL EEPROM Programming
Signal Time
CTLPT
3
FN6072.6
November 14, 2006
ISL45042
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9kΩ; Unless Otherwise Specified.
Typicals are at TA = +25°C (Continued)
PARAMETER
SYMBOL
Programming Time
TEMP
(°C)
TEST CONDITIONS
PT
MIN
TYP
Full
MAX
UNITS
100
ms
SET Voltage Resolution
SETVR
(Note 4)
Full
7
7
7
Bits
SET Differential Nonlinearity
SETDN
Monotonic Over Temperature
Full
-
-
±1
LSB
SET Zero-Scale Error
SETZSE
Full
-
-
±2
LSB
SET Full-Scale Error
SETFSE
Full
-
-
±8
LSB
SET Current
SET External Resistance
AVDD to SET Voltage Attenuation
OUT Settling Time
ISET
Through RSET (Note 7)
Full
-
20
-
μA
SETER
To GND, AVDD = 20V
Full
10
-
200
kΩ
To GND, AVDD = 4.5V
Full
2.25
-
45
kΩ
Full
-
1:20
-
V/V
Full
-
20
-
μs
Full
VSET +
0.5V
-
13
V
25 to 55
-
<10
-
mV
AVDD to SET
OUTST
OUT Voltage Range
to ±0.5 LSB Error Band (Note 5)
VOUT
OUT Voltage Drift
OUTVD
(Note 5)
NOTES:
2. CTL signal only needs to be greater than 4.9V to program EEPROM.
3. Tested at AVDD = 20V.
4. The Counter value is set to mid-scale ±4 LSB’s in the Production.
5. Simulated and Determined via Design and NOT Directly Tested.
6. Simulated Maximum Current Draw when Programming EEPROM is 23mA, should be considered when designing Power Supply.
7. A Typical Current of 20μA is Calculated using the AVDD = 10V and RSET = 24.9kΩ. The maximum suggested SET Current should be 120μA.
Application Information
The application circuit to adjust the VCOM voltage in an LCD
panel is shown in Figure 1. The ISL45042 has a 128-step
sink current resolution. The output is connected to an
external voltage divider, that results in decreasing the output
VCOM voltage as you increase the ISL45042 sink current.
AVDD
AVDD
ISL45042
CTL
CE
OUT
SET
ISink
R1
R2
RSET
CTL Pin
VCOM
The adjustment of the output VCOM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL, when the CE pin is high.
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200µs. The level and timing
needed to program the non-volatile memory is given in
Figure 2. It then takes a maximum of 100ms for the
programming to be completed inside the device.
4
BLUE
GREEN
RED
The output VCOM voltage is increased with a mid (Vdd/2) to
high transition (0.8*VDD) on CTL pin. The output VCOM
voltage is decreased with a mid (Vdd/2) to low transition
(0.3*VDD), on CTL pin (Reference Figure 6). Once the
minimum or maximum value is reached on the 128 steps,
the device will not overflow or underflow beyond that
minimum or maximum value.
+
-
COLUMN
DRIVER
SINGLE PIXEL
IN LCD PANEL
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
FN6072.6
November 14, 2006
ISL45042
To avoid unintentional adjustment, the ISL45042 guarantees
to reject CTL pulses shorter than 20µs.
CTL VOLTAGE
>200µs
During Initial Power-up (only), to avoid the possibility of a
false pulse (since the internal comparators come up in an
unknown state) the very first CTL pulse is ignored. See
Figure 6 for the timing information.
4.9V
CE Pin
CTLPT
TIME
FIGURE 2. EEPROM PROGRAMMING
When the part is programmed, the counter setting is loaded
into the non-volatile memory. This value will be loaded from
the nonvolatile memory during initial power-up or when the
CE pin is pulled low.
Once the programming is completed it is recommended that
the user float the CLT pin. The CTL pin is internally tied to a
resistor network connected to ground. If left floating, the
voltage at the CTL pin will equal VDD/2. Under these
conditions, no additional pulses will be seen by the Up/Down
counter via the CTL pin. To prevent further programming
ground the CE pin.
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1kΩ resistor and a shunt
0.01µF capacitor connected on the CTL pin. (See Figure 3)
To adjust the output voltage, the CE pin must be pulled high
(VDD). The CE pin has an internal pull-down resistor to
prevent unwanted reprogramming of the EEPROM. The
impedance of this resistor is 400kΩ to 500kΩ (RINTERNAL
Figure 5).
Transitions of the CE pin are recommended to be less than
10μ seconds.
Replacing Existing Mechanical Potentiometer
Circuits
Figure 4 shows the common adjustment mechanical circuits
and equivalent replacement with the ISL45042.
Expected Output Voltage
The ISL45042 provides an output sink current which lowers
the voltage on the external voltage divider (VCOM output
voltage). EQ. 1 and EQ. 2 can be used to calculate the
output current (IOUT) and output voltage (VOUT) values.
Setting
AVDD
IOUT = --------------------- X ----------------------------128
20 ( RSET )
(EQ. 1)
R2
Setting
R1
VOUT = ⎛ ----------------------⎞ AVDD ⎛ 1 – --------------------- X -----------------------------⎞
⎝ R1 + R2⎠
⎝
128
20 ( RSET )⎠
(EQ. 2)
ISL45042
1kΩ
CTL
0.01µF
NOTE: Where setting is an integer between 1 and 128.
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
AVDD
Ra
AVDD
AVDD
VCOM
Rb
+
ISL45042
SET
R1
VCOM
+
OUT
R2
Rc
R1 = Ra
R2 = Rb + Rc
RSET
RSET = (Ra(Rb + Rc)) / 20Rb
FIGURE 4. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042
5
FN6072.6
November 14, 2006
ISL45042
Table 1 gives the calculated value of VOUT for resistors
values of: RSET = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ, and
VADD = 10V.
TABLE 1. CALCULATED VCOM OUTPUT VOLTAGES
SETTING VALUE
VOUT
1
5.468
10
5.313
20
5.141
30
4.969
40
4.797
50
4.625
60
4.453
70
4.281
80
4.109
90
3.936
100
3.764
110
3.592
128
3.282
Generating VDD and CE supply from a Larger
Voltage Source
The CE pin has an internal pull-down resistor (RINTERNAL
Figure 5). The impedance of this resistor is 400kΩ-500kΩ. If
your design is using a resistor divider network to generate
the 3.3V supply (for both VDD and CE to enable
programming) from a larger voltage source, the 400kΩ
(worst case) resistor needs to be taken into account as a
parallel resistance when the CE pin is connected to this
source. Another design concern is to be able to provide
enough supply current during programming. The ISL45042
draws about 2mA during this process. Recommended
resistor values are shown in Figure 5. This design will result
in an additional 0.83mA quiescent current flowing through
resistors RA and RB..
VCC= 5V
ISL45042
RA
2kΩ
CE LOGIC
CE
VCE
RB
RSET Resistor
4kΩ
The external RSET resistor sets the full-scale sink current
that determines the lowest voltage of the external voltage
divider R1 and R2 (Figure 1). The maximum ISET current has
to be less than 120μA. The minimum RSET resistor with
AVDD equal to 10V is 4.17kΩ (10V/(20*120μA). Typical
applications with AVDD equal to 10V and RSET equal to
24.9kΩ will result in a set current equal to 20μA.
RINTERNAL = 400kΩ to 500kΩ
FIGURE 5. APPLICATION GENERATING VDD AND VCE
VOLTAGES
ISL45042 Truth Table
Power Supply Sequence
The recommendation for power supply sequence would be
to power down the part first (Vdd, AVdd), after 100msec if
programming has occurred, and then power down the
control power supplies (CTL, CE).
The ISL45042 truth table is shown in Table 2. For proper
operation the CE should be disabled (pulled low) before
powering the device down to assure that the glitches and
transients will not cause unwanted EEPROM overwriting.
TABLE 2. TRUTH TABLE
Verifying the Programmed Value
The following sequence can be used to verify the
programmed value without having to sequence the VDD
supply. To verify the programmed value, follow the steps
below. The ISL45042 will read memory contents and be set
to that value when the CE pin is grounded.
1. Power up the ISL45042.
2. CE pin = VDD.
INPUT
OUTPUT
CTL
CE
VDD
OUT
ICC
MEMORY
Mid to Hi
Hi
VDD
Increment
Normal
X
Mid to Lo
Hi
VDD
Decrement
Normal
X
X
Lo
VDD
No Change Increased
Read
>4.9V
Hi
VDD
No Change Increased
Program
3. Change counter value with CTL pin to desired value.
4. CTL = more than 4.9V and 200msec. Counter value
programmed.
5. Change the counter value with CTL pin to a different
value.
6. CE pin = Ground.
7. Check that the output value is the one programmed in
step #4.
6
FN6072.6
November 14, 2006
ISL45042
.
CEST
CTLIHRPW
CTLMTC
CTL HIGH
CTL
VDD/2
CTL LOW
CTLIHMPW
CTLILMPW
CTLILRPW
CE
STOP PROGRAMMING
START PROGRAMMING
START PROGRAMMING
COUNTER
OUTPUT
UNDEF.
78
NOTE:
AFTER POWER IS 1ST APPLIED,
THE VERY 1ST CTL PULSE IS IGNORED.
79
7A
7B
7A
IGNORES 1ST PULSE
AFTER PROGRAMMING
VCOM
THE TIMING DIAGRAM ABOVE SHOWS POST POWER-UP TIMING.
FIGURE 6. ISL45042 TIMMING DIAGRAM
7
FN6072.6
November 14, 2006
ISL45042
Thin Dual Flat No-Lead Plastic Package (TDFN)
L8.3x3A
2X
0.15 C A
A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.15 C B
E
SYMBOL
MIN
A
0.70
A1
-
A3
6
INDEX
AREA
b
TOP VIEW
B
0.10 C
//
C
SEATING
PLANE
SIDE VIEW
D2
(DATUM B)
A3
7
-
0.30
0.35
5, 8
2.40
7, 8, 9
1.60
7, 8, 9
-
2.30
-
1.50
-
0.65 BSC
-
k
0.25
-
-
-
L
0.20
0.30
0.40
8
N
8
Nd
4
8
2
3
Rev. 3 11/04
NOTES:
D2/2
1
6
INDEX
AREA
0.08 C
0.80
0.05
3.00 BSC
1.40
e
A
0.02
NOTES
3.00 BSC
2.20
E
E2
0.75
MAX
0.20 REF
0.25
D
D2
NOMINAL
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
NX k
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
E2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
8
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
5
(Nd-1)Xe
REF.
0.10 M C A B
BOTTOM VIEW
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-WEEC-2 except for the “L” min
dimension.
CL
(A1)
NX (b)
L1
5
10 L
e
SECTION "C-C"
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN6072.6
November 14, 2006