STMICROELECTRONICS TDA7491HV13TR

TDA7491HV
20 W + 20 W dual BTL class-D audio amplifier
Features
!
20 W + 20 W continuous output power:
RL = 8 Ω, THD = 10% at VCC = 18 V
!
Wide range single supply operation (5 V - 19 V)
!
High efficiency (η = 90%)
!
Four selectable, fixed gain settings of 20 dB,
26 dB, 30 dB and 32 dB
!
Differential inputs minimize common-mode
noise
!
Filterless operation
!
No ‘pop’ at turn-on/off
!
Standby and mute features
!
Short circuit protection
!
Thermal overload protection
!
Externally synchronizable
PowerSSO-36 with
exposed pad (or slug) down
Description
The TDA7491HV is a dual BTL class-D audio
amplifier with single power supply designed for
LCD TVs and monitors.
Thanks to the high efficiency and slug-down
package no heatsink is required.
Furthermore, the filterless operation allows a
reduction in the external component count.
The TDA7491HV is pin to pin compatible with the
TDA7491P and TDA7491LP.
Table 1.
Device summary
Order code
Operating Temp. range
Package
Packing
TDA7491HV
0° to 70° C
PowerSSO-36 (slug down)
Tube
TDA7491HV13TR
0° to 70° C
PowerSSO-36 (slug down)
Tape and reel
December 2007
Rev 1
1/26
www.st.com
26
Contents
TDA7491HV
Contents
1
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
4
2.1
Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
For 8 Ω loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
For 6 Ω loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
For 4 Ω loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/26
7.1
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2
Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3
Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4
Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.1
Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.2
Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.5
Filterless modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.6
Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.7
Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.9
Heatsink requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TDA7491HV
8
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
Device block diagram
1
TDA7491HV
Device block diagram
Figure 1 shows the block diagram of one of the two identical channels of the TDA7491HV.
Figure 1.
4/26
Internal block diagram (one channel only)
TDA7491HV
Pin description
2
Pin description
2.1
Pin-out
Figure 2.
Pin connection (top view)
5/26
Pin description
2.2
Pin list
Table 2.
Number
6/26
TDA7491HV
Pin description list
Name
Type
Description
1
SUB_GND
POWER
Connect to the frame
2,3
OUTPUTB
OUT
Positive PWM for right channel
4,5
PGNDB
POWER
Power stage round for right channel
6,7
PVCCB
POWER
Power supply for right channel
8,9
OUTNB
OUT
Negative PWM output for right channel
10,11
OUTNA
OUT
Negative PWM output for right channel
12,13
PVCCA
POWER
Power supply for left channel
14,15
PGNDA
POWER
Power stage round for left channel
16,17
OUTPA
OUT
Positive PWM output for left channel
18
PGND
POWER
Power stage round
19
VDDPW
OUT
3.3 V (nominal) regulator output referred to ground for power
stage
20
STBY
INPUT
Standby mode control
21
MUTE
INPUT
Mute mode control
22
INPA
INPUT
Positive differential input of left channel
23
INNA
INPUT
Negative differential input of left channel
24
ROSC
OUT
Master oscillator frequency-setting pin
25
SYNCLCK
IN/OUT
Clock in/out for external oscillator
26
VDDS
OUT
3.3 V (nominal) regulator output referred to ground for signal
blocks
27
SGND
POWER
Signal round
28
DIAG
OUT
Open-drain diagnostic output
29
SVR
OUT
Supply voltage rejection
30
GAIN0
INPUT
Gain setting input 1
31
GAIN1
INPUT
Gain setting input 2
32
INPB
INPUT
Positive differential input of right channel
33
INNB
INPUT
Negative differential input of right channel
34
VREF
OUT
Half VDDS (nominal) referred to ground
35
SVCC
POWER
Signal power supply
36
VSS
OUT
3.3 V (nominal) regulator output referred to power supply
TDA7491HV
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
23
V
0 to 70
°C
VCC
DC supply voltage for pins PVCCA, PVCCB, SVCC
Top
Operating temperature
Tj
Junction temperature
-40 to 150
°C
Tstg
Storage temperature
-40 to 150
°C
Thermal data
Table 4.
Thermal data
Symbol
Parameter
Rth j-case
Rth j-amb
Min
Typ
Max
Thermal resistance, junction to case
2
3
Thermal resistance, junction to ambient
(mounted on recommended PCB)(1)
24
Unit
°C/W
1. FR4 with vias to copper area of 9 cm2 (see also Section 7.9: Heatsink requirements on page 24).
3.3
Electrical specifications
Unless otherwise stated, the results in Table 5 below are given for the conditions:
VCC = 18 V, RL (load) = 8 Ω, ROSC = 39 kΩ, C1 = 100 nF, f = 1 kHz, GV = 20 dB, and
Tamb = 25° C.
Table 5.
Symbol
Electrical specifications
Parameter
Condition
Min
Typ
Max
Unit
18
V
VCC
Supply voltage for
pins PVCCA, PVCCB, SVCC
Iq
Total quiescent
26
35
mA
IqSTBY
Quiescent current in standby
2.5
5.0
µA
VOS
Output offset voltage
Play mode
-200
200
mV
VOS
Output offset voltage
Mute mode
-300
300
mV
IOC
Over current protection threshold RL = 0 Ω
Tj
Junction temperature at thermal
shut-down
Ri
Input resistance
VOV
Over voltage protection threshold
5
Differential input
3
5
A
150
°C
55
60
kΩ
19
21
7/26
Electrical specifications
Table 5.
TDA7491HV
Electrical specifications (continued)
Symbol
Parameter
RdsON
Power transistor on resistance
Po
Output power
Po
Output power
Condition
Typ
High side
0.2
Low side
0.2
THD = 10%
20
THD = 1%
16
RL = 8 Ω, THD = 10%
VCC = 12 V
9.5
Max
Ω
W
RL = 8 Ω, THD = 1%
VCC = 12 V
7.2
4.0
W
90
%
Dissipated power
Po = 20 W + 20 W,
THD = 10%
η
Efficiency
Po = 20 W + 20 W
THD
Total harmonic distortion
Po = 1 W
80
0.1
0.4
GAIN0 = L, GAIN1 = L
18
20
22
GAIN0 = L, GAIN1 = H
24
26
28
GAIN0 = H, GAIN1 = L
28
30
32
GAIN0 = H, GAIN1 = H
30
32
34
Closed loop gain
∆GV
Gain matching
CT
Cross talk
eN
Total input noise
SVRR
Supply voltage rejection ratio
Tr, Tf
Rise and fall times
FSW
Switching frequency
Output switching frequency
VinH
Digital input high (H)
VinL
Digital input low (L)
%
dB
-1
1
f = 1 kHz
50
A Curve, GV = 20 dB
20
f = 22 Hz to 22 kHz
25
dB
dB
µV
Fr = 100 Hz, Vr = 0.5 V,
CSVR = 10 µF
Internal oscillator
With internal oscillator
FSWR
Unit
W
PD
GV
Min
40
290
(1)
35
50
dB
50
ns
310
330
kHz
250
kHz
With external oscillator (2) 250
2.3
V
0.8
STBY < 0.5 V, MUTE = X
Function
Standby, mute and play modes
mode
Standby
STBY > 2.5 V, MUTE < 1 V Mute
STBY > 2.5 V, MUTE > 2 V Play
AMUTE
Mute attenuation
VMute = 1 V
60
1. FSW = 106 / (64 * ROSC + 440) kHz, fSYNCLK = 2 * FSW with R1 in kΩ (see Figure 22).
2. FSW = fSYNCLK / 2 with the frequency of the external oscillator.
8/26
80
dB
TDA7491HV
Characterization curves
4
Characterization curves
4.1
For 8 Ω loads
Output power vs supply voltage
Output Power (W)
Figure 3.
26
24
22
20
18
16
14
12
10
8
6
4
2
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage (V)
Figure 4.
THD + N vs output power
THD+N (%)
10
5
Vs=18V
Rl=8Ω
2
f=1kHz
1
0.5
L CH
0.2
0.1
0.05
R CH
0.02
0.01
100m
200m
500m
1
2
5
10
20
Po (W)
9/26
Characterization curves
Figure 5.
TDA7491HV
THD + N vs output power (without LC filter)
10
5
Vs=18V
Rl=8Ω
2
f=1kHz
1
L CH
0.5
0.2
0.1
R CH
0.05
0.02
0.01
100m
200m
500m
1
2
5
10
20
30
Po (W)
Figure 6.
THD + N vs frequency
THD +N (%)
10
5
Vs = 18V
2
Rl = 8 ohm
1
0.5
Pout =100mW
0.2
0.1
0.05
Pout =1 W
0.02
0.01
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 7.
Closed-loop gain vs frequency
Ampl (dB)
+2
+1.5
+1
Gain =32 dB
Gain =30 dB
+0.5
-0
-0.5
-1
Gain =26 dB
-1.5
-2
Gain =20 dB
Vs = 18V
-2.5
Rl = 8 ohm
-3
-3.5
@ f =1kHz, Po =1W
-4
-4.5
-5
20
50
100
200
500
1k
2k
Frequency (Hz)
10/26
5k
10k
20k
50k
TDA7491HV
Characterization curves
Figure 8.
Cross talk vs frequency
Cross Talk (dB)
+0
-10
-20
Vs =18V
-30
Rl =8 ohm
-40
0dB @ f =1kHz
-50
Po =1W
Lo to R
-60
-70
-80
Ro to L
-90
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Figure 9.
Power dissipation and efficiency vs output power (per channel)
8
7
6
5
4
3
2
1
Power Dissipation (W)
Efficiency (%)
Pout Per Channel (W)
100
90
80
70
60
50
40
30
20
10
0
0
0 1 2 3 4 5 6 7 8 9 1011 121314 15161718 1920
Pout Per Channel (W)
Attenuation (dB)
Figure 10. Attenuation vs mute voltage
10.00
0.00
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
0.00
Vs =18V
Rl =8 ohm
0 dB @ f =1kHz
Po =1W
0.50 1.00 1.50 2.00 2.50
Mute Voltage (V)
3.00
3.50
11/26
Characterization curves
TDA7491HV
Figure 11. Total quiescent current vs supply voltage
50
45
Iq (mA)
40
35
30
No Load
No Load
Play Mode
Play Mode
25
20
15
10
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
Supply Voltage (V)
SVR-Supply Ripple Rejection Ratio (dB)
Figure 12. Power supply rejection ratio vs frequency
+0
Vs =18V,
-10
Rl =8 ohm
Gain =20 dB
-20
0 dB @
-30
Ripple Frequency =100Hz
-40
L-Channel
Ripple Voltage = 500mV
-50
-60
R-Channel
-70
-80
-90
-100
20
50
100
200
500
1k
2k
5k
15
17
10k
Frequency (Hz)
4.2
For 6 Ω loads
Figure 13. Output power vs supply voltage
28
Output Power (W)
24
20
16
12
8
4
0
5
7
9
11
13
Supply Voltage (V)
12/26
19
20k
TDA7491HV
Characterization curves
Figure 14. THD vs output power
THD (%)
10
5
2
Vs = 18V
1
Rl = 6 ohm
f =1kHz
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
100m
200m
500m
1
2
5
10
20
30
Output Power (W)
Figure 15. Frequency response
Ampl (dB)
+2
+1.5
+1
+0.5
-0
-0.5
-1
Vs = 18V
-1.5
-2
Rl = 6 ohm
-2.5
f =1kHz
-3
Po =1W
-3.5
-4
-4.5
-5
20
50
100
200
500
1k
2k
5k
10k
20k
50k
Frequency (Hz)
Figure 16. THD vs frequency
THD (%)
10
5
2
Vs = 18V
1
Rl = 6 ohm
0.5
f =1kHz Po =1W
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
13/26
Characterization curves
TDA7491HV
Figure 17. Cross talk vs frequency
Cross Talk (dB)
+0
-10
-20
Vs =18V
-30
Rl =6 ohm
f =1kHz
-40
Po =1W
-50
-60
Lo to R
-70
-80
Ro to L
-90
-100
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
2k
5k
10k
20k
Frequency (Hz)
Figure 18. FFT performance (0 dB)
FFT (dB)
+10
+0
-10
-20
Vs =18V
-30
-40
Rl =6 ohm
-50
f =1kHz
-60
Po =1W
-70
-80
-90
-100
-110
-120
-130
-140
-150
20
50
100
200
500
1k
Frequency (Hz)
Figure 19. FFT performance (60 dB)
FFT (dB)
+10
+0
-10
-20
Vs =18V
-30
-40
Rl =6 ohm
-50
@ f =1kHz
-60
Po =1W
-70
-80
-90
-100
-110
-120
-130
-140
-150
20
50
100
200
500
1k
Frequency (Hz)
14/26
TDA7491HV
For 4 Ω loads
Figure 20. Output power vs supply
p voltage
Output Power (W)
4.3
Characterization curves
pp y
g (
)
22
20
18
16
14
12
10
8
6
4
2
0
5
6
7
8
9
10
11
12
13
14
Supply Voltage (V)
15/26
Package information
5
TDA7491HV
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: http://www.st.com.
Figure 21. PowerSSO-36 package dimensions
DM
I .
m m
TYP. M A
X .
2.4 7
2.4 0
0.0 7 5
0.3 6
0.3 2
10 .50
M N.
I
2.15
2 .1 5
0
0.18
0.23
10.10
A
A2
a1
b
c
D (1)
7 .4
E (1)
e
e3
F
G
G1
H
h
k
L
M
N
O
Q
S
T
U
X
Y
7.6
MIN .
0.08 4
0.084
0
0.00 7
0.00 9
0 .3 98
in c h
T YP. MAX.
0.097
0.09 4
0.00 3
0.014
0.012
0.413
0 .2 91
0.5
8 .5
2.3
Outline and mechanical data
0.299
0 .0 19
0.335
0 .0 90
0.1 0
0 .06
1 0.5 0 0.39 8
0.4 0
10.1 0
û
0.00 4
0 .0 02
0.413
0.01 6
5û
0.55
0.9 0
0.02 2
4.3
0.035
0 .1 69
10û
1 0û
1.2
0.8
2.9
.65
1.0
0 .0 47
0 .0 31
0 .1 14
0.144
0 .0 39
4.1
6.5
4 .7
7 .3
0.161
0.256
P owerSSO-36
er
Pow
0 .1 85
0 .2 87
exposed pad (or slug) down
A
A2
(1) "D” a n d“E" d on ot in clu de m ldo flash o rp ro rt u sio n sM o ld
fla sh
o r por trusio n ssh a ll n oet xce e d 0
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ee
r 0s( 0
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c
G a u g e p la n e 0 .2 5
h x 4 û5
L E A D C O P L A N A R IT Y
Y
M
k
e
T
a1
A
D
s ta n d -o ff
G
L
H
E
X
O
F
S
Q
U
B O T T O M V IE W
B
0 .1 M A B
b
e3
7587 1 3
1 A
16/26
TDA7491HV
6
Application circuit
Application circuit
Figure 22. Application circuit
TDA7491HV
Input settings for gain:
Input settings for standby, mute and play:
GAIN0 : GAIN1
Nominal gain
STBY : MUTE
Mode
0V:0V
0 V : 3.3 V
3.3 V : 0 V
3.3 V : 3.3 V
20 dB
26 dB
30 dB
32 dB
0V:0V
0 V : 3.3 V
3.3 V : 0 V
3.3 V : 3.3 V
Standby
Standby
Mute
Play
17/26
Application information
TDA7491HV
7
Application information
7.1
Mode selection
The three operating modes of the TDA7491HV are set by the two inputs STBY (pin 20) and
MUTE (pin 21).
"
Standby mode: all circuits are turned off, very low current consumption.
"
Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle.
"
Play mode: the amplifiers are active.
The protection functions of the TDA7491HV are realized by pulling down the voltages of the
STBY and MUTE inputs shown in Figure 23. The input current of the corresponding pins
must be limited to 200 µA.
Table 6.
Mode settings
Mode Selection
Standby
STBY
MUTE
L (1)
Mute
H
Play
H
X (don’t care)
(1)
L
H
1. Drive levels defined in Table 5: Electrical specifications on page 7.
Figure 23. STBY and MUTE circuit
TDA7491HV
Figure 24. Turn on/off sequence for minimizing speaker “pop”
18/26
TDA7491HV
7.2
Application information
Gain setting
The gain of the TDA7491HV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31).
Internally, the gain is set by changing the feedback resistors of the amplifier.
Table 7.
7.3
Gain settings
GAIN0
GAIN1
Nominal gain, Gv (dB)
0
0
20
0
1
26
1
0
30
1
1
32
Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor
(Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 25. For Ci = 220 nF the high-pass filter cut-off frequency is below 20 Hz:
fc = 1 / (2 * π * Ri * Ci)
Figure 25. Device input circuit and frequency response
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Application information
7.4
TDA7491HV
Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an
external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7491HV as master clock, while the other devices are in slave mode (that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.
7.4.1
Master mode (internal clock)
Using the internal oscillator, the output switching frequency, FSW, is controlled by the
resistor, ROSC, connected to pin ROSC:
FSW = 106 / (64 * ROSC + 440) kHz
where ROSC is in kΩ.
In master mode, pin SYNCLK is used as a clock output pin, whose frequency is:
FSYNCLK = 2 * FSW
For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given
below in Table 8.
7.4.2
Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in Table 8.
The output switching frequency of the slave devices is:
FSW = FSYNCLK / 2
Table 8.
How to set up SYNCLK
Mode
ROSC
SYNCLK
Master
ROSC < 60 kΩ
OUTPUT
Slave
Floating (not connected)
INPUT
Figure 26. Master and Slave Connection
TDA7491HV
20/26
TDA7491HV
TDA7491HV
7.5
Application information
Filterless modulation
The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM).
The differential output voltages change between zero and +Vcc and between zero and -Vcc.
This is in contrast to the traditional bipolar PWM outputs which change between +Vcc
and -Vcc.
An advantage of this scheme is that it effectively doubles the switching frequency of the
differential output waveform. The OUTP and OUTN are in the same phase when the input is
zero, then the switching current is low and the loss in the load is small. In practice, a short
delay is introduced between these two outputs in order to avoid the BTL output switching at
the same time.
TDA7491HV can be used without a filter before the speaker, because the frequency of the
TDA7491HV output is beyond the audio frequency, the audio signal can be recovered by the
inherent inductance of the speaker and natural filter of the human ear.
Figure 27. Unipolar PWM output
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Application information
7.6
TDA7491HV
Output low-pass filter
To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The
cutoff frequency should be larger than 22 kHz and much lower than the output switching
frequency. It is necessary to choose the L-C component values depending on the loud
speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are
shown in Figure 28 and Figure 29 below.
Figure 28. Typical LC filter for a 8-Ω speaker
Figure 29. Typical LC filter for a 4-Ω speaker
22/26
TDA7491HV
7.7
Application information
Protection function
The TDA7491HV is fully protected against over-voltages, under-voltages, over- currents and
thermal overloads as explained here. See also Table 5: Electrical specifications on page 7.
Over-voltage protection (OVP)
If the supply voltage exceeds 20 V (nominal) the over-voltage protection is activated which
forces the outputs to the high-impedance state. When the supply voltage drops to below the
threshold value the device restarts.
Under-voltage protection (UVP)
If the supply voltage drops below 4 V (nominal) the under-voltage protection is activated
which forces the outputs to the high-impedance state. When the supply voltage recovers the
device restarts.
Over-current protection (OCP)
If the output current exceeds 4 A (nominal) the over-current protection is activated which
forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If
the over-current condition is still present then the OCP remains active. The restart time,
TOC, is determined by the R-C components connected to pin STBY.
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145° C (nominally), the device goes to mute mode
and the positive and negative PWM outputs are forced to 50% duty cycle. At Tj = 155° C
(nominally), the device shuts down and the output is forced to the high impedance state.
When the device cools sufficiently the device restarts.
7.8
Diagnostic output
The output pin DIAG is an open drain transistor. When the protection is activated it is in the
high-impedance state. The pin can be connected to a power supply (< 20 V) by a pull-up
resistor whose value is limited by the maximum sinking current (200 µA) of the pin.
Figure 30. Behavior of pin DIAG for various protection conditions
TDA7491HV
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Application information
7.9
TDA7491HV
Heatsink requirements
A thermal resistance of 24° C/W can be obtained using the PCB copper ground layer with
16 vias connecting it to the contact area for the slug. Ensure that the copper ground area is
a nominal 9 cm2 for 24° C/W.
Figure 31 shows the derating curves for copper areas of 4 cm2 and 9 cm2.
As with most amplifiers, the power dissipated within the device depends primarily on the
supply voltage, the load impedance and the output modulation level.
The maximum estimated power dissipation for the TDA7491HV is less than 4 W. When
properly mounted on the above PCB the junction temperature could increase by 96° C.
However, with a musical program the dissipated power is about 40% less, leading to a
temperature increase of around 60° C. Even at the maximum recommended ambient
temperature for consumer applications of 50° C there is still a clear safety margin before the
maximum junction temperature (150° C) is reached.
Figure 31. Power derating curves for PCB usedgas heatsink
Pd (W)
8
7
Copper Area 3x3 cm
and via holes
6
5
TDA7491HV
TDA7491P
PSSO-36
PSSO36
4
3
Copper Area 2x2 cm
and via holes
2
1
0
0
20
40
60
80
Tamb ( °C)
24/26
100
120
140
160
TDA7491HV
8
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
11-Dec-2007
1
Changes
Initial release.
25/26
TDA7491HV
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