TI SN65HVD1050QDRQ1

SN65HVD1050-Q1
www.ti.com
SLLS696A – MAY 2006 – REVISED JUNE 2006
EMC OPTIMIZED CAN TRANSCEIVER
FEATURES
APPLICATIONS
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Qualified for Automotive Applications
Customer-Specific Configuration Control Can
Be Supported Along With Major-Change
Approval
Improved Drop In Replacement for the
TJA1050
Meets or Exceeds the Requirements of
ISO 11898-2
GIFT / ICT Compliant
ESD protection up to ±8 kV (Human Body
Model) on Bus Pins
High Electromagnetic Immunity (EMI)
Low Electromagnetic Emissions (EME)
Bus-Fault Protection of –27 V to 40 V
Dominant Time-Out Function
Thermal Shutdown Protection
Power-Up/Down Glitch-Free Bus Inputs and
Outputs
– High Input Impedance with Low VCC
– Monotonic Outputs During Power Cycling
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GMW3122 Dual Wire CAN Physical Layer
SAE J2284 High Speed CAN for Automotive
Applications
SAE J1939 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
Industrial Automation
– DeviceNet™ Data Buses (Vendor ID #806)
DESCRIPTION
The SN65HVD1050 meets or exceeds the
specifications of the ISO 11898 standard for use in
applications employing a Controller Area Network
(CAN). The device is qualified for use in automotive
applications.
As a CAN transceiver, this device provides
differential transmit capability to the bus and
differential receive capability to a CAN controller at
signaling rates up to 1 megabit per second (Mbps) (1).
(1)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
FUNCTION BLOCK DIAGRAM
8
Silent Mode
VCC
S
VCC
3
Dominant
Time-Out
Temperature
Protection
30 mA
VCC/2
5
Vref
30 mA
TXD
1
7
Driver
6
CANH
CANL
2
RXD
4
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNet is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN65HVD1050-Q1
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SLLS696A – MAY 2006 – REVISED JUNE 2006
DESCRIPTION (CONTINUED)
Designed for operation is especially harsh environments, the HVD1050 features cross-wire, over-voltage, and
loss of ground protection from –27 V to 40 V, over-temperature protection, a –12 V to 12 V common-mode
range, and will withstand voltage transients from –200 V to 200 V according to ISO 7637.
Pin 8 provides for two different modes of operation: high-speed or silent mode. The high-speed mode of
operation is selected by connecting S (pin 8) to ground.
If a high logic level is applied to the S pin of the SN65HVD1050, the device enters a listen-only silent mode
during which the driver is switched off while the receiver remains fully functional.
In silent mode, all bus activity is passed by the receiver output to the local protocol controller. When data
transmission is required, the local protocol controller reverses this low-current silent mode by placing a logic-low
on the S pin to resume full operation.
A dominant-time-out circuit in the SN65HVD1050 prevents the driver from blocking network communication with
a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge
is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the
next rising edge on TXD.
Vref (pin 5) is available as a VCC/2 voltage reference.
The SN65HVD1050 is characterized for operation from –40°C to 125°C.
SN65HVD1050
TXD
GND
VCC
RXD
1
8
2
7
3
6
4
5
S
CANH
CANL
Vref
ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKED
AS
ORDERING NUMBER
SN65HVD1050-Q1
SOIC-8
H1050Q
SN65HVD1050QDRQ1 (reel)
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
VCC
–0.3 V to 7 V
Voltage range at any bus terminal (CANH, CANL, Vref)
–27 V to 40 V
IO
Receiver output current
VI
Voltage input, transient pulse (3) (CANH, CANL)
VI
Voltage input range (TXD, S)
TJ
Junction temperature
(1)
(2)
(3)
2
Supply voltage (2)
20 mA
–200 V to 200 V
–0.5 V to 6 V
–40°C to 170°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6, and 7.
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ELECTROSTATIC DISCHARGE PROTECTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Human Body Model (2)
Electrostatic discharge
(1)
Charged Device
Model (3)
UNIT
Bus terminals and GND
±8 kV
All pins
±4 kV
All pins
±1.5 kV
±200 V
Machine Model
(1)
(2)
(3)
All typical values at 25°C.
Tested in accordance JEDEC Standard 22, Test Method A114-A.
Tested in accordance JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.75
5.25
V
VI or VIC
Voltage at any bus terminal (separately or common mode)
–12
12
V
VIH
High-level input voltage
2
5.25
V
VIL
Low-level input voltage
0
0.8
V
VID
Differential input voltage
–6
6
V
IOH
High-level output current
IOL
Low-level output current
TJ
Junction temperature
TXD, S
Driver
–70
Receiver
mA
–2
Driver
70
Receiver
mA
2
150
°C
TYP
MAX
UNIT
See Thermal Characteristics table
SUPPLY CURRENT
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC
5-V Supply current
TEST CONDITIONS
Silent mode
S at VCC, VI = VCC
Dominant
VI = 0 V, 60 Ω Load, S at 0 V
Recessive
VI = VCC, No Load, S at 0 V
MIN
6
10
50
70
6
10
TYP
MAX
mA
DEVICE SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
td(LOOP1)
td(LOOP2)
TEST CONDITIONS
Total loop delay, driver input to receiver output,
recessive to dominant
Total loop delay, driver input to receiver output,
dominant to recessive
MIN
90
230
90
230
Figure 9, S at 0 V
UNIT
ns
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
VO(D)
Bus output voltage (Dominant)
VO(R)
Bus output voltage (Recessive)
(1)
TEST CONDITIONS
CANH
CANL
VI = 0 V, S at 0 V, RL = 60 Ω, See Figure 1
and Figure 2
VI = 3 V, S at 0 V, RL = 60 Ω, See Figure 1
and Figure 2
MIN TYP (1)
2.9
3.4
0.8
2
MAX
4.5
1.5
2.3
3
UNIT
V
V
All typical values are at 25°C with a 5-V supply.
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DRIVER ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditiions (unless otherwise noted)
PARAMETER
VOD(D)
Differential output voltage (Dominant)
VOD(R)
Differential output voltage (Recessive)
VOC(ss)
Steady state common-mode output
voltage
MIN TYP (1)
TEST CONDITIONS
MAX
VI = 0 V, RL = 60 Ω, S at 0 V, See Figure 1,
Figure 2, and Figure 3
1.5
3
V
VI = 0 V, RL = 45 Ω, S at 0 V, See Figure 1,
Figure 2, and Figure 3
1.4
3
V
–0.012
0.012
–0.5
0.05
VI = 3 V, S at 0 V, See Figure 1 and Figure 2
VI = 3 V, S at 0 V, No Load
2
2.3
3
Change in steady-state common-mode
output voltage
IIH
High-level input current, TXD input
VI at VCC
–2
2
IIL
Low-level input current, TXD input
VI at 0 V
–50
–10
IO(off)
Power-off TXD output current
VCC at 0 V, TXD at 5 V
30
–105
Output capacitance
mV
µA
VCANH = 12 V, CANL Open, See Figure 11
–72
0.36
VCANL = –12 V, CANH Open, See Figure 11
–1
1
–0.5
VCANL = 12 V, CANH Open, See Figure 11
CO
V
1
VCANH = –12 V, CANL Open, See Figure 11
Short-circuit steady-state output current
V
S at 0 V, Figure 8
∆VOC(ss)
IOS(ss)
UNIT
71
105
MIN
TYP
MAX
25
65
120
25
45
120
mA
See receiver input capacitance
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high level output
tPHL
Propagation delay time, high-to-low level output
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from silent mode to dominant
See Figure 7
t(dom)
Dominant time-out
↓VI, See Figure 10
S at 0 V, See Figure 4
25
UNIT
ns
50
1
µs
700
µs
TYP (1)
MAX
UNIT
800
900
300
450
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+– VIT–)
VOH
High-level output voltage
IO = –2 mA, See Figure 6
VOL
Low-level output voltage
IO = 2 mA, See Figure 6
0.2
0.4
V
II(off)
Power-off bus input current
CANH or CANL = 5 V,
Other pin at 0 V,
VCC at 0 V, TXD at 0 V
165
250
µA
IO(off)
Power-off RXD leakage current
VCC at 0 V, RXD at 5 V
20
µA
CI
Input capacitance to ground, (CANH or CANL)
TXD at 3 V,
VI = 0.4 sin (4E6πt) + 2.5 V
CID
Differential input capacitance
TXD at 3 V, VI = 0.4 sin (4E6πt)
RID
Differential input resistance
RIN
Input resistance, (CANH or CANL)
(1)
4
TEST CONDITIONS
S at 0 V, See Table 1
TXD at 3 V, S at 0 V
All typical values are at 25°C with a 5-V supply.
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500
650
100
125
4
4.6
mV
V
13
pF
5
30
15
80
30
40
kΩ
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SLLS696A – MAY 2006 – REVISED JUNE 2006
RECEIVER ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
RI(m)
TEST CONDITIONS
Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] x 100%
V(CANH) = V(CANL)
MIN
TYP (1)
MAX
–3%
0%
3%
UNIT
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tr
Output signal rise time
tf
Output signal fall time
S at 0 V or VCC, See Figure 6
MIN
TYP
MAX
UNIT
60
100
130
ns
45
70
130
ns
8
ns
8
ns
S-PIN CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IIH
High level input current
S at 2 V
IIL
Low level input current
S at 0.8 V
MIN
TYP
MAX
20
40
70
5
20
30
UNIT
µA
VREF-PIN CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VO
Reference output voltage
TEST CONDITIONS
–50 µA < IO < 50 µA
MIN
0.4 VCC
TYP
MAX
0.5 VCC 0.6 VCC
UNIT
V
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K thermal
resistance (1)
MIN
TYP
Junction-to-air thermal resistance
θJB
Junction-to-board thermal resistance
53
θJC
Junction-to-case thermal resistance
79
PD
Average power dissipation
VCC = 5 V, Tj = 27°C, RL = 60 Ω, S at 0 V, Input to TXD
at 500 kHz, 50% duty cycle square wave. CL at RXD =
15 pF
(1)
131
°C/W
112
VCC = 5.5 V, Tj = 130°C, RL = 45 Ω, S at 0 V, Input to
TXD at 500 kHz, 50% duty cycle square wave. CL at
RXD = 15 pF
Thermal shutdown temperature
UNIT
211
θJA
High-K thermal resistance
MAX
mW
170
190
°C
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.
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SLLS696A – MAY 2006 – REVISED JUNE 2006
FUNCTION TABLES
DRIVER
INPUTS
(1)
OUTPUTS
BUS STATE
TXD (1)
S (1)
CANH (1)
CANL (1)
L
L or Open
H
L
DOMINANT
H
X
Z
Z
RECESSIVE
Open
X
Z
Z
RECESSIVE
X
H
Z
Z
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
RECEIVER
(1)
DIFFERENTIAL INPUTS
VID = V(CANH) – V(CANL)
OUTPUT RXD (1)
BUS STATE
VID≥ 0.9 V
L
DOMINANT
0.5 V < VID < 0.9 V
?
?
VID≤ 0.5 V
H
RECESSIVE
Open
H
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
PARAMETER MEASUREMENT INFORMATION
IO(CANH)
II
Dominant
VOD
RL
VO(CANH) + VO(CANL)
Recessive
2.5 V
2
S
I I(S)
+
VI(S)
_
VOC
I O(CANL)
V O(CANL)
1.5 V
Figure 1. Driver Voltage, Current, and Test Definition
CANH
0V
TXD
VOD
S
CANL
VO(CANL)
Figure 2. Bus Logic State Voltage Definitions
330 W +1%
RL
+
_
−2 V 3 VTEST 3 7 V
330 W +1%
Figure 3. Driver VOD Test Circuit
6
VO(CANH)
VO (CANH)
TXD
VI
3.5 V
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PARAMETER MEASUREMENT INFORMATION (continued)
CANH
VCC
VI
TXD
VCC/2
0V
RL = 60 W
±1%
VO
tPLH
CL = 100 pF
(see Note B)
VI
VO
(See Note A)
VCC/2
tPHL
VO(D)
90%
0.9 V
0.5 V
10%
S
CANL
tr
VO(R)
tf
Figure 4. Driver Test Circuit and Voltage Waveforms
CANH
RXD
VI (CANH)
IO
VID
V
+ VI (CANL)
VIC = I (CANH)
2
VI (CANL)
VO
CANL
Figure 5. Receiver Voltage and Current Definitions
3.5 V
CANH
VI
V
RXD
1.5 V
tPLH
CANL
1.5 V
S
2.4 V
IO
I
(See Note A)
2V
CL = 15 pF + 20%
(See Note B)
VO
VO
tPHL
90%
0.7 VCC
VOH
0.3 VCC
10%
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤ 6
ns, tf≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 6. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
R
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
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VOL
VOH
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DUT
CANH
TXD
0V
CL
S
VI
60 W
+1%
0V
VOH
CANL
NOTE: CL = 100 pF
includes
instrumentation
and fixture capacitance
within ±20%
RXD
+
VO
_
VCC
50 %
VI
15 pF +20%
50 %
VO
VOL
ten
NOTE: All VI input pulses are supplied by a generator having the
following characteristics: tr or tf ≤ 6 ns, Pulse Repetition Rate
(PRR) = 25 kHz, 50% duty cycle
Figure 7. ten Test Circuit and Waveform
27 W +1%
VI
DVOC(SS)
CANH
TXD
VOC
CANL
S
27 W +1%
47 nF V = VO(CANH) + VO(CANL)
+20% OC
2
NOTE: All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Common Mode Output Voltage Test and Waveforms
DUT
VCC
CANH
VI
TXD
S
CL
60 W
±1%
TXD Input
0V
+
tloop1
tloop2
VOH
CANL
RXD Output
RXD
50%
50%
50%
NOTE: CL = 100 pF
includes instrumentation
and fixture capacitance
within±20%
VO
_
15 pF ±20%
A.
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. t(LOOP) Test Circuit and Waveform
8
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VCC
VI
TXD
RL = 60 W
+1%
VI
(See Note A)
S
0V
VOD
CL
(See Note B)
VOD(D)
VOD
900 mV
500 mV
CANH
0V
tdom
A.
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 10. Dominant Time-Out Test Circuit and Waveforms
| IOS(SS) |
| IOS(P) |
IOS
200 ms
CANH
TXD
0V
0 V or VCC
12 V
S
CANL
VIN
−12 V or 12 V
Vin
0V
or
0V
10 ms
Vin
−12 V
Figure 11. Driver Short-Circuit Current Test and Waveform
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DEVICE INFORMATION
Table 2. Parametric Cross Reference With the TJA1050
TJA1050 (1)
PARAMETER
HVD1050
TRANSMITTER SECTION
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
Driver IIH
IIL
Low-level input current
Driver IIL
ILI
Power-off bus input current
Receiver II(off)
IO(SC)
Short-circuit output current
Driver IOS(SS)
VO(dom)
Dominant output voltage
Driver VO(D)
Vi(dif)(th)
Differential input voltage
Receiver VIT and recommended VID
Vi(dif)(hys)
Diffrential input hysteresis
Receiver Vhys
VO(reces)
Recessive output voltage
Driver VO(R)
VO(dif)(bus)
Differential bus voltage
Driver VOD(D) and VOD(R)
Ri(cm)
CANH, CANL input resistance
Receiver RIN
Ri(dif)
Differential input resistance
Receiver RID
Ri(cm)(m)
Input resistance matching
Receiver RI (m)
Ci
Input capacitance to ground
Receiver CI
Ci(dif)
Differential input capacitance
Receiver CID
IOH
High-level output current
Recommended IOH
IOL
Low-level output current
Recommended IOL
Vref
Reference output voltage
BUS SECTION
RECEIVER SECTION
Vref PIN SECTION
VO
TIMING SECTION
td(TXD-BUSon)
Delay TXD to bus active
Driver tPLH
td(TXD-BUSoff)
Delay TXD to bus inactive
Driver tPHL
td(BUSon-RXD)
Delay bus active to RXD
Receiver tPHL
td(BUSoff-RXD)
Delay bus inactive to RXD
Receiver tPLH
td(TXD-BUSon) + td(BUSon-RXD)
Device tLOOP1
td(TXD-BUSoff) + td(BUSoff-RXD)
Device tLOOP2
tdom(TXD)
Dominant time out
Driver t(dom)
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
IIH
IIL
Low-level input current
IIL
S PIN SECTION
(1)
10
From TJA1050 Product Specification, Philips Semiconductors, 2002 May 16.
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Equivalent Input and Output Schematic Diagrams
TXD Input
Vcc
RXD Output
Vcc
25 W
4.3 kW
Output
Input
6V
6V
CANL Input
CANH Input
Vcc
Vcc
10 kW
10 kW
20 kW
20 kW
Input
Input
10 kW
40 V
10 kW
40 V
CANH and CANL Outputs
S Input
Vcc
Vcc
CANH
4.3 kW
Input
6V
CANL
40 kW
40 V
40 V
Vref Output
Vcc
2 kW
Output
2 kW
40 V
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TYPICAL CHARACTERISTICS
150
145
140
DOMINANT-TO-RECESSIVE LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
t LOOP2 − Dominant-to-Recessive Loop Time − ns
t LOOP1− Recessive-to-Dominant Loop Time − ns
RECESSIVE-TO-DOMINANT LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 4.75 V
135
130
VCC = 5 V
125
VCC = 5.25 V
120
−40
0
25
70
TA − Free-Air Temperature − °C
160
VCC = 5.25 V
155
VCC = 5 V
150
145
VCC = 4.75 V
140
0
25
70
125
TA − Free-Air Temperature − °C
Figure 12.
Figure 13.
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
90
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
RXD = 15 pF
80
35
30
25
20
15
10
5
70
60
50
40
30
20
TA = 255C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
10
0
0
200
400
500
600
800
Signaling Rate − kbps
1000
−10
Figure 14.
12
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
−40
I OL − Low-Level Output Current − mA
I CC − RMS Supply Current − mA
40
165
125
50
45
170
0
1
2
3
4
5
VOCANL − Low-Level Output Voltage − V
Figure 15.
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SLLS696A – MAY 2006 – REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TA = 25 C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
-70
-60
-50
-40
-30
-20
-10
3
Dominant Driver Differential Output Voltage − V
-0
1
S at 0 V,
RL = 60 W,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
0.5
0
25
70
TA − Free-Air Temperature − °C
Figure 16.
Figure 17.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
125
6
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
VIT+
VIT−
5
30
25
20
15
10
VCM = 12 V
4
VCM = 2.5 V
3
VCM = −12 V
2
TA = 255C,
VCC = 5 V,
S at 0 V,
RXD = 15 pF
1
0.65
0.60
5.25
0.70
5
0.75
3.5
4
4.5
VCC − Supply Voltage − V
0.85
3
0.80
2
0.85
1
−1
1
0.80
0
0.70
0
5
0.75
35
VCC = 4.75 V
1.5
0.65
40
2
−40
VO − Receiver Output Voltage − V
I O − Differential Driver Output Current − mA
45
VCC = 5.25 V
0
0
1
2
3
4
5
VOCANH − High-Level Output Voltage − V
50
VCC = 5 V
2.5
0.60
I OH − High-Level Output Current − mA
-80
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE (across VCC)
VID − Differential Input Voltage − V
Figure 18.
Figure 19.
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13
SN65HVD1050-Q1
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SLLS696A – MAY 2006 – REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
TYPICAL ELECTROMAGNETIC EMISSIONS
UP TO 50 MHZ (Peak Amplitude)
TYPICAL ELECTROMAGNETIC
IMMUNITY PERFORMANCE
80
dBm
DB mV
60
40
20
0
0.1
Figure 20.
14
1
10
f − Frequency − MHz
Figure 21.
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100
1000
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN65HVD1050QDRQ1
ACTIVE
SOIC
D
Pins Package Eco Plan (2)
Qty
8
2500 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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