SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 D D D D D D D D DW OR N PACKAGE (TOP VIEW) Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Very Low Power Consumption 5 mW Typ Wide Driver Supply Voltage . . . ± 4.5 V to ± 15 V Driver Output Slew Rate Limited to 30 V/µs Max Receiver Input Hysteresis . . . 1000 mV Typ Push-Pull Receiver Outputs On-Chip Receiver 1-µs Noise Filter Functionally interchangeable With Motorola MC145404 VDD 1RA 1DY 2RA 2DY 3RA 3DY 4RA 4DY VSS 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1RY 1DA 2RY 2DA 3RY 3DA 4RY 4DA GND description The SN75C1154 is a low-power BiMOS device containing four independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device has been designed to conform to ANSI EIA/TIA-232-E. The drivers and receivers of the SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs and the receivers have filters that reject input noise pulses of shorter than 1 µs. Both these features eliminate the need for external components. The SN75C1154 is designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of the input signals. If this is not the case or for other uses, it is recommended that the SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. The SN75C1154 is characterized for operation from 0°C to 70°C. logic symbol† 1RA 2RA 3RA 4RA 1DY 2DY 3DY 4DY logic diagram (positive logic) 2 19 4 17 6 15 8 13 3 18 5 16 7 14 9 12 1RY 2RY typical of each receiver RA 2, 4, 6, 8 19, 17, 15, 13 RY 3RY 4RY 1DA typical of each driver DY 3, 5, 7, 9 18, 16, 14, 12 DA 2DA 3DA 4DA † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 schematics of inputs and outputs EQUIVALENT DRIVER INPUT VDD Input DA EQUIVALENT DRIVER OUTPUT VDD Internal 1.4-V Reference 160 Ω VSS 74 Ω GND Output DY 72 Ω VSS Input RA EQUIVALENT RECEIVER INPUT 3.4 kΩ EQUIVALENT RECEIVER OUTPUT VCC 1.5 kΩ ESD Protection ESD Protection Output RY 530 Ω GND GND Resistor values shown are nominal. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Supply voltage, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 V to 30 V Output voltage range, VO: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VSS – 6 V) to (VDD + 6 V) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to (VCC + 0.3 V) Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: SN75C1154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to the network GND terminal. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING DW 1125 mW 9.0 mW/°C 720 mW N 1150 mW 9.2 mW/°C 736 mW recommended operating conditions MIN NOM MAX Supply voltage, VDD 4.5 12 15 V Supply voltage, VSS – 4.5 – 12 – 15 V Supply voltage, VCC 4.5 5 6 V VDD ± 25 V Input voltage, voltage VI High-level input voltage, VIH Low-level input voltage, VIL High-level output current, IOH High-level output current, IOL Driver VSS+2 Receiver 2 Driver 0.8 Receiver Operating free-air temperature, TA 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V –1 mA 3.2 mA 70 °C 3 SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 DRIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V, VCC = 5 V ±10% (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V TYP† 4 4.5 10 10.8 MAX UNIT VOH High level output voltage High-level VIL = 0.8 V,, See Figure 1 VOL Low-level output voltage g (see Note 2) VIH = 2 V,, See Figure 1 RL = 3 kΩ,, High-level input current See Figure 2 1 µA Low-level input current VI = 5 V, VI = 0, See Figure 2 –1 µA IOS(H) High-level g short circuit output current‡ VI = 0 0.8 8V V, VO = 0 or VSS, See Figure 1 – 7.5 75 – 12 – 19.5 19 5 mA IOS(L) Low-level short circuit output current‡ VI = 2 V V, VO = 0 or VDD, See Figure 1 75 7.5 12 19 5 19.5 mA IDD Supply current from VDD No load load, All inputs at 2 V or 0 0.8 8V VDD = 5 V, VDD = 12 V VSS = – 5 V VSS = – 12 V 115 250 115 250 ISS Supply current from VSS No load load, All inputs at 2 V or 0 0.8 8V VDD = 5 V, VDD = 12 V VSS = – 5 V VSS = – 12 V – 115 – 250 – 115 – 250 IIH IIL RL = 3 kΩ,, MIN V – 4.4 –4 – 10.7 – 10 V µA µA ro Output resistance VDD = VSS = VCC = 0, VO = – 2 V to 2 V, See Note 3 300 400 Ω † All typical values are at TA = 25°C. ‡ Not more than one output should be shorted at one time. NOTES: 2. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic levels only. 3. Test conditions are those specified by EIA/TIA-232-E. switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ±10%, TA = 25°C PARAMETER tPLH tPHL tTLH tTHL tTLH tTHL TEST CONDITIONS MIN TYP MAX 1.2 3 µs 2.5 3.5 µs 0.53 2 3.2 µs 0.53 2 3.2 µs Propagation delay time, low- to high-level output§ Propagation delay time, high- to low-level output§ Transition time, low- to high-level output¶ RL = 3 to 7 kΩ, CL = 15 pF, See Figure 3 UNIT Transition time, high- to low-level output¶ Transition time, low- to high-level output# RL = 3 to 7 kΩ, CL = 2500 pF, See Figure 3 1 2 µs Transition time, high- to low-level output# RL = 3 to 7 kΩ, CL = 2500 pF, See Figure 3 1 2 µs SR Output slew rate RL = 3 to 7 kΩ, CL = 15 pF, See Figure 3 4 10 30 V/µs § tPHL and tPLH include the additional time due to on-chip slew rate control and are measured at the 50% points. ¶ Measured between 10% and 90% points of output waveform. # Measured between 3 V and – 3 V points of output waveform (EIA/TIA-232-E conditions) with all unused inputs tied either high or low. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 RECEIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = –12 V, = 5 V ± 10% (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT VIT IT+ Positive-going g g input threshold voltage See Figure 5 17 1.7 21 2.1 2 55 2.55 V VIT IT– Negative-going g g g input threshold voltage See Figure 5 0 65 0.65 1 1 25 1.25 V Vhys Input hysteresis voltage (VIT+ – VIT–) 600 1000 VI = 0.75 V, IOH = – 20 µA, See Figure 5 and Note 4 3.5 VCC = 4.5 V VCC = 5 V 2.8 4.4 3.8 4.9 VCC = 5.5 V See Figure 5 4.3 VOH High level output voltage High-level VI = 0.75 0 75 V, V See Figure 5 IOH = – 1 mA, A VOL Low-level output voltage VI = 3 V, VI = 25 V IOL = 3.2 mA, IIH High level input current High-level mV V 5.4 0.17 0.4 3.6 4.6 8.3 VI = 3 V VI = – 25 V 0.43 0.55 1 – 3.6 –5 – 8.3 VI = – 3 V – 0.43 – 0.55 –1 V mA IIL Low level input current Low-level IOS(H) Short circuit output at high level Short-circuit VI = 0 0.75 75 V V, VO = 0 0, See Figure 4 –8 – 15 mA IOS(L) Short circuit output at low level Short-circuit VI = VCC, VO = VCC, See Figure 4 13 25 mA ICC Supply current from VCC No load, All inputs at 0 or 5 V 400 600 400 600 VDD = 5 V, VDD = 12 V, VSS = – 5 V VSS = – 12 V µA † All typical values are at TA = 25°C. NOTE 4: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs will remain in the high state. switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10%, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low- to high-level output tTLH tTHL Transition time, low- to high-level output Propagation delay time, high- to low-level output CL = 50 pF, pF RL = 5 kΩ kΩ, Transition time, high- to low-level output See Figure 6 MIN TYP MAX 3 4 UNIT µs 3 4 µs 300 450 ns 100 300 ns tw(N) CL = 50 pF, RL = 5 kΩ 1 4 µs ‡ The receiver ignores any positive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any positive- or negative-going pulse greater than the maximum of tw(N). Duration of longest pulse rejected as noise‡ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 PARAMETER MEASUREMENT INFORMATION IOSL VDD VCC VDD VCC VDD or GND – IOSH IIH VSS or GND VI VI – IIL RL = 3 kΩ VO VI VSS VSS Figure 1. Driver Test Circuit VOH, VOL, IOSL, IOSH Figure 2. Driver Test Circuit, IIL, IIH 3V VDD Input VCC Input 1.5 1.5 0V Pulse Generator (see Note A) tPHL RL CL (see Note B) tPLH 90% 50% 10% Output 50% 10% tTHL VSS VOH 90% tTLH VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms VDD VCC VI – IOS(H) VDD VCC IOS(L) VIT, VI VOH VCC VOL VSS IOL VSS Figure 4. Receiver Test Circuit, IOSH, IOSL 6 – IOH POST OFFICE BOX 655303 Figure 5. Receiver Test Circuit, VIT, VOL, VOH • DALLAS, TEXAS 75265 SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS SLLS151C – DECEMBER 1988 – REVISED MARCH 1997 PARAMETER MEASUREMENT INFORMATION 4V VDD Input Input VCC 50% 50% 0V Pulse Generator (see Note A) tPHL RL CL (see Note B) tPLH 90% 90% 50% 10% Output 50% 10% tTHL VSS tTLH VOH VOL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 6. Receiver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated