TI SN74F161ADR

SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
D
D
D
D, DB, OR N PACKAGE
(TOP VIEW)
Internal Look-Ahead Circuitry for Fast
Counting
Carry Output for N-Bit Cascading
Fully Synchronous Operation for Counting
CLR
CLK
A
B
C
D
ENP
GND
description
1
16
2
15
3
14
4
13
5
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
12
This synchronous, presettable, 4-bit binary
6
11
counter has internal carry look-ahead circuitry
7
10
for use in high-speed counting designs.
8
9
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However,
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is asynchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop
outputs to low, regardless of the levels of CLK, LOAD, ENP, and ENT.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORMATION
PACKAGE†
TA
PDIP – N
0°C to 70°C
SOIC – D
SSOP – DB
ORDERABLE
PART NUMBER
Tube
SN74F161AN
Tube
SN74F161AD
Tape and reel
SN74F161ADR
Tape and reel
SN74F161ADBR
TOP-SIDE
MARKING
SN74F161AN
F161A
F161A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
state diagram
0
2
3
4
15
5
14
6
13
7
12
2
1
11
POST OFFICE BOX 655303
10
9
• DALLAS, TEXAS 75265
8
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
logic diagram (positive logic)
CLR
LOAD
ENT
ENP
1
9
10
15
7
RCO
R
14
CLK
A
2
3
G2
QA
1, 2T/C3
1, 3D
M1
R
13
G2
QB
1, 2T/C3
B
4
1, 3D
M1
R
12
G2
QC
1, 2T/C3
C
5
1, 3D
M1
R
11
G2
QD
1, 2T/C3
D
6
1, 3D
M1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
logic symbol, each flip-flop
R
TE
R
Q1
1, 2T/C3
CLK
D
Q1
G2
Q2
1, 3D
Q2
LOAD
M1
logic diagram, each flip-flop (positive logic)
R
TE
(Toggle
Enable)
Q1
CLK
Q2
D
LOAD
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
typical clear, preset, count, and inhibit sequences
The following timing sequence is illustrated below:
1. Clear outputs to zero
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
Data
Inputs
B
C
D
CLK
ENP
ENT
QA
Data
Outputs
QB
QC
QD
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
V
Input clamp current
–18
mA
IOH
IOL
High-level output current
–1
mA
Low-level output current
20
mA
High-level input voltage
2
V
V
TA
Operating free-air temperature
0
70
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = – 18 mA
IOH = – 1 mA
VCC = 4.75 V,
VCC = 4.5 V,
IOH = – 1 mA
IOL = 20 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
MIN
2.5
TYP‡
ENT, LOAD
0.3
V
0.5
V
0.1
mA
20
µA
– 0.6
VCC = 5.5 V,
VI = 0.5 V
– 1.2
mA
– 0.6
VCC = 5.5 V,
VCC = 5.5 V
VO = 0
– 60
37
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
6
V
2.7
CLR
IOS§
ICC
UNIT
– 1.2
3.4
ENP, CLK, A, B, C, D
IIL
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–150
mA
55
mA
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
fclock
Clock frequency
CLK high or low (loading)
tw
Pulse duration
CLK (counting)
tsu
ENP and ENT before CLK↑
Data after CLK↑
th
Hold time
LOAD after CLK↑
ENP and ENT after CLK↑
tsu
Inactive-state setup time, CLR high before CLK↑†
† Inactive-state setup time also is referred to as recovery time.
0
100
MIN
0
5
5
4
4
Low
6
7
5
5
High or low
LOAD before CLK↑
Setup time
MAX
High
CLR low
Data before CLK↑
MIN
5
5
High
11
11.5
Low
8.5
9.5
High
11
11.5
Low
5
5
High or low
2
2
High
2
2
Low
0
0
High or low
0
0
6
6
MAX
UNIT
90
MHz
ns
ns
ns
ns
switching characteristics (see Note 4)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V TO 5.5 V,
CL = 50 PF,
RL = 500 Ω,
TA = MIN TO MAX‡
MIN
MAX
100
120
2.7
5.1
7.5
2.7
8.5
2.7
7.1
10
2.7
11
3.2
5.6
8.5
3.2
9.5
3.2
5.6
8.5
3.2
9.5
4.2
9.6
14
4.2
15
4.2
9.6
14
4.2
15
1.7
4.1
7.5
1.7
8.5
1.7
4.1
7.5
1.7
8.5
Any Q
4.7
8.6
12
4.7
13
RCO
3.7
7.6
10.5
3.7
11.5
CLK (LOAD high)
Any Q
CLK (LOAD low)
Any Q
CLK
RCO
ENT
RCO
CLR
VCC = 5 V,
CL = 50 PF,
RL = 500 Ω,
TA = 25°C
MIN
TYP
MAX
90
UNIT
MHz
ns
ns
ns
ns
ns
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 4: Load circuits and waveforms are shown in Figure 1.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74F161A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS056B – MARCH 1987 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
From Output
Under Test
CL
(see Note A)
Test
Point
500 Ω
7V
Open
500 Ω S1
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Collector
Open
7V
Open
7V
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
VOH
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOH
1.5 V
VOL
1.5 V
0V
tPZL
tPLZ
≈3.5 V
1.5 V
tPZH
tPLH
1.5 V
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns,
duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74F161AD
ACTIVE
SOIC
D
16
SN74F161ADBR
ACTIVE
SSOP
DB
SN74F161ADBRE4
ACTIVE
SSOP
SN74F161ADBRG4
ACTIVE
SN74F161ADE4
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SSOP
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74F161ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74F161ADR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74F161ADRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74F161ADRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74F161AN
ACTIVE
PDIP
N
16
CU NIPDAU
N / A for Pkg Type
25
Pb-Free
(RoHS)
TBD
Call TI
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74F161AN3
OBSOLETE
PDIP
N
16
SN74F161ANE4
ACTIVE
PDIP
N
16
Call TI
SN74F161ANSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74F161ANSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74F161ANSRG4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
16-Jul-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74F161ADBR
DB
16
MLA
330
16
8.2
6.6
2.5
12
16
Q1
SN74F161ADR
D
16
FMX
330
16
6.5
10.3
2.1
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
SN74F161ADBR
DB
SN74F161ADR
D
16
MLA
346.0
346.0
33.0
16
FMX
342.9
336.6
28.58
Pack Materials-Page 2
Height (mm)
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated