SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
D 300-Mbps to 660-Mbps Serial LVDS Data
D
D
D
Payload Bandwidth at 30-MHz to 66-MHz
System Clock
Pin-Compatible Superset of NSM
DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power
Consumption <450 mW (Typ) at 66 MHz
Synchronization Mode for Faster Lock
D
D
D
D
D
D
Lock Indicator
No External Components Required for PLL
Low-Cost 28-Pin SSOP Package
Industrial Temperature Qualified,
TA = −40°C to 85°C
Programmable Edge Trigger on Clock
Flow-Through Pinout for Easy PCB Layout
SN65LV1023
Serializer
SYNC1
SYNC2
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
TCLK_R/F
TCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SN65LV1224
Deserializer
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DVCC
DVCC
AVCC
AGND
PWRDN
AGND
D O+
D O−
AGND
DEN
AGND
AVCC
DGND
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AGND
RCLK_R/F
REFCLK
AVCC
RI+
RI−
PWRDN
REN
RCLK
LOCK
AVCC
AGND
AGND
DGND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
DVCC
DGND
DVCC
DGND
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
description
The SN65LV1023 serializer and SN65LV1224 deserializer comprise a 10-bit serdes chipset designed to
transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 30 MHz
to 66 MHz. Including overhead, this translates into a serial data rate between 360-Mbps and 792-Mbps payload
encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC
patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,
the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is
available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1023 and SN65LV1224 are characterized for operation over ambient air temperature of –40°C to
85°C.
ORDERING INFORMATION
DEVICE
PART NUMBER
Serializer
SN65LV1023DB
Deserializer
SN65LV1224DB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002 − 2005, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
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block diagrams
SN65LVDS1023
SN65LVDS1224
TCLK
(30 MHZ to
66 MHz)
PLL
Timing /
Control
Y+
A−
Y−
PLL
DEN
Clock
Recovery
SYNC1
SYNC2
10
Output Latch
TCLK_R/F
A+
Serial-to-Parallel
Input Latch
DIN
Parallel-to-Serial
LVDS
10
Timing /
Control
DOUT
REFCLK
REN
LOCK
RCLK_R/F
RCLK
(30 MHz to
66 MHz)
functional description
The SN65LV1023 and SN65LV1224 are a 10-bit serializer/deserializer chipset designed to transmit data over
differential backplanes or unshielded twisted pair (UTP) at clock speeds from 30 MHz to 66 MHz. The chipset
has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down
mode, and high-impedance mode. The following sections describe each state of operation.
initialization mode
Initialization of both devices must occur before data transmission can commence. Initialization refers to
synchronization of the serializer and deserializer PLLs to local clocks.
When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state,
while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device
begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an
external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs
remain in the high-impedance state, while the PLL locks to the TCLK.
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functional description (continued)
synchronization mode
The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be
accomplished in one of two ways:
D Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six
ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the
deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC
patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid SYNC1 or
SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.
When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock
information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC
patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low.
When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the
deserializer LOCK output directly to SYNC1 or SYNC2.
D Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the
serializer to send special SYNC patterns. This allows the SN65LV1224 to operate in open-loop applications.
Equally important is the deserializer’s ability to support hot insertion into a running backplane. In the
open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because
lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary
constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK
when the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer
could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive
multitransition (RMT); see Figure 1 for RMT examples. This occurs when more than one low-high transition
takes place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the
data pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock
exists. Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false
lock pattern changes. Notice that the RMT pattern only affects the deserializer lock time, and once the
deserializer is in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary
happens each cycle. The deserializer does not go into lock unitil it finds a unique four consecutive cycles of data
boundary (stop/start bits) at the same position.
The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive
cycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event
of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a
high-impedance state. The user’s system should monitor the LOCK pin in order to detect a loss of
synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if
reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as
previously noted.
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synchronization mode (continued)
DIN0 Held Low and DIN1 Held High
Stop
Bit
Start
Bit
DIN0
Stop
Bit
Start
Bit
Stop
Bit
Start
Bit
Stop
Bit
Start
Bit
DIN1
DIN4 Held Low and DIN5 Held High
Stop
Bit
Start
Bit
DIN4
DIN5
DIN8 Held Low and DIN9 Held High
Stop
Bit
Start
Bit
DIN8
DIN9
Figure 1. RMT Pattern Examples
data transmission mode
After initialization and synchronization, the serializer accepts parallel data from inputs DIN0 – DIN9. The serializer
uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to
strobe incoming data. If either of the SYNC inputs is high for 6 TCLK cycles, the data at DIN0 −DIN9 is ignored
regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent.
After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the
register. The start bit is always high and the stop bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO±)
at 12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 × 12 = 792 Mbps. Because
only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz,
the useful data rate is 66 × 10 = 660 Mbps. The data source, which provides TCLK, must be in the range of
30 MHz to 66 MHz.
4
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functional description (continued)
The serializer outputs (DO±) can drive point-to-point connections or limited multipoint or multidrop backplanes.
The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the serializer output pins enter the high-impedance state.
Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks
to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low, otherwise
ROUT0 – ROUT9 is invalid. The ROUT0−ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to
be used is selected by the RCLK_R/F input. The ROUT0 – ROUT9, LOCK and RCLK outputs can drive a maximum
of three CMOS input gates (15-pF load. total for all three) with a 66-MHz clock.
power down
When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the
power-down state, a low-power sleep mode, to reduce power consumption. The deserializer enters power down
when you drive PWRDN and REN low. The serializer enters power down when you drive PWRDN low. In power
down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces
supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high.
Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and
resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer
initialize and drives LOCK high until lock to the LVDS clock occurs.
high-impedance mode
The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output
pins (DO+ and DO−) into a high-impedance state. When you drive DEN high, the serializer returns to the
previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the
REN pin is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins
(ROUT0 – ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active,
reflecting the state of the PLL.
Deserializer Truth Table
INPUTS
OUTPUTS
PWRDN
REN
ROUT[0:9]
LOCK
H
H
RCLK
H
Z
H
Z
H
Active
L
Active
L
X
Z
Z
Z
H
L
Z
Active
Z
NOTES: 1. LOCK output reflects the state of the deserializer with regard
to the selected data stream.
2. RCLK active indicates the RCLK is running if the deserializer
is locked. The timing of RCLK with respect to ROUT is
determined by RCLK_R/F.
3. ROUT and RCLK are 3-stated when LOCK is asserted high.
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Terminal Functions
serializer
PIN
NAME
18, 20, 23, 25
AGND
Analog circuit ground (PLL and analog circuits)
17, 26
Analog circuit power supply (PLL and analog circuits)
19
AVCC
DEN
15, 16
DGND
Digital circuit ground
3 −12
DIN0 − DIN9
21
DO −
22
DO +
DVCC
PWRDN
Noninverting LVDS differential output
1, 2
SYNC1,
SYNC2
LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted high
for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If after
completion of the transmission of 1026 patterns SYNC continues to be asserted, then the transmission
continues until SYNC is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC pattern
tranmission initiates.
13
TCLK_R/F
LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data strobe.
14
TCLK
LVTTL-level reference clock input. The SN65LV1023 accepts a 30-MHz to 66-MHz clock. TCLK strobes
parallel data into the input latch and provides a reference frequency to the PLL.
27, 28
24
DESCRIPTION
LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial data
output.
Parallel LVTTL data inputs
Inverting LVDS differential output
Digital circuit power supply
LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedance
state, putting the device into a low-power mode.
deserializer
PIN
NAME
1, 12, 13
AGND
Analog circuit ground (PLL and analog circuits)
4, 11
AVCC
DGND
Analog circuit power supply (PLL and analog circuits)
14, 20, 22
21, 23
DVCC
Digital circuit power supply
10
LOCK
LVTTL level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge.
7
PWRDN
LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state,
putting the device into a low-power mode.
2
RCLK_R/F
LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data
strobe.
9
RCLK
3
REFCLK
8
REN
LVTTL logic input. Low places ROUT0−ROUT9 and RCLK in the high-impedance state.
5
RI+
Serial data input. Noninverting LVDS differential input
6
RI−
ROUT0−ROUT9
15 −19,
24 −28
6
DESCRIPTION
Digital circuit ground
LVTTL level output recovered clock. Use RCLK to strobe ROUTx.
LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency.
Serial data input. Inverting LVDS differential input
Parallel LVTTL data outputs
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absolute maximum ratings (unless otherwise noted)†
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
LVTTL input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VCC + 0.3 V)
LVTTL output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VCC + 0.3 V)
LVDS receiver input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.9 V
LVDS driver output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.9 V
LVDS output short circuit duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ms
Electrostatic discharge: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 6 kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 200 V
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Lead temperature (soldering, 4 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Maximum package power dissipation, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.27 W
Package derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 mW/°C above 25°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC}
3
3.3
3.6
V
Receiver input voltage range
0
2.4
V
ID
2
V
100
mVP−P
°C
ǒ Ǔ
V
V
ID
2
Receiver input common mode range, VCM
2.4 –
Supply noise voltage
Operating free-air temperature, TA
−40
25
85
UNIT
‡ By design, DVCC and AVCC are separated internally and does not matter what the difference is for DVCC−AVCC, as long as both are within
3 V to 3.6 V.
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electrical characteristics over recommended operating supply and temperature ranges (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note 4)
VIH
VIL
High-level input voltage
2
Low-level input voltage
GND
VCL
IIN
Input clamp voltage
ICL = −18 mA
VIN = 0 V or 3.6 V
Input current (see Note 5)
−200
VCC
0.8
V
−0.86
−1.5
V
±100
200
µA
VCC
0.8
V
−1.5
V
200
µA
V
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (see Note 6)
VIH
VIL
High-level input voltage
2
Low-level input voltage
GND
VCL
Input clamp voltage
ICL = −18 mA
IIN
Input current (pull-up and pull-down
resistors on inputs)
VIN = 0 V or 3.6 V
−200
IOH = − 5 mA
IOL = 5 mA
2.2
3
0.25
VCC
0.5
V
GND
−15
−47
−85
mA
−10
±1
10
µA
350
450
VOH
VOL
High-level output voltage
IOS
IOZ
Output short-circuit current
Low-level output voltage
−0.62
VOUT = 0 V
PWRDN or REN = 0.8 V, VOUT = 0 V or VCC
High-impedance output current
V
V
SERIALIZER LVDS DC SPECIFICATIONS (apply to pins DO+ and DO −)
RL = 27 Ω, See Figure 18
VOD
∆VOD
Output differential voltage (DO+)–(DO−)
VOS
∆VOS
Offset voltage
IOS
Output short circuit current
D0 = 0 V, DINx = high,
PWRDN and DEN = 2.4 V
IOZ
IOX
High-impedance output current
PWRDN or DEN = 0.8 V, DO = 0 V or VCC
Power-off output current
VCC = 0 V, DO = 0 V or 3.6 V
CO
Output single-ended capacitance
Output differential voltage unbalance
mV
35
1.1
mV
1.2
1.3
V
4.8
35
mV
−10
−90
mA
−10
±1
10
µA
−20
±1
Offset voltage unbalance
25
µA
1±20%
pF
50
mV
DESERIALIZER LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
VTL
Differential threshold high voltage
IIN
Input current
CI
Input single-ended capacitance
VCM = 1.1 V
Differential threshold low voltage
−50
VIN = 2.4 V, VCC = 3.6 V or 0 V
VIN = 0 V, VCC = 3.6 V or 0 V
mV
−10
±1
15
−10
± 0.05
10
0.5±20%
µA
A
pF
SERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
f = 30 MHz
30
45
f = 66 MHz
55
70
200
500
f = 30 MHz
40
50
f = 66 MHz
80
95
ICCXR Deserializer supply current, power down PWRDN = 0.8 V, REN = 0.8 V
0.36
NOTES: 4. Apply to DIN0 −DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN
5. High IIN values are due to pull-up and pull-down resistors on the inputs.
6. Apply to pins PWRDN, RCLK_R/F, REN, REFCLK = inputs; apply to pins ROUTx, RCLK, LOCK = outputs
1
ICCD
RL = 27 Ω, See Figure 2
Serializer supply current worst case
ICCXD Serializer supply current
PWRDN = 0.8 V
DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
ICCR
8
Deserializer supply current, worst case
CL = 15 pF, See Figure 3
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mA
µA
mA
mA
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
serializer timing requirements for TCLK over recommended operating supply and temperature
ranges (unless otherwise specified)
PARAMETER
MIN
TYP
MAX
UNIT
15.15
T
33.33
ns
Transmit clock high time
0.4T
0.5T
0.6T
ns
Transmit clock low time
0.4T
0.5T
0.6T
ns
3
6
ns
tTCP
tTCIH
Transmit clock period
tTCIL
tt(CLK)
tJIT
TCLK input jitter
TEST CONDITIONS
TCLK input transition time
See Figure 17
150
ps
(RMS)
serializer switching characteristics over recommended operating supply and temperature ranges
(unless otherwise specified)
PARAMETER
TEST CONDITIONS
tTLH(L)
tLTHL(L)
LVDS low-to-high transition time
tsu(DI)
tsu(DI)
DIN0−DIN9 setup to TCLK
td(HZ)
td(LZ)
DO± high-to-high-impedance-state delay
LVDS high-to-low transition time
RL = 27 Ω, CL = 10 pF to GND,
See Figure 7
DIN0−DIN9 hold from TCLK
td(ZH)
td(ZL)
DO± high-to-high-impedance-state-to-low
delay
SYNC pulse duration
Serializer PLL lock time
td(S)
Serializer delay
tDJIT
Deterministic jitter
tRJIT
Random jitter
MAX
0.2
0.4
ns
0.25
0.4
ns
ns
2.5
5
2.5
5
5
10
6.5
10
6×tTCP
1026×tTCP
66 MHz
ns
t
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TCP ) 3.6
2
ns
230
RL = 27 Ω, CL = 10 pF to GND
RL = 2.7 Ω, CL = 10 pF to GND
ns
ns
RL = 27 Ω, See Figure 11
30 MHz
UNIT
ns
4
RL = 27 Ω, CL = 10 pF to GND,
See Figure 8
RL = 27 Ω, See Figure 10
TYP
0.5
DO± low-to-high-impedance-state delay
DO± high-to-high-impedance-state-tohigh delay
tw(SPW)
t(PLD)
MIN
RL = 27 Ω, CL = 10 pF to GND,
See Figure 4
150
10
19
ps
ps
(RMS)
9
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
deserializer timing requirements for REFCLK over recommended operating supply and
temperature ranges (unless otherwise specified)
PARAMETER
tRFCP
tRFDC
REFCLK period
tt(RF)
REFCLK transition time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
15.15
T
33.33
ns
30%
50%
70%
3
6
REFCLK duty cycle
ns
deserializer switching characteristics over recommended operating supply and temperature
ranges (unless otherwise specified)
PARAMETER
TEST CONDITIONS
t(RCP)
Receiver out clock
period
t(RCP) = t(TCP),
See Figure 11
RCLK
tTLH(C)
CMOS/TTL low-to-high
transition time
tTHL(C)
CMOS/TTL high-to-low
transition time
CL = 15 pF,
See Figure 5
ROUT0 −ROUT9,
LOCK, RCLK
Deserializer delay,
See Figure 12
Room temperature,
3.3 V
30 MHz
td(D)
t(ROS)
ROUTx data valid before
RCLK
t(ROH)
ROUTx data valid after
RCLK
t(RDC)
RCLK duty cycle
td(HZ)
High-to-high-impedance
state delay
td(LZ)
Low-to-high-impedance
state delay
High-impedance stateto-high delay
td(ZL)
High-impedance-state-to
-low delay
t(DSR1)
Deserializer PLL lock
time from PWRDN
(with SYNCPAT)
t(DSR2)
Deserializer PLL lock
time from SYNCPAT
td(ZHLK)
High-impedance-state
to-high delay
(power up)
66 MHz
RCLK 66 MHz
30 MHz
66 MHz
See Figure 14
See Figure 15,
Figure 16, and
Note 7
MIN
TYP
15.15
RCLK 30 MHz
See Figure 13
td(HR)
PIN/FREQ
MAX
UNIT
33.33
ns
1.2
2.5
1.1
2.5
ns
2×tRCP + 7
2×tRCP + 4
2.833×tRCP + 11
2.833×tRCP + 7
ns
0.4×tRCP
0.4×tRCP
0.5×tRCP
0.5×tRCP
−0.4×tRCP
−0.4×tRCP
−0.5×tRCP
−0.5×tRCP
40%
50%
60%
6.5
8
ns
4.7
8
ns
5.3
8
ns
4.7
8
ns
ns
ROUT0 −ROUT9
30 MHz
(1024+26)tRFCP
66 MHz
(1024+26)tRFCP
30 MHz
0.3
66 MHz
0.2
3
LOCK
µs
ns
NOTE 7: t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the
powerdown mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer
when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify
deserializer PLL performance tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
deserializer switching characteristics over recommended operating supply and temperature
ranges (unless otherwise specified) (continued)
PARAMETER
tRNM
Deserializer noise
margin
TEST CONDITIONS
See Figure 17 and
Note 8
PIN/FREQ
MIN
TYP
30 MHz
1380
66 MHz
540
MAX
UNIT
ps
NOTE 8: tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
timing diagrams and test circuits
TCLK
ODD DIN
EVEN DIN
Figure 2. Worst-Case Serializer ICC Test Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 3. Worst-Case Deserializer ICC Test Pattern
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
timing diagrams and test circuits (continued)
10 pF
tTLH(L)
DO +
tTHL(L)
RL
80%
Vdiff
80%
20%
20%
DO −
10 pF
Vdiff = (DO+) − (DO−)
Figure 4. Serializer LVDS Output Load and Transition Times
Deserializer
CMOS/TTL Output
tTHL(C)
tTLH(C)
80%
15 pF
80%
20%
20%
Figure 5. Deserializer CMOS/TTL Output Load and Transition Times
tt(CLK)
TCLK
tt(CLK)
90%
3V
90%
10%
10%
0V
Figure 6. Serializer Input Clock Transition Time
tTCP
1.5 V
TCLK
1.5 V
For TCLK_R/F = Low
1.5 V
th(DI)
tsu(DI)
DIN [9:0]
1.5 V
Setup
Hold
Figure 7. Serializer Setup/Hold Times
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.5 V
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
timing diagrams and test circuits (continued)
Parasitic Package and
Trace Capacitance
3V
DEN
1.5 V
1.5 V
0V
td(HZ)
VOH
13.5 Ω
DO +
50%
1.1 V
DO −
td(ZH)
DO ±
50%
1.1 V
td(ZL)
td(LZ)
13.5 Ω
DEN
1.1 V
50%
50%
VOL
Figure 8. Serializer High-Impedance-State Test Circuit and Timing
PWRDN
2V
0.8 V
1026 Cycles
td(HZ) or td(LZ)
TCLK
td(ZH) or td(ZL)
tPLD
DO ±
3-State
Output Active
3-State
Figure 9. Serializer PLL Lock Time and PWRDN High-Impedance-State Delays
POST OFFICE BOX 655303
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13
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
REN
PWRDN
TCLK
tw(SP)
SYNC1
or
SYNC2
DO ±
DATA
SYNC Pattern
TCLK
SYNC1
or
SYNC2
tw(SP) Min. Timing Met
DO ±
SYNC Pattern
DATA
Figure 10. SYNC Timing Delays
DIN
DIN0 − DIN9 SYMBOL N
DIN0 − DIN9 SYMBOL N+1
td(S)
TCLK
Timing for TCLK_R/F = High
Start
D00 − D09 SYMBOL N−1
Bit
Stop
Bit
Start
Bit
DO
Figure 11. Serializer Delay
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D00 − D09 SYMBOL N
Stop
Bit
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
Start
Bit
D00 − D09 SYMBOL N
Stop
Bit
Start
Bit
D00 − D09 SYMBOL N+1
Stop
Bit
Start
Bit
D00 − D09 SYMBOL N+2
RI
Stop
Bit
1.2 V
1V
tDD
RCLK
Timing for TCLK_R/F = High
ROUT
ROUT0 − ROUT9 SYMBOL N−1
ROUT0 − ROUT9 SYMBOL N+1
ROUT0 − ROUT9 SYMBOL N
Figure 12. Deserializer Delay
tLow
tHigh
RCLK
RCLK_R/F = Low
tHigh
tLow
RCLK
RCLK_R/F = High
tROH
tROS
ROUT [9:0]
Data Valid
Before RCLK
1.5 V
Data Valid
After RCLK
1.5 V
Figure 13. Deserializer Data Valid Out Times
VOH
7 V x (LZ/ZL), Open (HZ/ZH)
REN
500 Ω
450 Ω
1.5 V
1.5 V
VOL
Scope
td(LZ)
50 Ω
VOL
ROUT[9:0]
VOL + 0.5 V
td(HZ)
VOH
VOH − 0.5 V
td(ZL)
VOL + 0.5 V
td(ZH)
VOH − 0.5 V
Figure 14. Deserializer High-Impedance-State Test Circuit and Timing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
timing diagrams and test circuits (continued)
PWRDN
2V
0.8 V
REFCLK
1.5 V
t(DSR1)
DATA
RI±
Not Important
td(ZHL)
LOCK
SYNC Patterns
3-State
3-State
td(HZ) or td(LZ)
td(ZH) or td(ZL)
ROUT[9:0]
3-State
3-State
SYNC Symbol or DIN[9:0]
RCLK
3-State
3-State
RCLK_R/F = Low
REN
Figure 15. Deserializer PLL Lock Times and PWRDN 3-State Delays
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• DALLAS, TEXAS 75265
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
timing diagrams and test circuits (continued)
3.6 V
3V
VCC
0V
PWRDN
0.8 V
REFCLK
t(DSR2)
DATA
1.2 V
RI±
Not Important
1V
SYNC Patterns
LOCK
3-State
td(ZH) or td(ZL)
ROUT[9:0]
td(HZ) or td(LZ)
3-State
3-State
SYNC Symbol or DIN[9:0]
RCLK
3-State
3-State
REN
Figure 16. Deserilaizer PLL Lock Time From SyncPAT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
timing diagrams and test circuits (continued)
1.2 V
VTH
VTL
RI±
1V
tDJIT
tDJIT
tRNM
tRNM
tSW
Ideal Sampling Position
tSW: Setup and Hold Time (Internal Data Sampling Window)
tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK
tRNM: Receiver Noise Margin Time
Figure 17. Receiver LVDS Input Skew Margin
DO +
RL
10
DIN
Parallel-to-Serial
DO −
> TCLK
VOD = (DO+) − (DO−)
Differential Output Signal Is Shown as (DO+) − (DO−)
Figure 18. VOD Diagram
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• DALLAS, TEXAS 75265
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°−ā 8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
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