TI CD74HC4059E

[ /Title
(CD74
HC4059
)
/Subject
(HighSpeed
CMOS
Logic
CMOS
Pro-
CD54HC4059, CD74HC4059
Data sheet acquired from Harris Semiconductor
SCHS206B
High-Speed CMOS Logic
CMOS Programmable Divide-by-N Counter
February 1998 - Revised May 2003
Features
Description
• Synchronous Programmable ÷N Counter N = 3 to 9999
or 15999
The ’HC4059 are high-speed silicon-gate devices that are
pin-compatible with the CD4059A devices of the CD4000B
series. These devices are divide-by-N down-counters that
can be programmed to divide an input frequency by any
number “N” from 3 to 15,999. The output signal is a pulse
one clock cycle wide occurring at a rate equal to the input
frequency divide by N. The down-counter is preset by means
of 16 jam inputs.
• Presettable Down-Counter
• Fully Static Operation
• Mode-Select Control of Initial Decade Counting
Function (÷10, 8, 5, 4, 2)
• Master Preset Initialization
The three Mode-Select Inputs Ka, Kb and Kc determine the
modulus (“divide-by” number) of the first and last counting
sections in accordance with the truth table. Every time the first
(fastest) counting section goes through one cycle, it reduces by
1 the number that has been preset (jammed) into the three
decades of the intermediate counting section an the last
counting section, which consists of flip-flops that are not
needed for opening the first counting section. For example, in
the ÷2 mode, only one flip-flop is needed in the first counting
section. Therefore the last counting section has three flip-flops
that can be preset to a maximum count of seven with a place
value of thousands. If ÷10 is desired for the first section, Ka is
set “high”, Kb “high” and Kc “low”. Jam inputs J1, J2, J3, and J4
are used to preset the first counting section and there is no last
counting section. The intermediate counting section consists of
three cascaded BCD decade (÷10) counters presettable by
means of Jam Inputs J5 through J16.
• Latchable ÷N Output
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
The Mode-Select Inputs permit frequency-synthesizer
channel separations of 10, 12.5, 20, 25 or 50 parts. These
inputs set the maximum value of N at 9999 (when the first
counting section divides by 5 or 10) or 15,999 (when the first
counting section divides by 8, 4, or 2).
Applications
• Communications Digital Frequency Synthesizers;
VHF, UHF, FM, AM, etc.
• Fixed or Programmable Frequency Division
The three decades of the intermediate counter can be preset
to a binary 15 instead of a binary 9, while their place values
are still 1, 10, and 100, multiplied by the number of the ÷N
mode. For example, in the ÷8 mode, the number from which
counting down begins can be preset to:
3rd Decade
1500
2nd Decade
150
1st Decade
15
Last Counting Section
1000
• “Time Out” Timer for Consumer-Application Industrial
Controls
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC4059F3A
-55 to 125
24 Ld CERDIP
CD74HC4059E
-55 to 125
24 Ld PDIP
CD74HC4059M96
-55 to 125
24 Ld SOIC
The total of these numbers (2665) times 8 equals 12,320.
The first counting section can be preset to 7. Therefore,
21,327 is the maximum possible count in the ÷8 mode.
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
The highest count of the various modes is shown in the
Extended Counter Range column. Control inputs Kb and Kc
can be used to initiate and lock the counter in the “master
preset” state. In this condition the flip-flops in the counter are
preset in accordance with the jam inputs and the counter
remains in that state as long as Kb and Kc both remain low. The
counter begins to count down from the preset state when a
counting mode other than the master preset mode is selected.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC4059, CD74HC4059
Pinout
The counter should always be put in the master preset mode
before the ÷5 mode is selected. Whenever the master preset
mode is used, control signals Kb = “low” and Kc = “low” must
be applied for at least 3 full clock pulses.
CD54HC4059
(CERDIP)
CD74HC4059
(PDIP, SOIC)
TOP VIEW
After Preset Mode inputs have been changed to one of the ÷
modes, the next positive-going clock transition changes an
internal flip-flop so that the countdown can begin at the
second positive-going clock transition. Thus, after an MP
(Master Preset) mode, there is always one extra count
before the output goes high. Figure 1 illustrates a total count
of 3 (÷8 mode). If the Master Preset mode is started two
clock cycles or less before an output pulse, the output pulse
will appear at the time due. If the Master Preset Mode is not
used, the counter jumps back to the “Jam” count when the
output pulse appears.
A “high” on the Latch Enable input will cause the counter
output to remain high once an output pulse occurs, and to
remain in the high state until the latch input returns to “low”.
If the Latch Enable is “low”, the output pulse will remain high
for only one cycle of the clock-input signal.
CP 1
24 VCC
LE 2
23 Q
J1 3
22 J5
J2 4
21 J6
J3 5
20 J7
J4 6
19 J8
J16 7
18 J9
J15 8
17 J10
J14 9
16 J11
J13 10
15 J12
Kc 11
14 Ka
GND 12
13 Kb
Functional Diagram
J1 - J16
CP
Ka
f IN
Q =  -------
 N
Kb
Kc
LE
TRUTH TABLE
COUNTER RANGE
MODE SELECT INPUT
FIRST COUNTING SECTION
CAN BE
PRESET
MODE
TO A MAX
DIVIDES-BY
OF:
(NOTE 1)
JAM
INPUTS
USED:
LAST COUNTING SECTION
CAN BE
PRESET
MODE
TO A MAX
DIVIDES-BY
OF:
DESIGN
EXTENDED
(NOTE 1)
JAM
INPUTS
USED:
MAX
MAX
Ka
Kb
Kc
H
H
H
2
1
J1
8
7
J2, J3, J4
15,999
17,331
L
H
H
4
3
J1, J2
4
3
J3, J4
15,999
18,663
H
L
H
5
(Note 2)
4
J1, J2, J3
2
1
J4
9,999
13,329
L
L
H
8
7
J1, J2, J3
2
1
J4
15,999
21,327
H
H
L
10
9
J1, J2, J3, J4
1
0
-
9,999
16,659
X
L
L
-
-
Master Preset
Master Preset
X = Don’t care
NOTES:
1. J1 = Least Significant Bit. J4 = Most Significant Bit.
2. Operation in the 5mode (1st counting section) requires going through the Master Preset mode prior to going into the 5mode. At power
turn-on, Kc must be “low” for a period of 3 input clock pulses after VCC reaches a minimum of 3V.
2
CD54HC4059, CD74HC4059
How to Preset the HC/HCT4059 to Desired ÷N
The value N is determined as follows:
N
Preset Value = Mode
(EQ. 1)
N = (MODE†) (1000 x Decade 5 Preset + 100 x Decade 4
Preset + 10 x Decade 3 Preset + 1 x Decade 2 Preset) +
Decade 1 Preset
Example:
N = 8479, Mode = 5
† MODE = First counting section divider (10, 8, 5, 4 or 2)
To calculate preset values for any N count, divide the N
count by the Mode. The resultant is the corresponding
preset values of the 5th through 2nd decade with the
remainder being equal to the 1st decade value.
(EQ. 2)
Mode Select = 5
Ka Kb Kc
H L H
1695 + 4 (Preset Values)
5 | 8479
Mode
N
Program Jam Inputs (BCD)
4
J1
L
1
J2 J3
L
9
5
J4
J5 J6 J7
H
H
H
L
J9 J10
J8
H
H
L
6
J11
J12
J13
J14
J15
J16
L
H
L
H
H
L
L
NOTE: To verify the results, use Equation 1:
N = 5 (1000 x 1 + 100 x 6 + 10 x 9 + 1 x 5) + 4
N = 8479
PROGRAM JAM INPUTS (BCD)
J1
J2 J3
3
12
4
J4
5
J5
6
J6
22
J7
21
J8
20
J9 J10 J11 J12
19
18
17
16
J13 J14 J15 J16
15
10
9
8
7
P.E.
GND
PRESETTABLE LOGIC
24
VCC
CLOCK
INPUT
FIRST
COUNTING
SECTION
÷10, 8, 5, 4, 2
1
LAST
COUNTING
SECTION
÷1, 2, 2, 4, 8
INTERMEDIATE COUNTING SECTION
÷10
÷10
÷10
RECOGNITION
GATING
14
Ka
MODE
SELECT
INPUTS
13
Kb
11
MODE
CONTROL
PRESET
ENABLE
Kc
23
2
OUTPUT
STAGE
LATCH
ENABLE
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
3
DIVIDE-BY-N
OUTPUT
CD54HC4059, CD74HC4059
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical)
θJA (oC/W)
E (PDIP) Package (Note 3) . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package (Note 4). . . . . . . . . . . . . . . . . . .
46
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. The package thermal impedance is calculated in accordance with JESD 51-3.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
Quiescent Device
Current
-55oC TO 125oC
VI (V)
IO (mA)
VIH
-
-
2
1.5
-
-
1.5
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
VIL
VOH
-
VIH or
VIL
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
-40oC TO 85oC
SYMBOL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
25oC
VCC
(V)
-
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
1.5
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
4
CD54HC4059, CD74HC4059
Prerequisite for Switching Specifications
25oC
PARAMETER
Pulse Width CP
Setup Time
Kb, Kc to CP
CP Frequency
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tW
2
90
-
-
115
-
-
135
-
-
ns
4.5
18
-
-
23
-
-
27
-
-
ns
6
15
-
-
20
-
-
23
-
-
ns
2
75
-
-
95
-
-
110
-
-
ns
4.5
15
-
-
19
-
-
22
-
-
ns
6
13
-
-
16
-
-
19
-
-
ns
2
5
-
-
4
-
-
4
-
-
MHz
4.5
27
-
-
22
-
-
18
-
-
MHz
6
32
-
-
26
-
-
21
-
-
MHz
tSU
fMAX
Switching Specifications Input tr, tf = 6ns
PARAMETER
Propagation Delay,
CP to Q
Propagation Delay,
LE to Q
Output Transition Time
CP Frequency
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tPLH, tPHL
CL = 50pF
2
-
-
200
-
250
-
300
ns
4.5
-
-
40
-
50
-
60
ns
6
-
-
34
-
43
-
51
ns
CL = 15pF
5
-
17
-
-
-
-
-
ns
CL = 50pF
2
-
-
175
-
220
-
265
ns
4.5
-
-
35
-
44
-
53
ns
6
-
-
30
-
37
-
45
ns
CL = 15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
tPLH, tPHL
tTHL, tTLH
fMAX
CL = 15pF
5
-
54
-
-
-
-
-
MHz
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
36
-
-
-
-
-
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per package.
6. PD = CPD VCC2 fi + Σ CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
5
CD54HC4059, CD74HC4059
Test Circuits and Waveforms
tr = 6ns
tfCL
trCL
CLOCK
90%
10%
I
tWL + tWH =
fCL
tf = 6ns
VCC
50%
10%
tWL
50%
VCC
90%
50%
10%
INPUT
GND
50%
tTHL
GND
tTLH
90%
50%
10%
tWH
INVERTING
OUTPUT
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tPHL
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tfCL
trCL
CLOCK
INPUT
VCC
90%
50%
10%
GND
tH(H)
tH(L)
VCC
DATA
INPUT
50%
GND
tSU(H)
tSU(L)
tTLH
90%
tTHL
90%
50%
10%
tPLH
tPHL
OUTPUT
tREM
VCC
SET, RESET
OR PRESET
tPLH
50%
GND
IC
CL
50pF
FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL
TIME, AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-8944501JA
ACTIVE
CDIP
J
24
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC4059F3A
ACTIVE
CDIP
J
24
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC4059E
ACTIVE
PDIP
N
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC4059EE4
ACTIVE
PDIP
N
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC4059M96
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4059M96E4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4059M96G4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CD74HC4059M96
Package Package Pins
Type Drawing
SOIC
DW
24
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.75
15.7
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC4059M96
SOIC
DW
24
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002
N (R–PDIP–T24)
PLASTIC DUAL–IN–LINE
1.222 (31,04) MAX
24
13
0.360 (9,14) MAX
1
12
0.070 (1,78) MAX
0.200 (5,08) MAX
0.425 (10,80) MAX
0.020 (0,51) MIN
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0’–15’
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
0.010 (0,25) NOM
4040051–3/D 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–010
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
B
13
24
C
1
12
0.065 (1,65)
0.045 (1,14)
Lens Protrusion (Lens Optional)
0.010 (0.25) MAX
0.175 (4,45)
0.140 (3,56)
0.090 (2,29)
0.060 (1,53)
A
Seating Plane
0.018 (0,46) MIN
24
PINS **
DIM
”A”
”B”
”C”
NARR
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
28
WIDE
NARR
40
32
WIDE
NARR
WIDE
NARR
WIDE
MAX
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
MIN
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
MAX
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
MIN
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
MAX
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
MIN
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
4040084/C 10/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI008 – OCTOBER 1994
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.610 (15,49)
0.590 (14,99)
0.020 (0,51) MIN
Seating Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.125 (3,18) MIN
0.010 (0,25) M
PINS **
0°– 15°
0.010 (0,25) NOM
24
28
32
40
48
52
A MAX
1.270
(32,26)
1.450
(36,83)
1.650
(41,91)
2.090
(53,09)
2.450
(62,23)
2.650
(67,31)
A MIN
1.230
(31,24)
1.410
(35,81)
1.610
(40,89)
2.040
(51,82)
2.390
(60,71)
2.590
(65,79)
DIM
4040053 / B 04/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MS-011
Falls within JEDEC MS-015 (32 pin only)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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