TDA7705 Highly integrated tuner for AM/FM car radio Features ■ Fully integrated VCO for world tuning ■ High performance PLL for fast RDS system ■ AM/FM mixers with high image rejection ■ Integrated AM-LNA and AM-PINDIODE ■ Automatic self alignment for preselection and image rejection ■ Digital IF signal processing, high performance and drift-free ■ Integrated IF-filters with high selectivity, high dynamic range and adaptive bandwidth control ■ RDS demodulation with group and block synchronization ■ High performance stereodecoder with noiseblanker ■ I2C/SPI bus controlled ■ Single 5 V supply ■ LQFP64 package Description The TDA7705 highly integrated tuner (HIT) is a new generation of high performance tuners for carradio applications. Table 1. March 2010 LQFP64 It contains mixers and IF amplifiers for AM and FM, fully integrated VCO and PLL synthesizer, IF-processing including adaptive bandwidth control, stereo decoder and RDS decoder on a single chip. The utilization of digital signal processing results in numerous advantages against today's tuners: very low number of external components, very small space occupation and easy application, very high selectivity due to digital filters, high flexibility by software control and automatic alignment. Device summary Order code Package Packing TDA7705 LQFP64 (10x10x1.4mm) Tray TDA7705TR LQFP64 (10x10x1.4mm) Tape and reel Doc ID 15938 Rev 8 1/42 www.st.com 1 Contents TDA7705 Contents 1 2 3 2/42 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 FM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 FM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 AM - LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 AM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 AM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 IF A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 Audio D/A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13.1 Serial interface choice / boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13.2 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.13.3 SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.1 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.2 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.3 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.4 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.5 Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 15938 Rev 8 TDA7705 Contents 3.5 3.4.6 IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.7 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.8 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.9 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.10 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.11 Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.1 FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.2 AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.3 AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.4 AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.5 WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 Front-end processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Weak signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 5.2 6 FM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.3 Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.4 Stereo blend- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.5 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.6 Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.1 Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.3 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 Application schematic example with SPI-bus and tuned preselection . . . 39 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 15938 Rev 8 3/42 List of tables TDA7705 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. 4/42 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Boot mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Register 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Stereo blend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 De-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 15938 Rev 8 TDA7705 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C "read" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI "read" sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FM input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AM MW input set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AM LW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AM SW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WX input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FM wide-band application / I2C control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Example of FM tuned (narrow-band) application / SPI control . . . . . . . . . . . . . . . . . . . . . . 39 LQFP64 (10x10x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . . 40 Doc ID 15938 Rev 8 5/42 Block diagram and pins description TDA7705 1 Block diagram and pins description 1.1 Block diagram Functional block diagram DSP RDS RDSINT Figure 1. DLL Supply OSC :N AGC AM Doc ID 15938 Rev 8 VCO PLL FREF :8 AGC DAC 6/42 Audio Out STEREO DAC SPI ADC ADC I2C/ NCO SUM TDA7705 Pin description VCC-DAC OSCout OSCin GND-DAC DACoutL GND-IFADC DACoutR LIFrefL LIFrefH VCC-IFADC VCC-PLL GND-PLL VCOdec LFref VCC-VCO Pin connection (top view) GND-VCO Figure 2. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LFI 1 48 GND-1V2 PLLTEST 2 47 VDD-1V2 DAC 3 46 TEST TCAGCFM 4 45 RSTN FMMIX1dec 5 44 MODE FMMIX1in 6 43 GPIO0 FMMIX2in 7 42 GPIO1 GND-RF 8 41 GPIO2 FMPINDRV 9 40 GPIO3 VCC-RF 10 39 RDSINT TCAM 11 38 VDD-1V2 AMPINDRV 12 37 SCL/CLK PINDdec 13 36 SDA/MOSI PINDin 14 35 SPI_MISO GND-LNA 15 34 SPI_CS LNAin 16 33 GND-3V3 Table 2. Pin # VDD-3V3 REG-1V2 VCCREG12 VCC-DIG GND-DIG VREFdec VREF165 GND-IF AMMIXdec AMMIXin1 AMMIXin2 LNAdec2 LNAout2 LNAin2 LNAout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LNAdec 1.2 Block diagram and pins description AC00418 Pin description Pin name Function 1 LF1 PLL loopfilter output 2 PLLTEST PLL test output / GPO 3 DAC FM tuning DAC output 4 TCAGCFM FM AGC time constant 5 FMMIX1dec FM mixer decoupling 6 FMIX1in FM mixer input 1 7 FMIX2in FM mixer input 2 8 GND-RF RF Ground 9 FMPINDRV FM AGC PIN diode driver 10 VCC-RF 5V supply for RF section 11 TCAM AM AGC time constant 12 AMPINDRV AM AGC external PIN diode driver 13 PINDdec AM AGC internal PIN diode decoupling 14 PINDin AM AGC internal PIN diode input 15 GND-LNA AM LNA and internal PIN diode GND 16 LNAin AM LNA input Doc ID 15938 Rev 8 7/42 Block diagram and pins description Table 2. Pin # 8/42 TDA7705 Pin description (continued) Pin name Function 17 LNAdec AM LNA decoupling 18 LNAout AM LNA output first stage 19 LNAin2 AM LNA input 2nd stage 20 LNAout2 AM LNA output 21 LNAdec2 AM LNA decoupling 2nd stage 22 AMMIXin2 AM mixer input 2 23 AMMIXin1 AM mixer input 1 24 AMMIXdec AM mixer decoupling 25 GND-IF IF and Vref GND 26 VREF165 1.65V reference voltage decoupling 27 VREFdec 3.3V reference voltage decoupling 28 GND-DIG Digital GND 29 VCC-DIG 5V supply for digital logic 30 VCCreg1V2 VCC of 1.2V regulator 31 REG1V2 1.2V regulator output 32 VDD-3V3 3.3V VDD output / decoupling 33 GND-3V3 3.3V VDD GND 34 SPI_CS SPI chip select 35 SPI_MISO SPI Data output 36 SDA / SPI_MOSI I2C bus data / SPI data input 37 SCL / SPI_CLK I2C bus Clock / SPI clock 38 VDD-1V2 1.2V DSP supply 39 RDSINT RDS interrupt 40 GPIO3 Reserved 41 GPIO2 Reserved 42 GPIO 1 Reserved 43 GPIO 0 Reserved 44 MODE For debug purpose only, connected to GND 45 RSTN Reset pin (active low) 46 TEST Test input 47 VDD-1V2 1.2V DSP supply 48 GND-1V2 Digital GND for 1.2V VDD 49 VCC-DAC 5V supply of audio DAC 50 OSCout Xtal osc output 51 OSCin Xtal osc input Doc ID 15938 Rev 8 TDA7705 Block diagram and pins description Table 2. Pin # Pin description (continued) Pin name Function 52 GND-DAC Audio DAC GND 53 DACoutL Audio output left 54 DACoutR Audio output right 55 GND-IFADC IF ADC GND 56 LIFrefL IF ADC reference low 57 LIFrefH IF ADC reference high 58 VCC-IFADC 5V supply of IF ADC 59 VCC-PLL 5V supply of PLL 60 GND-PLL PLL GND 61 VCO-dec VCO decoupling 62 LFref Loopfilter reference 63 VCC-VCO 5V supply of VCO 64 GND-VCO VCO GND Doc ID 15938 Rev 8 9/42 Function description TDA7705 2 Function description 2.1 FM - mixers The image-rejection mixer has two FM inputs, selectable through software. These inputs feed stages with different gains, noise figures, and IIP3. They are optimized for best performance in case of a passive tuned prestage and for a passive fixed bandpass without tuning for low-cost application respectively. The second input offers also the possibility of an easy addition of a weather-band preselection filter. The input frequency is downconverted to low IF with high image rejection. The tuned application is supported by an 8-bit tuning DAC. The alignment of the DAC is performed automatically. 2.2 FM - AGC The programmable RFAGC senses the mixer input whereas the IFAGC senses the IFADC input to avoid overload. The PIN diode driver is able to drive external PIN diodes with a current value as high as 15mA. The time constant of the FM-AGC is defined by an external capacitor. 2.3 AM - LNA The AM-LNA is integrated with low noise and high IIP2 and IIP3. The gain of the LNA is controlled by the AGC. The maximum gain is set with an external resistor, typically 26 dB with 1 kΩ. 2.4 AM - AGC The programmable AM-RF-AGC senses the mixer inputs and controls the internal PIN diode and LNA gain. First the LNA gain is reduced by about 10dB, then the PIN diodes are activated to attenuate the signal. The time constant of the AM-AGC is defined with an external capacitor and programmable internal currents. 2.5 AM - mixers The image-rejection mixer has two AM inputs selectable via software. It easily supports lowcost applications for extended frequency bands like SW, DRM. The input frequency is converted to low IF with high image rejection. 10/42 Doc ID 15938 Rev 8 TDA7705 2.6 Function description IF A/D converters A high performance IQ-IFADC converts the IF-signal to digital IF for subsequent digital signal processing. 2.7 Audio D/A converters A stereo DAC provides the left / right audio signals after IF-processing and stereodecoding by the DSP. 2.8 VCO The VCO is fully integrated without any external tuning component. It covers all FM frequency bands including EU, US , Japan, EastEU, Weatherband and AM-bands including LW, MW, SW. 2.9 PLL The high speed tuning PLL is able to settle within about 300 µs for fast RDS applications. The frequency step can be as low as 5 kHz in FM and 500 Hz in AM. 2.10 Crystal oscillator The device works with a 37.05 MHz fundamental tone crystal, and can be used also with a 3rd overtone 37.05 MHz crystal. 2.11 DSP The DSP and its hardware accelerators perform all the digital signal processing. The main program is fixed in ROM. Control parameters are copied in RAM and are accessible and modifiable there, thus allowing parametric performance optimization. It performs: ● digital down-conversion of IF ● bandwidth selection with variable controlled bandwidth ● FM and AM noiseblanking ● FM/AM demodulation with softmute, high-cut, weak signal processing and quality detection ● FM stereo decoding with stereo blend ● RDS demodulation including error correction and block synchronization with generation of an RDS interrupt for the main µP ● Autonomous control of RDS-AF tests ● Self alignment of preselection tuning Doc ID 15938 Rev 8 11/42 Function description 2.12 TDA7705 IO interface pins The TDA7705 has the following IO pins: PLLTEST pin 2 general purpose output SPI_CS pin 34 serial communication with µP SPI_MISO pin 35 serial communication with µP SDA/MOSI pin 36 serial communication with µP SCL/CLK pin 37 serial communication with µP RDSINT pin 39 serial communication with µP RSTN pin 45 reset pin driven by µP The pins labeled GPIO0, 1, 2 and 3 (pins 43 to 40) are reserved. The pin PLLTEST output voltage can be freely programmed via software and be used to drive switches if needed by the application. All the inputs are voltage-tolerant up to 3.5 V . The outputs can drive currents up to 0.5 mA from the internal 3.3 V supply line. 2.13 Serial interface The device is controlled with a standard I2C bus or SPI interface. Through the serial bus the processing parameters can be modifed and the signal quality parameters and the RDS information can be read out. The operation of the device is handled through high level commands sent by the main carradio µP through the serial interface, which allow to simplify the operations carried out in the main µP. The high level commands include among others: 2.13.1 ● set frequency (which allows to avoid computing the PLL divider factors); ● start seek (the seek operation can be carried out by the TDA7705 in a completely autonomous fashion); ● RDS seek/search (jumps to AF and quality measurements are automatically sequenced). Serial interface choice / boot mode The device can communicate with the main µP with two different standard serial protocols: SPI and I2C. The configuration is chosen by setting the proper value (0V or 3.3V) at pins 35 and 39 and it is latched (e.g. made effective) when the RSTN line transitions from low to high (when RSTN is low, the IC is in reset mode). The voltage level forced to pins 35 and 39 must be released to start the system operation a suitable time after the RSTN line has gone high. The list of configurations is shown in the following table: 12/42 Doc ID 15938 Rev 8 TDA7705 Table 3. Function description Boot mode pin configuration I2C (addr. 0 x C2) Configuration: Pin I2C (addr. 0 x C8) SPI at reset operation at reset operation at reset operation 39 RDSINT 0 in RDS interrupt out 0 in RDS interrupt out 1 in RDS interrupt out 37 SCL x I2C SCL in x I2C SCL in x SPI CLK in 36 SDA x I2C SDA in/out x I2C SDA in/out x SPI MOSI in 35 (SPI_MISO) 0 in - 1 in - 1 in SPI MISO out 34 (SPI_CS) x - x - x SPI SS in If I2C serial bus is chosen as means of communication with the controlling device, two chip addresses are possible: 0xC2/C3 or 0xC8/C9, depending on the initial configuration of pins 35 and 39. The status of pins 35 and 39 during the reset phase can be set to: high, through external <10 kΩ resistors tied to 3.3V (pin 32), or low, by not forcing any voltage on them from outside, as 50 kohm internal pull-down resistors are present on said pins. To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the RSTN line low until the IC supply pins have reached their steady state, and then for an additional time Treset (see Section 3.4.8). 2.13.2 I2C bus protocol I2C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires an acknowledge after any 8-bit transmission. A "write" communication example is shown in the figure below, for an unspecified number of data bytes (see the relevant technical documentation for frame structure description): Figure 3. I2C "write" sequence SDA a7 SCL clk1 START a6 … clk2 … address a0 clk8 d7 clk9 ACK Doc ID 15938 Rev 8 clk1 d6 … clk2 … data d0 clk8 clk9 ACK STOP 13/42 Function description TDA7705 The sequence consists of the following phases: ● START: SDA line transitioning from H to L with SCL fixed H. This signifies a new transmission is starting; ● data latching: on the rising SCL edge. The SDA line can transition only when SCL is low (otherwise its transitions are interpreted as either a START or a STOP transition); ● ACKnowledge: on the 9th SCL pulse the µP keeps the SDA line H, and the TDA7705 pulls it down if communication has been successful. Lack of the acknowledge pulse generation from the TDA7705 means that the communication has failed; ● a chip address byte must be sent at the beginning of the transmission. The value can be C2 or C8 (according to the mode chosen at start-up during boot) for "write"; ● as many data bytes as needed can follow the address before the communication is terminated. See the next section for details on the frame format; ● STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the transmission. Red lines represent transmissions from the TDA7705 to the µP. A "read" communication example is shown in the figure below, for an unspecified number of data bytes (see later on for frame structure decription): Figure 4. I2C "read" sequence SDA a7 SCL clk1 START a6 … clk2 … address a0 clk8 d7 clk9 ACK clk1 d6 … clk2 … data d0 clk8 clk9 ACK STOP The sequence is very similar to the "write" one and has the same constraints for start, stop, data latching. The differences follow: ● a chip address must always be sent by the µP to the TDA7705; the address must be C3 (if C2 had been selected at boot) or C9 (if C8 had been selected at boot); ● a header is transmitted after the chip address (the same happens for "write") before data are transferred from the TDA7705 to the µP. See the relevant technical documentation for details on the frame format; ● when data are transmitted from the TDA7705 to the µP, the µP keeps the SDA line H; ● the ACKnowledge pulse is generated by the µP for those data bytes that are sent by the TDA7705 to the µP. Failure of the µP to generate an ACK pulse on the 9th CLK pulse has the same effect on the TDA7705 as a STOP. The max. clock speed is 500 kbit/s. 2.13.3 SPI bus protocol SPI requires four signals: clock (CLK), master output/slave input (MOSI - for communication from the µP to the TDA7705), master input/slave output (MISO - for communication from the TDA7705 to the µP), chip select (CS). CLK is generated by the master device and is used for synchronization. MOSI and MISO are the data lines. The CS line is unique for each device in an SPI bus. The µP pulls low the TDA7705 CS line to select it for communication. The protocol does not foresee any transmission acknowledgement. The SPI protocol has four possible modes of operation as far as data latching is concerned: 14/42 Doc ID 15938 Rev 8 TDA7705 Function description Figure 5. SPI modes In the case of the TDA7705, the data are latched on the clock's rising edge, with CPOL = 1 and CPHA = 1 (mode 3 in the figure above). According to the specification of this mode, the polarity of the CLK line when no communication is taking place is high. A "write" communication example is shown in the figure below, for an unspecified number of bits (see the relevant technical documentation for frame structure description): Figure 6. SPI "write" sequence CS CLK MOSI MSB ... ... ... ... ... ... ... ... ... ... LSB The start condition is signaled by the CS line going low, and the stop condition by the CS line going high. It is not allowed to toggle the CS line while the communication is going on. A "read" communication example is shown in the figure below, for an unspecified number of bits (see the relevant technical documentation for frame structure description ): Figure 7. SPI "read" sequence CS CLK MOSI MSB ... ... ... ... LSB MISO MSB ... ... ... ... LSB The red line is controlled by the TDA7705, whereas the black lines are controlled by the µP. Doc ID 15938 Rev 8 15/42 Electrical specifications TDA7705 3 Electrical specifications 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameter Test condition Min Typ Max Units VCC Supply voltage - - - 5.5 V Tstg Storage temperature - -55 - 150 °C VESD 3.2 Human body model ≥ ±2000 Charged device model ≥ ±450 Charged device model, corner pins ≥ ±750 Machine model ≥ ±150 ESD withstand voltage V Thermal data Table 5. Thermal data Symbol RTh j-amb Parameter Test condition Thermal resistance junction-to-ambient LQFP64 10x10, double-layer JEDEC PCB 3.3 General key parameters Table 6. General key parameters Symbol Parameter Test condition Value Units 55 °C/W Min Typ Max Units VCC 5 V supply voltage - 4.7 5 5.25 V ICC Supply current @ 5 V - - 220 295 mA Ambient temperature range - -40 - 85 °C 2 - - V 1.08 1.2 1.32 V V1V2 = 1.08 V see note (2) - - 120 mA V1V2 = 1.2 V see note (2) - 80 135 mA V1V2 = 1.32 V see note (2) - - 150 mA Tamb VVCCREG12 VCCREG12 supply voltage V1V2 I1V2 Digital core 1.2V supply voltage Digital core 1.2 V supply current see note (1) when supplied externally see note (2) 1. In the typical application supplied from 5V with a series resistor. 2. When the 1.2 V supply is applied externally, and not using the internal 1.2 V regulator. 16/42 Doc ID 15938 Rev 8 TDA7705 3.4 Electrical specifications Electrical characteristics VCC = 4.7 V to 5.25 V; Tamb = -40 °C to +85 °C; unless otherwise specified. 3.4.1 FM - section Table 7. FM - section Symbol Parameter Test condition Min Typ Max Units 90 130 170 kΩ Mix 1, Rsource = 1.5 kΩ, noiseless - 2.5 3.1 Mix 2, Rsource = 800 Ω, noiseless - 2 122 125 FM IMR mixer Rin Vnoise IIP3 Input resistance Input noise voltage 3rd order intercept point - nV/√Hz Mix 1 up to Vin/tone = 90 dBµV Mix 2 up to Vin/tone = 85 dBµV 2.5 dBµV - 118 121 dBµV Mix 1, min setting - 87 - Mix 1, max setting - 93 - Mix 2, min setting - 85 - Mix 2, max setting - 91 - Threshold steps - - 2 - dB Threshold error @ Tamb = 27 °C 1.5 dB dB/K FM AGC RFAGC threshold, referred to mixer input; RF level RFAGC-Thr -1.5 Threshold temperature drift IFAGC-Thr dBµV - 0.016 - Mix 1, min setting - 81 - Mix 1, max setting - 85 - Mix 2, min setting - 77 - Mix 2, max setting - 81 - Threshold steps - - 2 - dB Threshold error @ Tamb = 27 °C 1.5 dB Threshold temperature drift - 0.016 - dB/K 12 - - mA 3 - 20 µA 0.4 - - mA IFAGC threshold, referred to mixer input; at tuned frequency RF level -1.5 (1) - Pin diode source current @ Tamb = 27 °C; see note - Pin diode sink current - - Pin diode source current in constant current mode @ Tamb = 27 °C; see note(1) dBµV 1. The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature dependency described by: ΔI/Io = ΔT/To, with Io being the current at ambient temperature (25 °C) and To the ambient temperature (25°C) expressed in Kelvin, that is 298 K. Doc ID 15938 Rev 8 17/42 Electrical specifications 3.4.2 AM - section Table 8. AM - section Symbol TDA7705 Parameter Test condition Min Typ Max Units 20 30 45 kΩ dBµV AM IMR Mixer Rin Vout_max VN,in Input resistance - Max. output voltage without clipping - 126 - Mix 1, Rsource = 1 kΩ, noiseless - 8.5 12 Mix 2, Rsource = 1 kΩ, noiseless - 8.5 12 Input noise voltage nV/√Hz IIP3 3rd order intercept point Mix 1,2 up to Vin/tone = 90 dBµV 126 129 - dBµV IIP2 2nd order intercept point Mix1 1,2 up to Vin/tone = 90 dBµV - 158 - dBµV N=2,3,4,5,6 - 100 - N=7,9 - 85 - LO hsupp LO harmonic suppression dB AM LNA Gain Voltage gain 21 25 28 Min Gain (AGC controlled) Max Gain, Rext = 1 kΩ - 12 - dB Rin Input resistance - - 1000 kΩ Cin Input capacitance - - 20 pF VN,in Input noise voltage - - 1.0 1.4 nV/√Hz IIP3 3rd order intercept point @ maximum LNA gain - 125 - dBµV @ maximum LNA gain - 143 - dBµV IIP2 nd 2 order intercept point AM PIN diode IIP2 2nd order intercept point Full attenuation, Csource = 80 pF, f=1 MHz - 140 - dBµV Rmin Minimum resistance - - 50 80 Ω Input capacitance High ohmic - 12 - pF Referred to mixer input RF level Mix 1,2 min setting - 87 - Mix 1,2 max setting - 93 - Threshold steps - - 1 - Cin AM AGC AGC-Thr Thr-steps dBµV Threshold error @ Tamb = 27 °C -2.5 - 2.5 Threshold temperature drift - -3 - 3 - Pin diode source current @ Tamb = 27 °C; see note(1) 2 - 10 mA - Pin diode sink current - 15 35 50 µA - Pin diode source current in constant current mode @ Tamb = 27 °C; see note(1) 1.5 2.5 3.5 mA 1. The current is generated by a PTAT (Proportional To Absolute Temperature) source, and has therefore a temperature dependency described by: ΔI/Io = ΔT/To, with Io being the current at ambient temperature (25 °C) and To the ambient temperature (25 °C) expressed in Kelvin, that is 298 K. 18/42 Doc ID 15938 Rev 8 dB TDA7705 Electrical specifications 3.4.3 VCO Table 9. VCO Symbol FVCO Parameter Test condition Min Typ Units 1550 MHz Frequency range VCO - PN Phase noise of LO Locked VCO; values referred @ 100MHz @ 100 Hz @ 1 kHz @ 10 kHz - -100 -115 -115 - dBc/Hz dev Deviation error (rms) FM reception, deemphasis 50µs, faudio = 20 Hz...20 kHz - 5 - Hz Test condition Min Typ Max Units 3.4.4 Phase locked loop Table 10. Phase locked loop Symbol 1100 Max Parameter Settling time FM Δf < 10 kHz - 300 - µs FM step FM frequency step - - 5 - kHz AM step AM frequency step - - 500 - Hz Tsettle 3.4.5 Tuning DAC Table 11. Tuning DAC Symbol Res Parameter Test condition Min Typ Max Units Resolution 8 bit - 18 - mV Voutmin Min output voltage - - 0.6 0.7 V Voutmax Max ouput voltage - VCC-0.2 VCC-0.1 - V Rout Output impdedance - 1.5 2.5 3.5 kΩ DNL Diff. Non linearity - - - 0.5 LSB Tconv Conversion time - - 20 - µs 3.4.6 IF ADC Table 12. IF ADC Symbol DRFM VN,in FM DRAM VN,in AM Parameter Test condition Min Typ Max Units Dynamic range in FM BW = ±200 kHz - 90 - dB Input noise referred to mixer input mixer 1 mixer 2 - 1.1 0.7 1.9 1.2 nV/√Hz Dynamic range in AM BW = ±4 kHz - 103 - dB Input noise referred to mixer input - - 6.9 12 nV/√Hz Doc ID 15938 Rev 8 19/42 Electrical specifications 3.4.7 Audio DAC Table 13. Audio DAC Symbol TDA7705 Parameter Test condition Min Typ Max Units Vout Max. output voltage Full scale - 1 - Vrms BW Bandwidth 1dB attenuation - 15 - KHz Rout Output resistance - 600 750 900 Ω Output noise - - 60 95 µVrms Distortion -6 dBFS - 0.03 0.04 % Min Typ Max Units 2.9 3.2 - V VN, out THD 3.4.8 IO interface pins Table 14. IO interface pins Symbol Parameter Test condition - High level output voltage (all IOs except GPO pin 2) - GPIOs source current (all IOs Total sourced current by all in source mode except pin 2) GPIOs - - 1.25 mA - Low level output voltage (all IOs except GPO pin 2) Iout = -1 mA - 0.1 0.3 V - Input voltage range - 0 - 3.5 V - High level input voltage - 2.0 - - V - Low level input voltage - - - 0.8 V Treset Reset time Minimum time during which pin RSTN must be low so as to reset the device 10 - - µs Tlatch Minimum time during which the voltage applied at pins 25 Boot mode configuration latch and 39 must be kept in order time to latch the correct boot mode (serial bus configuration) 10 - - µs 1 mA 20/42 Iout = 500 µA - GPO PLLTEST (pin 2) max source current - - - - GPO PLLTEST (pin 2) max sink current - -1 - - GPO PLLTEST (pin 2) minimum high level output voltage Iout = 1 mA 2.8 3.1 - V GPO PLLTEST (pin 2) maximum high level output voltage Iout = 1 mA - 0.1 0.3 V Doc ID 15938 Rev 8 mA TDA7705 3.4.9 Electrical specifications I2C interface The following parameters apply to the serial bus communication when I2C protocol has been selected at start-up. For the other electrical characteristics of the pins, Section 3.4.8 applies. The parameters of the following table are defined as in Figure 8. Table 15. I2C interface Symbol Parameter Min Max Units - 500 kHz fSCL SCL Clock frequency tAA SCL low to SDA data valid 0.3 - µs tbuf time the bus must be kept free before a new transmisison 1.3 - µs START condition hold time 0.6 - µs tLOW Clock low period 1.3 - µs tHIGH Clock high period 0.6 - µs tSU-SDA START condition setup time 0.1 - µs tHD-DAT Data input hold time 0 0.9 µs tSU-DAT Data input setup time 0.1 - µs tR SDA & SCL rise time - 0.3 µs tF SDA & SCL fall time - 0.3 µs 0.6 - µs - 0.3 µs tHD-STA Stop condition setup time tSU-STOP Data out time tDH Figure 8. I2C bus timing diagram tHIGH tR tLOW tF SCL tSU-STA tHD-DAT tSU-STOP tSU-DAT tHD-SDA SDA IN tAA tDH tbuf SDA OUT D95AU378A Doc ID 15938 Rev 8 21/42 Electrical specifications 3.4.10 TDA7705 SPI interface The following parameters apply to the serial bus communication when SPI protocol has been selected at start-up. For the other electrical characteristics of the pins, Section 3.4.8 applies. Table 16. SPI interface Symbol Parameter Min Max Unit fSCK Clock frequency - 4.0 MHz tSU Data setup time 25 - ns tH Data hold time 25 - ns tWH SCK high time 50 - ns tWL SCK low time 50 - ns tRI Input rise time - 2 µs tFI Input fall time - 2 µs tV Output valid from clock low - 50 ns 25 - ns 25 ns tHO Output hold time tDIS Output disable time tCS CS high time 25 - ns tCSS CS setup time 25 - ns tCSH CS hold time 25 - ns Figure 9. SPI bus timing diagram tCS V IH SPI_SS VIL SPI_CLK tCSH tCSS VIH tWH tWL VIL tH tSU VIH VALID IN SPI_MOSI VIL tRI tFI tV SPI_MISO VOH HI-Z tHO tDIS HI-Z VOL 3.4.11 Warning When the TDA7705 is not powered on, the internal ESD protection diodes pull-down keep the I2C/SPI lines connected to ground. This implies that the I2C/SPI bus connected to the TDA7705 may not be used to drive other devices when the TDA7705 is powered off. 22/42 Doc ID 15938 Rev 8 TDA7705 3.5 Electrical specifications Overall system performance All measurements obtained with application of Figure 16 (FM tuned application / SPI control) unless otherwise specified. 3.5.1 FM overall system performance Antenna level equivalence: 0 dBµV = 1 µVrms (Antenna terminal voltage with 50 Ω source). Figure 10. FM input set-up 50Ω Vrf + 6dB A 50Ω Vrf 50Ω PCB UNDER TEST Vrf + 6dB Input level referred to signal generator loaded with 50 Ω (Vrf, node 'A'); no antenna dummy; AM input not connected. Frf = 98.1 MHz, Vrf = 60 dBµV, mono modulation, fdev = 40 kHz, faudio = 1 kHz. De-emphasis = 50 µs. Unless otherwise specified Table 17. FM overall system performance Parameter Test condition Min Typ Max Units Tuning range FM Eu (can be modified by the user) (automatic FE alignment available) 87.5 - 108 MHz Tuning step FM Eu (can be modified by the user) - 100 - kHz Tuning range FM US (can be modified by the user) (automatic FE alignment available) 87.5 - 107.9 MHz Tuning step FM US (can be modified by the user) - 200 - kHz Tuning range FM Jp (can be modified by the user) (automatic FE alignment available) 76 - 90 MHz Tuning step FM Jp (can be modified by the user) - 100 - kHz Tuning range FM EEu (can be modified by the user) (automatic FE alignment not available) 65 - 74 MHz Tuning step FM EEu (can be modified by the user) - 100 - kHz Sensitivity S/N =26dB - -7 -4 dBµV S/N @ 10 dBµV, no highcut, DISS BW = #3 - 55 - dB @ 60 dBµV, mono 72 75 - dB @ 60 dBµV, Deviation = 75 kHz, mono 78 81 - dB @ 60 dBµV, stereo 70 73 - dB Ultimate S/N Doc ID 15938 Rev 8 23/42 Electrical specifications Table 17. TDA7705 FM overall system performance (continued) Parameter Test condition Typ Max Units Distortion Deviation= 75 kHz - 0.05 - % Max deviation THD=3% - 140 - kHz Adjacent channel selectivity ΔF=100kHz, SINAD=30dB desired 40 dBµV, dev=40kHz, 400Hz undesired. dev=40kHz, 1KHz - 25 - dB Alternate channel selectivity ΔF=200 kHz, SINAD=30 dB desired 40 dB µV, dev=40kHz, 400 Hz undesired. dev=40kHz, 1kHz - 63 - dB Max. strong signal interferer Desired = 10 dBµV SINAD = 30 dB Undesired ΔF = 5 MHz dev = 40 kHz, 1 kHz - 94 - dBµV Desired = 10 dBµV Max. strong signal interferer SINAD = 30 dB no preselection (“wide-band”) Undesired ΔF = 5 MHz application dev = 40 kHz, 1 kHz - 88 - dBµV Desired = 40 dBµV, dev = 40 kHz, 400 Hz, SINAD = 30 dB Undesired1 = ±400 kHz, dev = 40 kHz, 1 kHz Undesired2 = ±800 kHz, no mod - 103 - dBµV Desired = 40 dBµV, dev = 40 kHz, 400 Hz, SINAD = 30 dB Undesired1 = ±1 MHz, dev=40kHz, 1 kHz Undesired2=±2MHz, no mod - 106 - dBµV - 103 - dBµV - 104 - dBµV - 70 - dB 3 signal performance(1) Desired = 40 dBµV, dev = 40 kHz, 400 Hz, SINAD = 30 dB Undesired1 = ±400 kHz, dev = 40 kHz, 1 kHz (1) Undesired2 = ±800 kHz, no 3 signal performance no preselection (“wide-band”) mod application Desired = 40 dBµV, dev=40kHz, 400 Hz, SINAD=30 dB Undesired1 =±1 MHz, dev=40kHz, 1 kHz Undesired2=±2MHz, no mod AM suppression 24/42 Min m =30 % Doc ID 15938 Rev 8 TDA7705 Electrical specifications Table 17. FM overall system performance (continued) Parameter Test condition Image rejection - Logarithmic field strength indicator @40 dBµV read “FM_Smeter_log” Min Typ Max Units - 80 - dB -0.3 -0.27 (equiv. to 43 dBµV) -- -0.33 (equiv. to 37 dBµV) 1. Signal levels referred to combiner output. 3.5.2 AM MW overall system performance Antenna level equivalence: 0 dBµV = 1 µVrms. Figure 11. AM MW input set up Vrf + 6dB 15pF A 50Ω 30Ω 50Ω Vrf PCB UNDER TEST 68pF Level referred to SG output before antenna dummy (Vrf, node 'A'); capacitive dummy 15pF+68pF, FM input not connected. Frf = 999 kHz (1000 kHz for US), Vrf =74 dBµV, mod = 30%, faudio =400 Hz, unless otherwise specified. Table 18. AM MW overall system performance Parameter Test condition Min Typ Max Units Tuning range MW Eu/Jp (can be modified by the user) 531 - 1629 kHz Tuning step MW Eu/Jp (can be modified by the user) - 9 - kHz Tuning range MW US (can be modified by the user) 530 - 1710 kHz Tuning step MW US (can be modified by the user) - 10 - kHz Sensitivity S/N = 20 dB - 27 30 dBµV Ultimate S/N @ 80 dBµV 63 66 - dB AGC F.O.M. Ref.=74 dBµV -10dB drop point 50 62 65 dB Distortion m = 80 % - 0.1 - % Adjacent channel selectivity ΔF=9 kHz, SINAD = 26 dB undesired. m=30%, 1 kHz - 42 - dB Alternate channel selectivity ΔF=18 kHz, SINAD=26 dB undesired. m=30%, 1kHz - 50 - dB Doc ID 15938 Rev 8 25/42 Electrical specifications Table 18. TDA7705 AM MW overall system performance (continued) Parameter Min Typ Max Units ΔF= ±40 kHz desired = 40 dBµV undesired = 100 dBµV, m= 30%, 1 kHz - 15 - dB ΔF=±400kHz desired=40 dBµV undesired=100 dBµV, m=30%, 1kHz 17 - - dB ΔF=±40 kHz desired=40 dBµV undesired=110 dBµV, m=30%, 1 kHz - 4 - dB ΔF=±400kHz desired=40 dBµV undesired=110 dBµV, m=30%, 1kHz - 4 - dB ΔF=±40kHz desired=80 dBµV undesired=100 dBµV, m=30%, 1kHz - - 10 dB ΔF=±400kHz desired=80 dBµV undesired=100 dBµV, m=30%, 1kHz - - 10 dB Image rejection - - 80 - dB Logarithmic field strength indicator @60 dBµV read “AM_Smeter_log” 0.47 0.43 (equiv. to 63 dBµV) - Strong signal interferer SNR Strong signal interferer suppression Strong signal interferer cross-modulation 26/42 Test condition Doc ID 15938 Rev 8 0.50 (equiv. to 57 dBµV) TDA7705 3.5.3 Electrical specifications AM LW overall system performance Antenna level equivalence: 0 dBµV = 1 µVrms Figure 12. AM LW input set-up Vrf + 6dB 15pF A 50Ω 30Ω 50Ω Vrf PCB UNDER TEST 68pF Level referred to SG output before antenna dummy (Vrf, node 'A'); capacitive dummy 15pF+68pF; FM input not connected. Frf = 216 kHz, Vrf =74 dBµV, mod = 30 %, faudio = 400 Hz, unless otherwise specified. Table 19. AM LW overall system performance Parameter Test condition Min Typ Max Units Tuning range LW (can be modified by the user) 144 - 288 kHz Tuning step LW (can be modified by the user) - 1 - kHz Sensitivity S/N =20 dB - 30 33 dBµV Ultimate S/N @ 80 dBµV 63 66 - dB AGC F.O.M. Ref.=74 dBµV -10dB drop point 50 62 65 dB Distortion m = 80 % - 0.1 - % Image rejection - - 80 - dB Doc ID 15938 Rev 8 27/42 Electrical specifications 3.5.4 TDA7705 AM SW overall system performance Antenna level equivalence: 0dBµV = 1µVrms Figure 13. AM SW input set-up Vrf + 6dB 15pF A 50Ω 30Ω 50Ω Vrf PCB UNDER TEST 68pF Level referred to SG output before antenna dummy (Vrf, node 'A'); capacitive dummy 15pF+68pF; FM input not connected. Frf = 6000 kHz, Vrf =74 dBµV, mod = 30 %, faudio = 400 Hz, unless otherwise specified. Table 20. AM SW overall system performance Parameter 28/42 Test condition Min Typ Max Units Tuning range LW (can be modified by the user) 2300 - 30000 kHz Tuning step LW (can be modified by the user) - 1 - kHz Sensitivity S/N =20dB - 29 32 dBµV Ultimate S/N @ 80 dBµV 63 66 - dB AGC F.O.M. Ref.=74 dBµV -10dB drop point 50 62 65 dB Distortion m = 80 % - 0.3 - % Image rejection - - 80 - dB Doc ID 15938 Rev 8 TDA7705 3.5.5 Electrical specifications WX overall system performance Antenna level equivalence: 0 dBµV = 1 µVrms (Antenna terminal voltage with 50Ω source). Figure 14. WX input set-up 50Ω A Vrf + 6dB 50Ω Vrf 50Ω PCB UNDER TEST Vrf + 6dB Input level referred to signal generator loaded with 50 Ω (Vrf, node 'A'); no antenna dummy; AM input not connected. Frf =162.475 MHz, Vrf = 60 dBµV, mono modulation, fdev = 3 kHz, faudio =400 Hz. De-emphasis = 75 µs. Application: WX using mixer input 2, in conjunction with FM narrow-band. Unless otherwise specified. Table 21. WX overall system performance Parameter Test condition Min Typ Max Units Sensitivity S/N = 26 dB - -7 - dBµV Ultimate S/N @ 60 dBµV - 81 - dB Distortion Deviation= 4.5 kHz - 0.8 - % Max deviation THD = 3 % - > 5 kHz - kHz Adjacent channel Selectivity ΔF= 25 kHz, SINAD = 30 dB desired 40 dBµV, dev =2.0 kHz, 400 Hz undesired. dev= 3 kHz, 1 kHz - 70 - dB Alternate Channel Selectivity ΔF=50kHz, SINAD=30dB desired 40 dBµV, dev=2.0kHz, 400Hz undesired. dev=2.0kHz, 1kHz - 70 - dB Doc ID 15938 Rev 8 29/42 Front-end processing 4 TDA7705 Front-end processing All the parameters in this section refer to the programmability of the FE part of the device (registers). The part of the registers that are not described here have either fixed values or values written by the tuner drivers, and are described in the proper technical documentation. Table 22. Register 0x00 Register number MSB Register definition LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AM mixer input selector 0 1 input #1 1 0 input #2 AM PIN diode 0 internal 1 external AM AGC mode 0 LNA and PIN diode 1 PIN diode only AM AGC time constant 0 0 slow (125 ms with 1 µF) 0 1 medium (25 ms with 1 µF) 1 1 fast (5 ms with 1 µF) AM AGC threshold @ mixin 0 0 0 90 dBµV 0 0 1 91 dBµV 0 1 0 92 dBµV 0 1 1 93 dBµV 1 0 0 90 dBµV 1 0 1 89 dBµV 1 1 0 88 dBµV 1 1 1 87 dBµV AM AGC attack time constant 30/42 0 normal 1 fast Doc ID 15938 Rev 8 TDA7705 Table 23. Front-end processing Register 0x01 Register number MSB Register definition LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FM mixer input selector 0 1 1 0 input #1 1 0 0 1 input #2 FM mixer gain 0 high 1 low FM AGC time constant 0 normal 1 fast FM AGC output mode 0 0 normal 0 1 constant 15 mA 1 0 constant 1 mA Table 24. Register 0x02 Register number MSB Register definition LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FM RF AGC threshold @ mixin 0 0 87 dBµV 0 1 89 dBµV 1 0 91 dBµV 1 1 93 dBµV FM iF AGC threshold @ IFADC in 0 0 120 dBµV 0 1 122 dBµV 1 0 124 dBµV Tuning DAC enable 0 off 1 on Tuning DAC programming(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 … … … … … … … … … 1 1 1 1 1 1 1 0 510 1 1 1 1 1 1 1 1 511 1. Normally handled by tuner drivers. Doc ID 15938 Rev 8 31/42 Front-end processing Table 25. TDA7705 Register 0x05 Register number MSB Register definition LSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLLTEST output status 0 low 1 high 32/42 Doc ID 15938 Rev 8 TDA7705 5 Weak signal processing Weak signal processing All the parameters in this section refer to the programmability of the DSP part of the device. The typical values are those set by default parameters (start-up without parametric change from main µP); the max and the min values refer to the programmability range. The values are referred to the typical application (Figure 16: Example of FM tuned (narrow-band) application / SPI control). Wherever the possible values are a discrete set, all the possible programmable values are displayed. 5.1 FM IF-processing 5.1.1 Dynamic channel selection filter (DISS) Table 26. Dynamic channel selection filter (DISS) (discrete set) Symbol DISS BW Parameter Min Typ Max Units IF filter #6 - ±150 - kHz IF filter #5 - ±110 - kHz IF filter #4 - ±80 - kHz - ±60 - kHz IF filter #2 - ±45 - kHz IF filter #1 - ±35 - kHz IF filter #0 - ±25 - kHz Test condition Min Typ Max Units IF filter #3 5.1.2 Soft mute Table 27. Soft mute (continuous set) Symbol Test condition response: - 3dB Parameter SMsp Start point vs. field strength audio atten = 1 dB read “FM_softmute” no adjacent channel present 0 6 20 dBµV SMep End point vs. field strength audio atten = SMd + 1 dB read “FM_softmute” no adjacent channel present -6 -6 10 dBµV SMd Depth - -30 -15 0 dB SMtauatt Field strength LPF cut-off frequency for soft mute activation - 0.1 100 4000 Hz SMtaurel Field strength LPF cut-off frequency for soft mute release - 0.1 1 4000 Hz Doc ID 15938 Rev 8 33/42 Weak signal processing TDA7705 5.1.3 Adjacent channel mute Table 28. Adjacent channel mute (continuous set) Symbol ACMd Parameter Min Typ Max Units SMd 0 0 dB Test condition Min Typ Max Units Depth 5.1.4 Stereo blend- Table 29. Stereo blend (continuous set) Symbol Test condition Parameter MaxSep Maximum stereo separation field strength = 80 dBµV, pilot deviation = 6.75 kHz 0 40 50 dB SBFSsp Start point vs. field strength separation = MaxSep - 1 dB no multipath present 20 50 60 dBµV SBFSep End point vs. field strength separation = 1 dB no multipath present 20 30 60 dBµV Field strength-related SBFStM2S transition time from mono to stereo Vrf step-like variation from 20 dBµV to 80 dBµV 0.001 3 20 s Field strength-related SBFStS2M transition time from stereo to mono Vrf step-like variation from 80 dBµV to 20 dBµV 0.001 0.5 20 s Start point vs. multipath separation = MaxSep - 1 dB equivalent 19 kHz AM modulation depth; field strength = 80 dBµV 5 10 80 % End point vs. multipath separation = 1 dB equivalent 19 kHz AM modulation depth; field strength = 80 dBµV 5 30 80 % SBMPtM2S Multipath -related transition time from mono to stereo Vrf step-like variation from 20 dBµV to 80 dBµV 0.001 1 20 s SBMPtS2M Multipath -related transition time from stereo to mono Vrf step-like variation from 80 dBµV to 20 dBµV 0.001 0.001 20 s 0.8 2.74 7 kHz - 0.01 - kHz SBMPsp SBMPep Threshold on pilot tone Pil ThrM2S Pilot detector stereo threshold deviation for mono-stereo transition Pilot detector threshold Pil ThrHyst hysteresis 34/42 Difference in pil. det. deviation threshold for stereo to mono transition compared to PilThrM2S Doc ID 15938 Rev 8 TDA7705 Weak signal processing 5.1.5 High cut control Table 30. High cut control (continuous set) Symbol Parameter Test condition Min Typ Max Units HCFSsp Start point vs. field strength minimum RF level for widest HC filter (filter # 7) no multipath present 0 50 50 dBµV HCFSep End point vs. field strength maximum RF level for narrowest HC filter (filter # 0) no multipath present 0 30 40 dBµV Field strength-related HCFStW2N transition time from wide to narrow band Vrf step-like variation from 60 dBµV to 10 dBµV Field strength-related HCFStN2W transition time from narrow to wide band Vrf step-like variation from 0 dBµV to 60 dBµV (1) 14 100 s Start point vs. multipath minimum RF level for widest HC filter (filter # 7) equivalent 19 kHz AM modulation depth; field strength = 80 dBµV 5 10 150 (2) % End point vs. multipath maximum RF level for narrowest HC filter (filter # 0) equivalent 19 kHz AM modulation depth; field strength = 80 dBµV 5 30 150 (2) % HCMPsp HCMPep (1) - Multipath -related transition HCMPtN2W time from narrow to wide band Vrf step-like variation from 20 dBµV to 80 dBµV 0.001 0.001 20 s HCMPtW2N Multipath -related transition time from wide to narrow Vrf step-like variation from 80 dBµV to 20 dBµV 0.001 0.001 20 s HCmaxBW Filter #7, -3 dB response Maximum cut-off frequency of frequency, input signal with high cut filter bank pre-emphasis HCmin BW 14 18 kHz HCminBW Minimum cut-off frequency of high cut filter bank Filter #0, -3 dB response frequency, input signal with pre-emphasis 0.1 3 HCma xBW kHz HCnumFilt Number of discrete HC filters - - 8 (3) - - 1. Depends only on field strength filter time constant. 2. Means that 100% equivalent 19 kHz AM modulation depth will not achieve full band narrowing. 3. Intermediate filters (#6 - #1) cut-off frequencies exponentially spaced between HCmaxBW and HCminBW. Doc ID 15938 Rev 8 35/42 Weak signal processing Table 31. TDA7705 De-emphasis filter (continuous set) Symbol Parameter Test condition Min Typ Max De-emphasis time constant 1 - - 50 - De-emphasis time constant 2 - - 75 - Test condition Min Typ Max Units Pilot 9%, 19 kHz, ref=40 kHz - 60 - dB f = 38 kHz - 70 - dB f = 57 kHz - 70 - dB f = 76 kHz - 80 - dB Min Typ Max Units - ±3.7 - kHz Test condition Min Typ Max Units DEtc µs 5.1.6 Stereo decoder Table 32. Stereo decoder Symbol PilSup SubcSup Parameter Pilot signal suppression Subcarrier suppression 5.2 AM IF-processing 5.2.1 Channel selection filter Table 33. Channel selection filter Symbol CSF BW Units Parameter Channel selection filter BW 5.2.2 Soft mute Table 34. Soft mute (continuous set) Symbol Test condition response: - 3dB Parameter SMsp Start point vs. field strength audio atten = 1 dB read “FM_softmute” no adjacent channel present 0 25 40 dBµV SMep End point vs. field strength audio atten = SMd + 1 dB read “FM_softmute” no adjacent channel present 0 0 30 dBµV SMd Depth - -40 -24 0 dB SMtauatt Transition time for field strength-dependent soft mute activation 0.001 0.1 10 s SMtaurel Transition time for field strength-dependent soft mute release 0.001 3 10 s 36/42 Doc ID 15938 Rev 8 TDA7705 Weak signal processing 5.2.3 High cut control Table 35. High cut control (continuous set) Symbol Parameter Test condition Min Typ Max Units HCFSsp Start point vs. field strength minimum RF level for widest HC filter (filter # 7) no multipath present 0 40 50 dBµV HCFSep End point vs. field strength maximum RF level for narrowest HC filter (filter # 0) no multipath present 0 30 50 dBµV Field strength-related HCFStW2N transition time from wide to narrow band Vrf step-like variation from 60 dBµV to 10 dBµV 0.001 0.2 20 s Field strength-related HCFStN2W transition time from narrow to wide band Vrf step-like variation from 0 dBµV to 60 dBµV 0.001 10 20 s HCmin BW 14 18 kHz 1 3 HCma xBW kHz - 8 - - HCmaxBW Filter #7, -3 dB response Maximum cut-off frequency of frequency, input signal with high cut filter bank pre-emphasis HCminBW Minimum cut-off frequency of high cut filter bank HCnumFilt Number of discrete HC filters Filter #0, -3 dB response frequency, input signal with pre-emphasis Doc ID 15938 Rev 8 37/42 FMANT KP2311E 22pF LLQ2012-FR22 TOKO 1K GND-RF 22pF 220 10nF 15pF KP2311E 10nF AMANT VRF GND-RF 220pF 68uH 5.6K GND-RF 1uF 100nF 10nF 220nF GND-RF 2.2uF GND-RF 10nF PLL TEST 4.7nF 1µF 1uF LNAin GND-LNA PINDin PINDdec AMPINDRV TCAM VCC-RF FMPINDRV GND-RF FMMIX2in FMMIX1in FMMIX1dec TCAGCFM DAC PLLTEST LF1 GND-RF 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100nF 100 1K 100nF 17 LLQ2012-FR22 TOKO 64 GND-VCO LNAdec 63 VCC-VCO 62 100nF 61 1. Note: components marked with a * are being considered for replacement with resistors, pending optimization test results. 10nF 120pF 19 LNAout 18 LFref LNAin2 60 VCOdec 20 GND-PLL LNAout2 68uH LNAdec2 59 22 100nF DACOUT_L 100nF TDA7705 AMMIXin2 * 23 AMMIXin1 GND-RF 1K GND-RF AMMIXdec 24 VREF165 26 1uF * 27 VREFdec * 1uF GND-IF 25 68pF 21 100nF VCC-PLL 58 VCC-IFADC 56 LIFrefL 57 LIFrefH 55 GND-IFADC DACOUT_R 54 DACoutR 53 28 52 DACoutL GND-DIG 29 GND-DAC 49 2 1 GND-3V3 SPI_CS SPI_MISO SDA SCL VDD-1V2 RDSINT GPIO3 GPIO2 GPIO1 AFS MODE RSTN TEST VDD-1V2 DIG_GND 33 34 35 VDIG DIG_GND SCL RDSINT RSTN SDA_MOSI DIG_GND 100nF DIG_GND DIG_GND 100nF VDIG 36 1uF 100nF 37 38 39 40 41 42 43 44 45 46 47 48 37.05MHz NDK5032 XTAL GND-1V2 VCC-DAC 50 OSCout REG-1V2 51 30 VCC-DIG 100nF OSCin VCCREG12 470nF Doc ID 15938 Rev 8 VDD-3V3 38/42 31 Basic application schematic 32 6.1 27 1/2W Application schematics 1uF 6 10nF VIF Application schematics TDA7705 Figure 15. FM wide-band application / I2C control 20pF FMANT 100nF 1nF 2 1 KP2311E 220 LLQ2012-FR18 TOKO C25 GND-RF LLQ2012-FR39 TOKO 1nF 1K5 KP2311E 2 1 GND-RF 6pF 15pF C31 2 AMANT VRF 1 R6 68K 3 C28 220pF 39pF 68uH 5.6K GND-RF 1uF 100nF 1 GND-RF 1 2.2uF GND-RF 220nF 5pF 10nF PLL TEST 4.7nF 9 8 7 6 5 4 3 2 1 1uF LNAin GND-LNA PINDin PINDdec AMPINDRV TCAM VCC-RF FMPINDRV GND-RF FMMIX2in FMMIX1in FMMIX1dec TCAGCFM DAC PLLTEST LF1 GND-RF 16 15 14 13 12 11 10 1µF 100nF 100 1K 100nF 17 D3 KV1770 64 100nF 61 10nF 120pF GND-VCO LNAdec 63 VCC-VCO 62 19 LNAout 18 LFref LNAin2 60 VCOdec 20 GND-PLL LNAout2 59 22 100nF DACOUT_L 53 TDA7705 AMMIXin2 * 1 23 AMMIXin1 GND-RF 1K 21 100nF 100nF 24 GND-RF AMMIXdec 68pF GND-IF 25 VREF165 26 1uF * 27 LNAdec2 68uH VCC-PLL 58 VCC-IFADC 56 LIFrefL 57 LIFrefH 55 GND-IFADC DACOUT_R 54 DACoutR * 50 OSCout 49 2 1 GND-3V3 SPI_CS SPI_MISO SDA SCL VDD-1V2 RDSINT GPIO3 GPIO2 GPIO1 AFS MODE RSTN TEST VDD-1V2 DIG_GND VDIG CS 34 DIG_GND SPI_MISO 35 33 SCL SDA_MOSI 36 100nF 37 RDSINT RSTN 100nF VDIG 38 1uF 100nF 39 40 41 42 43 44 45 46 47 48 37.05MHz NDK5032 XTAL GND-1V2 VCC-DAC 52 DACoutL GND-DIG 28 VREFdec 1uF GND-DAC VCC-DIG 29 100nF 51 OSCin 30 VCCREG12 470nF REG-1V2 31 VDD-3V3 32 VIF 1uF Doc ID 15938 Rev 8 10nF 10nF C23 12pF L6 TOKO E558CN-1000101 DIG_GND DIG_GND 6.2 27 1/2W TDA7705 Application schematics Application schematic example with SPI-bus and tuned preselection Figure 16. Example of FM tuned (narrow-band) application / SPI control 1. Note: components marked with a * are being considered for replacement with resistors, pending optimization test results. 39/42 Package information 7 TDA7705 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 17. LQFP64 (10x10x1.4mm) mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. A MIN. TYP. 1.60 0.063 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 0.006 0.22 0.27 0.0066 0.0086 0.0106 0.20 0.0035 0.055 0.057 B 0.17 C 0.09 D 11.80 12.00 12.20 0.464 0.472 0.480 D1 9.80 10.00 10.20 0.386 0.394 0.401 0.0079 D3 7.50 0.295 e 0.50 0.0197 E 11.80 12.00 12.20 0.464 0.472 0.480 E1 9.80 10.00 10.20 0.386 0.394 0.401 0.45 0.60 0.75 0.0177 0.0236 0.0295 E3 7.50 L OUTLINE AND MECHANICAL DATA MAX. 0.295 L1 1.00 K 0˚ (min.), 3.5˚ (min.), 7˚(max.) 0.0393 ccc 0.080 LQFP64 (10 x 10 x 1.4mm) 0.0031 D D1 A D3 A2 A1 48 33 49 32 0.08mm ccc E E1 E3 B B Seating Plane 17 64 1 16 C L L1 e K TQFP64 0051434 F 40/42 Doc ID 15938 Rev 8 TDA7705 8 Revision history Revision history Table 36. Document revision history Date Revision Changes 31-Jul-2007 1 Initial release. 01-Aug-2008 2 Full update datasheet. 08-May-2009 3 Document status promoted from preliminary data to datasheet. Updated Table 1: Device summary on page 1. Updated Section 3: Electrical specifications on page 16. Updated Section 4: Front-end processing on page 30. Updated Section 5: Weak signal processing on page 33. Updated Section 6: Application schematics on page 38. 09-Jun-2009 4 Updated Table 5: Thermal data on page 16. Updated the value of “Adjacent channel selectivity” parameter in the Table 17: FM overall system performance. 01-Jul-2009 5 Updated Figure 17: LQFP64 (10x10x1.4mm) mechanical data and package dimensions on page 40. 13-Jan-2010 6 Modified Table 1: Device summary on page 1 Modified Table 5: Thermal data on page 16. Modified Section 3.5.5: WX overall system performance on page 29. Modified Section 7: Package information on page 40. 29-Jan-2010 7 Minor text changes in Section 2.13. Modified min. value of “tHD-DAT” parameter in Table 15: I2C interface on page 21. 22-Mar-2010 8 Added Section 3.4.11: Warning on page 22. Doc ID 15938 Rev 8 41/42 TDA7705 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 42/42 Doc ID 15938 Rev 8